1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _LINUX_PGTABLE_H
3#define _LINUX_PGTABLE_H
4
5#include <linux/pfn.h>
6#include <asm/pgtable.h>
7
8#define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT)
9#define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT)
10
11#ifndef __ASSEMBLY__
12#ifdef CONFIG_MMU
13
14#include <linux/mm_types.h>
15#include <linux/bug.h>
16#include <linux/errno.h>
17#include <asm-generic/pgtable_uffd.h>
18#include <linux/page_table_check.h>
19
20#if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
22#error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED
23#endif
24
25/*
26 * On almost all architectures and configurations, 0 can be used as the
27 * upper ceiling to free_pgtables(): on many architectures it has the same
28 * effect as using TASK_SIZE. However, there is one configuration which
29 * must impose a more careful limit, to avoid freeing kernel pgtables.
30 */
31#ifndef USER_PGTABLES_CEILING
32#define USER_PGTABLES_CEILING 0UL
33#endif
34
35/*
36 * This defines the first usable user address. Platforms
37 * can override its value with custom FIRST_USER_ADDRESS
38 * defined in their respective <asm/pgtable.h>.
39 */
40#ifndef FIRST_USER_ADDRESS
41#define FIRST_USER_ADDRESS 0UL
42#endif
43
44/*
45 * This defines the generic helper for accessing PMD page
46 * table page. Although platforms can still override this
47 * via their respective <asm/pgtable.h>.
48 */
49#ifndef pmd_pgtable
50#define pmd_pgtable(pmd) pmd_page(pmd)
51#endif
52
53/*
54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD]
55 *
56 * The pXx_index() functions return the index of the entry in the page
57 * table page which would control the given virtual address
58 *
59 * As these functions may be used by the same code for different levels of
60 * the page table folding, they are always available, regardless of
61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0
62 * because in such cases PTRS_PER_PxD equals 1.
63 */
64
65static inline unsigned long pte_index(unsigned long address)
66{
67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
68}
69
70#ifndef pmd_index
71static inline unsigned long pmd_index(unsigned long address)
72{
73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
74}
75#define pmd_index pmd_index
76#endif
77
78#ifndef pud_index
79static inline unsigned long pud_index(unsigned long address)
80{
81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
82}
83#define pud_index pud_index
84#endif
85
86#ifndef pgd_index
87/* Must be a compile-time constant, so implement it as a macro */
88#define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
89#endif
90
91#ifndef pte_offset_kernel
92static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
93{
94 return (pte_t *)pmd_page_vaddr(pmd: *pmd) + pte_index(address);
95}
96#define pte_offset_kernel pte_offset_kernel
97#endif
98
99#ifdef CONFIG_HIGHPTE
100#define __pte_map(pmd, address) \
101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address)))
102#define pte_unmap(pte) do { \
103 kunmap_local((pte)); \
104 rcu_read_unlock(); \
105} while (0)
106#else
107static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address)
108{
109 return pte_offset_kernel(pmd, address);
110}
111static inline void pte_unmap(pte_t *pte)
112{
113 rcu_read_unlock();
114}
115#endif
116
117void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable);
118
119/* Find an entry in the second-level page table.. */
120#ifndef pmd_offset
121static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
122{
123 return pud_pgtable(pud: *pud) + pmd_index(address);
124}
125#define pmd_offset pmd_offset
126#endif
127
128#ifndef pud_offset
129static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address)
130{
131 return p4d_pgtable(p4d: *p4d) + pud_index(address);
132}
133#define pud_offset pud_offset
134#endif
135
136static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address)
137{
138 return (pgd + pgd_index(address));
139};
140
141/*
142 * a shortcut to get a pgd_t in a given mm
143 */
144#ifndef pgd_offset
145#define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address))
146#endif
147
148/*
149 * a shortcut which implies the use of the kernel's pgd, instead
150 * of a process's
151 */
152#ifndef pgd_offset_k
153#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
154#endif
155
156/*
157 * In many cases it is known that a virtual address is mapped at PMD or PTE
158 * level, so instead of traversing all the page table levels, we can get a
159 * pointer to the PMD entry in user or kernel page table or translate a virtual
160 * address to the pointer in the PTE in the kernel page tables with simple
161 * helpers.
162 */
163static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
164{
165 return pmd_offset(pud_offset(p4d: p4d_offset(pgd_offset(mm, va), address: va), address: va), address: va);
166}
167
168static inline pmd_t *pmd_off_k(unsigned long va)
169{
170 return pmd_offset(pud_offset(p4d: p4d_offset(pgd_offset_k(va), address: va), address: va), address: va);
171}
172
173static inline pte_t *virt_to_kpte(unsigned long vaddr)
174{
175 pmd_t *pmd = pmd_off_k(va: vaddr);
176
177 return pmd_none(pmd: *pmd) ? NULL : pte_offset_kernel(pmd, address: vaddr);
178}
179
180#ifndef pmd_young
181static inline int pmd_young(pmd_t pmd)
182{
183 return 0;
184}
185#endif
186
187/*
188 * A facility to provide lazy MMU batching. This allows PTE updates and
189 * page invalidations to be delayed until a call to leave lazy MMU mode
190 * is issued. Some architectures may benefit from doing this, and it is
191 * beneficial for both shadow and direct mode hypervisors, which may batch
192 * the PTE updates which happen during this window. Note that using this
193 * interface requires that read hazards be removed from the code. A read
194 * hazard could result in the direct mode hypervisor case, since the actual
195 * write to the page tables may not yet have taken place, so reads though
196 * a raw PTE pointer after it has been modified are not guaranteed to be
197 * up to date. This mode can only be entered and left under the protection of
198 * the page table locks for all page tables which may be modified. In the UP
199 * case, this is required so that preemption is disabled, and in the SMP case,
200 * it must synchronize the delayed page table writes properly on other CPUs.
201 */
202#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
203#define arch_enter_lazy_mmu_mode() do {} while (0)
204#define arch_leave_lazy_mmu_mode() do {} while (0)
205#define arch_flush_lazy_mmu_mode() do {} while (0)
206#endif
207
208#ifndef set_ptes
209
210#ifndef pte_next_pfn
211static inline pte_t pte_next_pfn(pte_t pte)
212{
213 return __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT));
214}
215#endif
216
217/**
218 * set_ptes - Map consecutive pages to a contiguous range of addresses.
219 * @mm: Address space to map the pages into.
220 * @addr: Address to map the first page at.
221 * @ptep: Page table pointer for the first entry.
222 * @pte: Page table entry for the first page.
223 * @nr: Number of pages to map.
224 *
225 * May be overridden by the architecture, or the architecture can define
226 * set_pte() and PFN_PTE_SHIFT.
227 *
228 * Context: The caller holds the page table lock. The pages all belong
229 * to the same folio. The PTEs are all in the same PMD.
230 */
231static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
232 pte_t *ptep, pte_t pte, unsigned int nr)
233{
234 page_table_check_ptes_set(mm, ptep, pte, nr);
235
236 arch_enter_lazy_mmu_mode();
237 for (;;) {
238 set_pte(ptep, pte);
239 if (--nr == 0)
240 break;
241 ptep++;
242 pte = pte_next_pfn(pte);
243 }
244 arch_leave_lazy_mmu_mode();
245}
246#endif
247#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1)
248
249#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
250extern int ptep_set_access_flags(struct vm_area_struct *vma,
251 unsigned long address, pte_t *ptep,
252 pte_t entry, int dirty);
253#endif
254
255#ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
256#ifdef CONFIG_TRANSPARENT_HUGEPAGE
257extern int pmdp_set_access_flags(struct vm_area_struct *vma,
258 unsigned long address, pmd_t *pmdp,
259 pmd_t entry, int dirty);
260extern int pudp_set_access_flags(struct vm_area_struct *vma,
261 unsigned long address, pud_t *pudp,
262 pud_t entry, int dirty);
263#else
264static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
265 unsigned long address, pmd_t *pmdp,
266 pmd_t entry, int dirty)
267{
268 BUILD_BUG();
269 return 0;
270}
271static inline int pudp_set_access_flags(struct vm_area_struct *vma,
272 unsigned long address, pud_t *pudp,
273 pud_t entry, int dirty)
274{
275 BUILD_BUG();
276 return 0;
277}
278#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
279#endif
280
281#ifndef ptep_get
282static inline pte_t ptep_get(pte_t *ptep)
283{
284 return READ_ONCE(*ptep);
285}
286#endif
287
288#ifndef pmdp_get
289static inline pmd_t pmdp_get(pmd_t *pmdp)
290{
291 return READ_ONCE(*pmdp);
292}
293#endif
294
295#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
296static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
297 unsigned long address,
298 pte_t *ptep)
299{
300 pte_t pte = ptep_get(ptep);
301 int r = 1;
302 if (!pte_young(pte))
303 r = 0;
304 else
305 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
306 return r;
307}
308#endif
309
310#ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
311#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG)
312static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
313 unsigned long address,
314 pmd_t *pmdp)
315{
316 pmd_t pmd = *pmdp;
317 int r = 1;
318 if (!pmd_young(pmd))
319 r = 0;
320 else
321 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
322 return r;
323}
324#else
325static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
326 unsigned long address,
327 pmd_t *pmdp)
328{
329 BUILD_BUG();
330 return 0;
331}
332#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */
333#endif
334
335#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
336int ptep_clear_flush_young(struct vm_area_struct *vma,
337 unsigned long address, pte_t *ptep);
338#endif
339
340#ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
341#ifdef CONFIG_TRANSPARENT_HUGEPAGE
342extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
343 unsigned long address, pmd_t *pmdp);
344#else
345/*
346 * Despite relevant to THP only, this API is called from generic rmap code
347 * under PageTransHuge(), hence needs a dummy implementation for !THP
348 */
349static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
350 unsigned long address, pmd_t *pmdp)
351{
352 BUILD_BUG();
353 return 0;
354}
355#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
356#endif
357
358#ifndef arch_has_hw_nonleaf_pmd_young
359/*
360 * Return whether the accessed bit in non-leaf PMD entries is supported on the
361 * local CPU.
362 */
363static inline bool arch_has_hw_nonleaf_pmd_young(void)
364{
365 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG);
366}
367#endif
368
369#ifndef arch_has_hw_pte_young
370/*
371 * Return whether the accessed bit is supported on the local CPU.
372 *
373 * This stub assumes accessing through an old PTE triggers a page fault.
374 * Architectures that automatically set the access bit should overwrite it.
375 */
376static inline bool arch_has_hw_pte_young(void)
377{
378 return false;
379}
380#endif
381
382#ifndef arch_check_zapped_pte
383static inline void arch_check_zapped_pte(struct vm_area_struct *vma,
384 pte_t pte)
385{
386}
387#endif
388
389#ifndef arch_check_zapped_pmd
390static inline void arch_check_zapped_pmd(struct vm_area_struct *vma,
391 pmd_t pmd)
392{
393}
394#endif
395
396#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
397static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
398 unsigned long address,
399 pte_t *ptep)
400{
401 pte_t pte = ptep_get(ptep);
402 pte_clear(mm, address, ptep);
403 page_table_check_pte_clear(mm, pte);
404 return pte;
405}
406#endif
407
408static inline void ptep_clear(struct mm_struct *mm, unsigned long addr,
409 pte_t *ptep)
410{
411 ptep_get_and_clear(mm, addr, ptep);
412}
413
414#ifdef CONFIG_GUP_GET_PXX_LOW_HIGH
415/*
416 * For walking the pagetables without holding any locks. Some architectures
417 * (eg x86-32 PAE) cannot load the entries atomically without using expensive
418 * instructions. We are guaranteed that a PTE will only either go from not
419 * present to present, or present to not present -- it will not switch to a
420 * completely different present page without a TLB flush inbetween; which we
421 * are blocking by holding interrupts off.
422 *
423 * Setting ptes from not present to present goes:
424 *
425 * ptep->pte_high = h;
426 * smp_wmb();
427 * ptep->pte_low = l;
428 *
429 * And present to not present goes:
430 *
431 * ptep->pte_low = 0;
432 * smp_wmb();
433 * ptep->pte_high = 0;
434 *
435 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'.
436 * We load pte_high *after* loading pte_low, which ensures we don't see an older
437 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't
438 * picked up a changed pte high. We might have gotten rubbish values from
439 * pte_low and pte_high, but we are guaranteed that pte_low will not have the
440 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only
441 * operates on present ptes we're safe.
442 */
443static inline pte_t ptep_get_lockless(pte_t *ptep)
444{
445 pte_t pte;
446
447 do {
448 pte.pte_low = ptep->pte_low;
449 smp_rmb();
450 pte.pte_high = ptep->pte_high;
451 smp_rmb();
452 } while (unlikely(pte.pte_low != ptep->pte_low));
453
454 return pte;
455}
456#define ptep_get_lockless ptep_get_lockless
457
458#if CONFIG_PGTABLE_LEVELS > 2
459static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
460{
461 pmd_t pmd;
462
463 do {
464 pmd.pmd_low = pmdp->pmd_low;
465 smp_rmb();
466 pmd.pmd_high = pmdp->pmd_high;
467 smp_rmb();
468 } while (unlikely(pmd.pmd_low != pmdp->pmd_low));
469
470 return pmd;
471}
472#define pmdp_get_lockless pmdp_get_lockless
473#define pmdp_get_lockless_sync() tlb_remove_table_sync_one()
474#endif /* CONFIG_PGTABLE_LEVELS > 2 */
475#endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */
476
477/*
478 * We require that the PTE can be read atomically.
479 */
480#ifndef ptep_get_lockless
481static inline pte_t ptep_get_lockless(pte_t *ptep)
482{
483 return ptep_get(ptep);
484}
485#endif
486
487#ifndef pmdp_get_lockless
488static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
489{
490 return pmdp_get(pmdp);
491}
492static inline void pmdp_get_lockless_sync(void)
493{
494}
495#endif
496
497#ifdef CONFIG_TRANSPARENT_HUGEPAGE
498#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
499static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
500 unsigned long address,
501 pmd_t *pmdp)
502{
503 pmd_t pmd = *pmdp;
504
505 pmd_clear(pmdp);
506 page_table_check_pmd_clear(mm, pmd);
507
508 return pmd;
509}
510#endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */
511#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
512static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
513 unsigned long address,
514 pud_t *pudp)
515{
516 pud_t pud = *pudp;
517
518 pud_clear(pudp);
519 page_table_check_pud_clear(mm, pud);
520
521 return pud;
522}
523#endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */
524#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
525
526#ifdef CONFIG_TRANSPARENT_HUGEPAGE
527#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
528static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
529 unsigned long address, pmd_t *pmdp,
530 int full)
531{
532 return pmdp_huge_get_and_clear(mm: vma->vm_mm, addr: address, pmdp);
533}
534#endif
535
536#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
537static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
538 unsigned long address, pud_t *pudp,
539 int full)
540{
541 return pudp_huge_get_and_clear(mm: vma->vm_mm, addr: address, pudp);
542}
543#endif
544#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
545
546#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
547static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
548 unsigned long address, pte_t *ptep,
549 int full)
550{
551 return ptep_get_and_clear(mm, address, ptep);
552}
553#endif
554
555
556/*
557 * If two threads concurrently fault at the same page, the thread that
558 * won the race updates the PTE and its local TLB/Cache. The other thread
559 * gives up, simply does nothing, and continues; on architectures where
560 * software can update TLB, local TLB can be updated here to avoid next page
561 * fault. This function updates TLB only, do nothing with cache or others.
562 * It is the difference with function update_mmu_cache.
563 */
564#ifndef __HAVE_ARCH_UPDATE_MMU_TLB
565static inline void update_mmu_tlb(struct vm_area_struct *vma,
566 unsigned long address, pte_t *ptep)
567{
568}
569#define __HAVE_ARCH_UPDATE_MMU_TLB
570#endif
571
572/*
573 * Some architectures may be able to avoid expensive synchronization
574 * primitives when modifications are made to PTE's which are already
575 * not present, or in the process of an address space destruction.
576 */
577#ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
578static inline void pte_clear_not_present_full(struct mm_struct *mm,
579 unsigned long address,
580 pte_t *ptep,
581 int full)
582{
583 pte_clear(mm, addr: address, ptep);
584}
585#endif
586
587#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
588extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
589 unsigned long address,
590 pte_t *ptep);
591#endif
592
593#ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
594extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
595 unsigned long address,
596 pmd_t *pmdp);
597extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
598 unsigned long address,
599 pud_t *pudp);
600#endif
601
602#ifndef pte_mkwrite
603static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma)
604{
605 return pte_mkwrite_novma(pte);
606}
607#endif
608
609#if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite)
610static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma)
611{
612 return pmd_mkwrite_novma(pmd);
613}
614#endif
615
616#ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
617struct mm_struct;
618static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
619{
620 pte_t old_pte = ptep_get(ptep);
621 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
622}
623#endif
624
625/*
626 * On some architectures hardware does not set page access bit when accessing
627 * memory page, it is responsibility of software setting this bit. It brings
628 * out extra page fault penalty to track page access bit. For optimization page
629 * access bit can be set during all page fault flow on these arches.
630 * To be differentiate with macro pte_mkyoung, this macro is used on platforms
631 * where software maintains page access bit.
632 */
633#ifndef pte_sw_mkyoung
634static inline pte_t pte_sw_mkyoung(pte_t pte)
635{
636 return pte;
637}
638#define pte_sw_mkyoung pte_sw_mkyoung
639#endif
640
641#ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
642#ifdef CONFIG_TRANSPARENT_HUGEPAGE
643static inline void pmdp_set_wrprotect(struct mm_struct *mm,
644 unsigned long address, pmd_t *pmdp)
645{
646 pmd_t old_pmd = *pmdp;
647 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
648}
649#else
650static inline void pmdp_set_wrprotect(struct mm_struct *mm,
651 unsigned long address, pmd_t *pmdp)
652{
653 BUILD_BUG();
654}
655#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
656#endif
657#ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
658#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
659#ifdef CONFIG_TRANSPARENT_HUGEPAGE
660static inline void pudp_set_wrprotect(struct mm_struct *mm,
661 unsigned long address, pud_t *pudp)
662{
663 pud_t old_pud = *pudp;
664
665 set_pud_at(mm, addr: address, pudp, pud: pud_wrprotect(pud: old_pud));
666}
667#else
668static inline void pudp_set_wrprotect(struct mm_struct *mm,
669 unsigned long address, pud_t *pudp)
670{
671 BUILD_BUG();
672}
673#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
674#endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
675#endif
676
677#ifndef pmdp_collapse_flush
678#ifdef CONFIG_TRANSPARENT_HUGEPAGE
679extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
680 unsigned long address, pmd_t *pmdp);
681#else
682static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
683 unsigned long address,
684 pmd_t *pmdp)
685{
686 BUILD_BUG();
687 return *pmdp;
688}
689#define pmdp_collapse_flush pmdp_collapse_flush
690#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
691#endif
692
693#ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
694extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
695 pgtable_t pgtable);
696#endif
697
698#ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
699extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
700#endif
701
702#ifndef arch_needs_pgtable_deposit
703#define arch_needs_pgtable_deposit() (false)
704#endif
705
706#ifdef CONFIG_TRANSPARENT_HUGEPAGE
707/*
708 * This is an implementation of pmdp_establish() that is only suitable for an
709 * architecture that doesn't have hardware dirty/accessed bits. In this case we
710 * can't race with CPU which sets these bits and non-atomic approach is fine.
711 */
712static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
713 unsigned long address, pmd_t *pmdp, pmd_t pmd)
714{
715 pmd_t old_pmd = *pmdp;
716 set_pmd_at(mm: vma->vm_mm, addr: address, pmdp, pmd);
717 return old_pmd;
718}
719#endif
720
721#ifndef __HAVE_ARCH_PMDP_INVALIDATE
722extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
723 pmd_t *pmdp);
724#endif
725
726#ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD
727
728/*
729 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent
730 * hugepage mapping in the page tables. This function is similar to
731 * pmdp_invalidate(), but should only be used if the access and dirty bits would
732 * not be cleared by the software in the new PMD value. The function ensures
733 * that hardware changes of the access and dirty bits updates would not be lost.
734 *
735 * Doing so can allow in certain architectures to avoid a TLB flush in most
736 * cases. Yet, another TLB flush might be necessary later if the PMD update
737 * itself requires such flush (e.g., if protection was set to be stricter). Yet,
738 * even when a TLB flush is needed because of the update, the caller may be able
739 * to batch these TLB flushing operations, so fewer TLB flush operations are
740 * needed.
741 */
742extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
743 unsigned long address, pmd_t *pmdp);
744#endif
745
746#ifndef __HAVE_ARCH_PTE_SAME
747static inline int pte_same(pte_t pte_a, pte_t pte_b)
748{
749 return pte_val(pte_a) == pte_val(pte_b);
750}
751#endif
752
753#ifndef __HAVE_ARCH_PTE_UNUSED
754/*
755 * Some architectures provide facilities to virtualization guests
756 * so that they can flag allocated pages as unused. This allows the
757 * host to transparently reclaim unused pages. This function returns
758 * whether the pte's page is unused.
759 */
760static inline int pte_unused(pte_t pte)
761{
762 return 0;
763}
764#endif
765
766#ifndef pte_access_permitted
767#define pte_access_permitted(pte, write) \
768 (pte_present(pte) && (!(write) || pte_write(pte)))
769#endif
770
771#ifndef pmd_access_permitted
772#define pmd_access_permitted(pmd, write) \
773 (pmd_present(pmd) && (!(write) || pmd_write(pmd)))
774#endif
775
776#ifndef pud_access_permitted
777#define pud_access_permitted(pud, write) \
778 (pud_present(pud) && (!(write) || pud_write(pud)))
779#endif
780
781#ifndef p4d_access_permitted
782#define p4d_access_permitted(p4d, write) \
783 (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
784#endif
785
786#ifndef pgd_access_permitted
787#define pgd_access_permitted(pgd, write) \
788 (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
789#endif
790
791#ifndef __HAVE_ARCH_PMD_SAME
792static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
793{
794 return pmd_val(pmd: pmd_a) == pmd_val(pmd: pmd_b);
795}
796#endif
797
798#ifndef pud_same
799static inline int pud_same(pud_t pud_a, pud_t pud_b)
800{
801 return pud_val(pud: pud_a) == pud_val(pud: pud_b);
802}
803#define pud_same pud_same
804#endif
805
806#ifndef __HAVE_ARCH_P4D_SAME
807static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b)
808{
809 return p4d_val(p4d: p4d_a) == p4d_val(p4d: p4d_b);
810}
811#endif
812
813#ifndef __HAVE_ARCH_PGD_SAME
814static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b)
815{
816 return pgd_val(pgd: pgd_a) == pgd_val(pgd: pgd_b);
817}
818#endif
819
820/*
821 * Use set_p*_safe(), and elide TLB flushing, when confident that *no*
822 * TLB flush will be required as a result of the "set". For example, use
823 * in scenarios where it is known ahead of time that the routine is
824 * setting non-present entries, or re-setting an existing entry to the
825 * same value. Otherwise, use the typical "set" helpers and flush the
826 * TLB.
827 */
828#define set_pte_safe(ptep, pte) \
829({ \
830 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \
831 set_pte(ptep, pte); \
832})
833
834#define set_pmd_safe(pmdp, pmd) \
835({ \
836 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \
837 set_pmd(pmdp, pmd); \
838})
839
840#define set_pud_safe(pudp, pud) \
841({ \
842 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \
843 set_pud(pudp, pud); \
844})
845
846#define set_p4d_safe(p4dp, p4d) \
847({ \
848 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \
849 set_p4d(p4dp, p4d); \
850})
851
852#define set_pgd_safe(pgdp, pgd) \
853({ \
854 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
855 set_pgd(pgdp, pgd); \
856})
857
858#ifndef __HAVE_ARCH_DO_SWAP_PAGE
859/*
860 * Some architectures support metadata associated with a page. When a
861 * page is being swapped out, this metadata must be saved so it can be
862 * restored when the page is swapped back in. SPARC M7 and newer
863 * processors support an ADI (Application Data Integrity) tag for the
864 * page as metadata for the page. arch_do_swap_page() can restore this
865 * metadata when a page is swapped back in.
866 */
867static inline void arch_do_swap_page(struct mm_struct *mm,
868 struct vm_area_struct *vma,
869 unsigned long addr,
870 pte_t pte, pte_t oldpte)
871{
872
873}
874#endif
875
876#ifndef __HAVE_ARCH_UNMAP_ONE
877/*
878 * Some architectures support metadata associated with a page. When a
879 * page is being swapped out, this metadata must be saved so it can be
880 * restored when the page is swapped back in. SPARC M7 and newer
881 * processors support an ADI (Application Data Integrity) tag for the
882 * page as metadata for the page. arch_unmap_one() can save this
883 * metadata on a swap-out of a page.
884 */
885static inline int arch_unmap_one(struct mm_struct *mm,
886 struct vm_area_struct *vma,
887 unsigned long addr,
888 pte_t orig_pte)
889{
890 return 0;
891}
892#endif
893
894/*
895 * Allow architectures to preserve additional metadata associated with
896 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function
897 * prototypes must be defined in the arch-specific asm/pgtable.h file.
898 */
899#ifndef __HAVE_ARCH_PREPARE_TO_SWAP
900static inline int arch_prepare_to_swap(struct page *page)
901{
902 return 0;
903}
904#endif
905
906#ifndef __HAVE_ARCH_SWAP_INVALIDATE
907static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
908{
909}
910
911static inline void arch_swap_invalidate_area(int type)
912{
913}
914#endif
915
916#ifndef __HAVE_ARCH_SWAP_RESTORE
917static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
918{
919}
920#endif
921
922#ifndef __HAVE_ARCH_PGD_OFFSET_GATE
923#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
924#endif
925
926#ifndef __HAVE_ARCH_MOVE_PTE
927#define move_pte(pte, prot, old_addr, new_addr) (pte)
928#endif
929
930#ifndef pte_accessible
931# define pte_accessible(mm, pte) ((void)(pte), 1)
932#endif
933
934#ifndef flush_tlb_fix_spurious_fault
935#define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address)
936#endif
937
938/*
939 * When walking page tables, get the address of the next boundary,
940 * or the end address of the range if that comes earlier. Although no
941 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
942 */
943
944#define pgd_addr_end(addr, end) \
945({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
946 (__boundary - 1 < (end) - 1)? __boundary: (end); \
947})
948
949#ifndef p4d_addr_end
950#define p4d_addr_end(addr, end) \
951({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \
952 (__boundary - 1 < (end) - 1)? __boundary: (end); \
953})
954#endif
955
956#ifndef pud_addr_end
957#define pud_addr_end(addr, end) \
958({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
959 (__boundary - 1 < (end) - 1)? __boundary: (end); \
960})
961#endif
962
963#ifndef pmd_addr_end
964#define pmd_addr_end(addr, end) \
965({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
966 (__boundary - 1 < (end) - 1)? __boundary: (end); \
967})
968#endif
969
970/*
971 * When walking page tables, we usually want to skip any p?d_none entries;
972 * and any p?d_bad entries - reporting the error before resetting to none.
973 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
974 */
975void pgd_clear_bad(pgd_t *);
976
977#ifndef __PAGETABLE_P4D_FOLDED
978void p4d_clear_bad(p4d_t *);
979#else
980#define p4d_clear_bad(p4d) do { } while (0)
981#endif
982
983#ifndef __PAGETABLE_PUD_FOLDED
984void pud_clear_bad(pud_t *);
985#else
986#define pud_clear_bad(p4d) do { } while (0)
987#endif
988
989void pmd_clear_bad(pmd_t *);
990
991static inline int pgd_none_or_clear_bad(pgd_t *pgd)
992{
993 if (pgd_none(pgd: *pgd))
994 return 1;
995 if (unlikely(pgd_bad(*pgd))) {
996 pgd_clear_bad(pgd);
997 return 1;
998 }
999 return 0;
1000}
1001
1002static inline int p4d_none_or_clear_bad(p4d_t *p4d)
1003{
1004 if (p4d_none(p4d: *p4d))
1005 return 1;
1006 if (unlikely(p4d_bad(*p4d))) {
1007 p4d_clear_bad(p4d);
1008 return 1;
1009 }
1010 return 0;
1011}
1012
1013static inline int pud_none_or_clear_bad(pud_t *pud)
1014{
1015 if (pud_none(pud: *pud))
1016 return 1;
1017 if (unlikely(pud_bad(*pud))) {
1018 pud_clear_bad(pud);
1019 return 1;
1020 }
1021 return 0;
1022}
1023
1024static inline int pmd_none_or_clear_bad(pmd_t *pmd)
1025{
1026 if (pmd_none(pmd: *pmd))
1027 return 1;
1028 if (unlikely(pmd_bad(*pmd))) {
1029 pmd_clear_bad(pmd);
1030 return 1;
1031 }
1032 return 0;
1033}
1034
1035static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma,
1036 unsigned long addr,
1037 pte_t *ptep)
1038{
1039 /*
1040 * Get the current pte state, but zero it out to make it
1041 * non-present, preventing the hardware from asynchronously
1042 * updating it.
1043 */
1044 return ptep_get_and_clear(mm: vma->vm_mm, addr, ptep);
1045}
1046
1047static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma,
1048 unsigned long addr,
1049 pte_t *ptep, pte_t pte)
1050{
1051 /*
1052 * The pte is non-present, so there's no hardware state to
1053 * preserve.
1054 */
1055 set_pte_at(vma->vm_mm, addr, ptep, pte);
1056}
1057
1058#ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1059/*
1060 * Start a pte protection read-modify-write transaction, which
1061 * protects against asynchronous hardware modifications to the pte.
1062 * The intention is not to prevent the hardware from making pte
1063 * updates, but to prevent any updates it may make from being lost.
1064 *
1065 * This does not protect against other software modifications of the
1066 * pte; the appropriate pte lock must be held over the transaction.
1067 *
1068 * Note that this interface is intended to be batchable, meaning that
1069 * ptep_modify_prot_commit may not actually update the pte, but merely
1070 * queue the update to be done at some later time. The update must be
1071 * actually committed before the pte lock is released, however.
1072 */
1073static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
1074 unsigned long addr,
1075 pte_t *ptep)
1076{
1077 return __ptep_modify_prot_start(vma, addr, ptep);
1078}
1079
1080/*
1081 * Commit an update to a pte, leaving any hardware-controlled bits in
1082 * the PTE unmodified.
1083 */
1084static inline void ptep_modify_prot_commit(struct vm_area_struct *vma,
1085 unsigned long addr,
1086 pte_t *ptep, pte_t old_pte, pte_t pte)
1087{
1088 __ptep_modify_prot_commit(vma, addr, ptep, pte);
1089}
1090#endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
1091#endif /* CONFIG_MMU */
1092
1093/*
1094 * No-op macros that just return the current protection value. Defined here
1095 * because these macros can be used even if CONFIG_MMU is not defined.
1096 */
1097
1098#ifndef pgprot_nx
1099#define pgprot_nx(prot) (prot)
1100#endif
1101
1102#ifndef pgprot_noncached
1103#define pgprot_noncached(prot) (prot)
1104#endif
1105
1106#ifndef pgprot_writecombine
1107#define pgprot_writecombine pgprot_noncached
1108#endif
1109
1110#ifndef pgprot_writethrough
1111#define pgprot_writethrough pgprot_noncached
1112#endif
1113
1114#ifndef pgprot_device
1115#define pgprot_device pgprot_noncached
1116#endif
1117
1118#ifndef pgprot_mhp
1119#define pgprot_mhp(prot) (prot)
1120#endif
1121
1122#ifdef CONFIG_MMU
1123#ifndef pgprot_modify
1124#define pgprot_modify pgprot_modify
1125static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
1126{
1127 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
1128 newprot = pgprot_noncached(newprot);
1129 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
1130 newprot = pgprot_writecombine(newprot);
1131 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
1132 newprot = pgprot_device(newprot);
1133 return newprot;
1134}
1135#endif
1136#endif /* CONFIG_MMU */
1137
1138#ifndef pgprot_encrypted
1139#define pgprot_encrypted(prot) (prot)
1140#endif
1141
1142#ifndef pgprot_decrypted
1143#define pgprot_decrypted(prot) (prot)
1144#endif
1145
1146/*
1147 * A facility to provide batching of the reload of page tables and
1148 * other process state with the actual context switch code for
1149 * paravirtualized guests. By convention, only one of the batched
1150 * update (lazy) modes (CPU, MMU) should be active at any given time,
1151 * entry should never be nested, and entry and exits should always be
1152 * paired. This is for sanity of maintaining and reasoning about the
1153 * kernel code. In this case, the exit (end of the context switch) is
1154 * in architecture-specific code, and so doesn't need a generic
1155 * definition.
1156 */
1157#ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
1158#define arch_start_context_switch(prev) do {} while (0)
1159#endif
1160
1161#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1162#ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION
1163static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1164{
1165 return pmd;
1166}
1167
1168static inline int pmd_swp_soft_dirty(pmd_t pmd)
1169{
1170 return 0;
1171}
1172
1173static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1174{
1175 return pmd;
1176}
1177#endif
1178#else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */
1179static inline int pte_soft_dirty(pte_t pte)
1180{
1181 return 0;
1182}
1183
1184static inline int pmd_soft_dirty(pmd_t pmd)
1185{
1186 return 0;
1187}
1188
1189static inline pte_t pte_mksoft_dirty(pte_t pte)
1190{
1191 return pte;
1192}
1193
1194static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
1195{
1196 return pmd;
1197}
1198
1199static inline pte_t pte_clear_soft_dirty(pte_t pte)
1200{
1201 return pte;
1202}
1203
1204static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
1205{
1206 return pmd;
1207}
1208
1209static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
1210{
1211 return pte;
1212}
1213
1214static inline int pte_swp_soft_dirty(pte_t pte)
1215{
1216 return 0;
1217}
1218
1219static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
1220{
1221 return pte;
1222}
1223
1224static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1225{
1226 return pmd;
1227}
1228
1229static inline int pmd_swp_soft_dirty(pmd_t pmd)
1230{
1231 return 0;
1232}
1233
1234static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1235{
1236 return pmd;
1237}
1238#endif
1239
1240#ifndef __HAVE_PFNMAP_TRACKING
1241/*
1242 * Interfaces that can be used by architecture code to keep track of
1243 * memory type of pfn mappings specified by the remap_pfn_range,
1244 * vmf_insert_pfn.
1245 */
1246
1247/*
1248 * track_pfn_remap is called when a _new_ pfn mapping is being established
1249 * by remap_pfn_range() for physical range indicated by pfn and size.
1250 */
1251static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1252 unsigned long pfn, unsigned long addr,
1253 unsigned long size)
1254{
1255 return 0;
1256}
1257
1258/*
1259 * track_pfn_insert is called when a _new_ single pfn is established
1260 * by vmf_insert_pfn().
1261 */
1262static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
1263 pfn_t pfn)
1264{
1265}
1266
1267/*
1268 * track_pfn_copy is called when vma that is covering the pfnmap gets
1269 * copied through copy_page_range().
1270 */
1271static inline int track_pfn_copy(struct vm_area_struct *vma)
1272{
1273 return 0;
1274}
1275
1276/*
1277 * untrack_pfn is called while unmapping a pfnmap for a region.
1278 * untrack can be called for a specific region indicated by pfn and size or
1279 * can be for the entire vma (in which case pfn, size are zero).
1280 */
1281static inline void untrack_pfn(struct vm_area_struct *vma,
1282 unsigned long pfn, unsigned long size,
1283 bool mm_wr_locked)
1284{
1285}
1286
1287/*
1288 * untrack_pfn_clear is called while mremapping a pfnmap for a new region
1289 * or fails to copy pgtable during duplicate vm area.
1290 */
1291static inline void untrack_pfn_clear(struct vm_area_struct *vma)
1292{
1293}
1294#else
1295extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1296 unsigned long pfn, unsigned long addr,
1297 unsigned long size);
1298extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
1299 pfn_t pfn);
1300extern int track_pfn_copy(struct vm_area_struct *vma);
1301extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
1302 unsigned long size, bool mm_wr_locked);
1303extern void untrack_pfn_clear(struct vm_area_struct *vma);
1304#endif
1305
1306#ifdef CONFIG_MMU
1307#ifdef __HAVE_COLOR_ZERO_PAGE
1308static inline int is_zero_pfn(unsigned long pfn)
1309{
1310 extern unsigned long zero_pfn;
1311 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
1312 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
1313}
1314
1315#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
1316
1317#else
1318static inline int is_zero_pfn(unsigned long pfn)
1319{
1320 extern unsigned long zero_pfn;
1321 return pfn == zero_pfn;
1322}
1323
1324static inline unsigned long my_zero_pfn(unsigned long addr)
1325{
1326 extern unsigned long zero_pfn;
1327 return zero_pfn;
1328}
1329#endif
1330#else
1331static inline int is_zero_pfn(unsigned long pfn)
1332{
1333 return 0;
1334}
1335
1336static inline unsigned long my_zero_pfn(unsigned long addr)
1337{
1338 return 0;
1339}
1340#endif /* CONFIG_MMU */
1341
1342#ifdef CONFIG_MMU
1343
1344#ifndef CONFIG_TRANSPARENT_HUGEPAGE
1345static inline int pmd_trans_huge(pmd_t pmd)
1346{
1347 return 0;
1348}
1349#ifndef pmd_write
1350static inline int pmd_write(pmd_t pmd)
1351{
1352 BUG();
1353 return 0;
1354}
1355#endif /* pmd_write */
1356#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1357
1358#ifndef pud_write
1359static inline int pud_write(pud_t pud)
1360{
1361 BUG();
1362 return 0;
1363}
1364#endif /* pud_write */
1365
1366#if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE)
1367static inline int pmd_devmap(pmd_t pmd)
1368{
1369 return 0;
1370}
1371static inline int pud_devmap(pud_t pud)
1372{
1373 return 0;
1374}
1375static inline int pgd_devmap(pgd_t pgd)
1376{
1377 return 0;
1378}
1379#endif
1380
1381#if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
1382 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1383static inline int pud_trans_huge(pud_t pud)
1384{
1385 return 0;
1386}
1387#endif
1388
1389static inline int pud_trans_unstable(pud_t *pud)
1390{
1391#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
1392 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1393 pud_t pudval = READ_ONCE(*pud);
1394
1395 if (pud_none(pud: pudval) || pud_trans_huge(pud: pudval) || pud_devmap(pud: pudval))
1396 return 1;
1397 if (unlikely(pud_bad(pudval))) {
1398 pud_clear_bad(pud);
1399 return 1;
1400 }
1401#endif
1402 return 0;
1403}
1404
1405#ifndef CONFIG_NUMA_BALANCING
1406/*
1407 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is
1408 * perfectly valid to indicate "no" in that case, which is why our default
1409 * implementation defaults to "always no".
1410 *
1411 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE
1412 * page protection due to NUMA hinting. NUMA hinting faults only apply in
1413 * accessible VMAs.
1414 *
1415 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault,
1416 * looking at the VMA accessibility is sufficient.
1417 */
1418static inline int pte_protnone(pte_t pte)
1419{
1420 return 0;
1421}
1422
1423static inline int pmd_protnone(pmd_t pmd)
1424{
1425 return 0;
1426}
1427#endif /* CONFIG_NUMA_BALANCING */
1428
1429#endif /* CONFIG_MMU */
1430
1431#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
1432
1433#ifndef __PAGETABLE_P4D_FOLDED
1434int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot);
1435void p4d_clear_huge(p4d_t *p4d);
1436#else
1437static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1438{
1439 return 0;
1440}
1441static inline void p4d_clear_huge(p4d_t *p4d) { }
1442#endif /* !__PAGETABLE_P4D_FOLDED */
1443
1444int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
1445int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
1446int pud_clear_huge(pud_t *pud);
1447int pmd_clear_huge(pmd_t *pmd);
1448int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
1449int pud_free_pmd_page(pud_t *pud, unsigned long addr);
1450int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
1451#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
1452static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1453{
1454 return 0;
1455}
1456static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1457{
1458 return 0;
1459}
1460static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1461{
1462 return 0;
1463}
1464static inline void p4d_clear_huge(p4d_t *p4d) { }
1465static inline int pud_clear_huge(pud_t *pud)
1466{
1467 return 0;
1468}
1469static inline int pmd_clear_huge(pmd_t *pmd)
1470{
1471 return 0;
1472}
1473static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
1474{
1475 return 0;
1476}
1477static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
1478{
1479 return 0;
1480}
1481static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
1482{
1483 return 0;
1484}
1485#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
1486
1487#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
1488#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1489/*
1490 * ARCHes with special requirements for evicting THP backing TLB entries can
1491 * implement this. Otherwise also, it can help optimize normal TLB flush in
1492 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the
1493 * entire TLB if flush span is greater than a threshold, which will
1494 * likely be true for a single huge page. Thus a single THP flush will
1495 * invalidate the entire TLB which is not desirable.
1496 * e.g. see arch/arc: flush_pmd_tlb_range
1497 */
1498#define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
1499#define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
1500#else
1501#define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
1502#define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
1503#endif
1504#endif
1505
1506struct file;
1507int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
1508 unsigned long size, pgprot_t *vma_prot);
1509
1510#ifndef CONFIG_X86_ESPFIX64
1511static inline void init_espfix_bsp(void) { }
1512#endif
1513
1514extern void __init pgtable_cache_init(void);
1515
1516#ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED
1517static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot)
1518{
1519 return true;
1520}
1521
1522static inline bool arch_has_pfn_modify_check(void)
1523{
1524 return false;
1525}
1526#endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */
1527
1528/*
1529 * Architecture PAGE_KERNEL_* fallbacks
1530 *
1531 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either
1532 * because they really don't support them, or the port needs to be updated to
1533 * reflect the required functionality. Below are a set of relatively safe
1534 * fallbacks, as best effort, which we can count on in lieu of the architectures
1535 * not defining them on their own yet.
1536 */
1537
1538#ifndef PAGE_KERNEL_RO
1539# define PAGE_KERNEL_RO PAGE_KERNEL
1540#endif
1541
1542#ifndef PAGE_KERNEL_EXEC
1543# define PAGE_KERNEL_EXEC PAGE_KERNEL
1544#endif
1545
1546/*
1547 * Page Table Modification bits for pgtbl_mod_mask.
1548 *
1549 * These are used by the p?d_alloc_track*() set of functions an in the generic
1550 * vmalloc/ioremap code to track at which page-table levels entries have been
1551 * modified. Based on that the code can better decide when vmalloc and ioremap
1552 * mapping changes need to be synchronized to other page-tables in the system.
1553 */
1554#define __PGTBL_PGD_MODIFIED 0
1555#define __PGTBL_P4D_MODIFIED 1
1556#define __PGTBL_PUD_MODIFIED 2
1557#define __PGTBL_PMD_MODIFIED 3
1558#define __PGTBL_PTE_MODIFIED 4
1559
1560#define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED)
1561#define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED)
1562#define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED)
1563#define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED)
1564#define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED)
1565
1566/* Page-Table Modification Mask */
1567typedef unsigned int pgtbl_mod_mask;
1568
1569#endif /* !__ASSEMBLY__ */
1570
1571#if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
1572#ifdef CONFIG_PHYS_ADDR_T_64BIT
1573/*
1574 * ZSMALLOC needs to know the highest PFN on 32-bit architectures
1575 * with physical address space extension, but falls back to
1576 * BITS_PER_LONG otherwise.
1577 */
1578#error Missing MAX_POSSIBLE_PHYSMEM_BITS definition
1579#else
1580#define MAX_POSSIBLE_PHYSMEM_BITS 32
1581#endif
1582#endif
1583
1584#ifndef has_transparent_hugepage
1585#define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE)
1586#endif
1587
1588#ifndef has_transparent_pud_hugepage
1589#define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1590#endif
1591/*
1592 * On some architectures it depends on the mm if the p4d/pud or pmd
1593 * layer of the page table hierarchy is folded or not.
1594 */
1595#ifndef mm_p4d_folded
1596#define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
1597#endif
1598
1599#ifndef mm_pud_folded
1600#define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
1601#endif
1602
1603#ifndef mm_pmd_folded
1604#define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
1605#endif
1606
1607#ifndef p4d_offset_lockless
1608#define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address)
1609#endif
1610#ifndef pud_offset_lockless
1611#define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address)
1612#endif
1613#ifndef pmd_offset_lockless
1614#define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address)
1615#endif
1616
1617/*
1618 * p?d_leaf() - true if this entry is a final mapping to a physical address.
1619 * This differs from p?d_huge() by the fact that they are always available (if
1620 * the architecture supports large pages at the appropriate level) even
1621 * if CONFIG_HUGETLB_PAGE is not defined.
1622 * Only meaningful when called on a valid entry.
1623 */
1624#ifndef pgd_leaf
1625#define pgd_leaf(x) 0
1626#endif
1627#ifndef p4d_leaf
1628#define p4d_leaf(x) 0
1629#endif
1630#ifndef pud_leaf
1631#define pud_leaf(x) 0
1632#endif
1633#ifndef pmd_leaf
1634#define pmd_leaf(x) 0
1635#endif
1636
1637#ifndef pgd_leaf_size
1638#define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT)
1639#endif
1640#ifndef p4d_leaf_size
1641#define p4d_leaf_size(x) P4D_SIZE
1642#endif
1643#ifndef pud_leaf_size
1644#define pud_leaf_size(x) PUD_SIZE
1645#endif
1646#ifndef pmd_leaf_size
1647#define pmd_leaf_size(x) PMD_SIZE
1648#endif
1649#ifndef pte_leaf_size
1650#define pte_leaf_size(x) PAGE_SIZE
1651#endif
1652
1653/*
1654 * Some architectures have MMUs that are configurable or selectable at boot
1655 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it
1656 * helps to have a static maximum value.
1657 */
1658
1659#ifndef MAX_PTRS_PER_PTE
1660#define MAX_PTRS_PER_PTE PTRS_PER_PTE
1661#endif
1662
1663#ifndef MAX_PTRS_PER_PMD
1664#define MAX_PTRS_PER_PMD PTRS_PER_PMD
1665#endif
1666
1667#ifndef MAX_PTRS_PER_PUD
1668#define MAX_PTRS_PER_PUD PTRS_PER_PUD
1669#endif
1670
1671#ifndef MAX_PTRS_PER_P4D
1672#define MAX_PTRS_PER_P4D PTRS_PER_P4D
1673#endif
1674
1675/* description of effects of mapping type and prot in current implementation.
1676 * this is due to the limited x86 page protection hardware. The expected
1677 * behavior is in parens:
1678 *
1679 * map_type prot
1680 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC
1681 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes
1682 * w: (no) no w: (no) no w: (yes) yes w: (no) no
1683 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
1684 *
1685 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes
1686 * w: (no) no w: (no) no w: (copy) copy w: (no) no
1687 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
1688 *
1689 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and
1690 * MAP_PRIVATE (with Enhanced PAN supported):
1691 * r: (no) no
1692 * w: (no) no
1693 * x: (yes) yes
1694 */
1695#define DECLARE_VM_GET_PAGE_PROT \
1696pgprot_t vm_get_page_prot(unsigned long vm_flags) \
1697{ \
1698 return protection_map[vm_flags & \
1699 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \
1700} \
1701EXPORT_SYMBOL(vm_get_page_prot);
1702
1703#endif /* _LINUX_PGTABLE_H */
1704

source code of linux/include/linux/pgtable.h