1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* linux/include/linux/scx200.h |
3 | |
4 | Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com> |
5 | |
6 | Defines for the National Semiconductor SCx200 Processors |
7 | */ |
8 | |
9 | /* Interesting stuff for the National Semiconductor SCx200 CPU */ |
10 | |
11 | extern unsigned scx200_cb_base; |
12 | |
13 | #define scx200_cb_present() (scx200_cb_base!=0) |
14 | |
15 | /* F0 PCI Header/Bridge Configuration Registers */ |
16 | #define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */ |
17 | #define SCx200_DOCCS_CTRL 0x7c /* DOCCS Control Register */ |
18 | |
19 | /* GPIO Register Block */ |
20 | #define SCx200_GPIO_SIZE 0x2c /* Size of GPIO register block */ |
21 | |
22 | /* General Configuration Block */ |
23 | #define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */ |
24 | |
25 | /* Watchdog Timer */ |
26 | #define SCx200_WDT_OFFSET 0x00 /* offset within configuration block */ |
27 | #define SCx200_WDT_SIZE 0x05 /* size */ |
28 | |
29 | #define SCx200_WDT_WDTO 0x00 /* Time-Out Register */ |
30 | #define SCx200_WDT_WDCNFG 0x02 /* Configuration Register */ |
31 | #define SCx200_WDT_WDSTS 0x04 /* Status Register */ |
32 | #define SCx200_WDT_WDSTS_WDOVF (1<<0) /* Overflow bit */ |
33 | |
34 | /* High Resolution Timer */ |
35 | #define SCx200_TIMER_OFFSET 0x08 |
36 | #define SCx200_TIMER_SIZE 0x06 |
37 | |
38 | /* Clock Generators */ |
39 | #define SCx200_CLOCKGEN_OFFSET 0x10 |
40 | #define SCx200_CLOCKGEN_SIZE 0x10 |
41 | |
42 | /* Pin Multiplexing and Miscellaneous Configuration Registers */ |
43 | #define SCx200_MISC_OFFSET 0x30 |
44 | #define SCx200_MISC_SIZE 0x10 |
45 | |
46 | #define SCx200_PMR 0x30 /* Pin Multiplexing Register */ |
47 | #define SCx200_MCR 0x34 /* Miscellaneous Configuration Register */ |
48 | #define SCx200_INTSEL 0x38 /* Interrupt Selection Register */ |
49 | #define SCx200_IID 0x3c /* IA On a Chip Identification Number Reg */ |
50 | #define SCx200_REV 0x3d /* Revision Register */ |
51 | #define SCx200_CBA 0x3e /* Configuration Base Address Register */ |
52 | #define SCx200_CBA_SCRATCH 0x64 /* Configuration Base Address Scratchpad */ |
53 | |