| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Internal header file for Samsung S3C2410 serial ports (UART0-2) |
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| 4 | * |
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| 5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
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| 6 | * |
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| 7 | * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk) |
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| 8 | * |
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| 9 | * Adapted from: |
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| 10 | * |
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| 11 | * Internal header file for MX1ADS serial ports (UART1 & 2) |
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| 12 | * |
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| 13 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __ASM_ARM_REGS_SERIAL_H |
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| 17 | #define __ASM_ARM_REGS_SERIAL_H |
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| 18 | |
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| 19 | #define S3C2410_URXH (0x24) |
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| 20 | #define S3C2410_UTXH (0x20) |
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| 21 | #define S3C2410_ULCON (0x00) |
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| 22 | #define S3C2410_UCON (0x04) |
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| 23 | #define S3C2410_UFCON (0x08) |
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| 24 | #define S3C2410_UMCON (0x0C) |
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| 25 | #define S3C2410_UBRDIV (0x28) |
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| 26 | #define S3C2410_UTRSTAT (0x10) |
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| 27 | #define S3C2410_UERSTAT (0x14) |
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| 28 | #define S3C2410_UFSTAT (0x18) |
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| 29 | #define S3C2410_UMSTAT (0x1C) |
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| 30 | |
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| 31 | #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) |
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| 32 | |
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| 33 | #define S3C2410_LCON_CS5 (0x0) |
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| 34 | #define S3C2410_LCON_CS6 (0x1) |
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| 35 | #define S3C2410_LCON_CS7 (0x2) |
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| 36 | #define S3C2410_LCON_CS8 (0x3) |
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| 37 | #define S3C2410_LCON_CSMASK (0x3) |
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| 38 | |
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| 39 | #define S3C2410_LCON_PNONE (0x0) |
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| 40 | #define S3C2410_LCON_PEVEN (0x5 << 3) |
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| 41 | #define S3C2410_LCON_PODD (0x4 << 3) |
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| 42 | #define S3C2410_LCON_PMASK (0x7 << 3) |
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| 43 | |
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| 44 | #define S3C2410_LCON_STOPB (1<<2) |
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| 45 | #define S3C2410_LCON_IRM (1<<6) |
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| 46 | |
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| 47 | #define S3C2440_UCON_CLKMASK (3<<10) |
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| 48 | #define S3C2440_UCON_CLKSHIFT (10) |
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| 49 | #define S3C2440_UCON_PCLK (0<<10) |
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| 50 | #define S3C2440_UCON_UCLK (1<<10) |
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| 51 | #define S3C2440_UCON_PCLK2 (2<<10) |
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| 52 | #define S3C2440_UCON_FCLK (3<<10) |
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| 53 | #define S3C2443_UCON_EPLL (3<<10) |
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| 54 | |
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| 55 | #define S3C6400_UCON_CLKMASK (3<<10) |
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| 56 | #define S3C6400_UCON_CLKSHIFT (10) |
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| 57 | #define S3C6400_UCON_PCLK (0<<10) |
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| 58 | #define S3C6400_UCON_PCLK2 (2<<10) |
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| 59 | #define S3C6400_UCON_UCLK0 (1<<10) |
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| 60 | #define S3C6400_UCON_UCLK1 (3<<10) |
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| 61 | |
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| 62 | #define S3C2440_UCON2_FCLK_EN (1<<15) |
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| 63 | #define S3C2440_UCON0_DIVMASK (15 << 12) |
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| 64 | #define S3C2440_UCON1_DIVMASK (15 << 12) |
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| 65 | #define S3C2440_UCON2_DIVMASK (7 << 12) |
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| 66 | #define S3C2440_UCON_DIVSHIFT (12) |
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| 67 | |
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| 68 | #define S3C2412_UCON_CLKMASK (3<<10) |
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| 69 | #define S3C2412_UCON_CLKSHIFT (10) |
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| 70 | #define S3C2412_UCON_UCLK (1<<10) |
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| 71 | #define S3C2412_UCON_USYSCLK (3<<10) |
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| 72 | #define S3C2412_UCON_PCLK (0<<10) |
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| 73 | #define S3C2412_UCON_PCLK2 (2<<10) |
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| 74 | |
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| 75 | #define S3C2410_UCON_CLKMASK (1 << 10) |
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| 76 | #define S3C2410_UCON_CLKSHIFT (10) |
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| 77 | #define S3C2410_UCON_UCLK (1<<10) |
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| 78 | #define S3C2410_UCON_SBREAK (1<<4) |
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| 79 | |
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| 80 | #define S3C2410_UCON_TXILEVEL (1<<9) |
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| 81 | #define S3C2410_UCON_RXILEVEL (1<<8) |
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| 82 | #define S3C2410_UCON_TXIRQMODE (1<<2) |
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| 83 | #define S3C2410_UCON_RXIRQMODE (1<<0) |
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| 84 | #define S3C2410_UCON_RXFIFO_TOI (1<<7) |
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| 85 | #define S3C2443_UCON_RXERR_IRQEN (1<<6) |
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| 86 | #define S3C2410_UCON_LOOPBACK (1<<5) |
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| 87 | |
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| 88 | #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
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| 89 | S3C2410_UCON_RXILEVEL | \ |
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| 90 | S3C2410_UCON_TXIRQMODE | \ |
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| 91 | S3C2410_UCON_RXIRQMODE | \ |
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| 92 | S3C2410_UCON_RXFIFO_TOI) |
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| 93 | |
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| 94 | #define S3C64XX_UCON_TXBURST_1 (0<<20) |
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| 95 | #define S3C64XX_UCON_TXBURST_4 (1<<20) |
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| 96 | #define S3C64XX_UCON_TXBURST_8 (2<<20) |
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| 97 | #define S3C64XX_UCON_TXBURST_16 (3<<20) |
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| 98 | #define S3C64XX_UCON_TXBURST_MASK (0xf<<20) |
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| 99 | #define S3C64XX_UCON_RXBURST_1 (0<<16) |
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| 100 | #define S3C64XX_UCON_RXBURST_4 (1<<16) |
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| 101 | #define S3C64XX_UCON_RXBURST_8 (2<<16) |
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| 102 | #define S3C64XX_UCON_RXBURST_16 (3<<16) |
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| 103 | #define S3C64XX_UCON_RXBURST_MASK (0xf<<16) |
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| 104 | #define S3C64XX_UCON_TIMEOUT_SHIFT (12) |
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| 105 | #define S3C64XX_UCON_TIMEOUT_MASK (0xf<<12) |
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| 106 | #define S3C64XX_UCON_EMPTYINT_EN (1<<11) |
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| 107 | #define S3C64XX_UCON_DMASUS_EN (1<<10) |
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| 108 | #define S3C64XX_UCON_TXINT_LEVEL (1<<9) |
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| 109 | #define S3C64XX_UCON_RXINT_LEVEL (1<<8) |
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| 110 | #define S3C64XX_UCON_TIMEOUT_EN (1<<7) |
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| 111 | #define S3C64XX_UCON_ERRINT_EN (1<<6) |
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| 112 | #define S3C64XX_UCON_TXMODE_DMA (2<<2) |
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| 113 | #define S3C64XX_UCON_TXMODE_CPU (1<<2) |
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| 114 | #define S3C64XX_UCON_TXMODE_MASK (3<<2) |
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| 115 | #define S3C64XX_UCON_RXMODE_DMA (2<<0) |
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| 116 | #define S3C64XX_UCON_RXMODE_CPU (1<<0) |
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| 117 | #define S3C64XX_UCON_RXMODE_MASK (3<<0) |
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| 118 | |
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| 119 | #define S3C2410_UFCON_FIFOMODE (1<<0) |
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| 120 | #define S3C2410_UFCON_TXTRIG0 (0<<6) |
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| 121 | #define S3C2410_UFCON_RXTRIG8 (1<<4) |
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| 122 | #define S3C2410_UFCON_RXTRIG12 (2<<4) |
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| 123 | |
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| 124 | /* S3C2440 FIFO trigger levels */ |
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| 125 | #define S3C2440_UFCON_RXTRIG1 (0<<4) |
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| 126 | #define S3C2440_UFCON_RXTRIG8 (1<<4) |
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| 127 | #define S3C2440_UFCON_RXTRIG16 (2<<4) |
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| 128 | #define S3C2440_UFCON_RXTRIG32 (3<<4) |
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| 129 | |
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| 130 | #define S3C2440_UFCON_TXTRIG0 (0<<6) |
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| 131 | #define S3C2440_UFCON_TXTRIG16 (1<<6) |
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| 132 | #define S3C2440_UFCON_TXTRIG32 (2<<6) |
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| 133 | #define S3C2440_UFCON_TXTRIG48 (3<<6) |
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| 134 | |
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| 135 | #define S3C2410_UFCON_RESETBOTH (3<<1) |
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| 136 | #define S3C2410_UFCON_RESETTX (1<<2) |
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| 137 | #define S3C2410_UFCON_RESETRX (1<<1) |
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| 138 | |
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| 139 | #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
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| 140 | S3C2410_UFCON_TXTRIG0 | \ |
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| 141 | S3C2410_UFCON_RXTRIG8 ) |
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| 142 | |
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| 143 | #define S3C2410_UMCOM_AFC (1<<4) |
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| 144 | #define S3C2410_UMCOM_RTS_LOW (1<<0) |
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| 145 | |
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| 146 | #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ |
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| 147 | #define S3C2412_UMCON_AFC_56 (1<<5) |
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| 148 | #define S3C2412_UMCON_AFC_48 (2<<5) |
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| 149 | #define S3C2412_UMCON_AFC_40 (3<<5) |
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| 150 | #define S3C2412_UMCON_AFC_32 (4<<5) |
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| 151 | #define S3C2412_UMCON_AFC_24 (5<<5) |
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| 152 | #define S3C2412_UMCON_AFC_16 (6<<5) |
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| 153 | #define S3C2412_UMCON_AFC_8 (7<<5) |
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| 154 | |
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| 155 | #define S3C2410_UFSTAT_TXFULL (1<<9) |
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| 156 | #define S3C2410_UFSTAT_RXFULL (1<<8) |
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| 157 | #define S3C2410_UFSTAT_TXMASK (15<<4) |
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| 158 | #define S3C2410_UFSTAT_TXSHIFT (4) |
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| 159 | #define S3C2410_UFSTAT_RXMASK (15<<0) |
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| 160 | #define S3C2410_UFSTAT_RXSHIFT (0) |
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| 161 | |
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| 162 | /* UFSTAT S3C2443 same as S3C2440 */ |
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| 163 | #define S3C2440_UFSTAT_TXFULL (1<<14) |
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| 164 | #define S3C2440_UFSTAT_RXFULL (1<<6) |
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| 165 | #define S3C2440_UFSTAT_TXSHIFT (8) |
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| 166 | #define S3C2440_UFSTAT_RXSHIFT (0) |
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| 167 | #define S3C2440_UFSTAT_TXMASK (63<<8) |
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| 168 | #define S3C2440_UFSTAT_RXMASK (63) |
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| 169 | |
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| 170 | #define S3C2410_UTRSTAT_TIMEOUT (1<<3) |
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| 171 | #define S3C2410_UTRSTAT_TXE (1<<2) |
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| 172 | #define S3C2410_UTRSTAT_TXFE (1<<1) |
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| 173 | #define S3C2410_UTRSTAT_RXDR (1<<0) |
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| 174 | |
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| 175 | #define S3C2410_UERSTAT_OVERRUN (1<<0) |
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| 176 | #define S3C2410_UERSTAT_FRAME (1<<2) |
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| 177 | #define S3C2410_UERSTAT_BREAK (1<<3) |
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| 178 | #define S3C2443_UERSTAT_PARITY (1<<1) |
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| 179 | |
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| 180 | #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ |
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| 181 | S3C2410_UERSTAT_FRAME | \ |
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| 182 | S3C2410_UERSTAT_BREAK) |
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| 183 | |
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| 184 | #define S3C2410_UMSTAT_CTS (1<<0) |
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| 185 | #define S3C2410_UMSTAT_DeltaCTS (1<<2) |
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| 186 | |
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| 187 | #define S3C2443_DIVSLOT (0x2C) |
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| 188 | |
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| 189 | /* S3C64XX interrupt registers. */ |
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| 190 | #define S3C64XX_UINTP 0x30 |
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| 191 | #define S3C64XX_UINTSP 0x34 |
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| 192 | #define S3C64XX_UINTM 0x38 |
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| 193 | |
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| 194 | #define S3C64XX_UINTM_RXD (0) |
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| 195 | #define S3C64XX_UINTM_ERROR (1) |
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| 196 | #define S3C64XX_UINTM_TXD (2) |
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| 197 | #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD) |
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| 198 | #define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_UINTM_ERROR) |
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| 199 | #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD) |
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| 200 | |
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| 201 | /* Following are specific to S5PV210 */ |
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| 202 | #define S5PV210_UCON_CLKMASK (1<<10) |
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| 203 | #define S5PV210_UCON_CLKSHIFT (10) |
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| 204 | #define S5PV210_UCON_PCLK (0<<10) |
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| 205 | #define S5PV210_UCON_UCLK (1<<10) |
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| 206 | |
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| 207 | #define S5PV210_UFCON_TXTRIG0 (0<<8) |
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| 208 | #define S5PV210_UFCON_TXTRIG4 (1<<8) |
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| 209 | #define S5PV210_UFCON_TXTRIG8 (2<<8) |
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| 210 | #define S5PV210_UFCON_TXTRIG16 (3<<8) |
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| 211 | #define S5PV210_UFCON_TXTRIG32 (4<<8) |
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| 212 | #define S5PV210_UFCON_TXTRIG64 (5<<8) |
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| 213 | #define S5PV210_UFCON_TXTRIG128 (6<<8) |
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| 214 | #define S5PV210_UFCON_TXTRIG256 (7<<8) |
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| 215 | |
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| 216 | #define S5PV210_UFCON_RXTRIG1 (0<<4) |
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| 217 | #define S5PV210_UFCON_RXTRIG4 (1<<4) |
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| 218 | #define S5PV210_UFCON_RXTRIG8 (2<<4) |
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| 219 | #define S5PV210_UFCON_RXTRIG16 (3<<4) |
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| 220 | #define S5PV210_UFCON_RXTRIG32 (4<<4) |
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| 221 | #define S5PV210_UFCON_RXTRIG64 (5<<4) |
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| 222 | #define S5PV210_UFCON_RXTRIG128 (6<<4) |
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| 223 | #define S5PV210_UFCON_RXTRIG256 (7<<4) |
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| 224 | |
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| 225 | #define S5PV210_UFSTAT_TXFULL (1<<24) |
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| 226 | #define S5PV210_UFSTAT_RXFULL (1<<8) |
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| 227 | #define S5PV210_UFSTAT_TXMASK (255<<16) |
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| 228 | #define S5PV210_UFSTAT_TXSHIFT (16) |
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| 229 | #define S5PV210_UFSTAT_RXMASK (255<<0) |
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| 230 | #define S5PV210_UFSTAT_RXSHIFT (0) |
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| 231 | |
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| 232 | #define S3C2410_UCON_CLKSEL0 (1 << 0) |
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| 233 | #define S3C2410_UCON_CLKSEL1 (1 << 1) |
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| 234 | #define S3C2410_UCON_CLKSEL2 (1 << 2) |
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| 235 | #define S3C2410_UCON_CLKSEL3 (1 << 3) |
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| 236 | |
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| 237 | /* Default values for s5pv210 UCON and UFCON uart registers */ |
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| 238 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
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| 239 | S3C2410_UCON_RXILEVEL | \ |
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| 240 | S3C2410_UCON_TXIRQMODE | \ |
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| 241 | S3C2410_UCON_RXIRQMODE | \ |
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| 242 | S3C2410_UCON_RXFIFO_TOI | \ |
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| 243 | S3C2443_UCON_RXERR_IRQEN) |
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| 244 | |
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| 245 | #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
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| 246 | S5PV210_UFCON_TXTRIG4 | \ |
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| 247 | S5PV210_UFCON_RXTRIG4) |
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| 248 | |
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| 249 | #define APPLE_S5L_UCON_RXTO_ENA 9 |
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| 250 | #define APPLE_S5L_UCON_RXTHRESH_ENA 12 |
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| 251 | #define APPLE_S5L_UCON_TXTHRESH_ENA 13 |
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| 252 | #define APPLE_S5L_UCON_RXTO_ENA_MSK (1 << APPLE_S5L_UCON_RXTO_ENA) |
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| 253 | #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_RXTHRESH_ENA) |
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| 254 | #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_TXTHRESH_ENA) |
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| 255 | |
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| 256 | #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ |
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| 257 | S3C2410_UCON_RXIRQMODE | \ |
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| 258 | S3C2410_UCON_RXFIFO_TOI) |
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| 259 | #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ |
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| 260 | APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ |
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| 261 | APPLE_S5L_UCON_TXTHRESH_ENA_MSK) |
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| 262 | |
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| 263 | #define APPLE_S5L_UTRSTAT_RXTHRESH (1<<4) |
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| 264 | #define APPLE_S5L_UTRSTAT_TXTHRESH (1<<5) |
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| 265 | #define APPLE_S5L_UTRSTAT_RXTO (1<<9) |
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| 266 | #define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) |
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| 267 | |
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| 268 | #ifndef __ASSEMBLY__ |
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| 269 | |
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| 270 | #include <linux/serial_core.h> |
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| 271 | |
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| 272 | /* configuration structure for per-machine configurations for the |
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| 273 | * serial port |
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| 274 | * |
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| 275 | * the pointer is setup by the machine specific initialisation from the |
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| 276 | * arch/arm/mach-s3c/ directory. |
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| 277 | */ |
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| 278 | |
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| 279 | struct s3c2410_uartcfg { |
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| 280 | unsigned char hwport; /* hardware port number */ |
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| 281 | unsigned char unused; |
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| 282 | unsigned short flags; |
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| 283 | upf_t uart_flags; /* default uart flags */ |
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| 284 | unsigned int clk_sel; |
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| 285 | |
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| 286 | unsigned int has_fracval; |
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| 287 | |
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| 288 | unsigned long ucon; /* value of ucon for port */ |
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| 289 | unsigned long ulcon; /* value of ulcon for port */ |
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| 290 | unsigned long ufcon; /* value of ufcon for port */ |
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| 291 | }; |
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| 292 | |
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| 293 | #endif /* __ASSEMBLY__ */ |
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| 294 | |
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| 295 | #endif /* __ASM_ARM_REGS_SERIAL_H */ |
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| 296 | |
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| 297 | |
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