| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* sm501-regs.h |
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| 3 | * |
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| 4 | * Copyright 2006 Simtec Electronics |
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| 5 | * |
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| 6 | * Silicon Motion SM501 register definitions |
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| 7 | */ |
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| 8 | |
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| 9 | /* System Configuration area */ |
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| 10 | /* System config base */ |
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| 11 | #define SM501_SYS_CONFIG (0x000000) |
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| 12 | |
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| 13 | /* config 1 */ |
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| 14 | #define SM501_SYSTEM_CONTROL (0x000000) |
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| 15 | |
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| 16 | #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) |
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| 17 | #define SM501_SYSCTRL_MEM_TRISTATE (1<<1) |
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| 18 | #define SM501_SYSCTRL_CRT_TRISTATE (1<<2) |
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| 19 | |
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| 20 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) |
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| 21 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) |
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| 22 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) |
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| 23 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) |
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| 24 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) |
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| 25 | |
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| 26 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) |
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| 27 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) |
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| 28 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) |
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| 29 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) |
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| 30 | |
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| 31 | #define SM501_SYSCTRL_2D_ENGINE_STATUS (1<<19) |
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| 32 | |
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| 33 | /* miscellaneous control */ |
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| 34 | |
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| 35 | #define SM501_MISC_CONTROL (0x000004) |
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| 36 | |
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| 37 | #define SM501_MISC_BUS_SH (0x0) |
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| 38 | #define SM501_MISC_BUS_PCI (0x1) |
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| 39 | #define SM501_MISC_BUS_XSCALE (0x2) |
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| 40 | #define SM501_MISC_BUS_NEC (0x6) |
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| 41 | #define SM501_MISC_BUS_MASK (0x7) |
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| 42 | |
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| 43 | #define SM501_MISC_VR_62MB (1<<3) |
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| 44 | #define SM501_MISC_CDR_RESET (1<<7) |
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| 45 | #define SM501_MISC_USB_LB (1<<8) |
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| 46 | #define SM501_MISC_USB_SLAVE (1<<9) |
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| 47 | #define SM501_MISC_BL_1 (1<<10) |
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| 48 | #define SM501_MISC_MC (1<<11) |
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| 49 | #define SM501_MISC_DAC_POWER (1<<12) |
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| 50 | #define SM501_MISC_IRQ_INVERT (1<<16) |
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| 51 | #define SM501_MISC_SH (1<<17) |
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| 52 | |
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| 53 | #define SM501_MISC_HOLD_EMPTY (0<<18) |
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| 54 | #define SM501_MISC_HOLD_8 (1<<18) |
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| 55 | #define SM501_MISC_HOLD_16 (2<<18) |
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| 56 | #define SM501_MISC_HOLD_24 (3<<18) |
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| 57 | #define SM501_MISC_HOLD_32 (4<<18) |
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| 58 | #define SM501_MISC_HOLD_MASK (7<<18) |
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| 59 | |
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| 60 | #define SM501_MISC_FREQ_12 (1<<24) |
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| 61 | #define SM501_MISC_PNL_24BIT (1<<25) |
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| 62 | #define SM501_MISC_8051_LE (1<<26) |
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| 63 | |
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| 64 | |
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| 65 | |
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| 66 | #define SM501_GPIO31_0_CONTROL (0x000008) |
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| 67 | #define SM501_GPIO63_32_CONTROL (0x00000C) |
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| 68 | #define SM501_DRAM_CONTROL (0x000010) |
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| 69 | |
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| 70 | /* command list */ |
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| 71 | #define SM501_ARBTRTN_CONTROL (0x000014) |
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| 72 | |
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| 73 | /* command list */ |
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| 74 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
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| 75 | |
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| 76 | /* interrupt debug */ |
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| 77 | #define SM501_RAW_IRQ_STATUS (0x000028) |
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| 78 | #define SM501_RAW_IRQ_CLEAR (0x000028) |
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| 79 | #define SM501_IRQ_STATUS (0x00002C) |
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| 80 | #define SM501_IRQ_MASK (0x000030) |
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| 81 | #define SM501_DEBUG_CONTROL (0x000034) |
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| 82 | |
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| 83 | /* power management */ |
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| 84 | #define SM501_POWERMODE_P2X_SRC (1<<29) |
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| 85 | #define SM501_POWERMODE_V2X_SRC (1<<20) |
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| 86 | #define SM501_POWERMODE_M_SRC (1<<12) |
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| 87 | #define SM501_POWERMODE_M1_SRC (1<<4) |
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| 88 | |
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| 89 | #define SM501_CURRENT_GATE (0x000038) |
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| 90 | #define SM501_CURRENT_CLOCK (0x00003C) |
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| 91 | #define SM501_POWER_MODE_0_GATE (0x000040) |
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| 92 | #define SM501_POWER_MODE_0_CLOCK (0x000044) |
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| 93 | #define SM501_POWER_MODE_1_GATE (0x000048) |
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| 94 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) |
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| 95 | #define SM501_SLEEP_MODE_GATE (0x000050) |
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| 96 | #define SM501_POWER_MODE_CONTROL (0x000054) |
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| 97 | |
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| 98 | /* power gates for units within the 501 */ |
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| 99 | #define SM501_GATE_HOST (0) |
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| 100 | #define SM501_GATE_MEMORY (1) |
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| 101 | #define SM501_GATE_DISPLAY (2) |
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| 102 | #define SM501_GATE_2D_ENGINE (3) |
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| 103 | #define SM501_GATE_CSC (4) |
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| 104 | #define SM501_GATE_ZVPORT (5) |
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| 105 | #define SM501_GATE_GPIO (6) |
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| 106 | #define SM501_GATE_UART0 (7) |
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| 107 | #define SM501_GATE_UART1 (8) |
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| 108 | #define SM501_GATE_SSP (10) |
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| 109 | #define SM501_GATE_USB_HOST (11) |
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| 110 | #define SM501_GATE_USB_GADGET (12) |
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| 111 | #define SM501_GATE_UCONTROLLER (17) |
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| 112 | #define SM501_GATE_AC97 (18) |
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| 113 | |
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| 114 | /* panel clock */ |
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| 115 | #define SM501_CLOCK_P2XCLK (24) |
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| 116 | /* crt clock */ |
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| 117 | #define SM501_CLOCK_V2XCLK (16) |
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| 118 | /* main clock */ |
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| 119 | #define SM501_CLOCK_MCLK (8) |
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| 120 | /* SDRAM controller clock */ |
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| 121 | #define SM501_CLOCK_M1XCLK (0) |
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| 122 | |
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| 123 | /* config 2 */ |
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| 124 | #define SM501_PCI_MASTER_BASE (0x000058) |
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| 125 | #define SM501_ENDIAN_CONTROL (0x00005C) |
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| 126 | #define SM501_DEVICEID (0x000060) |
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| 127 | /* 0x050100A0 */ |
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| 128 | |
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| 129 | #define SM501_DEVICEID_SM501 (0x05010000) |
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| 130 | #define SM501_DEVICEID_IDMASK (0xffff0000) |
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| 131 | #define SM501_DEVICEID_REVMASK (0x000000ff) |
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| 132 | |
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| 133 | #define SM501_PLLCLOCK_COUNT (0x000064) |
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| 134 | #define SM501_MISC_TIMING (0x000068) |
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| 135 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) |
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| 136 | |
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| 137 | #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
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| 138 | |
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| 139 | /* GPIO base */ |
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| 140 | #define SM501_GPIO (0x010000) |
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| 141 | #define SM501_GPIO_DATA_LOW (0x00) |
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| 142 | #define SM501_GPIO_DATA_HIGH (0x04) |
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| 143 | #define SM501_GPIO_DDR_LOW (0x08) |
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| 144 | #define SM501_GPIO_DDR_HIGH (0x0C) |
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| 145 | #define SM501_GPIO_IRQ_SETUP (0x10) |
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| 146 | #define SM501_GPIO_IRQ_STATUS (0x14) |
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| 147 | #define SM501_GPIO_IRQ_RESET (0x14) |
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| 148 | |
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| 149 | /* I2C controller base */ |
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| 150 | #define SM501_I2C (0x010040) |
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| 151 | #define SM501_I2C_BYTE_COUNT (0x00) |
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| 152 | #define SM501_I2C_CONTROL (0x01) |
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| 153 | #define SM501_I2C_STATUS (0x02) |
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| 154 | #define SM501_I2C_RESET (0x02) |
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| 155 | #define SM501_I2C_SLAVE_ADDRESS (0x03) |
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| 156 | #define SM501_I2C_DATA (0x04) |
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| 157 | |
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| 158 | /* SSP base */ |
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| 159 | #define SM501_SSP (0x020000) |
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| 160 | |
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| 161 | /* Uart 0 base */ |
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| 162 | #define SM501_UART0 (0x030000) |
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| 163 | |
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| 164 | /* Uart 1 base */ |
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| 165 | #define SM501_UART1 (0x030020) |
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| 166 | |
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| 167 | /* USB host port base */ |
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| 168 | #define SM501_USB_HOST (0x040000) |
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| 169 | |
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| 170 | /* USB slave/gadget base */ |
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| 171 | #define SM501_USB_GADGET (0x060000) |
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| 172 | |
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| 173 | /* USB slave/gadget data port base */ |
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| 174 | #define SM501_USB_GADGET_DATA (0x070000) |
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| 175 | |
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| 176 | /* Display controller/video engine base */ |
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| 177 | #define SM501_DC (0x080000) |
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| 178 | |
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| 179 | /* common defines for the SM501 address registers */ |
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| 180 | #define SM501_ADDR_FLIP (1<<31) |
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| 181 | #define SM501_ADDR_EXT (1<<27) |
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| 182 | #define SM501_ADDR_CS1 (1<<26) |
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| 183 | #define SM501_ADDR_MASK (0x3f << 26) |
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| 184 | |
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| 185 | #define SM501_FIFO_MASK (0x3 << 16) |
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| 186 | #define SM501_FIFO_1 (0x0 << 16) |
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| 187 | #define SM501_FIFO_3 (0x1 << 16) |
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| 188 | #define SM501_FIFO_7 (0x2 << 16) |
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| 189 | #define SM501_FIFO_11 (0x3 << 16) |
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| 190 | |
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| 191 | /* common registers for panel and the crt */ |
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| 192 | #define SM501_OFF_DC_H_TOT (0x000) |
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| 193 | #define SM501_OFF_DC_V_TOT (0x008) |
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| 194 | #define SM501_OFF_DC_H_SYNC (0x004) |
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| 195 | #define SM501_OFF_DC_V_SYNC (0x00C) |
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| 196 | |
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| 197 | #define SM501_DC_PANEL_CONTROL (0x000) |
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| 198 | |
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| 199 | #define SM501_DC_PANEL_CONTROL_FPEN (1<<27) |
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| 200 | #define SM501_DC_PANEL_CONTROL_BIAS (1<<26) |
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| 201 | #define SM501_DC_PANEL_CONTROL_DATA (1<<25) |
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| 202 | #define SM501_DC_PANEL_CONTROL_VDD (1<<24) |
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| 203 | #define SM501_DC_PANEL_CONTROL_DP (1<<23) |
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| 204 | |
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| 205 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) |
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| 206 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) |
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| 207 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) |
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| 208 | |
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| 209 | #define SM501_DC_PANEL_CONTROL_DE (1<<20) |
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| 210 | |
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| 211 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) |
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| 212 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) |
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| 213 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) |
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| 214 | |
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| 215 | #define SM501_DC_PANEL_CONTROL_CP (1<<14) |
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| 216 | #define SM501_DC_PANEL_CONTROL_VSP (1<<13) |
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| 217 | #define SM501_DC_PANEL_CONTROL_HSP (1<<12) |
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| 218 | #define SM501_DC_PANEL_CONTROL_CK (1<<9) |
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| 219 | #define SM501_DC_PANEL_CONTROL_TE (1<<8) |
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| 220 | #define SM501_DC_PANEL_CONTROL_VPD (1<<7) |
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| 221 | #define SM501_DC_PANEL_CONTROL_VP (1<<6) |
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| 222 | #define SM501_DC_PANEL_CONTROL_HPD (1<<5) |
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| 223 | #define SM501_DC_PANEL_CONTROL_HP (1<<4) |
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| 224 | #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) |
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| 225 | #define SM501_DC_PANEL_CONTROL_EN (1<<2) |
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| 226 | |
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| 227 | #define SM501_DC_PANEL_CONTROL_8BPP (0<<0) |
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| 228 | #define SM501_DC_PANEL_CONTROL_16BPP (1<<0) |
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| 229 | #define SM501_DC_PANEL_CONTROL_32BPP (2<<0) |
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| 230 | |
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| 231 | |
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| 232 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) |
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| 233 | #define SM501_DC_PANEL_COLOR_KEY (0x008) |
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| 234 | #define SM501_DC_PANEL_FB_ADDR (0x00C) |
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| 235 | #define SM501_DC_PANEL_FB_OFFSET (0x010) |
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| 236 | #define SM501_DC_PANEL_FB_WIDTH (0x014) |
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| 237 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) |
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| 238 | #define SM501_DC_PANEL_TL_LOC (0x01C) |
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| 239 | #define SM501_DC_PANEL_BR_LOC (0x020) |
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| 240 | #define SM501_DC_PANEL_H_TOT (0x024) |
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| 241 | #define SM501_DC_PANEL_H_SYNC (0x028) |
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| 242 | #define SM501_DC_PANEL_V_TOT (0x02C) |
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| 243 | #define SM501_DC_PANEL_V_SYNC (0x030) |
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| 244 | #define SM501_DC_PANEL_CUR_LINE (0x034) |
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| 245 | |
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| 246 | #define SM501_DC_VIDEO_CONTROL (0x040) |
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| 247 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) |
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| 248 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) |
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| 249 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) |
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| 250 | #define SM501_DC_VIDEO_TL_LOC (0x050) |
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| 251 | #define SM501_DC_VIDEO_BR_LOC (0x054) |
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| 252 | #define SM501_DC_VIDEO_SCALE (0x058) |
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| 253 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) |
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| 254 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) |
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| 255 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) |
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| 256 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) |
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| 257 | |
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| 258 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) |
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| 259 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) |
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| 260 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) |
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| 261 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) |
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| 262 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) |
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| 263 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) |
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| 264 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) |
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| 265 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) |
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| 266 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) |
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| 267 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) |
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| 268 | |
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| 269 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) |
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| 270 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) |
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| 271 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) |
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| 272 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) |
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| 273 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) |
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| 274 | |
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| 275 | #define SM501_HWC_EN (1<<31) |
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| 276 | |
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| 277 | #define SM501_OFF_HWC_ADDR (0x00) |
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| 278 | #define SM501_OFF_HWC_LOC (0x04) |
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| 279 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) |
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| 280 | #define SM501_OFF_HWC_COLOR_3 (0x0C) |
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| 281 | |
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| 282 | #define SM501_DC_ALPHA_CONTROL (0x100) |
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| 283 | #define SM501_DC_ALPHA_FB_ADDR (0x104) |
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| 284 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) |
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| 285 | #define SM501_DC_ALPHA_TL_LOC (0x10C) |
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| 286 | #define SM501_DC_ALPHA_BR_LOC (0x110) |
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| 287 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) |
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| 288 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) |
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| 289 | |
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| 290 | #define SM501_DC_CRT_CONTROL (0x200) |
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| 291 | |
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| 292 | #define SM501_DC_CRT_CONTROL_TVP (1<<15) |
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| 293 | #define SM501_DC_CRT_CONTROL_CP (1<<14) |
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| 294 | #define SM501_DC_CRT_CONTROL_VSP (1<<13) |
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| 295 | #define SM501_DC_CRT_CONTROL_HSP (1<<12) |
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| 296 | #define SM501_DC_CRT_CONTROL_VS (1<<11) |
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| 297 | #define SM501_DC_CRT_CONTROL_BLANK (1<<10) |
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| 298 | #define SM501_DC_CRT_CONTROL_SEL (1<<9) |
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| 299 | #define SM501_DC_CRT_CONTROL_TE (1<<8) |
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| 300 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
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| 301 | #define SM501_DC_CRT_CONTROL_GAMMA (1<<3) |
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| 302 | #define SM501_DC_CRT_CONTROL_ENABLE (1<<2) |
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| 303 | |
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| 304 | #define SM501_DC_CRT_CONTROL_8BPP (0<<0) |
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| 305 | #define SM501_DC_CRT_CONTROL_16BPP (1<<0) |
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| 306 | #define SM501_DC_CRT_CONTROL_32BPP (2<<0) |
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| 307 | |
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| 308 | #define SM501_DC_CRT_FB_ADDR (0x204) |
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| 309 | #define SM501_DC_CRT_FB_OFFSET (0x208) |
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| 310 | #define SM501_DC_CRT_H_TOT (0x20C) |
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| 311 | #define SM501_DC_CRT_H_SYNC (0x210) |
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| 312 | #define SM501_DC_CRT_V_TOT (0x214) |
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| 313 | #define SM501_DC_CRT_V_SYNC (0x218) |
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| 314 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) |
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| 315 | #define SM501_DC_CRT_CUR_LINE (0x220) |
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| 316 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) |
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| 317 | |
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| 318 | #define SM501_DC_CRT_HWC_BASE (0x230) |
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| 319 | #define SM501_DC_CRT_HWC_ADDR (0x230) |
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| 320 | #define SM501_DC_CRT_HWC_LOC (0x234) |
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| 321 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) |
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| 322 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) |
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| 323 | |
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| 324 | #define SM501_DC_PANEL_PALETTE (0x400) |
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| 325 | |
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| 326 | #define SM501_DC_VIDEO_PALETTE (0x800) |
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| 327 | |
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| 328 | #define SM501_DC_CRT_PALETTE (0xC00) |
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| 329 | |
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| 330 | /* Zoom Video port base */ |
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| 331 | #define SM501_ZVPORT (0x090000) |
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| 332 | |
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| 333 | /* AC97/I2S base */ |
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| 334 | #define SM501_AC97 (0x0A0000) |
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| 335 | |
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| 336 | /* 8051 micro controller base */ |
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| 337 | #define SM501_UCONTROLLER (0x0B0000) |
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| 338 | |
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| 339 | /* 8051 micro controller SRAM base */ |
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| 340 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
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| 341 | |
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| 342 | /* DMA base */ |
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| 343 | #define SM501_DMA (0x0D0000) |
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| 344 | |
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| 345 | /* 2d engine base */ |
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| 346 | #define SM501_2D_ENGINE (0x100000) |
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| 347 | #define SM501_2D_SOURCE (0x00) |
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| 348 | #define SM501_2D_DESTINATION (0x04) |
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| 349 | #define SM501_2D_DIMENSION (0x08) |
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| 350 | #define SM501_2D_CONTROL (0x0C) |
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| 351 | #define SM501_2D_PITCH (0x10) |
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| 352 | #define SM501_2D_FOREGROUND (0x14) |
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| 353 | #define SM501_2D_BACKGROUND (0x18) |
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| 354 | #define SM501_2D_STRETCH (0x1C) |
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| 355 | #define SM501_2D_COLOR_COMPARE (0x20) |
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| 356 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) |
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| 357 | #define SM501_2D_MASK (0x28) |
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| 358 | #define SM501_2D_CLIP_TL (0x2C) |
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| 359 | #define SM501_2D_CLIP_BR (0x30) |
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| 360 | #define SM501_2D_MONO_PATTERN_LOW (0x34) |
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| 361 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) |
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| 362 | #define SM501_2D_WINDOW_WIDTH (0x3C) |
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| 363 | #define SM501_2D_SOURCE_BASE (0x40) |
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| 364 | #define SM501_2D_DESTINATION_BASE (0x44) |
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| 365 | #define SM501_2D_ALPHA (0x48) |
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| 366 | #define SM501_2D_WRAP (0x4C) |
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| 367 | #define SM501_2D_STATUS (0x50) |
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| 368 | |
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| 369 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) |
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| 370 | #define SM501_CSC_CONSTANTS (0xCC) |
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| 371 | #define SM501_CSC_Y_SOURCE_X (0xD0) |
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| 372 | #define SM501_CSC_Y_SOURCE_Y (0xD4) |
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| 373 | #define SM501_CSC_U_SOURCE_BASE (0xD8) |
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| 374 | #define SM501_CSC_V_SOURCE_BASE (0xDC) |
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| 375 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) |
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| 376 | #define SM501_CSC_SOURCE_PITCH (0xE4) |
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| 377 | #define SM501_CSC_DESTINATION (0xE8) |
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| 378 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) |
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| 379 | #define SM501_CSC_DESTINATION_PITCH (0xF0) |
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| 380 | #define SM501_CSC_SCALE_FACTOR (0xF4) |
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| 381 | #define SM501_CSC_DESTINATION_BASE (0xF8) |
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| 382 | #define SM501_CSC_CONTROL (0xFC) |
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| 383 | |
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| 384 | /* 2d engine data port base */ |
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| 385 | #define SM501_2D_ENGINE_DATA (0x110000) |
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| 386 | |
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