| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __LINUX_SMSCPHY_H__ |
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| 3 | #define __LINUX_SMSCPHY_H__ |
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| 4 | |
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| 5 | #define MII_LAN83C185_ISF 29 /* Interrupt Source Flags */ |
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| 6 | #define MII_LAN83C185_IM 30 /* Interrupt Mask */ |
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| 7 | #define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */ |
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| 8 | #define MII_LAN83C185_SPECIAL_MODES 18 /* Special Modes Register */ |
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| 9 | |
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| 10 | #define MII_LAN83C185_ISF_INT1 (1<<1) /* Auto-Negotiation Page Received */ |
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| 11 | #define MII_LAN83C185_ISF_INT2 (1<<2) /* Parallel Detection Fault */ |
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| 12 | #define MII_LAN83C185_ISF_INT3 (1<<3) /* Auto-Negotiation LP Ack */ |
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| 13 | #define MII_LAN83C185_ISF_INT4 (1<<4) /* Link Down */ |
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| 14 | #define MII_LAN83C185_ISF_INT5 (1<<5) /* Remote Fault Detected */ |
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| 15 | #define MII_LAN83C185_ISF_INT6 (1<<6) /* Auto-Negotiation complete */ |
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| 16 | #define MII_LAN83C185_ISF_INT7 (1<<7) /* ENERGYON */ |
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| 17 | |
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| 18 | #define MII_LAN83C185_ISF_INT_ALL (0x0e) |
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| 19 | |
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| 20 | #define MII_LAN83C185_ISF_INT_PHYLIB_EVENTS \ |
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| 21 | (MII_LAN83C185_ISF_INT6 | MII_LAN83C185_ISF_INT4 | \ |
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| 22 | MII_LAN83C185_ISF_INT7) |
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| 23 | |
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| 24 | #define MII_LAN83C185_EDPWRDOWN (1 << 13) /* EDPWRDOWN */ |
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| 25 | #define MII_LAN83C185_ENERGYON (1 << 1) /* ENERGYON */ |
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| 26 | |
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| 27 | #define MII_LAN83C185_MODE_MASK 0xE0 |
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| 28 | #define MII_LAN83C185_MODE_POWERDOWN 0xC0 /* Power Down mode */ |
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| 29 | #define MII_LAN83C185_MODE_ALL 0xE0 /* All capable mode */ |
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| 30 | |
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| 31 | int smsc_phy_config_intr(struct phy_device *phydev); |
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| 32 | irqreturn_t smsc_phy_handle_interrupt(struct phy_device *phydev); |
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| 33 | int smsc_phy_config_init(struct phy_device *phydev); |
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| 34 | int lan87xx_read_status(struct phy_device *phydev); |
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| 35 | int smsc_phy_get_tunable(struct phy_device *phydev, |
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| 36 | struct ethtool_tunable *tuna, void *data); |
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| 37 | int smsc_phy_set_tunable(struct phy_device *phydev, |
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| 38 | struct ethtool_tunable *tuna, const void *data); |
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| 39 | int smsc_phy_probe(struct phy_device *phydev); |
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| 40 | |
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| 41 | #define MII_LAN874X_PHY_MMD_WOL_WUCSR 0x8010 |
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| 42 | #define MII_LAN874X_PHY_MMD_WOL_WUF_CFGA 0x8011 |
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| 43 | #define MII_LAN874X_PHY_MMD_WOL_WUF_CFGB 0x8012 |
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| 44 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK0 0x8021 |
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| 45 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK1 0x8022 |
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| 46 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK2 0x8023 |
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| 47 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK3 0x8024 |
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| 48 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK4 0x8025 |
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| 49 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK5 0x8026 |
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| 50 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK6 0x8027 |
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| 51 | #define MII_LAN874X_PHY_MMD_WOL_WUF_MASK7 0x8028 |
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| 52 | #define MII_LAN874X_PHY_MMD_WOL_RX_ADDRA 0x8061 |
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| 53 | #define MII_LAN874X_PHY_MMD_WOL_RX_ADDRB 0x8062 |
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| 54 | #define MII_LAN874X_PHY_MMD_WOL_RX_ADDRC 0x8063 |
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| 55 | #define MII_LAN874X_PHY_MMD_MCFGR 0x8064 |
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| 56 | |
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| 57 | #define MII_LAN874X_PHY_PME1_SET (2 << 13) |
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| 58 | #define MII_LAN874X_PHY_PME2_SET (2 << 11) |
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| 59 | #define MII_LAN874X_PHY_PME_SELF_CLEAR BIT(9) |
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| 60 | #define MII_LAN874X_PHY_WOL_PFDA_FR BIT(7) |
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| 61 | #define MII_LAN874X_PHY_WOL_WUFR BIT(6) |
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| 62 | #define MII_LAN874X_PHY_WOL_MPR BIT(5) |
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| 63 | #define MII_LAN874X_PHY_WOL_BCAST_FR BIT(4) |
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| 64 | #define MII_LAN874X_PHY_WOL_PFDAEN BIT(3) |
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| 65 | #define MII_LAN874X_PHY_WOL_WUEN BIT(2) |
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| 66 | #define MII_LAN874X_PHY_WOL_MPEN BIT(1) |
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| 67 | #define MII_LAN874X_PHY_WOL_BCSTEN BIT(0) |
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| 68 | |
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| 69 | #define MII_LAN874X_PHY_WOL_FILTER_EN BIT(15) |
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| 70 | #define MII_LAN874X_PHY_WOL_FILTER_MCASTTEN BIT(9) |
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| 71 | #define MII_LAN874X_PHY_WOL_FILTER_BCSTEN BIT(8) |
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| 72 | |
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| 73 | #define MII_LAN874X_PHY_PME_SELF_CLEAR_DELAY 0x1000 /* 81 milliseconds */ |
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| 74 | |
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| 75 | #endif /* __LINUX_SMSCPHY_H__ */ |
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| 76 | |
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