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| 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
|---|---|
| 2 | /* |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * Copyright(c) 2018 Intel Corporation |
| 7 | */ |
| 8 | |
| 9 | #ifndef __INCLUDE_SOUND_SOF_DAI_H__ |
| 10 | #define __INCLUDE_SOUND_SOF_DAI_H__ |
| 11 | |
| 12 | #include <sound/sof/header.h> |
| 13 | #include <sound/sof/dai-intel.h> |
| 14 | #include <sound/sof/dai-imx.h> |
| 15 | #include <sound/sof/dai-amd.h> |
| 16 | #include <sound/sof/dai-mediatek.h> |
| 17 | |
| 18 | /* |
| 19 | * DAI Configuration. |
| 20 | * |
| 21 | * Each different DAI type will have it's own structure and IPC cmd. |
| 22 | */ |
| 23 | |
| 24 | #define SOF_DAI_FMT_I2S 1 /**< I2S mode */ |
| 25 | #define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */ |
| 26 | #define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */ |
| 27 | #define SOF_DAI_FMT_DSP_A 4 /**< L data MSB after FRM LRC */ |
| 28 | #define SOF_DAI_FMT_DSP_B 5 /**< L data MSB during FRM LRC */ |
| 29 | #define SOF_DAI_FMT_PDM 6 /**< Pulse density modulation */ |
| 30 | |
| 31 | #define SOF_DAI_FMT_CONT (1 << 4) /**< continuous clock */ |
| 32 | #define SOF_DAI_FMT_GATED (0 << 4) /**< clock is gated */ |
| 33 | |
| 34 | #define SOF_DAI_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */ |
| 35 | #define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */ |
| 36 | #define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */ |
| 37 | #define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */ |
| 38 | |
| 39 | #define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */ |
| 40 | #define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */ |
| 41 | #define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */ |
| 42 | #define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */ |
| 43 | |
| 44 | /* keep old definitions for backwards compatibility */ |
| 45 | #define SOF_DAI_FMT_CBM_CFM SOF_DAI_FMT_CBP_CFP |
| 46 | #define SOF_DAI_FMT_CBS_CFM SOF_DAI_FMT_CBC_CFP |
| 47 | #define SOF_DAI_FMT_CBM_CFS SOF_DAI_FMT_CBP_CFC |
| 48 | #define SOF_DAI_FMT_CBS_CFS SOF_DAI_FMT_CBC_CFC |
| 49 | |
| 50 | #define SOF_DAI_FMT_FORMAT_MASK 0x000f |
| 51 | #define SOF_DAI_FMT_CLOCK_MASK 0x00f0 |
| 52 | #define SOF_DAI_FMT_INV_MASK 0x0f00 |
| 53 | #define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000 |
| 54 | |
| 55 | /* |
| 56 | * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE |
| 57 | * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above |
| 58 | * commands. |
| 59 | */ |
| 60 | #define SOF_DAI_CONFIG_FLAGS_CMD_MASK 0xF |
| 61 | #define SOF_DAI_CONFIG_FLAGS_NONE 0 /**< DAI_CONFIG sent without stage information */ |
| 62 | #define SOF_DAI_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< DAI_CONFIG sent during hw_params stage */ |
| 63 | #define SOF_DAI_CONFIG_FLAGS_HW_FREE BIT(1) /**< DAI_CONFIG sent during hw_free stage */ |
| 64 | /**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */ |
| 65 | #define SOF_DAI_CONFIG_FLAGS_PAUSE BIT(2) |
| 66 | #define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4 |
| 67 | #define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT) |
| 68 | /* |
| 69 | * This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline |
| 70 | * stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available |
| 71 | * ABI 3.20 onwards. |
| 72 | */ |
| 73 | #define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0) |
| 74 | |
| 75 | /** \brief Types of DAI */ |
| 76 | enum sof_ipc_dai_type { |
| 77 | SOF_DAI_INTEL_NONE = 0, /**< None */ |
| 78 | SOF_DAI_INTEL_SSP, /**< Intel SSP */ |
| 79 | SOF_DAI_INTEL_DMIC, /**< Intel DMIC */ |
| 80 | SOF_DAI_INTEL_HDA, /**< Intel HD/A */ |
| 81 | SOF_DAI_INTEL_ALH, /**< Intel ALH */ |
| 82 | SOF_DAI_IMX_SAI, /**< i.MX SAI */ |
| 83 | SOF_DAI_IMX_ESAI, /**< i.MX ESAI */ |
| 84 | SOF_DAI_AMD_BT, /**< AMD ACP BT*/ |
| 85 | SOF_DAI_AMD_SP, /**< AMD ACP SP */ |
| 86 | SOF_DAI_AMD_DMIC, /**< AMD ACP DMIC */ |
| 87 | SOF_DAI_MEDIATEK_AFE, /**< Mediatek AFE */ |
| 88 | SOF_DAI_AMD_HS, /**< Amd HS */ |
| 89 | SOF_DAI_AMD_SP_VIRTUAL, /**< AMD ACP SP VIRTUAL */ |
| 90 | SOF_DAI_AMD_HS_VIRTUAL, /**< AMD ACP HS VIRTUAL */ |
| 91 | SOF_DAI_IMX_MICFIL, /** < i.MX MICFIL PDM */ |
| 92 | SOF_DAI_AMD_SDW, /**< AMD ACP SDW */ |
| 93 | }; |
| 94 | |
| 95 | /* general purpose DAI configuration */ |
| 96 | struct sof_ipc_dai_config { |
| 97 | struct sof_ipc_cmd_hdr hdr; |
| 98 | uint32_t type; /**< DAI type - enum sof_ipc_dai_type */ |
| 99 | uint32_t dai_index; /**< index of this type dai */ |
| 100 | |
| 101 | /* physical protocol and clocking */ |
| 102 | uint16_t format; /**< SOF_DAI_FMT_ */ |
| 103 | uint8_t group_id; /**< group ID, 0 means no group (ABI 3.17) */ |
| 104 | uint8_t flags; /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */ |
| 105 | |
| 106 | /* reserved for future use */ |
| 107 | uint32_t reserved[8]; |
| 108 | |
| 109 | /* HW specific data */ |
| 110 | union { |
| 111 | struct sof_ipc_dai_ssp_params ssp; |
| 112 | struct sof_ipc_dai_dmic_params dmic; |
| 113 | struct sof_ipc_dai_hda_params hda; |
| 114 | struct sof_ipc_dai_alh_params alh; |
| 115 | struct sof_ipc_dai_esai_params esai; |
| 116 | struct sof_ipc_dai_sai_params sai; |
| 117 | struct sof_ipc_dai_acp_params acpbt; |
| 118 | struct sof_ipc_dai_acp_params acpsp; |
| 119 | struct sof_ipc_dai_acpdmic_params acpdmic; |
| 120 | struct sof_ipc_dai_acp_params acphs; |
| 121 | struct sof_ipc_dai_mtk_afe_params afe; |
| 122 | struct sof_ipc_dai_micfil_params micfil; |
| 123 | struct sof_ipc_dai_acp_sdw_params acp_sdw; |
| 124 | }; |
| 125 | } __packed; |
| 126 | |
| 127 | struct sof_dai_private_data { |
| 128 | struct sof_ipc_comp_dai *comp_dai; |
| 129 | struct sof_ipc_dai_config *dai_config; |
| 130 | }; |
| 131 | |
| 132 | #endif |
| 133 |
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