1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
2 | /* |
3 | * linux/mdio.h: definitions for MDIO (clause 45) transceivers |
4 | * Copyright 2006-2009 Solarflare Communications Inc. |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License version 2 as published |
8 | * by the Free Software Foundation, incorporated herein by reference. |
9 | */ |
10 | |
11 | #ifndef _UAPI__LINUX_MDIO_H__ |
12 | #define _UAPI__LINUX_MDIO_H__ |
13 | |
14 | #include <linux/types.h> |
15 | #include <linux/mii.h> |
16 | |
17 | /* MDIO Manageable Devices (MMDs). */ |
18 | #define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ |
19 | * Physical Medium Dependent */ |
20 | #define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ |
21 | #define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ |
22 | #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ |
23 | #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ |
24 | #define MDIO_MMD_TC 6 /* Transmission Convergence */ |
25 | #define MDIO_MMD_AN 7 /* Auto-Negotiation */ |
26 | #define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ |
27 | #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ |
28 | #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ |
29 | |
30 | /* Generic MDIO registers. */ |
31 | #define MDIO_CTRL1 MII_BMCR |
32 | #define MDIO_STAT1 MII_BMSR |
33 | #define MDIO_DEVID1 MII_PHYSID1 |
34 | #define MDIO_DEVID2 MII_PHYSID2 |
35 | #define MDIO_SPEED 4 /* Speed ability */ |
36 | #define MDIO_DEVS1 5 /* Devices in package */ |
37 | #define MDIO_DEVS2 6 |
38 | #define MDIO_CTRL2 7 /* 10G control 2 */ |
39 | #define MDIO_STAT2 8 /* 10G status 2 */ |
40 | #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ |
41 | #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ |
42 | #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ |
43 | #define MDIO_PKGID1 14 /* Package identifier */ |
44 | #define MDIO_PKGID2 15 |
45 | #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ |
46 | #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ |
47 | #define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */ |
48 | #define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */ |
49 | #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ |
50 | #define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */ |
51 | #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ |
52 | #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ |
53 | #define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */ |
54 | #define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */ |
55 | #define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */ |
56 | #define MDIO_AN_CTRL2 64 /* AN THP bypass request control */ |
57 | |
58 | /* Media-dependent registers. */ |
59 | #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ |
60 | #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ |
61 | #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. |
62 | * Lanes B-D are numbered 134-136. */ |
63 | #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */ |
64 | #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ |
65 | #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ |
66 | #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ |
67 | #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ |
68 | #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ |
69 | #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ |
70 | #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */ |
71 | #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */ |
72 | #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */ |
73 | #define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */ |
74 | #define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */ |
75 | #define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */ |
76 | #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */ |
77 | #define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */ |
78 | #define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */ |
79 | #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */ |
80 | #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */ |
81 | #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */ |
82 | #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */ |
83 | #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */ |
84 | #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */ |
85 | #define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */ |
86 | #define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */ |
87 | |
88 | /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ |
89 | #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ |
90 | #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ |
91 | #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ |
92 | #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ |
93 | #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ |
94 | #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ |
95 | |
96 | /* Control register 1. */ |
97 | /* Enable extended speed selection */ |
98 | #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) |
99 | /* All speed selection bits */ |
100 | #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) |
101 | #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX |
102 | #define MDIO_CTRL1_LPOWER BMCR_PDOWN |
103 | #define MDIO_CTRL1_RESET BMCR_RESET |
104 | #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 |
105 | #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 |
106 | #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 |
107 | #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK |
108 | #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK |
109 | #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART |
110 | #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE |
111 | #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ |
112 | #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */ |
113 | |
114 | /* 10 Gb/s */ |
115 | #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) |
116 | /* 10PASS-TS/2BASE-TL */ |
117 | #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) |
118 | /* 2.5 Gb/s */ |
119 | #define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) |
120 | /* 5 Gb/s */ |
121 | #define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) |
122 | |
123 | /* Status register 1. */ |
124 | #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ |
125 | #define MDIO_STAT1_LSTATUS BMSR_LSTATUS |
126 | #define MDIO_STAT1_FAULT 0x0080 /* Fault */ |
127 | #define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ |
128 | #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE |
129 | #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT |
130 | #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE |
131 | #define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ |
132 | #define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ |
133 | |
134 | /* Speed register. */ |
135 | #define MDIO_SPEED_10G 0x0001 /* 10G capable */ |
136 | #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ |
137 | #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ |
138 | #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ |
139 | #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ |
140 | #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ |
141 | #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ |
142 | #define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */ |
143 | #define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */ |
144 | |
145 | /* Device present registers. */ |
146 | #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) |
147 | #define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0) |
148 | #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) |
149 | #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) |
150 | #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) |
151 | #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) |
152 | #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) |
153 | #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) |
154 | #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) |
155 | #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) |
156 | #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) |
157 | #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) |
158 | |
159 | /* Control register 2. */ |
160 | #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ |
161 | #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ |
162 | #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ |
163 | #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ |
164 | #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ |
165 | #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ |
166 | #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ |
167 | #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ |
168 | #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ |
169 | #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ |
170 | #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ |
171 | #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ |
172 | #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ |
173 | #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ |
174 | #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ |
175 | #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ |
176 | #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ |
177 | #define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ |
178 | #define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ |
179 | #define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */ |
180 | #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ |
181 | #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ |
182 | #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ |
183 | #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ |
184 | #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ |
185 | |
186 | /* Status register 2. */ |
187 | #define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ |
188 | #define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ |
189 | #define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ |
190 | #define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ |
191 | #define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ |
192 | #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ |
193 | #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ |
194 | #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ |
195 | #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ |
196 | #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ |
197 | #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ |
198 | #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ |
199 | #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ |
200 | #define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ |
201 | #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ |
202 | #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ |
203 | #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ |
204 | #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ |
205 | #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ |
206 | #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ |
207 | #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ |
208 | |
209 | /* Transmit disable register. */ |
210 | #define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ |
211 | #define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ |
212 | #define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ |
213 | #define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ |
214 | #define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ |
215 | |
216 | /* Receive signal detect register. */ |
217 | #define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ |
218 | #define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ |
219 | #define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ |
220 | #define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ |
221 | #define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ |
222 | |
223 | /* Extended abilities register. */ |
224 | #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ |
225 | #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ |
226 | #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ |
227 | #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ |
228 | #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ |
229 | #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ |
230 | #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ |
231 | #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ |
232 | #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ |
233 | #define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */ |
234 | #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ |
235 | |
236 | /* AN Clause 73 linkword */ |
237 | #define MDIO_AN_C73_0_S_MASK GENMASK(4, 0) |
238 | #define MDIO_AN_C73_0_E_MASK GENMASK(9, 5) |
239 | #define MDIO_AN_C73_0_PAUSE BIT(10) |
240 | #define MDIO_AN_C73_0_ASM_DIR BIT(11) |
241 | #define MDIO_AN_C73_0_C2 BIT(12) |
242 | #define MDIO_AN_C73_0_RF BIT(13) |
243 | #define MDIO_AN_C73_0_ACK BIT(14) |
244 | #define MDIO_AN_C73_0_NP BIT(15) |
245 | #define MDIO_AN_C73_1_T_MASK GENMASK(4, 0) |
246 | #define MDIO_AN_C73_1_1000BASE_KX BIT(5) |
247 | #define MDIO_AN_C73_1_10GBASE_KX4 BIT(6) |
248 | #define MDIO_AN_C73_1_10GBASE_KR BIT(7) |
249 | #define MDIO_AN_C73_1_40GBASE_KR4 BIT(8) |
250 | #define MDIO_AN_C73_1_40GBASE_CR4 BIT(9) |
251 | #define MDIO_AN_C73_1_100GBASE_CR10 BIT(10) |
252 | #define MDIO_AN_C73_1_100GBASE_KP4 BIT(11) |
253 | #define MDIO_AN_C73_1_100GBASE_KR4 BIT(12) |
254 | #define MDIO_AN_C73_1_100GBASE_CR4 BIT(13) |
255 | #define MDIO_AN_C73_1_25GBASE_R_S BIT(14) |
256 | #define MDIO_AN_C73_1_25GBASE_R BIT(15) |
257 | #define MDIO_AN_C73_2_2500BASE_KX BIT(0) |
258 | #define MDIO_AN_C73_2_5GBASE_KR BIT(1) |
259 | |
260 | /* PHY XGXS lane state register. */ |
261 | #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 |
262 | #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 |
263 | #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 |
264 | #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 |
265 | #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 |
266 | |
267 | /* PMA 10GBASE-T pair swap & polarity */ |
268 | #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ |
269 | #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ |
270 | #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ |
271 | #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ |
272 | #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ |
273 | #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ |
274 | |
275 | /* PMA 10GBASE-T TX power register. */ |
276 | #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ |
277 | |
278 | /* PMA 10GBASE-T SNR registers. */ |
279 | /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ |
280 | #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 |
281 | #define MDIO_PMA_10GBT_SNR_MAX 127 |
282 | |
283 | /* PMA 10GBASE-R FEC ability register. */ |
284 | #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ |
285 | #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ |
286 | |
287 | /* PMA 10GBASE-R Fast Retrain status and control register. */ |
288 | #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 /* Fast retrain enable */ |
289 | |
290 | /* PCS 10GBASE-R/-T status register 1. */ |
291 | #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ |
292 | |
293 | /* PCS 10GBASE-R/-T status register 2. */ |
294 | #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff |
295 | #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 |
296 | |
297 | /* AN 10GBASE-T control register. */ |
298 | #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 /* Advertise 2.5GBASE-T fast retrain */ |
299 | #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */ |
300 | #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */ |
301 | #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ |
302 | |
303 | /* AN 10GBASE-T status register. */ |
304 | #define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */ |
305 | #define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */ |
306 | #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ |
307 | #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ |
308 | #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ |
309 | #define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ |
310 | #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ |
311 | #define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ |
312 | #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ |
313 | |
314 | /* 10BASE-T1L PMA control */ |
315 | #define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001 /* Enable loopback mode */ |
316 | #define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400 /* Enable EEE mode */ |
317 | #define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 /* Low-power mode */ |
318 | #define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000 /* Enable 2.4 Vpp operating mode */ |
319 | #define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000 /* Transmit disable */ |
320 | #define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000 /* MA reset */ |
321 | |
322 | /* 10BASE-T1L PMA status register. */ |
323 | #define MDIO_PMA_10T1L_STAT_LINK 0x0001 /* PMA receive link up */ |
324 | #define MDIO_PMA_10T1L_STAT_FAULT 0x0002 /* Fault condition detected */ |
325 | #define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 /* Receive polarity is reversed */ |
326 | #define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 /* Able to detect fault on receive path */ |
327 | #define MDIO_PMA_10T1L_STAT_EEE 0x0400 /* PHY has EEE ability */ |
328 | #define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */ |
329 | #define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 /* PHY has 2.4 Vpp operating mode ability */ |
330 | #define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 /* PHY has loopback ability */ |
331 | |
332 | /* 10BASE-T1L PCS control register. */ |
333 | #define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */ |
334 | #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */ |
335 | |
336 | /* BASE-T1 PMA/PMD extended ability register. */ |
337 | #define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001 /* 100BASE-T1 Ability */ |
338 | #define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 /* 1000BASE-T1 Ability */ |
339 | #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */ |
340 | |
341 | /* BASE-T1 auto-negotiation advertisement register [15:0] */ |
342 | #define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP |
343 | #define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM |
344 | #define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 /* Force Master/slave Configuration */ |
345 | #define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT |
346 | #define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK |
347 | #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE |
348 | |
349 | /* BASE-T1 auto-negotiation advertisement register [31:16] */ |
350 | #define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */ |
351 | #define MDIO_AN_T1_ADV_M_MST 0x0010 /* advertise master preference */ |
352 | |
353 | /* BASE-T1 auto-negotiation advertisement register [47:32] */ |
354 | #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */ |
355 | #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */ |
356 | |
357 | /* BASE-T1 AN LP Base Page ability register [15:0] */ |
358 | #define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP |
359 | #define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM |
360 | #define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 /* LP Force Master/slave Configuration */ |
361 | #define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT |
362 | #define MDIO_AN_T1_LP_L_ACK LPA_LPACK |
363 | #define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE |
364 | |
365 | /* BASE-T1 AN LP Base Page ability register [31:16] */ |
366 | #define MDIO_AN_T1_LP_M_MST 0x0010 /* LP master preference */ |
367 | #define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */ |
368 | |
369 | /* BASE-T1 AN LP Base Page ability register [47:32] */ |
370 | #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */ |
371 | #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */ |
372 | |
373 | /* 10BASE-T1 AN control register */ |
374 | #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */ |
375 | |
376 | /* 10BASE-T1 AN status register */ |
377 | #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */ |
378 | |
379 | /* BASE-T1 PMA/PMD control register */ |
380 | #define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F /* Type selection (Strap) */ |
381 | #define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 /* Select 1000BASE-T1 */ |
382 | #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ |
383 | |
384 | /* 1000BASE-T1 PCS control register */ |
385 | #define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800 /* Low power mode */ |
386 | #define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000 /* Global PMA transmit disable */ |
387 | #define MDIO_PCS_1000BT1_CTRL_RESET 0x8000 /* Software reset value */ |
388 | |
389 | /* 1000BASE-T1 PCS status register */ |
390 | #define MDIO_PCS_1000BT1_STAT_LINK 0x0004 /* PCS Link is up */ |
391 | #define MDIO_PCS_1000BT1_STAT_FAULT 0x0080 /* There is a fault condition */ |
392 | |
393 | |
394 | /* EEE Supported/Advertisement/LP Advertisement registers. |
395 | * |
396 | * EEE capability Register (3.20), Advertisement (7.60) and |
397 | * Link partner ability (7.61) registers have and can use the same identical |
398 | * bit masks. |
399 | */ |
400 | #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ |
401 | #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ |
402 | /* Note: the two defines above can be potentially used by the user-land |
403 | * and cannot remove them now. |
404 | * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros |
405 | * using the previous ones (that can be considered obsolete). |
406 | */ |
407 | #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */ |
408 | #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */ |
409 | #define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ |
410 | #define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ |
411 | #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ |
412 | #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ |
413 | #define MDIO_EEE_40GR_FW 0x0100 /* 40G R fast wake */ |
414 | #define MDIO_EEE_40GR_DS 0x0200 /* 40G R deep sleep */ |
415 | #define MDIO_EEE_100GR_FW 0x1000 /* 100G R fast wake */ |
416 | #define MDIO_EEE_100GR_DS 0x2000 /* 100G R deep sleep */ |
417 | |
418 | #define MDIO_EEE_2_5GT 0x0001 /* 2.5GT EEE cap */ |
419 | #define MDIO_EEE_5GT 0x0002 /* 5GT EEE cap */ |
420 | |
421 | /* AN MultiGBASE-T AN control 2 */ |
422 | #define MDIO_AN_THP_BP2_5GT 0x0008 /* 2.5GT THP bypass request */ |
423 | |
424 | /* 2.5G/5G Extended abilities register. */ |
425 | #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ |
426 | #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ |
427 | |
428 | /* LASI RX_ALARM control/status registers. */ |
429 | #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ |
430 | #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ |
431 | #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ |
432 | #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ |
433 | #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ |
434 | |
435 | /* LASI TX_ALARM control/status registers. */ |
436 | #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ |
437 | #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ |
438 | #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ |
439 | #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ |
440 | #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ |
441 | #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ |
442 | |
443 | /* LASI control/status registers. */ |
444 | #define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ |
445 | #define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ |
446 | #define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ |
447 | |
448 | /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ |
449 | |
450 | #define MDIO_PHY_ID_C45 0x8000 |
451 | #define MDIO_PHY_ID_PRTAD 0x03e0 |
452 | #define MDIO_PHY_ID_DEVAD 0x001f |
453 | #define MDIO_PHY_ID_C45_MASK \ |
454 | (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) |
455 | |
456 | static inline __u16 mdio_phy_id_c45(int prtad, int devad) |
457 | { |
458 | return MDIO_PHY_ID_C45 | (prtad << 5) | devad; |
459 | } |
460 | |
461 | /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/ |
462 | #define MDIO_USXGMII_EEE_CLK_STP 0x0080 /* EEE clock stop supported */ |
463 | #define MDIO_USXGMII_EEE 0x0100 /* EEE supported */ |
464 | #define MDIO_USXGMII_SPD_MASK 0x0e00 /* USXGMII speed mask */ |
465 | #define MDIO_USXGMII_FULL_DUPLEX 0x1000 /* USXGMII full duplex */ |
466 | #define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 /* USXGMII duplex and speed bits */ |
467 | #define MDIO_USXGMII_10 0x0000 /* 10Mbps */ |
468 | #define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */ |
469 | #define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */ |
470 | #define MDIO_USXGMII_100 0x0200 /* 100Mbps */ |
471 | #define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */ |
472 | #define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */ |
473 | #define MDIO_USXGMII_1000 0x0400 /* 1000Mbps */ |
474 | #define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */ |
475 | #define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */ |
476 | #define MDIO_USXGMII_10G 0x0600 /* 10Gbps */ |
477 | #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */ |
478 | #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */ |
479 | #define MDIO_USXGMII_2500 0x0800 /* 2500Mbps */ |
480 | #define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */ |
481 | #define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */ |
482 | #define MDIO_USXGMII_5000 0x0a00 /* 5000Mbps */ |
483 | #define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */ |
484 | #define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */ |
485 | #define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */ |
486 | |
487 | #endif /* _UAPI__LINUX_MDIO_H__ */ |
488 | |