1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Driver for Digigram pcxhr compatible soundcards
4	*
5	* main file with alsa callbacks
6	*
7	* Copyright (c) 2004 by Digigram <alsa@digigram.com>
8	*/
9
10
11	#include <linux/init.h>
12	#include <linux/interrupt.h>
13	#include <linux/slab.h>
14	#include <linux/pci.h>
15	#include <linux/dma-mapping.h>
16	#include <linux/delay.h>
17	#include <linux/module.h>
18	#include <linux/mutex.h>
19
20	#include <sound/core.h>
21	#include <sound/initval.h>
22	#include <sound/info.h>
23	#include <sound/control.h>
24	#include <sound/pcm.h>
25	#include <sound/pcm_params.h>
26	#include "pcxhr.h"
27	#include "pcxhr_mixer.h"
28	#include "pcxhr_hwdep.h"
29	#include "pcxhr_core.h"
30	#include "pcxhr_mix22.h"
31
32	#define DRIVER_NAME "pcxhr"
33
34	MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
35	"Marc Titinger <titinger@digigram.com>");
36	MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
37	MODULE_LICENSE("GPL");
38
39	static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
40	static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
41	static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
42	static bool mono[SNDRV_CARDS]; /* capture mono only */
43
44	module_param_array(index, int, NULL, 0444);
45	MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
46	module_param_array(id, charp, NULL, 0444);
47	MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
48	module_param_array(enable, bool, NULL, 0444);
49	MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
50	module_param_array(mono, bool, NULL, 0444);
51	MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
52
53	enum {
54	PCI_ID_VX882HR,
55	PCI_ID_PCX882HR,
56	PCI_ID_VX881HR,
57	PCI_ID_PCX881HR,
58	PCI_ID_VX882E,
59	PCI_ID_PCX882E,
60	PCI_ID_VX881E,
61	PCI_ID_PCX881E,
62	PCI_ID_VX1222HR,
63	PCI_ID_PCX1222HR,
64	PCI_ID_VX1221HR,
65	PCI_ID_PCX1221HR,
66	PCI_ID_VX1222E,
67	PCI_ID_PCX1222E,
68	PCI_ID_VX1221E,
69	PCI_ID_PCX1221E,
70	PCI_ID_VX222HR,
71	PCI_ID_VX222E,
72	PCI_ID_PCX22HR,
73	PCI_ID_PCX22E,
74	PCI_ID_VX222HRMIC,
75	PCI_ID_VX222E_MIC,
76	PCI_ID_PCX924HR,
77	PCI_ID_PCX924E,
78	PCI_ID_PCX924HRMIC,
79	PCI_ID_PCX924E_MIC,
80	PCI_ID_VX442HR,
81	PCI_ID_PCX442HR,
82	PCI_ID_VX442E,
83	PCI_ID_PCX442E,
84	PCI_ID_VX822HR,
85	PCI_ID_PCX822HR,
86	PCI_ID_VX822E,
87	PCI_ID_PCX822E,
88	PCI_ID_LAST
89	};
90
91	static const struct pci_device_id pcxhr_ids[] = {
92	{ 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
93	{ 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
94	{ 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
95	{ 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
96	{ 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
97	{ 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
98	{ 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
99	{ 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
100	{ 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
101	{ 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
102	{ 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
103	{ 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
104	{ 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
105	{ 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
106	{ 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
107	{ 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
108	{ 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
109	{ 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
110	{ 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
111	{ 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
112	{ 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
113	{ 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
114	{ 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
115	{ 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
116	{ 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
117	{ 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
118	{ 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, },
119	{ 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, },
120	{ 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, },
121	{ 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, },
122	{ 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, },
123	{ 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, },
124	{ 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, },
125	{ 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, },
126	{ 0, }
127	};
128
129	MODULE_DEVICE_TABLE(pci, pcxhr_ids);
130
131	struct board_parameters {
132	char* board_name;
133	short playback_chips;
134	short capture_chips;
135	short fw_file_set;
136	short firmware_num;
137	};
138	static const struct board_parameters pcxhr_board_params[] = {
139	[PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 },
140	[PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 },
141	[PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 },
142	[PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 },
143	[PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 },
144	[PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 },
145	[PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 },
146	[PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 },
147	[PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 },
148	[PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 },
149	[PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 },
150	[PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 },
151	[PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 },
152	[PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 },
153	[PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 },
154	[PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 },
155	[PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 },
156	[PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 },
157	[PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 },
158	[PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 },
159	[PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 },
160	[PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 },
161	[PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 },
162	[PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 },
163	[PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 },
164	[PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 },
165	[PCI_ID_VX442HR] = { "VX442HR", 2, 2, 0, 41 },
166	[PCI_ID_PCX442HR] = { "PCX442HR", 2, 2, 0, 41 },
167	[PCI_ID_VX442E] = { "VX442e", 2, 2, 1, 41 },
168	[PCI_ID_PCX442E] = { "PCX442e", 2, 2, 1, 41 },
169	[PCI_ID_VX822HR] = { "VX822HR", 4, 1, 2, 42 },
170	[PCI_ID_PCX822HR] = { "PCX822HR", 4, 1, 2, 42 },
171	[PCI_ID_VX822E] = { "VX822e", 4, 1, 3, 42 },
172	[PCI_ID_PCX822E] = { "PCX822e", 4, 1, 3, 42 },
173	};
174
175	/* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
176	/* VX222HR, VX222e, PCX22HR and PCX22e */
177	#define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
178	/* some boards do not support 192kHz on digital AES input plugs */
179	#define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
180	(x->fw_file_set == 0) || \
181	(x->fw_file_set == 2))
182
183	static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
184	unsigned int* realfreq)
185	{
186	unsigned int reg;
187
188	if (freq < 6900 || freq > 110000)
189	return -EINVAL;
190	reg = (28224000 * 2) / freq;
191	reg = (reg - 1) / 2;
192	if (reg < 0x200)
193	*pllreg = reg + 0x800;
194	else if (reg < 0x400)
195	*pllreg = reg & 0x1ff;
196	else if (reg < 0x800) {
197	*pllreg = ((reg >> 1) & 0x1ff) + 0x200;
198	reg &= ~1;
199	} else {
200	*pllreg = ((reg >> 2) & 0x1ff) + 0x400;
201	reg &= ~3;
202	}
203	if (realfreq)
204	*realfreq = (28224000 / (reg + 1));
205	return 0;
206	}
207
208
209	#define PCXHR_FREQ_REG_MASK 0x1f
210	#define PCXHR_FREQ_QUARTZ_48000 0x00
211	#define PCXHR_FREQ_QUARTZ_24000 0x01
212	#define PCXHR_FREQ_QUARTZ_12000 0x09
213	#define PCXHR_FREQ_QUARTZ_32000 0x08
214	#define PCXHR_FREQ_QUARTZ_16000 0x04
215	#define PCXHR_FREQ_QUARTZ_8000 0x0c
216	#define PCXHR_FREQ_QUARTZ_44100 0x02
217	#define PCXHR_FREQ_QUARTZ_22050 0x0a
218	#define PCXHR_FREQ_QUARTZ_11025 0x06
219	#define PCXHR_FREQ_PLL 0x05
220	#define PCXHR_FREQ_QUARTZ_192000 0x10
221	#define PCXHR_FREQ_QUARTZ_96000 0x18
222	#define PCXHR_FREQ_QUARTZ_176400 0x14
223	#define PCXHR_FREQ_QUARTZ_88200 0x1c
224	#define PCXHR_FREQ_QUARTZ_128000 0x12
225	#define PCXHR_FREQ_QUARTZ_64000 0x1a
226
227	#define PCXHR_FREQ_WORD_CLOCK 0x0f
228	#define PCXHR_FREQ_SYNC_AES 0x0e
229	#define PCXHR_FREQ_AES_1 0x07
230	#define PCXHR_FREQ_AES_2 0x0b
231	#define PCXHR_FREQ_AES_3 0x03
232	#define PCXHR_FREQ_AES_4 0x0d
233
234	static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
235	unsigned int *reg, unsigned int *freq)
236	{
237	unsigned int val, realfreq, pllreg;
238	struct pcxhr_rmh rmh;
239	int err;
240
241	realfreq = rate;
242	switch (mgr->use_clock_type) {
243	case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
244	switch (rate) {
245	case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
246	case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
247	case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
248	case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
249	case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
250	case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
251	case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
252	case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
253	case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
254	case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
255	case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
256	case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
257	case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
258	case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
259	case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
260	default :
261	val = PCXHR_FREQ_PLL;
262	/* get the value for the pll register */
263	err = pcxhr_pll_freq_register(freq: rate, pllreg: &pllreg, realfreq: &realfreq);
264	if (err)
265	return err;
266	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_ACCESS_IO_WRITE);
267	rmh.cmd[0] |= IO_NUM_REG_GENCLK;
268	rmh.cmd[1] = pllreg & MASK_DSP_WORD;
269	rmh.cmd[2] = pllreg >> 24;
270	rmh.cmd_len = 3;
271	err = pcxhr_send_msg(mgr, rmh: &rmh);
272	if (err < 0) {
273	dev_err(&mgr->pci->dev,
274	"error CMD_ACCESS_IO_WRITE "
275	"for PLL register : %x!\n", err);
276	return err;
277	}
278	}
279	break;
280	case PCXHR_CLOCK_TYPE_WORD_CLOCK:
281	val = PCXHR_FREQ_WORD_CLOCK;
282	break;
283	case PCXHR_CLOCK_TYPE_AES_SYNC:
284	val = PCXHR_FREQ_SYNC_AES;
285	break;
286	case PCXHR_CLOCK_TYPE_AES_1:
287	val = PCXHR_FREQ_AES_1;
288	break;
289	case PCXHR_CLOCK_TYPE_AES_2:
290	val = PCXHR_FREQ_AES_2;
291	break;
292	case PCXHR_CLOCK_TYPE_AES_3:
293	val = PCXHR_FREQ_AES_3;
294	break;
295	case PCXHR_CLOCK_TYPE_AES_4:
296	val = PCXHR_FREQ_AES_4;
297	break;
298	default:
299	return -EINVAL;
300	}
301	*reg = val;
302	*freq = realfreq;
303	return 0;
304	}
305
306
307	static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
308	unsigned int rate,
309	int *changed)
310	{
311	unsigned int val, realfreq, speed;
312	struct pcxhr_rmh rmh;
313	int err;
314
315	err = pcxhr_get_clock_reg(mgr, rate, reg: &val, freq: &realfreq);
316	if (err)
317	return err;
318
319	/* codec speed modes */
320	if (rate < 55000)
321	speed = 0; /* single speed */
322	else if (rate < 100000)
323	speed = 1; /* dual speed */
324	else
325	speed = 2; /* quad speed */
326	if (mgr->codec_speed != speed) {
327	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_ACCESS_IO_WRITE); /* mute outputs */
328	rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
329	if (DSP_EXT_CMD_SET(mgr)) {
330	rmh.cmd[1] = 1;
331	rmh.cmd_len = 2;
332	}
333	err = pcxhr_send_msg(mgr, rmh: &rmh);
334	if (err)
335	return err;
336
337	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_ACCESS_IO_WRITE); /* set speed ratio */
338	rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
339	rmh.cmd[1] = speed;
340	rmh.cmd_len = 2;
341	err = pcxhr_send_msg(mgr, rmh: &rmh);
342	if (err)
343	return err;
344	}
345	/* set the new frequency */
346	dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val);
347	err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
348	value: val, changed);
349	if (err)
350	return err;
351
352	mgr->sample_rate_real = realfreq;
353	mgr->cur_clock_type = mgr->use_clock_type;
354
355	/* unmute after codec speed modes */
356	if (mgr->codec_speed != speed) {
357	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_ACCESS_IO_READ); /* unmute outputs */
358	rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
359	if (DSP_EXT_CMD_SET(mgr)) {
360	rmh.cmd[1] = 1;
361	rmh.cmd_len = 2;
362	}
363	err = pcxhr_send_msg(mgr, rmh: &rmh);
364	if (err)
365	return err;
366	mgr->codec_speed = speed; /* save new codec speed */
367	}
368
369	dev_dbg(&mgr->pci->dev, "%s to %dHz (realfreq=%d)\n", __func__,
370	rate, realfreq);
371	return 0;
372	}
373
374	#define PCXHR_MODIFY_CLOCK_S_BIT 0x04
375
376	#define PCXHR_IRQ_TIMER_FREQ 92000
377	#define PCXHR_IRQ_TIMER_PERIOD 48
378
379	int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
380	{
381	struct pcxhr_rmh rmh;
382	int err, changed;
383
384	if (rate == 0)
385	return 0; /* nothing to do */
386
387	if (mgr->is_hr_stereo)
388	err = hr222_sub_set_clock(mgr, rate, changed: &changed);
389	else
390	err = pcxhr_sub_set_clock(mgr, rate, changed: &changed);
391
392	if (err)
393	return err;
394
395	if (changed) {
396	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_MODIFY_CLOCK);
397	rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
398	if (rate < PCXHR_IRQ_TIMER_FREQ)
399	rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
400	else
401	rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
402	rmh.cmd[2] = rate;
403	rmh.cmd_len = 3;
404	err = pcxhr_send_msg(mgr, rmh: &rmh);
405	if (err)
406	return err;
407	}
408	return 0;
409	}
410
411
412	static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
413	enum pcxhr_clock_type clock_type,
414	int *sample_rate)
415	{
416	struct pcxhr_rmh rmh;
417	unsigned char reg;
418	int err, rate;
419
420	switch (clock_type) {
421	case PCXHR_CLOCK_TYPE_WORD_CLOCK:
422	reg = REG_STATUS_WORD_CLOCK;
423	break;
424	case PCXHR_CLOCK_TYPE_AES_SYNC:
425	reg = REG_STATUS_AES_SYNC;
426	break;
427	case PCXHR_CLOCK_TYPE_AES_1:
428	reg = REG_STATUS_AES_1;
429	break;
430	case PCXHR_CLOCK_TYPE_AES_2:
431	reg = REG_STATUS_AES_2;
432	break;
433	case PCXHR_CLOCK_TYPE_AES_3:
434	reg = REG_STATUS_AES_3;
435	break;
436	case PCXHR_CLOCK_TYPE_AES_4:
437	reg = REG_STATUS_AES_4;
438	break;
439	default:
440	return -EINVAL;
441	}
442	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_ACCESS_IO_READ);
443	rmh.cmd_len = 2;
444	rmh.cmd[0] |= IO_NUM_REG_STATUS;
445	if (mgr->last_reg_stat != reg) {
446	rmh.cmd[1] = reg;
447	err = pcxhr_send_msg(mgr, rmh: &rmh);
448	if (err)
449	return err;
450	udelay(usec: 100); /* wait minimum 2 sample_frames at 32kHz ! */
451	mgr->last_reg_stat = reg;
452	}
453	rmh.cmd[1] = REG_STATUS_CURRENT;
454	err = pcxhr_send_msg(mgr, rmh: &rmh);
455	if (err)
456	return err;
457	switch (rmh.stat[1] & 0x0f) {
458	case REG_STATUS_SYNC_32000 : rate = 32000; break;
459	case REG_STATUS_SYNC_44100 : rate = 44100; break;
460	case REG_STATUS_SYNC_48000 : rate = 48000; break;
461	case REG_STATUS_SYNC_64000 : rate = 64000; break;
462	case REG_STATUS_SYNC_88200 : rate = 88200; break;
463	case REG_STATUS_SYNC_96000 : rate = 96000; break;
464	case REG_STATUS_SYNC_128000 : rate = 128000; break;
465	case REG_STATUS_SYNC_176400 : rate = 176400; break;
466	case REG_STATUS_SYNC_192000 : rate = 192000; break;
467	default: rate = 0;
468	}
469	dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate);
470	*sample_rate = rate;
471	return 0;
472	}
473
474
475	int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
476	enum pcxhr_clock_type clock_type,
477	int *sample_rate)
478	{
479	if (mgr->is_hr_stereo)
480	return hr222_get_external_clock(mgr, clock_type,
481	sample_rate);
482	else
483	return pcxhr_sub_get_external_clock(mgr, clock_type,
484	sample_rate);
485	}
486
487	/*
488	* start or stop playback/capture substream
489	*/
490	static int pcxhr_set_stream_state(struct snd_pcxhr *chip,
491	struct pcxhr_stream *stream)
492	{
493	int err;
494	struct pcxhr_rmh rmh;
495	int stream_mask, start;
496
497	if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
498	start = 1;
499	else {
500	if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
501	dev_err(chip->card->dev,
502	"%s CANNOT be stopped\n", __func__);
503	return -EINVAL;
504	}
505	start = 0;
506	}
507	if (!stream->substream)
508	return -EINVAL;
509
510	stream->timer_abs_periods = 0;
511	stream->timer_period_frag = 0; /* reset theoretical stream pos */
512	stream->timer_buf_periods = 0;
513	stream->timer_is_synced = 0;
514
515	stream_mask =
516	stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
517
518	pcxhr_init_rmh(rmh: &rmh, cmd: start ? CMD_START_STREAM : CMD_STOP_STREAM);
519	pcxhr_set_pipe_cmd_params(rmh: &rmh, capture: stream->pipe->is_capture,
520	param1: stream->pipe->first_audio, param2: 0, param3: stream_mask);
521
522	chip = snd_pcm_substream_chip(stream->substream);
523
524	err = pcxhr_send_msg(mgr: chip->mgr, rmh: &rmh);
525	if (err)
526	dev_err(chip->card->dev,
527	"ERROR %s err=%x;\n", __func__, err);
528	stream->status =
529	start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
530	return err;
531	}
532
533	#define HEADER_FMT_BASE_LIN 0xfed00000
534	#define HEADER_FMT_BASE_FLOAT 0xfad00000
535	#define HEADER_FMT_INTEL 0x00008000
536	#define HEADER_FMT_24BITS 0x00004000
537	#define HEADER_FMT_16BITS 0x00002000
538	#define HEADER_FMT_UPTO11 0x00000200
539	#define HEADER_FMT_UPTO32 0x00000100
540	#define HEADER_FMT_MONO 0x00000080
541
542	static int pcxhr_set_format(struct pcxhr_stream *stream)
543	{
544	int err, is_capture, sample_rate, stream_num;
545	struct snd_pcxhr *chip;
546	struct pcxhr_rmh rmh;
547	unsigned int header;
548
549	chip = snd_pcm_substream_chip(stream->substream);
550	switch (stream->format) {
551	case SNDRV_PCM_FORMAT_U8:
552	header = HEADER_FMT_BASE_LIN;
553	break;
554	case SNDRV_PCM_FORMAT_S16_LE:
555	header = HEADER_FMT_BASE_LIN |
556	HEADER_FMT_16BITS | HEADER_FMT_INTEL;
557	break;
558	case SNDRV_PCM_FORMAT_S16_BE:
559	header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
560	break;
561	case SNDRV_PCM_FORMAT_S24_3LE:
562	header = HEADER_FMT_BASE_LIN |
563	HEADER_FMT_24BITS | HEADER_FMT_INTEL;
564	break;
565	case SNDRV_PCM_FORMAT_S24_3BE:
566	header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
567	break;
568	case SNDRV_PCM_FORMAT_FLOAT_LE:
569	header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
570	break;
571	default:
572	dev_err(chip->card->dev,
573	"error %s() : unknown format\n", __func__);
574	return -EINVAL;
575	}
576
577	sample_rate = chip->mgr->sample_rate;
578	if (sample_rate <= 32000 && sample_rate !=0) {
579	if (sample_rate <= 11025)
580	header |= HEADER_FMT_UPTO11;
581	else
582	header |= HEADER_FMT_UPTO32;
583	}
584	if (stream->channels == 1)
585	header |= HEADER_FMT_MONO;
586
587	is_capture = stream->pipe->is_capture;
588	stream_num = is_capture ? 0 : stream->substream->number;
589
590	pcxhr_init_rmh(rmh: &rmh, cmd: is_capture ?
591	CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
592	pcxhr_set_pipe_cmd_params(rmh: &rmh, capture: is_capture, param1: stream->pipe->first_audio,
593	param2: stream_num, param3: 0);
594	if (is_capture) {
595	/* bug with old dsp versions: */
596	/* bit 12 also sets the format of the playback stream */
597	if (DSP_EXT_CMD_SET(chip->mgr))
598	rmh.cmd[0] |= 1<<10;
599	else
600	rmh.cmd[0] |= 1<<12;
601	}
602	rmh.cmd[1] = 0;
603	rmh.cmd_len = 2;
604	if (DSP_EXT_CMD_SET(chip->mgr)) {
605	/* add channels and set bit 19 if channels>2 */
606	rmh.cmd[1] = stream->channels;
607	if (!is_capture) {
608	/* playback : add channel mask to command */
609	rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
610	rmh.cmd_len = 3;
611	}
612	}
613	rmh.cmd[rmh.cmd_len++] = header >> 8;
614	rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
615	err = pcxhr_send_msg(mgr: chip->mgr, rmh: &rmh);
616	if (err)
617	dev_err(chip->card->dev,
618	"ERROR %s err=%x;\n", __func__, err);
619	return err;
620	}
621
622	static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
623	{
624	int err, is_capture, stream_num;
625	struct pcxhr_rmh rmh;
626	struct snd_pcm_substream *subs = stream->substream;
627	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
628
629	is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
630	stream_num = is_capture ? 0 : subs->number;
631
632	dev_dbg(chip->card->dev,
633	"%s(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", __func__,
634	is_capture ? 'c' : 'p',
635	chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
636	subs->runtime->dma_bytes, subs->number);
637
638	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_UPDATE_R_BUFFERS);
639	pcxhr_set_pipe_cmd_params(rmh: &rmh, capture: is_capture, param1: stream->pipe->first_audio,
640	param2: stream_num, param3: 0);
641
642	/* max buffer size is 2 MByte */
643	snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
644	/* size in bits */
645	rmh.cmd[1] = subs->runtime->dma_bytes * 8;
646	/* most significant byte */
647	rmh.cmd[2] = subs->runtime->dma_addr >> 24;
648	/* this is a circular buffer */
649	rmh.cmd[2] |= 1<<19;
650	/* least 3 significant bytes */
651	rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
652	rmh.cmd_len = 4;
653	err = pcxhr_send_msg(mgr: chip->mgr, rmh: &rmh);
654	if (err)
655	dev_err(chip->card->dev,
656	"ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
657	return err;
658	}
659
660
661	#if 0
662	static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
663	snd_pcm_uframes_t *sample_count)
664	{
665	struct pcxhr_rmh rmh;
666	int err;
667	pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
668	pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
669	pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
670	1<<stream->pipe->first_audio);
671	err = pcxhr_send_msg(chip->mgr, &rmh);
672	if (err == 0) {
673	*sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
674	*sample_count += (snd_pcm_uframes_t)rmh.stat[1];
675	}
676	dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
677	return err;
678	}
679	#endif
680
681	static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
682	struct pcxhr_pipe **pipe)
683	{
684	if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
685	*pipe = stream->pipe;
686	return 1;
687	}
688	return 0;
689	}
690
691	static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr)
692	{
693	int i, j, err;
694	struct pcxhr_pipe *pipe;
695	struct snd_pcxhr *chip;
696	int capture_mask = 0;
697	int playback_mask = 0;
698
699	#ifdef CONFIG_SND_DEBUG_VERBOSE
700	ktime_t start_time, stop_time, diff_time;
701
702	start_time = ktime_get();
703	#endif
704	guard(mutex)(T: &mgr->setup_mutex);
705
706	/* check the pipes concerned and build pipe_array */
707	for (i = 0; i < mgr->num_cards; i++) {
708	chip = mgr->chip[i];
709	for (j = 0; j < chip->nb_streams_capt; j++) {
710	if (pcxhr_stream_scheduled_get_pipe(stream: &chip->capture_stream[j], pipe: &pipe))
711	capture_mask |= (1 << pipe->first_audio);
712	}
713	for (j = 0; j < chip->nb_streams_play; j++) {
714	if (pcxhr_stream_scheduled_get_pipe(stream: &chip->playback_stream[j], pipe: &pipe)) {
715	playback_mask |= (1 << pipe->first_audio);
716	break; /* add only once, as all playback
717	* streams of one chip use the same pipe
718	*/
719	}
720	}
721	}
722	if (capture_mask == 0 && playback_mask == 0) {
723	dev_err(&mgr->pci->dev, "%s : no pipes\n", __func__);
724	return;
725	}
726
727	dev_dbg(&mgr->pci->dev, "%s : playback_mask=%x capture_mask=%x\n",
728	__func__, playback_mask, capture_mask);
729
730	/* synchronous stop of all the pipes concerned */
731	err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, start: 0);
732	if (err) {
733	dev_err(&mgr->pci->dev, "%s : "
734	"error stop pipes (P%x C%x)\n",
735	__func__, playback_mask, capture_mask);
736	return;
737	}
738
739	/* the dsp lost format and buffer info with the stop pipe */
740	for (i = 0; i < mgr->num_cards; i++) {
741	struct pcxhr_stream *stream;
742	chip = mgr->chip[i];
743	for (j = 0; j < chip->nb_streams_capt; j++) {
744	stream = &chip->capture_stream[j];
745	if (pcxhr_stream_scheduled_get_pipe(stream, pipe: &pipe)) {
746	err = pcxhr_set_format(stream);
747	err = pcxhr_update_r_buffer(stream);
748	}
749	}
750	for (j = 0; j < chip->nb_streams_play; j++) {
751	stream = &chip->playback_stream[j];
752	if (pcxhr_stream_scheduled_get_pipe(stream, pipe: &pipe)) {
753	err = pcxhr_set_format(stream);
754	err = pcxhr_update_r_buffer(stream);
755	}
756	}
757	}
758	/* start all the streams */
759	for (i = 0; i < mgr->num_cards; i++) {
760	struct pcxhr_stream *stream;
761	chip = mgr->chip[i];
762	for (j = 0; j < chip->nb_streams_capt; j++) {
763	stream = &chip->capture_stream[j];
764	if (pcxhr_stream_scheduled_get_pipe(stream, pipe: &pipe))
765	err = pcxhr_set_stream_state(chip, stream);
766	}
767	for (j = 0; j < chip->nb_streams_play; j++) {
768	stream = &chip->playback_stream[j];
769	if (pcxhr_stream_scheduled_get_pipe(stream, pipe: &pipe))
770	err = pcxhr_set_stream_state(chip, stream);
771	}
772	}
773
774	/* synchronous start of all the pipes concerned */
775	err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, start: 1);
776	if (err) {
777	dev_err(&mgr->pci->dev, "%s : "
778	"error start pipes (P%x C%x)\n",
779	__func__, playback_mask, capture_mask);
780	return;
781	}
782
783	/* put the streams into the running state now
784	* (increment pointer by interrupt)
785	*/
786	guard(mutex)(T: &mgr->lock);
787	for ( i =0; i < mgr->num_cards; i++) {
788	struct pcxhr_stream *stream;
789	chip = mgr->chip[i];
790	for(j = 0; j < chip->nb_streams_capt; j++) {
791	stream = &chip->capture_stream[j];
792	if(stream->status == PCXHR_STREAM_STATUS_STARTED)
793	stream->status = PCXHR_STREAM_STATUS_RUNNING;
794	}
795	for (j = 0; j < chip->nb_streams_play; j++) {
796	stream = &chip->playback_stream[j];
797	if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
798	/* playback will already have advanced ! */
799	stream->timer_period_frag += mgr->granularity;
800	stream->status = PCXHR_STREAM_STATUS_RUNNING;
801	}
802	}
803	}
804
805	#ifdef CONFIG_SND_DEBUG_VERBOSE
806	stop_time = ktime_get();
807	diff_time = ktime_sub(stop_time, start_time);
808	dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n",
809	(long)(ktime_to_ns(diff_time)), err);
810	#endif
811	}
812
813
814	/*
815	* trigger callback
816	*/
817	static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
818	{
819	struct pcxhr_stream *stream;
820	struct snd_pcm_substream *s;
821	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
822
823	switch (cmd) {
824	case SNDRV_PCM_TRIGGER_START:
825	dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n");
826	if (snd_pcm_stream_linked(substream: subs)) {
827	snd_pcm_group_for_each_entry(s, subs) {
828	if (snd_pcm_substream_chip(s) != chip)
829	continue;
830	stream = s->runtime->private_data;
831	stream->status =
832	PCXHR_STREAM_STATUS_SCHEDULE_RUN;
833	snd_pcm_trigger_done(substream: s, master: subs);
834	}
835	pcxhr_start_linked_stream(mgr: chip->mgr);
836	} else {
837	stream = subs->runtime->private_data;
838	dev_dbg(chip->card->dev, "Only one Substream %c %d\n",
839	stream->pipe->is_capture ? 'C' : 'P',
840	stream->pipe->first_audio);
841	if (pcxhr_set_format(stream))
842	return -EINVAL;
843	if (pcxhr_update_r_buffer(stream))
844	return -EINVAL;
845
846	stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
847	if (pcxhr_set_stream_state(chip, stream))
848	return -EINVAL;
849	stream->status = PCXHR_STREAM_STATUS_RUNNING;
850	}
851	break;
852	case SNDRV_PCM_TRIGGER_STOP:
853	dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n");
854	snd_pcm_group_for_each_entry(s, subs) {
855	stream = s->runtime->private_data;
856	stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
857	if (pcxhr_set_stream_state(chip, stream))
858	return -EINVAL;
859	snd_pcm_trigger_done(substream: s, master: subs);
860	}
861	break;
862	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
863	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
864	/* TODO */
865	default:
866	return -EINVAL;
867	}
868	return 0;
869	}
870
871
872	static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
873	{
874	struct pcxhr_rmh rmh;
875	int err;
876
877	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_SET_TIMER_INTERRUPT);
878	if (start) {
879	/* last dsp time invalid */
880	mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
881	rmh.cmd[0] |= mgr->granularity;
882	}
883	err = pcxhr_send_msg(mgr, rmh: &rmh);
884	if (err < 0)
885	dev_err(&mgr->pci->dev, "error %s err(%x)\n", __func__,
886	err);
887	return err;
888	}
889
890	/*
891	* prepare callback for all pcms
892	*/
893	static int pcxhr_prepare(struct snd_pcm_substream *subs)
894	{
895	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
896	struct pcxhr_mgr *mgr = chip->mgr;
897	int err = 0;
898
899	dev_dbg(chip->card->dev,
900	"%s : period_size(%lx) periods(%x) buffer_size(%lx)\n", __func__,
901	subs->runtime->period_size, subs->runtime->periods,
902	subs->runtime->buffer_size);
903
904	guard(mutex)(T: &mgr->setup_mutex);
905
906	do {
907	/* only the first stream can choose the sample rate */
908	/* set the clock only once (first stream) */
909	if (mgr->sample_rate != subs->runtime->rate) {
910	err = pcxhr_set_clock(mgr, rate: subs->runtime->rate);
911	if (err)
912	break;
913	if (mgr->sample_rate == 0)
914	/* start the DSP-timer */
915	err = pcxhr_hardware_timer(mgr, start: 1);
916	mgr->sample_rate = subs->runtime->rate;
917	}
918	} while(0); /* do only once (so we can use break instead of goto) */
919
920	return err;
921	}
922
923
924	/*
925	* HW_PARAMS callback for all pcms
926	*/
927	static int pcxhr_hw_params(struct snd_pcm_substream *subs,
928	struct snd_pcm_hw_params *hw)
929	{
930	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
931	struct pcxhr_mgr *mgr = chip->mgr;
932	struct pcxhr_stream *stream = subs->runtime->private_data;
933
934	guard(mutex)(T: &mgr->setup_mutex);
935
936	/* set up channels */
937	stream->channels = params_channels(p: hw);
938	/* set up format for the stream */
939	stream->format = params_format(p: hw);
940
941	return 0;
942	}
943
944
945	/*
946	* CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
947	*/
948	static const struct snd_pcm_hardware pcxhr_caps =
949	{
950	.info = (SNDRV_PCM_INFO_MMAP |
951	SNDRV_PCM_INFO_INTERLEAVED |
952	SNDRV_PCM_INFO_MMAP_VALID |
953	SNDRV_PCM_INFO_SYNC_START),
954	.formats = (SNDRV_PCM_FMTBIT_U8 |
955	SNDRV_PCM_FMTBIT_S16_LE |
956	SNDRV_PCM_FMTBIT_S16_BE |
957	SNDRV_PCM_FMTBIT_S24_3LE |
958	SNDRV_PCM_FMTBIT_S24_3BE |
959	SNDRV_PCM_FMTBIT_FLOAT_LE),
960	.rates = (SNDRV_PCM_RATE_CONTINUOUS |
961	SNDRV_PCM_RATE_8000_192000),
962	.rate_min = 8000,
963	.rate_max = 192000,
964	.channels_min = 1,
965	.channels_max = 2,
966	.buffer_bytes_max = (32*1024),
967	/* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
968	.period_bytes_min = (2*PCXHR_GRANULARITY),
969	.period_bytes_max = (16*1024),
970	.periods_min = 2,
971	.periods_max = (32*1024/PCXHR_GRANULARITY),
972	};
973
974
975	static int pcxhr_open(struct snd_pcm_substream *subs)
976	{
977	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
978	struct pcxhr_mgr *mgr = chip->mgr;
979	struct snd_pcm_runtime *runtime = subs->runtime;
980	struct pcxhr_stream *stream;
981	int err;
982
983	guard(mutex)(T: &mgr->setup_mutex);
984
985	/* copy the struct snd_pcm_hardware struct */
986	runtime->hw = pcxhr_caps;
987
988	if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
989	dev_dbg(chip->card->dev, "%s playback chip%d subs%d\n",
990	__func__, chip->chip_idx, subs->number);
991	stream = &chip->playback_stream[subs->number];
992	} else {
993	dev_dbg(chip->card->dev, "%s capture chip%d subs%d\n",
994	__func__, chip->chip_idx, subs->number);
995	if (mgr->mono_capture)
996	runtime->hw.channels_max = 1;
997	else
998	runtime->hw.channels_min = 2;
999	stream = &chip->capture_stream[subs->number];
1000	}
1001	if (stream->status != PCXHR_STREAM_STATUS_FREE){
1002	/* streams in use */
1003	dev_err(chip->card->dev, "%s chip%d subs%d in use\n",
1004	__func__, chip->chip_idx, subs->number);
1005	return -EBUSY;
1006	}
1007
1008	/* float format support is in some cases buggy on stereo cards */
1009	if (mgr->is_hr_stereo)
1010	runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1011
1012	/* buffer-size should better be multiple of period-size */
1013	err = snd_pcm_hw_constraint_integer(runtime,
1014	SNDRV_PCM_HW_PARAM_PERIODS);
1015	if (err < 0)
1016	return err;
1017
1018	/* if a sample rate is already used or fixed by external clock,
1019	* the stream cannot change
1020	*/
1021	if (mgr->sample_rate)
1022	runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1023	else {
1024	if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1025	int external_rate;
1026	if (pcxhr_get_external_clock(mgr, clock_type: mgr->use_clock_type,
1027	sample_rate: &external_rate) ||
1028	external_rate == 0) {
1029	/* cannot detect the external clock rate */
1030	return -EBUSY;
1031	}
1032	runtime->hw.rate_min = external_rate;
1033	runtime->hw.rate_max = external_rate;
1034	}
1035	}
1036
1037	stream->status = PCXHR_STREAM_STATUS_OPEN;
1038	stream->substream = subs;
1039	stream->channels = 0; /* not configured yet */
1040
1041	runtime->private_data = stream;
1042
1043	/* better get a divisor of granularity values (96 or 192) */
1044	snd_pcm_hw_constraint_step(runtime, cond: 0,
1045	SNDRV_PCM_HW_PARAM_BUFFER_SIZE, step: 32);
1046	snd_pcm_hw_constraint_step(runtime, cond: 0,
1047	SNDRV_PCM_HW_PARAM_PERIOD_SIZE, step: 32);
1048	snd_pcm_set_sync(substream: subs);
1049
1050	mgr->ref_count_rate++;
1051
1052	return 0;
1053	}
1054
1055
1056	static int pcxhr_close(struct snd_pcm_substream *subs)
1057	{
1058	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1059	struct pcxhr_mgr *mgr = chip->mgr;
1060	struct pcxhr_stream *stream = subs->runtime->private_data;
1061
1062	guard(mutex)(T: &mgr->setup_mutex);
1063
1064	dev_dbg(chip->card->dev, "%s chip%d subs%d\n", __func__,
1065	chip->chip_idx, subs->number);
1066
1067	/* sample rate released */
1068	if (--mgr->ref_count_rate == 0) {
1069	mgr->sample_rate = 0; /* the sample rate is no more locked */
1070	pcxhr_hardware_timer(mgr, start: 0); /* stop the DSP-timer */
1071	}
1072
1073	stream->status = PCXHR_STREAM_STATUS_FREE;
1074	stream->substream = NULL;
1075
1076	return 0;
1077	}
1078
1079
1080	static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1081	{
1082	u_int32_t timer_period_frag;
1083	int timer_buf_periods;
1084	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1085	struct snd_pcm_runtime *runtime = subs->runtime;
1086	struct pcxhr_stream *stream = runtime->private_data;
1087
1088	guard(mutex)(T: &chip->mgr->lock);
1089
1090	/* get the period fragment and the nb of periods in the buffer */
1091	timer_period_frag = stream->timer_period_frag;
1092	timer_buf_periods = stream->timer_buf_periods;
1093
1094	return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1095	timer_period_frag);
1096	}
1097
1098
1099	static const struct snd_pcm_ops pcxhr_ops = {
1100	.open = pcxhr_open,
1101	.close = pcxhr_close,
1102	.prepare = pcxhr_prepare,
1103	.hw_params = pcxhr_hw_params,
1104	.trigger = pcxhr_trigger,
1105	.pointer = pcxhr_stream_pointer,
1106	};
1107
1108	/*
1109	*/
1110	int pcxhr_create_pcm(struct snd_pcxhr *chip)
1111	{
1112	int err;
1113	struct snd_pcm *pcm;
1114	char name[32];
1115
1116	snprintf(buf: name, size: sizeof(name), fmt: "pcxhr %d", chip->chip_idx);
1117	err = snd_pcm_new(card: chip->card, id: name, device: 0,
1118	playback_count: chip->nb_streams_play,
1119	capture_count: chip->nb_streams_capt, rpcm: &pcm);
1120	if (err < 0) {
1121	dev_err(chip->card->dev, "cannot create pcm %s\n", name);
1122	return err;
1123	}
1124	pcm->private_data = chip;
1125
1126	if (chip->nb_streams_play)
1127	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &pcxhr_ops);
1128	if (chip->nb_streams_capt)
1129	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &pcxhr_ops);
1130
1131	pcm->info_flags = 0;
1132	pcm->nonatomic = true;
1133	strscpy(pcm->name, name);
1134
1135	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1136	data: &chip->mgr->pci->dev,
1137	size: 32*1024, max: 32*1024);
1138	chip->pcm = pcm;
1139	return 0;
1140	}
1141
1142	static int pcxhr_chip_free(struct snd_pcxhr *chip)
1143	{
1144	kfree(objp: chip);
1145	return 0;
1146	}
1147
1148	static int pcxhr_chip_dev_free(struct snd_device *device)
1149	{
1150	struct snd_pcxhr *chip = device->device_data;
1151	return pcxhr_chip_free(chip);
1152	}
1153
1154
1155	/*
1156	*/
1157	static int pcxhr_create(struct pcxhr_mgr *mgr,
1158	struct snd_card *card, int idx)
1159	{
1160	int err;
1161	struct snd_pcxhr *chip;
1162	static const struct snd_device_ops ops = {
1163	.dev_free = pcxhr_chip_dev_free,
1164	};
1165
1166	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1167	if (!chip)
1168	return -ENOMEM;
1169
1170	chip->card = card;
1171	chip->chip_idx = idx;
1172	chip->mgr = mgr;
1173	card->sync_irq = mgr->irq;
1174
1175	if (idx < mgr->playback_chips)
1176	/* stereo or mono streams */
1177	chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1178
1179	if (idx < mgr->capture_chips) {
1180	if (mgr->mono_capture)
1181	chip->nb_streams_capt = 2; /* 2 mono streams */
1182	else
1183	chip->nb_streams_capt = 1; /* or 1 stereo stream */
1184	}
1185
1186	err = snd_device_new(card, type: SNDRV_DEV_LOWLEVEL, device_data: chip, ops: &ops);
1187	if (err < 0) {
1188	pcxhr_chip_free(chip);
1189	return err;
1190	}
1191
1192	mgr->chip[idx] = chip;
1193
1194	return 0;
1195	}
1196
1197	/* proc interface */
1198	static void pcxhr_proc_info(struct snd_info_entry *entry,
1199	struct snd_info_buffer *buffer)
1200	{
1201	struct snd_pcxhr *chip = entry->private_data;
1202	struct pcxhr_mgr *mgr = chip->mgr;
1203
1204	snd_iprintf(buffer, "\n%s\n", mgr->name);
1205
1206	/* stats available when embedded DSP is running */
1207	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1208	struct pcxhr_rmh rmh;
1209	short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1210	short ver_min = (mgr->dsp_version >> 8) & 0xff;
1211	short ver_build = mgr->dsp_version & 0xff;
1212	snd_iprintf(buffer, "module version %s\n",
1213	PCXHR_DRIVER_VERSION_STRING);
1214	snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1215	ver_maj, ver_min, ver_build);
1216	if (mgr->board_has_analog)
1217	snd_iprintf(buffer, "analog io available\n");
1218	else
1219	snd_iprintf(buffer, "digital only board\n");
1220
1221	/* calc cpu load of the dsp */
1222	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_GET_DSP_RESOURCES);
1223	if( ! pcxhr_send_msg(mgr, rmh: &rmh) ) {
1224	int cur = rmh.stat[0];
1225	int ref = rmh.stat[1];
1226	if (ref > 0) {
1227	if (mgr->sample_rate_real != 0 &&
1228	mgr->sample_rate_real != 48000) {
1229	ref = (ref * 48000) /
1230	mgr->sample_rate_real;
1231	if (mgr->sample_rate_real >=
1232	PCXHR_IRQ_TIMER_FREQ)
1233	ref *= 2;
1234	}
1235	cur = 100 - (100 * cur) / ref;
1236	snd_iprintf(buffer, "cpu load %d%%\n", cur);
1237	snd_iprintf(buffer, "buffer pool %d/%d\n",
1238	rmh.stat[2], rmh.stat[3]);
1239	}
1240	}
1241	snd_iprintf(buffer, "dma granularity : %d\n",
1242	mgr->granularity);
1243	snd_iprintf(buffer, "dsp time errors : %d\n",
1244	mgr->dsp_time_err);
1245	snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1246	mgr->async_err_pipe_xrun);
1247	snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1248	mgr->async_err_stream_xrun);
1249	snd_iprintf(buffer, "dsp async last other error : %x\n",
1250	mgr->async_err_other_last);
1251	/* debug zone dsp */
1252	rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1253	rmh.cmd_len = 1;
1254	rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1255	rmh.dsp_stat = 0;
1256	rmh.cmd_idx = CMD_LAST_INDEX;
1257	if( ! pcxhr_send_msg(mgr, rmh: &rmh) ) {
1258	int i;
1259	if (rmh.stat_len > 8)
1260	rmh.stat_len = 8;
1261	for (i = 0; i < rmh.stat_len; i++)
1262	snd_iprintf(buffer, "debug[%02d] = %06x\n",
1263	i, rmh.stat[i]);
1264	}
1265	} else
1266	snd_iprintf(buffer, "no firmware loaded\n");
1267	snd_iprintf(buffer, "\n");
1268	}
1269	static void pcxhr_proc_sync(struct snd_info_entry *entry,
1270	struct snd_info_buffer *buffer)
1271	{
1272	struct snd_pcxhr *chip = entry->private_data;
1273	struct pcxhr_mgr *mgr = chip->mgr;
1274	static const char *textsHR22[3] = {
1275	"Internal", "AES Sync", "AES 1"
1276	};
1277	static const char *textsPCXHR[7] = {
1278	"Internal", "Word", "AES Sync",
1279	"AES 1", "AES 2", "AES 3", "AES 4"
1280	};
1281	const char **texts;
1282	int max_clock;
1283	if (mgr->is_hr_stereo) {
1284	texts = textsHR22;
1285	max_clock = HR22_CLOCK_TYPE_MAX;
1286	} else {
1287	texts = textsPCXHR;
1288	max_clock = PCXHR_CLOCK_TYPE_MAX;
1289	}
1290
1291	snd_iprintf(buffer, "\n%s\n", mgr->name);
1292	snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1293	texts[mgr->cur_clock_type]);
1294	snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1295	mgr->sample_rate_real);
1296	/* commands available when embedded DSP is running */
1297	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1298	int i, err, sample_rate;
1299	for (i = 1; i <= max_clock; i++) {
1300	err = pcxhr_get_external_clock(mgr, clock_type: i, sample_rate: &sample_rate);
1301	if (err)
1302	break;
1303	snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1304	texts[i], sample_rate);
1305	}
1306	} else
1307	snd_iprintf(buffer, "no firmware loaded\n");
1308	snd_iprintf(buffer, "\n");
1309	}
1310
1311	static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1312	struct snd_info_buffer *buffer)
1313	{
1314	struct snd_pcxhr *chip = entry->private_data;
1315	struct pcxhr_mgr *mgr = chip->mgr;
1316	/* commands available when embedded DSP is running */
1317	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1318	/* gpio ports on stereo boards only available */
1319	int value = 0;
1320	hr222_read_gpio(mgr, is_gpi: 1, value: &value); /* GPI */
1321	snd_iprintf(buffer, "GPI: 0x%x\n", value);
1322	hr222_read_gpio(mgr, is_gpi: 0, value: &value); /* GP0 */
1323	snd_iprintf(buffer, "GPO: 0x%x\n", value);
1324	} else
1325	snd_iprintf(buffer, "no firmware loaded\n");
1326	snd_iprintf(buffer, "\n");
1327	}
1328	static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1329	struct snd_info_buffer *buffer)
1330	{
1331	struct snd_pcxhr *chip = entry->private_data;
1332	struct pcxhr_mgr *mgr = chip->mgr;
1333	char line[64];
1334	int value;
1335	/* commands available when embedded DSP is running */
1336	if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1337	return;
1338	while (!snd_info_get_line(buffer, line, len: sizeof(line))) {
1339	if (sscanf(line, "GPO: 0x%x", &value) != 1)
1340	continue;
1341	hr222_write_gpo(mgr, value); /* GP0 */
1342	}
1343	}
1344
1345	/* Access to the results of the CMD_GET_TIME_CODE RMH */
1346	#define TIME_CODE_VALID_MASK 0x00800000
1347	#define TIME_CODE_NEW_MASK 0x00400000
1348	#define TIME_CODE_BACK_MASK 0x00200000
1349	#define TIME_CODE_WAIT_MASK 0x00100000
1350
1351	/* Values for the CMD_MANAGE_SIGNAL RMH */
1352	#define MANAGE_SIGNAL_TIME_CODE 0x01
1353	#define MANAGE_SIGNAL_MIDI 0x02
1354
1355	/* linear time code read proc*/
1356	static void pcxhr_proc_ltc(struct snd_info_entry *entry,
1357	struct snd_info_buffer *buffer)
1358	{
1359	struct snd_pcxhr *chip = entry->private_data;
1360	struct pcxhr_mgr *mgr = chip->mgr;
1361	struct pcxhr_rmh rmh;
1362	unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm;
1363	int err;
1364	/* commands available when embedded DSP is running */
1365	if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) {
1366	snd_iprintf(buffer, "no firmware loaded\n");
1367	return;
1368	}
1369	if (!mgr->capture_ltc) {
1370	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_MANAGE_SIGNAL);
1371	rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE;
1372	err = pcxhr_send_msg(mgr, rmh: &rmh);
1373	if (err) {
1374	snd_iprintf(buffer, "ltc not activated (%d)\n", err);
1375	return;
1376	}
1377	if (mgr->is_hr_stereo)
1378	hr222_manage_timecode(mgr, enable: 1);
1379	else
1380	pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE,
1381	REG_CONT_VALSMPTE, NULL);
1382	mgr->capture_ltc = 1;
1383	}
1384	pcxhr_init_rmh(rmh: &rmh, cmd: CMD_GET_TIME_CODE);
1385	err = pcxhr_send_msg(mgr, rmh: &rmh);
1386	if (err) {
1387	snd_iprintf(buffer, "ltc read error (err=%d)\n", err);
1388	return ;
1389	}
1390	ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf);
1391	ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf);
1392	ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf);
1393	ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf);
1394
1395	snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n",
1396	ltcHrs, ltcMin, ltcSec, ltcFrm);
1397	snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff,
1398	rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff);
1399	/*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n",
1400	rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/
1401	if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) {
1402	snd_iprintf(buffer, "warning: linear timecode not valid\n");
1403	}
1404	}
1405
1406	static void pcxhr_proc_init(struct snd_pcxhr *chip)
1407	{
1408	snd_card_ro_proc_new(card: chip->card, name: "info", private_data: chip, read: pcxhr_proc_info);
1409	snd_card_ro_proc_new(card: chip->card, name: "sync", private_data: chip, read: pcxhr_proc_sync);
1410	/* gpio available on stereo sound cards only */
1411	if (chip->mgr->is_hr_stereo)
1412	snd_card_rw_proc_new(card: chip->card, name: "gpio", private_data: chip,
1413	read: pcxhr_proc_gpio_read,
1414	write: pcxhr_proc_gpo_write);
1415	snd_card_ro_proc_new(card: chip->card, name: "ltc", private_data: chip, read: pcxhr_proc_ltc);
1416	}
1417	/* end of proc interface */
1418
1419	/*
1420	* release all the cards assigned to a manager instance
1421	*/
1422	static int pcxhr_free(struct pcxhr_mgr *mgr)
1423	{
1424	unsigned int i;
1425
1426	for (i = 0; i < mgr->num_cards; i++) {
1427	if (mgr->chip[i])
1428	snd_card_free(card: mgr->chip[i]->card);
1429	}
1430
1431	/* reset board if some firmware was loaded */
1432	if(mgr->dsp_loaded) {
1433	pcxhr_reset_board(mgr);
1434	dev_dbg(&mgr->pci->dev, "reset pcxhr !\n");
1435	}
1436
1437	/* release irq */
1438	if (mgr->irq >= 0)
1439	free_irq(mgr->irq, mgr);
1440
1441	pci_release_regions(mgr->pci);
1442
1443	/* free hostport purgebuffer */
1444	if (mgr->hostport.area) {
1445	snd_dma_free_pages(dmab: &mgr->hostport);
1446	mgr->hostport.area = NULL;
1447	}
1448
1449	kfree(objp: mgr->prmh);
1450
1451	pci_disable_device(dev: mgr->pci);
1452	kfree(objp: mgr);
1453	return 0;
1454	}
1455
1456	/*
1457	* probe function - creates the card manager
1458	*/
1459	static int pcxhr_probe(struct pci_dev *pci,
1460	const struct pci_device_id *pci_id)
1461	{
1462	static int dev;
1463	struct pcxhr_mgr *mgr;
1464	unsigned int i;
1465	int err;
1466	size_t size;
1467	char *card_name;
1468
1469	if (dev >= SNDRV_CARDS)
1470	return -ENODEV;
1471	if (! enable[dev]) {
1472	dev++;
1473	return -ENOENT;
1474	}
1475
1476	/* enable PCI device */
1477	err = pci_enable_device(dev: pci);
1478	if (err < 0)
1479	return err;
1480	pci_set_master(dev: pci);
1481
1482	/* check if we can restrict PCI DMA transfers to 32 bits */
1483	if (dma_set_mask(dev: &pci->dev, DMA_BIT_MASK(32)) < 0) {
1484	dev_err(&pci->dev,
1485	"architecture does not support 32bit PCI busmaster DMA\n");
1486	pci_disable_device(dev: pci);
1487	return -ENXIO;
1488	}
1489
1490	/* alloc card manager */
1491	mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1492	if (! mgr) {
1493	pci_disable_device(dev: pci);
1494	return -ENOMEM;
1495	}
1496
1497	if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1498	kfree(objp: mgr);
1499	pci_disable_device(dev: pci);
1500	return -ENODEV;
1501	}
1502	card_name =
1503	pcxhr_board_params[pci_id->driver_data].board_name;
1504	mgr->playback_chips =
1505	pcxhr_board_params[pci_id->driver_data].playback_chips;
1506	mgr->capture_chips =
1507	pcxhr_board_params[pci_id->driver_data].capture_chips;
1508	mgr->fw_file_set =
1509	pcxhr_board_params[pci_id->driver_data].fw_file_set;
1510	mgr->firmware_num =
1511	pcxhr_board_params[pci_id->driver_data].firmware_num;
1512	mgr->mono_capture = mono[dev];
1513	mgr->is_hr_stereo = (mgr->playback_chips == 1);
1514	mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1515	mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1516
1517	if (mgr->is_hr_stereo)
1518	mgr->granularity = PCXHR_GRANULARITY_HR22;
1519	else
1520	mgr->granularity = PCXHR_GRANULARITY;
1521
1522	/* resource assignment */
1523	err = pci_request_regions(pci, card_name);
1524	if (err < 0) {
1525	kfree(objp: mgr);
1526	pci_disable_device(dev: pci);
1527	return err;
1528	}
1529	for (i = 0; i < 3; i++)
1530	mgr->port[i] = pci_resource_start(pci, i);
1531
1532	mgr->pci = pci;
1533	mgr->irq = -1;
1534
1535	if (request_threaded_irq(irq: pci->irq, handler: pcxhr_interrupt,
1536	thread_fn: pcxhr_threaded_irq, IRQF_SHARED,
1537	KBUILD_MODNAME, dev: mgr)) {
1538	dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq);
1539	pcxhr_free(mgr);
1540	return -EBUSY;
1541	}
1542	mgr->irq = pci->irq;
1543
1544	snprintf(buf: mgr->name, size: sizeof(mgr->name),
1545	fmt: "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i",
1546	mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1547
1548	/* ISR lock */
1549	mutex_init(&mgr->lock);
1550	mutex_init(&mgr->msg_lock);
1551
1552	/* init setup mutex*/
1553	mutex_init(&mgr->setup_mutex);
1554
1555	mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1556	sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1557	PCXHR_SIZE_MAX_STATUS),
1558	GFP_KERNEL);
1559	if (! mgr->prmh) {
1560	pcxhr_free(mgr);
1561	return -ENOMEM;
1562	}
1563
1564	for (i=0; i < PCXHR_MAX_CARDS; i++) {
1565	struct snd_card *card;
1566	char tmpid[16];
1567	int idx;
1568
1569	if (i >= max(mgr->playback_chips, mgr->capture_chips))
1570	break;
1571	mgr->num_cards++;
1572
1573	if (index[dev] < 0)
1574	idx = index[dev];
1575	else
1576	idx = index[dev] + i;
1577
1578	snprintf(buf: tmpid, size: sizeof(tmpid), fmt: "%s-%d",
1579	id[dev] ? id[dev] : card_name, i);
1580	err = snd_card_new(parent: &pci->dev, idx, xid: tmpid, THIS_MODULE,
1581	extra_size: 0, card_ret: &card);
1582
1583	if (err < 0) {
1584	dev_err(&pci->dev, "cannot allocate the card %d\n", i);
1585	pcxhr_free(mgr);
1586	return err;
1587	}
1588
1589	strscpy(card->driver, DRIVER_NAME);
1590	snprintf(buf: card->shortname, size: sizeof(card->shortname),
1591	fmt: "Digigram [PCM #%d]", i);
1592	snprintf(buf: card->longname, size: sizeof(card->longname),
1593	fmt: "%s [PCM #%d]", mgr->name, i);
1594
1595	err = pcxhr_create(mgr, card, idx: i);
1596	if (err < 0) {
1597	snd_card_free(card);
1598	pcxhr_free(mgr);
1599	return err;
1600	}
1601
1602	if (i == 0)
1603	/* init proc interface only for chip0 */
1604	pcxhr_proc_init(chip: mgr->chip[i]);
1605
1606	err = snd_card_register(card);
1607	if (err < 0) {
1608	pcxhr_free(mgr);
1609	return err;
1610	}
1611	}
1612
1613	/* create hostport purgebuffer */
1614	size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1615	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev: &pci->dev,
1616	size, dmab: &mgr->hostport) < 0) {
1617	pcxhr_free(mgr);
1618	return -ENOMEM;
1619	}
1620	/* init purgebuffer */
1621	memset(mgr->hostport.area, 0, size);
1622
1623	/* create a DSP loader */
1624	err = pcxhr_setup_firmware(mgr);
1625	if (err < 0) {
1626	pcxhr_free(mgr);
1627	return err;
1628	}
1629
1630	pci_set_drvdata(pdev: pci, data: mgr);
1631	dev++;
1632	return 0;
1633	}
1634
1635	static void pcxhr_remove(struct pci_dev *pci)
1636	{
1637	pcxhr_free(mgr: pci_get_drvdata(pdev: pci));
1638	}
1639
1640	static struct pci_driver pcxhr_driver = {
1641	.name = KBUILD_MODNAME,
1642	.id_table = pcxhr_ids,
1643	.probe = pcxhr_probe,
1644	.remove = pcxhr_remove,
1645	};
1646
1647	module_pci_driver(pcxhr_driver);
1648