| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * mt6357.h -- mt6357 ALSA SoC audio codec driver |
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| 4 | * |
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| 5 | * Copyright (c) 2024 Baylibre |
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| 6 | * Author: Nicolas Belin <nbelin@baylibre.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __MT6357_H__ |
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| 10 | #define __MT6357_H__ |
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| 11 | |
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| 12 | #include <linux/types.h> |
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| 13 | |
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| 14 | /* Reg bit defines */ |
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| 15 | /* MT6357_GPIO_DIR0 */ |
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| 16 | #define MT6357_GPIO8_DIR_MASK BIT(8) |
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| 17 | #define MT6357_GPIO8_DIR_INPUT 0 |
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| 18 | #define MT6357_GPIO8_DIR_OUTPUT BIT(8) |
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| 19 | #define MT6357_GPIO9_DIR_MASK BIT(9) |
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| 20 | #define MT6357_GPIO9_DIR_INPUT 0 |
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| 21 | #define MT6357_GPIO9_DIR_OUTPUT BIT(9) |
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| 22 | #define MT6357_GPIO10_DIR_MASK BIT(10) |
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| 23 | #define MT6357_GPIO10_DIR_INPUT 0 |
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| 24 | #define MT6357_GPIO10_DIR_OUTPUT BIT(10) |
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| 25 | #define MT6357_GPIO11_DIR_MASK BIT(11) |
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| 26 | #define MT6357_GPIO11_DIR_INPUT 0 |
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| 27 | #define MT6357_GPIO11_DIR_OUTPUT BIT(11) |
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| 28 | #define MT6357_GPIO12_DIR_MASK BIT(12) |
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| 29 | #define MT6357_GPIO12_DIR_INPUT 0 |
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| 30 | #define MT6357_GPIO12_DIR_OUTPUT BIT(12) |
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| 31 | #define MT6357_GPIO13_DIR_MASK BIT(13) |
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| 32 | #define MT6357_GPIO13_DIR_INPUT 0 |
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| 33 | #define MT6357_GPIO13_DIR_OUTPUT BIT(13) |
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| 34 | #define MT6357_GPIO14_DIR_MASK BIT(14) |
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| 35 | #define MT6357_GPIO14_DIR_INPUT 0 |
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| 36 | #define MT6357_GPIO14_DIR_OUTPUT BIT(14) |
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| 37 | #define MT6357_GPIO15_DIR_MASK BIT(15) |
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| 38 | #define MT6357_GPIO15_DIR_INPUT 0 |
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| 39 | #define MT6357_GPIO15_DIR_OUTPUT BIT(15) |
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| 40 | |
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| 41 | /* MT6357_GPIO_MODE2 */ |
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| 42 | #define MT6357_GPIO8_MODE_MASK GENMASK(2, 0) |
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| 43 | #define MT6357_GPIO8_MODE_AUD_CLK_MOSI BIT(0) |
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| 44 | #define MT6357_GPIO8_MODE_GPIO 0 |
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| 45 | #define MT6357_GPIO9_MODE_MASK GENMASK(5, 3) |
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| 46 | #define MT6357_GPIO9_MODE_AUD_DAT_MOSI0 BIT(3) |
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| 47 | #define MT6357_GPIO9_MODE_GPIO 0 |
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| 48 | #define MT6357_GPIO10_MODE_MASK GENMASK(8, 6) |
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| 49 | #define MT6357_GPIO10_MODE_AUD_DAT_MOSI1 BIT(6) |
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| 50 | #define MT6357_GPIO10_MODE_GPIO 0 |
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| 51 | #define MT6357_GPIO11_MODE_MASK GENMASK(11, 9) |
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| 52 | #define MT6357_GPIO11_MODE_AUD_SYNC_MOSI BIT(9) |
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| 53 | #define MT6357_GPIO11_MODE_GPIO 0 |
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| 54 | |
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| 55 | /* MT6357_GPIO_MODE2_SET */ |
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| 56 | #define MT6357_GPIO8_MODE_SET_MASK GENMASK(2, 0) |
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| 57 | #define MT6357_GPIO8_MODE_SET_AUD_CLK_MOSI BIT(0) |
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| 58 | #define MT6357_GPIO9_MODE_SET_MASK GENMASK(5, 3) |
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| 59 | #define MT6357_GPIO9_MODE_SET_AUD_DAT_MOSI0 BIT(3) |
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| 60 | #define MT6357_GPIO10_MODE_SET_MASK GENMASK(8, 6) |
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| 61 | #define MT6357_GPIO10_MODE_SET_AUD_DAT_MOSI1 BIT(6) |
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| 62 | #define MT6357_GPIO11_MODE_SET_MASK GENMASK(11, 9) |
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| 63 | #define MT6357_GPIO11_MODE_SET_AUD_SYNC_MOSI BIT(9) |
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| 64 | |
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| 65 | /* MT6357_GPIO_MODE2_CLR */ |
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| 66 | #define MT6357_GPIO_MODE2_CLEAR_ALL GENMASK(15, 0) |
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| 67 | |
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| 68 | /* MT6357_GPIO_MODE3 */ |
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| 69 | #define MT6357_GPIO12_MODE_MASK GENMASK(2, 0) |
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| 70 | #define MT6357_GPIO12_MODE_AUD_CLK_MISO BIT(0) |
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| 71 | #define MT6357_GPIO12_MODE_GPIO 0 |
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| 72 | #define MT6357_GPIO13_MODE_MASK GENMASK(5, 3) |
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| 73 | #define MT6357_GPIO13_MODE_AUD_DAT_MISO0 BIT(3) |
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| 74 | #define MT6357_GPIO13_MODE_GPIO 0 |
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| 75 | #define MT6357_GPIO14_MODE_MASK GENMASK(8, 6) |
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| 76 | #define MT6357_GPIO14_MODE_AUD_DAT_MISO1 BIT(6) |
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| 77 | #define MT6357_GPIO14_MODE_GPIO 0 |
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| 78 | #define MT6357_GPIO15_MODE_MASK GENMASK(11, 9) |
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| 79 | #define MT6357_GPIO15_MODE_AUD_SYNC_MISO BIT(9) |
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| 80 | #define MT6357_GPIO15_MODE_GPIO 0 |
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| 81 | |
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| 82 | /* MT6357_GPIO_MODE3_SET */ |
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| 83 | #define MT6357_GPIO12_MODE_SET_MASK GENMASK(2, 0) |
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| 84 | #define MT6357_GPIO12_MODE_SET_AUD_CLK_MISO BIT(0) |
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| 85 | #define MT6357_GPIO13_MODE_SET_MASK GENMASK(5, 3) |
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| 86 | #define MT6357_GPIO13_MODE_SET_AUD_DAT_MISO0 BIT(3) |
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| 87 | #define MT6357_GPIO14_MODE_SET_MASK GENMASK(8, 6) |
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| 88 | #define MT6357_GPIO14_MODE_SET_AUD_DAT_MISO1 BIT(6) |
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| 89 | #define MT6357_GPIO15_MODE_SET_MASK GENMASK(11, 9) |
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| 90 | #define MT6357_GPIO15_MODE_SET_AUD_SYNC_MISO BIT(9) |
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| 91 | |
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| 92 | /* MT6357_GPIO_MODE3_CLR */ |
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| 93 | #define MT6357_GPIO_MODE3_CLEAR_ALL GENMASK(15, 0) |
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| 94 | |
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| 95 | /* MT6357_DCXO_CW14 */ |
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| 96 | #define MT6357_XO_AUDIO_EN_M_SFT 13 |
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| 97 | #define MT6357_XO_AUDIO_EN_M_MASK BIT(13) |
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| 98 | #define MT6357_XO_AUDIO_EN_M_ENABLE BIT(13) |
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| 99 | #define MT6357_XO_AUDIO_EN_M_DISABLE 0 |
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| 100 | |
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| 101 | /* MT6357_AUD_TOP_CKPDN_CON0 */ |
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| 102 | #define MT6357_AUDNCP_CK_PDN_SFT 6 |
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| 103 | #define MT6357_ZCD13M_CK_PDN_SFT 5 |
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| 104 | #define MT6357_AUDIF_CK_PDN_SFT 2 |
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| 105 | #define MT6357_AUD_CK_PDN_SFT 1 |
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| 106 | |
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| 107 | /* MT6357_AUDNCP_CLKDIV_CON0 */ |
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| 108 | #define MT6357_DIVCKS_CHG BIT(0) |
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| 109 | |
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| 110 | /* MT6357_AUDNCP_CLKDIV_CON1 */ |
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| 111 | #define MT6357_DIVCKS_ON BIT(0) |
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| 112 | |
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| 113 | /* MT6357_AUDNCP_CLKDIV_CON3 */ |
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| 114 | #define MT6357_DIVCKS_PWD_NCP_MASK BIT(0) |
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| 115 | #define MT6357_DIVCKS_PWD_NCP_DISABLE BIT(0) |
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| 116 | #define MT6357_DIVCKS_PWD_NCP_ENABLE 0 |
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| 117 | |
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| 118 | /* MT6357_AUDNCP_CLKDIV_CON4 */ |
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| 119 | #define MT6357_DIVCKS_PWD_NCP_ST_SEL_MASK GENMASK(1, 0) |
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| 120 | #define MT6357_DIVCKS_PWD_NCP_ST_50US 0 |
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| 121 | #define MT6357_DIVCKS_PWD_NCP_ST_100US 1 |
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| 122 | #define MT6357_DIVCKS_PWD_NCP_ST_150US 2 |
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| 123 | #define MT6357_DIVCKS_PWD_NCP_ST_200US 3 |
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| 124 | |
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| 125 | /* MT6357_AFE_UL_DL_CON0 */ |
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| 126 | #define MT6357_AFE_UL_LR_SWAP_SFT 15 |
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| 127 | #define MT6357_AFE_ON_SFT 0 |
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| 128 | |
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| 129 | /* MT6357_AFE_DL_SRC2_CON0_L */ |
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| 130 | #define MT6357_DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 |
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| 131 | |
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| 132 | /* MT6357_AFE_UL_SRC_CON0_H */ |
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| 133 | #define MT6357_C_TWO_DIGITAL_MIC_CTL_MASK BIT(7) |
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| 134 | #define MT6357_C_TWO_DIGITAL_MIC_ENABLE BIT(7) |
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| 135 | #define MT6357_C_TWO_DIGITAL_MIC_DISABLE 0 |
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| 136 | |
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| 137 | /* MT6357_AFE_UL_SRC_CON0_L */ |
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| 138 | #define MT6357_UL_SDM_3_LEVEL_CTL_MASK BIT(1) |
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| 139 | #define MT6357_UL_SDM_3_LEVEL_SELECT BIT(1) |
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| 140 | #define MT6357_UL_SDM_3_LEVEL_DESELECT 0 |
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| 141 | #define MT6357_UL_SRC_ON_TMP_CTL_MASK BIT(0) |
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| 142 | #define MT6357_UL_SRC_ENABLE BIT(0) |
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| 143 | #define MT6357_UL_SRC_DISABLE 0 |
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| 144 | |
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| 145 | /* MT6357_AFE_TOP_CON0 */ |
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| 146 | #define MT6357_UL_SINE_ON_SFT 1 |
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| 147 | #define MT6357_UL_SINE_ON_MASK BIT(1) |
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| 148 | #define MT6357_DL_SINE_ON_SFT 0 |
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| 149 | #define MT6357_DL_SINE_ON_MASK BIT(0) |
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| 150 | |
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| 151 | /* MT6357_AUDIO_TOP_CON0 */ |
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| 152 | #define MT6357_PDN_LPBK_CTL_SFT 15 |
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| 153 | #define MT6357_PDN_AFE_CTL_SFT 7 |
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| 154 | #define MT6357_PDN_DAC_CTL_SFT 6 |
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| 155 | #define MT6357_PDN_ADC_CTL_SFT 5 |
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| 156 | #define MT6357_PDN_I2S_DL_CTL_SFT 3 |
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| 157 | #define MT6357_PWR_CLK_DIS_CTL_SFT 2 |
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| 158 | #define MT6357_PDN_AFE_TESTMODEL_CTL_SFT 1 |
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| 159 | #define MT6357_PDN_RESERVED_SFT 0 |
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| 160 | |
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| 161 | /* MT6357_AFUNC_AUD_CON0 */ |
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| 162 | #define MT6357_CCI_AUD_ANACK_INVERT BIT(15) |
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| 163 | #define MT6357_CCI_AUD_ANACK_NORMAL 0 |
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| 164 | #define MT6357_CCI_AUDIO_FIFO_WPTR_SFT 12 |
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| 165 | #define MT6357_CCI_SCRAMBLER_CG_ENABLE BIT(11) |
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| 166 | #define MT6357_CCI_SCRAMBLER_CG_DISABLE 0 |
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| 167 | #define MT6357_CCI_LCK_INV_OUT_OF_PHASE BIT(10) |
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| 168 | #define MT6357_CCI_LCK_INV_IN_PHASE 0 |
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| 169 | #define MT6357_CCI_RAND_ENABLE BIT(9) |
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| 170 | #define MT6357_CCI_RAND_DISABLE 0 |
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| 171 | #define MT6357_CCI_SPLT_SCRMB_CLK_ON BIT(8) |
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| 172 | #define MT6357_CCI_SPLT_SCRMB_CLK_OFF 0 |
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| 173 | #define MT6357_CCI_SPLT_SCRMB_ON BIT(7) |
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| 174 | #define MT6357_CCI_SPLT_SCRMB_OFF 0 |
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| 175 | #define MT6357_CCI_AUD_IDAC_TEST_EN_FROM_TEST_IN BIT(6) |
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| 176 | #define MT6357_CCI_AUD_IDAC_TEST_EN_NORMAL_PATH 0 |
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| 177 | #define MT6357_CCI_ZERO_PADDING_DISABLE BIT(5) |
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| 178 | #define MT6357_CCI_ZERO_PADDING_ENABLE 0 |
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| 179 | #define MT6357_CCI_AUD_SPLIT_TEST_EN_FROM_TEST_IN BIT(4) |
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| 180 | #define MT6357_CCI_AUD_SPLIT_TEST_EN_NORMAL_PATH 0 |
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| 181 | #define MT6357_CCI_AUD_SDM_MUTE_L_REG_CTL BIT(3) |
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| 182 | #define MT6357_CCI_AUD_SDM_MUTE_L_NO_CTL 0 |
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| 183 | #define MT6357_CCI_AUD_SDM_MUTE_R_REG_CTL BIT(2) |
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| 184 | #define MT6357_CCI_AUD_SDM_MUTE_R_NO_CTL 0 |
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| 185 | #define MT6357_CCI_AUD_SDM_7BIT_FROM_SPLITTER3 BIT(1) |
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| 186 | #define MT6357_CCI_AUD_SDM_7BIT_FROM_SPLITTER1 0 |
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| 187 | #define MT6357_CCI_SCRAMBLER_ENABLE BIT(0) |
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| 188 | #define MT6357_CCI_SCRAMBLER_DISABLE 0 |
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| 189 | |
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| 190 | /* MT6357_AFUNC_AUD_CON2 */ |
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| 191 | #define MT6357_CCI_AUDIO_FIFO_ENABLE BIT(3) |
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| 192 | #define MT6357_CCI_AUDIO_FIFO_DISABLE 0 |
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| 193 | #define MT6357_CCI_ACD_MODE_NORMAL_PATH BIT(2) |
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| 194 | #define MT6357_CCI_ACD_MODE_TEST_PATH 0 |
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| 195 | #define MT6357_CCI_AFIFO_CLK_PWDB_ON BIT(1) |
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| 196 | #define MT6357_CCI_AFIFO_CLK_PWDB_DOWN 0 |
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| 197 | #define MT6357_CCI_ACD_FUNC_RSTB_RELEASE BIT(0) |
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| 198 | #define MT6357_CCI_ACD_FUNC_RSTB_RESET 0 |
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| 199 | |
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| 200 | /* MT6357_AFE_ADDA_MTKAIF_CFG0 */ |
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| 201 | #define MT6357_ADDA_MTKAIF_LPBK_CTL_MASK BIT(1) |
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| 202 | #define MT6357_ADDA_MTKAIF_LPBK_ENABLE BIT(1) |
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| 203 | #define MT6357_ADDA_MTKAIF_LPBK_DISABLE 0 |
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| 204 | |
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| 205 | /* MT6357_AFE_SGEN_CFG0 */ |
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| 206 | #define MT6357_SGEN_DAC_EN_CTL_SFT 7 |
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| 207 | #define MT6357_SGEN_DAC_ENABLE BIT(7) |
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| 208 | #define MT6357_SGEN_MUTE_SW_CTL_SFT 6 |
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| 209 | #define MT6357_SGEN_MUTE_SW_DISABLE 0 |
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| 210 | |
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| 211 | /* MT6357_AFE_DCCLK_CFG0 */ |
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| 212 | #define MT6357_DCCLK_DIV_MASK GENMASK(15, 5) |
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| 213 | #define MT6357_DCCLK_DIV_SFT 5 |
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| 214 | #define MT6357_DCCLK_DIV_RUN_VALUE (32 << MT6357_DCCLK_DIV_SFT) |
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| 215 | #define MT6357_DCCLK_DIV_STOP_VALUE (259 << MT6357_DCCLK_DIV_SFT) |
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| 216 | #define MT6357_DCCLK_PDN_MASK BIT(1) |
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| 217 | #define MT6357_DCCLK_PDN BIT(1) |
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| 218 | #define MT6357_DCCLK_OUTPUT 0 |
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| 219 | #define MT6357_DCCLK_GEN_ON_MASK BIT(0) |
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| 220 | #define MT6357_DCCLK_GEN_ON BIT(0) |
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| 221 | #define MT6357_DCCLK_GEN_OFF 0 |
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| 222 | |
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| 223 | /* MT6357_AFE_DCCLK_CFG1 */ |
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| 224 | #define MT6357_DCCLK_RESYNC_BYPASS_MASK BIT(8) |
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| 225 | #define MT6357_DCCLK_RESYNC_BYPASS BIT(8) |
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| 226 | |
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| 227 | /* MT6357_AFE_AUD_PAD_TOP */ |
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| 228 | #define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK GENMASK(15, 8) |
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| 229 | #define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_ENABLE (BIT(13) | BIT(12) | BIT(8)) |
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| 230 | #define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_DISABLE (BIT(13) | BIT(12)) |
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| 231 | #define MT6357_AUD_PAD_TX_FIFO_LPBK_MASK GENMASK(7, 0) |
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| 232 | #define MT6357_AUD_PAD_TX_FIFO_LPBK_ENABLE (BIT(5) | BIT(4) | BIT(0)) |
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| 233 | #define MT6357_AUD_PAD_TX_FIFO_LPBK_DISABLE 0 |
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| 234 | |
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| 235 | /* MT6357_AUDENC_ANA_CON0 */ |
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| 236 | #define MT6357_AUDADCLINPUTSEL_MASK GENMASK(14, 13) |
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| 237 | #define MT6357_AUDADCLINPUTSEL_PREAMPLIFIER BIT(14) |
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| 238 | #define MT6357_AUDADCLINPUTSEL_IDLE 0 |
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| 239 | #define MT6357_AUDADCLPWRUP_SFT 12 |
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| 240 | #define MT6357_AUDADCLPWRUP_MASK BIT(12) |
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| 241 | #define MT6357_AUDADCLPWRUP BIT(12) |
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| 242 | #define MT6357_AUDADCLPWRDOWN 0 |
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| 243 | #define MT6357_AUDPREAMPLGAIN_SFT 8 |
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| 244 | #define MT6357_AUDPREAMPLGAIN_MASK GENMASK(10, 8) |
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| 245 | #define MT6357_AUDPREAMPLGAIN_MAX 4 |
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| 246 | #define MT6357_AUDPREAMPLINPUTSEL_SFT 6 |
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| 247 | #define MT6357_AUDPREAMPLINPUTSEL_MASK_NOSFT GENMASK(1, 0) |
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| 248 | #define MT6357_AUDPREAMPLDCPRECHARGE_MASK BIT(2) |
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| 249 | #define MT6357_AUDPREAMPLDCPRECHARGE_ENABLE BIT(2) |
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| 250 | #define MT6357_AUDPREAMPLDCPRECHARGE_DISABLE 0 |
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| 251 | #define MT6357_AUDPREAMPLDCCEN_MASK BIT(1) |
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| 252 | #define MT6357_AUDPREAMPLDCCEN_DC BIT(1) |
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| 253 | #define MT6357_AUDPREAMPLDCCEN_AC 0 |
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| 254 | #define MT6357_AUDPREAMPLON_MASK BIT(0) |
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| 255 | #define MT6357_AUDPREAMPLON_ENABLE BIT(0) |
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| 256 | #define MT6357_AUDPREAMPLON_DISABLE 0 |
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| 257 | |
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| 258 | /* MT6357_AUDENC_ANA_CON1 */ |
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| 259 | #define MT6357_AUDADCRINPUTSEL_MASK GENMASK(14, 13) |
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| 260 | #define MT6357_AUDADCRINPUTSEL_PREAMPLIFIER BIT(14) |
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| 261 | #define MT6357_AUDADCRINPUTSEL_IDLE 0 |
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| 262 | #define MT6357_AUDADCRPWRUP_SFT 12 |
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| 263 | #define MT6357_AUDADCRPWRUP_MASK BIT(12) |
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| 264 | #define MT6357_AUDADCRPWRUP BIT(12) |
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| 265 | #define MT6357_AUDADCRPWRDOWN 0 |
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| 266 | #define MT6357_AUDPREAMPRGAIN_SFT 8 |
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| 267 | #define MT6357_AUDPREAMPRGAIN_MASK GENMASK(10, 8) |
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| 268 | #define MT6357_AUDPREAMPRGAIN_MAX 4 |
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| 269 | #define MT6357_AUDPREAMPRINPUTSEL_SFT 6 |
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| 270 | #define MT6357_AUDPREAMPRINPUTSEL_MASK_NOSFT GENMASK(1, 0) |
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| 271 | #define MT6357_AUDPREAMPRDCPRECHARGE_MASK BIT(2) |
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| 272 | #define MT6357_AUDPREAMPRDCPRECHARGE_ENABLE BIT(2) |
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| 273 | #define MT6357_AUDPREAMPRDCPRECHARGE_DISABLE 0 |
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| 274 | #define MT6357_AUDPREAMPRDCCEN_MASK BIT(1) |
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| 275 | #define MT6357_AUDPREAMPRDCCEN_DC BIT(1) |
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| 276 | #define MT6357_AUDPREAMPRDCCEN_AC 0 |
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| 277 | #define MT6357_AUDPREAMPRON_MASK BIT(0) |
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| 278 | #define MT6357_AUDPREAMPRON_ENABLE BIT(0) |
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| 279 | #define MT6357_AUDPREAMPRON_DISABLE 0 |
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| 280 | |
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| 281 | /* MT6357_AUDENC_ANA_CON6 */ |
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| 282 | #define MT6357_CLKSQ_EN_SFT 0 |
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| 283 | |
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| 284 | /* MT6357_AUDENC_ANA_CON7 */ |
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| 285 | #define MT6357_AUDDIGMICBIAS_MASK GENMASK(2, 1) |
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| 286 | #define MT6357_AUDDIGMICBIAS_DEFAULT_VALUE BIT(2) |
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| 287 | #define MT6357_AUDDIGMICBIAS_OFF 0 |
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| 288 | #define MT6357_AUDDIGMICEN_MASK BIT(0) |
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| 289 | #define MT6357_AUDDIGMICEN_ENABLE BIT(0) |
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| 290 | #define MT6357_AUDDIGMICEN_DISABLE 0 |
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| 291 | |
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| 292 | /* MT6357_AUDENC_ANA_CON8 */ |
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| 293 | #define MT6357_AUD_MICBIAS0_DCSW2N_EN_MASK BIT(14) |
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| 294 | #define MT6357_AUD_MICBIAS0_DCSW2N_ENABLE BIT(14) |
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| 295 | #define MT6357_AUD_MICBIAS0_DCSW2N_DISABLE 0 |
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| 296 | #define MT6357_AUD_MICBIAS0_DCSW2P2_EN_MASK BIT(13) |
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| 297 | #define MT6357_AUD_MICBIAS0_DCSW2P2_ENABLE BIT(13) |
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| 298 | #define MT6357_AUD_MICBIAS0_DCSW2P2_DISABLE 0 |
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| 299 | #define MT6357_AUD_MICBIAS0_DCSW2P1_EN_MASK BIT(12) |
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| 300 | #define MT6357_AUD_MICBIAS0_DCSW2P1_ENABLE BIT(12) |
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| 301 | #define MT6357_AUD_MICBIAS0_DCSW2P1_DISABLE 0 |
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| 302 | #define MT6357_AUD_MICBIAS0_DCSW0N_EN_MASK BIT(10) |
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| 303 | #define MT6357_AUD_MICBIAS0_DCSW0N_ENABLE BIT(10) |
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| 304 | #define MT6357_AUD_MICBIAS0_DCSWN_DISABLE 0 |
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| 305 | #define MT6357_AUD_MICBIAS0_DCSW0P2_EN_MASK BIT(9) |
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| 306 | #define MT6357_AUD_MICBIAS0_DCSW0P2_ENABLE BIT(9) |
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| 307 | #define MT6357_AUD_MICBIAS0_DCSW0P2_DISABLE 0 |
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| 308 | #define MT6357_AUD_MICBIAS0_DCSW0P1_EN_MASK BIT(8) |
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| 309 | #define MT6357_AUD_MICBIAS0_DCSW0P1_ENABLE BIT(8) |
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| 310 | #define MT6357_AUD_MICBIAS0_DCSW0P1_DISABLE 0 |
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| 311 | #define MT6357_AUD_MICBIAS0_VREF_MASK GENMASK(6, 4) |
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| 312 | #define MT6357_AUD_MICBIAS0_VREF_SFT 4 |
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| 313 | #define MT6357_AUD_MICBIAS0_PWD_SFT 0 |
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| 314 | |
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| 315 | #define MT6357_AUD_MICBIAS0_DC_MASK (MT6357_AUD_MICBIAS0_DCSW2N_EN_MASK | \ |
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| 316 | MT6357_AUD_MICBIAS0_DCSW2P2_EN_MASK | \ |
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| 317 | MT6357_AUD_MICBIAS0_DCSW2P1_EN_MASK | \ |
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| 318 | MT6357_AUD_MICBIAS0_DCSW0N_EN_MASK | \ |
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| 319 | MT6357_AUD_MICBIAS0_DCSW0P2_EN_MASK | \ |
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| 320 | MT6357_AUD_MICBIAS0_DCSW0P1_EN_MASK) |
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| 321 | |
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| 322 | #define MT6357_AUD_MICBIAS0_DC_ENABLE_ALL (MT6357_AUD_MICBIAS0_DCSW2N_ENABLE | \ |
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| 323 | MT6357_AUD_MICBIAS0_DCSW2P2_ENABLE | \ |
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| 324 | MT6357_AUD_MICBIAS0_DCSW2P1_ENABLE | \ |
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| 325 | MT6357_AUD_MICBIAS0_DCSW0N_ENABLE | \ |
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| 326 | MT6357_AUD_MICBIAS0_DCSW0P2_ENABLE | \ |
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| 327 | MT6357_AUD_MICBIAS0_DCSW0P1_ENABLE) |
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| 328 | |
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| 329 | #define MT6357_AUD_MICBIAS0_DC_ENABLE_P1 (MT6357_AUD_MICBIAS0_DCSW2P1_ENABLE | \ |
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| 330 | MT6357_AUD_MICBIAS0_DCSW0P1_ENABLE) |
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| 331 | |
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| 332 | #define MT6357_AUD_MICBIAS0_DC_DISABLE_ALL 0 |
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| 333 | |
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| 334 | /* MT6357_AUDENC_ANA_CON9 */ |
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| 335 | #define MT6357_AUD_MICBIAS1_DCSW1P_EN_MASK BIT(8) |
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| 336 | #define MT6357_AUD_MICBIAS1_DCSW1P_ENABLE BIT(8) |
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| 337 | #define MT6357_AUD_MICBIAS1_DCSW1P_DISABLE 0 |
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| 338 | #define MT6357_AUD_MICBIAS1_VREF_MASK GENMASK(6, 4) |
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| 339 | #define MT6357_AUD_MICBIAS1_VREF_SFT 4 |
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| 340 | #define MT6357_AUD_MICBIAS1_PWD_SFT 0 |
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| 341 | |
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| 342 | /* MT6357_AUDDEC_ANA_CON0 */ |
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| 343 | #define MT6357_AUD_HPR_SC_VAUDP15_MASK BIT(13) |
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| 344 | #define MT6357_AUD_HPR_SC_VAUDP15_DISABLE BIT(13) |
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| 345 | #define MT6357_AUD_HPR_SC_VAUDP15_ENABLE 0 |
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| 346 | #define MT6357_AUD_HPL_SC_VAUDP15_MASK BIT(12) |
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| 347 | #define MT6357_AUD_HPL_SC_VAUDP15_DISABLE BIT(12) |
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| 348 | #define MT6357_AUD_HPL_SC_VAUDP15_ENABLE 0 |
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| 349 | #define MT6357_AUD_HPR_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0) |
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| 350 | #define MT6357_AUD_HPR_MUX_INPUT_VAUDP15_SFT 10 |
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| 351 | #define MT6357_AUD_HPL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0) |
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| 352 | #define MT6357_AUD_HPL_MUX_INPUT_VAUDP15_SFT 8 |
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| 353 | #define MT6357_AUD_HPR_BIAS_VAUDP15_MASK BIT(7) |
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| 354 | #define MT6357_AUD_HPR_BIAS_VAUDP15_ENABLE BIT(7) |
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| 355 | #define MT6357_AUD_HPR_BIAS_VAUDP15_DISABLE 0 |
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| 356 | #define MT6357_AUD_HPL_BIAS_VAUDP15_MASK BIT(6) |
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| 357 | #define MT6357_AUD_HPL_BIAS_VAUDP15_ENABLE BIT(6) |
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| 358 | #define MT6357_AUD_HPL_BIAS_VAUDP15_DISABLE 0 |
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| 359 | #define MT6357_AUD_HPR_PWRUP_VAUDP15_MASK BIT(5) |
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| 360 | #define MT6357_AUD_HPR_PWRUP_VAUDP15_ENABLE BIT(5) |
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| 361 | #define MT6357_AUD_HPR_PWRUP_VAUDP15_DISABLE 0 |
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| 362 | #define MT6357_AUD_HPL_PWRUP_VAUDP15_MASK BIT(4) |
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| 363 | #define MT6357_AUD_HPL_PWRUP_VAUDP15_ENABLE BIT(4) |
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| 364 | #define MT6357_AUD_HPL_PWRUP_VAUDP15_DISABLE 0 |
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| 365 | #define MT6357_AUD_DACL_PWRUP_VA28_MASK BIT(3) |
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| 366 | #define MT6357_AUD_DACL_PWRUP_VA28_ENABLE BIT(3) |
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| 367 | #define MT6357_AUD_DACL_PWRUP_VA28_DISABLE 0 |
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| 368 | #define MT6357_AUD_DACR_PWRUP_VA28_MASK BIT(2) |
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| 369 | #define MT6357_AUD_DACR_PWRUP_VA28_ENABLE BIT(2) |
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| 370 | #define MT6357_AUD_DACR_PWRUP_VA28_DISABLE 0 |
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| 371 | #define MT6357_AUD_DACR_PWRUP_VAUDP15_MASK BIT(1) |
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| 372 | #define MT6357_AUD_DACR_PWRUP_VAUDP15_ENABLE BIT(1) |
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| 373 | #define MT6357_AUD_DACR_PWRUP_VAUDP15_DISABLE 0 |
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| 374 | #define MT6357_AUD_DACL_PWRUP_VAUDP15_MASK BIT(0) |
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| 375 | #define MT6357_AUD_DACL_PWRUP_VAUDP15_ENABLE BIT(0) |
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| 376 | #define MT6357_AUD_DACL_PWRUP_VAUDP15_DISABLE 0 |
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| 377 | |
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| 378 | /* MT6357_AUDDEC_ANA_CON1 */ |
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| 379 | #define MT6357_HPROUT_STG_CTRL_VAUDP15_MASK GENMASK(14, 12) |
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| 380 | #define MT6357_HPROUT_STG_CTRL_VAUDP15_SFT 12 |
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| 381 | #define MT6357_HPLOUT_STG_CTRL_VAUDP15_MASK GENMASK(10, 8) |
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| 382 | #define MT6357_HPLOUT_STG_CTRL_VAUDP15_SFT 8 |
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| 383 | #define MT6357_HPLOUT_STG_CTRL_VAUDP15_MAX 7 |
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| 384 | #define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_MASK BIT(7) |
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| 385 | #define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_ENABLE BIT(7) |
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| 386 | #define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_DISABLE 0 |
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| 387 | #define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_MASK BIT(6) |
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| 388 | #define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_ENABLE BIT(6) |
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| 389 | #define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_DISABLE 0 |
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| 390 | #define MT6357_HPR_AUX_FBRSW_VAUDP15_MASK BIT(5) |
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| 391 | #define MT6357_HPR_AUX_FBRSW_VAUDP15_ENABLE BIT(5) |
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| 392 | #define MT6357_HPR_AUX_FBRSW_VAUDP15_DISABLE 0 |
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| 393 | #define MT6357_HPL_AUX_FBRSW_VAUDP15_MASK BIT(4) |
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| 394 | #define MT6357_HPL_AUX_FBRSW_VAUDP15_ENABLE BIT(4) |
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| 395 | #define MT6357_HPL_AUX_FBRSW_VAUDP15_DISABLE 0 |
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| 396 | #define MT6357_HPROUT_AUX_PWRUP_VAUDP15_MASK BIT(3) |
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| 397 | #define MT6357_HPROUT_AUX_PWRUP_VAUDP15_ENABLE BIT(3) |
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| 398 | #define MT6357_HPROUT_AUX_PWRUP_VAUDP15_DISABLE 0 |
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| 399 | #define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_MASK BIT(2) |
|---|
| 400 | #define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_ENABLE BIT(2) |
|---|
| 401 | #define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_DISABLE 0 |
|---|
| 402 | #define MT6357_HPROUT_PWRUP_VAUDP15_MASK BIT(1) |
|---|
| 403 | #define MT6357_HPROUT_PWRUP_VAUDP15_ENABLE BIT(1) |
|---|
| 404 | #define MT6357_HPROUT_PWRUP_VAUDP15_DISABLE 0 |
|---|
| 405 | #define MT6357_HPLOUT_PWRUP_VAUDP15_MASK BIT(0) |
|---|
| 406 | #define MT6357_HPLOUT_PWRUP_VAUDP15_ENABLE BIT(0) |
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| 407 | #define MT6357_HPLOUT_PWRUP_VAUDP15_DISABLE 0 |
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| 408 | |
|---|
| 409 | /* MT6357_AUDDEC_ANA_CON2 */ |
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| 410 | #define MT6357_HPP_SHORT_2VCM_VAUDP15_MASK BIT(10) |
|---|
| 411 | #define MT6357_HPP_SHORT_2VCM_VAUDP15_ENABLE BIT(10) |
|---|
| 412 | #define MT6357_HPP_SHORT_2VCM_VAUDP15_DISABLE 0 |
|---|
| 413 | #define MT6357_AUD_REFN_DERES_VAUDP15_MASK BIT(9) |
|---|
| 414 | #define MT6357_AUD_REFN_DERES_VAUDP15_ENABLE BIT(9) |
|---|
| 415 | #define MT6357_AUD_REFN_DERES_VAUDP15_DISABLE 0 |
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| 416 | #define MT6357_HPROUT_STB_ENH_VAUDP15_MASK GENMASK(6, 4) |
|---|
| 417 | #define MT6357_HPROUT_STB_ENH_VAUDP15_OPEN 0 |
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| 418 | #define MT6357_HPROUT_STB_ENH_VAUDP15_NOPEN_P250 BIT(4) |
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| 419 | #define MT6357_HPROUT_STB_ENH_VAUDP15_N470_POPEN BIT(5) |
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| 420 | #define MT6357_HPROUT_STB_ENH_VAUDP15_N470_P250 (BIT(4) | BIT(5)) |
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| 421 | #define MT6357_HPROUT_STB_ENH_VAUDP15_NOPEN_P470 (BIT(4) | BIT(6)) |
|---|
| 422 | #define MT6357_HPROUT_STB_ENH_VAUDP15_N470_P470 (BIT(4) | BIT(5) | BIT(6)) |
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| 423 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_MASK GENMASK(2, 0) |
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| 424 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_OPEN 0 |
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| 425 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_NOPEN_P250 BIT(0) |
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| 426 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_POPEN BIT(1) |
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| 427 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P250 (BIT(0) | BIT(1)) |
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| 428 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_NOPEN_P470 (BIT(0) | BIT(2)) |
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| 429 | #define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P470 (BIT(0) | BIT(1) | BIT(2)) |
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| 430 | |
|---|
| 431 | /* MT6357_AUDDEC_ANA_CON3 */ |
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| 432 | #define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_MASK BIT(7) |
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| 433 | #define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_ENABLE BIT(7) |
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| 434 | #define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_DISABLE 0 |
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| 435 | #define MT6357_AUD_HS_SC_VAUDP15_MASK BIT(4) |
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| 436 | #define MT6357_AUD_HS_SC_VAUDP15_DISABLE BIT(4) |
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| 437 | #define MT6357_AUD_HS_SC_VAUDP15_ENABLE 0 |
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| 438 | #define MT6357_AUD_HS_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0) |
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| 439 | #define MT6357_AUD_HS_MUX_INPUT_VAUDP15_SFT 2 |
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| 440 | #define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_MASK BIT(1) |
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| 441 | #define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_ENABLE BIT(1) |
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| 442 | #define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_DISABLE 0 |
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| 443 | #define MT6357_AUD_HS_PWRUP_VAUDP15_MASK BIT(0) |
|---|
| 444 | #define MT6357_AUD_HS_PWRUP_VAUDP15_ENABLE BIT(0) |
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| 445 | #define MT6357_AUD_HS_PWRUP_VAUDP15_DISABLE 0 |
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| 446 | |
|---|
| 447 | /* MT6357_AUDDEC_ANA_CON4 */ |
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| 448 | #define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_MASK BIT(8) |
|---|
| 449 | #define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_ENABLE BIT(8) |
|---|
| 450 | #define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_DISABLE 0 |
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| 451 | #define MT6357_AUD_LOL_SC_VAUDP15_MASK BIT(4) |
|---|
| 452 | #define MT6357_AUD_LOL_SC_VAUDP15_DISABLE BIT(4) |
|---|
| 453 | #define MT6357_AUD_LOL_SC_VAUDP15_ENABLE 0 |
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| 454 | #define MT6357_AUD_LOL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0) |
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| 455 | #define MT6357_AUD_LOL_MUX_INPUT_VAUDP15_SFT 2 |
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| 456 | #define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_MASK BIT(1) |
|---|
| 457 | #define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_ENABLE BIT(1) |
|---|
| 458 | #define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_DISABLE 0 |
|---|
| 459 | #define MT6357_AUD_LOL_PWRUP_VAUDP15_MASK BIT(0) |
|---|
| 460 | #define MT6357_AUD_LOL_PWRUP_VAUDP15_ENABLE BIT(0) |
|---|
| 461 | #define MT6357_AUD_LOL_PWRUP_VAUDP15_DISABLE 0 |
|---|
| 462 | |
|---|
| 463 | /* MT6357_AUDDEC_ANA_CON6 */ |
|---|
| 464 | #define MT6357_HP_AUX_LOOP_GAIN_MASK GENMASK(15, 12) |
|---|
| 465 | #define MT6357_HP_AUX_LOOP_GAIN_SFT 12 |
|---|
| 466 | #define MT6357_HP_AUX_LOOP_GAIN_MAX 0x0f |
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| 467 | #define MT6357_HPR_AUX_CMFB_LOOP_MASK BIT(11) |
|---|
| 468 | #define MT6357_HPR_AUX_CMFB_LOOP_ENABLE BIT(11) |
|---|
| 469 | #define MT6357_HPR_AUX_CMFB_LOOP_DISABLE 0 |
|---|
| 470 | #define MT6357_HPL_AUX_CMFB_LOOP_MASK BIT(10) |
|---|
| 471 | #define MT6357_HPL_AUX_CMFB_LOOP_ENABLE BIT(10) |
|---|
| 472 | #define MT6357_HPL_AUX_CMFB_LOOP_DISABLE 0 |
|---|
| 473 | #define MT6357_HPRL_MAIN_CMFB_LOOP_MASK BIT(9) |
|---|
| 474 | #define MT6357_HPRL_MAIN_CMFB_LOOP_ENABLE BIT(9) |
|---|
| 475 | #define MT6357_HPRL_MAIN_CMFB_LOOP_DISABLE 0 |
|---|
| 476 | #define MT6357_HP_CMFB_RST_MASK BIT(7) |
|---|
| 477 | #define MT6357_HP_CMFB_RST_NORMAL BIT(7) |
|---|
| 478 | #define MT6357_HP_CMFB_RST_RESET 0 |
|---|
| 479 | #define MT6357_DAC_LOW_NOISE_MODE_MASK BIT(0) |
|---|
| 480 | #define MT6357_DAC_LOW_NOISE_MODE_ENABLE BIT(0) |
|---|
| 481 | #define MT6357_DAC_LOW_NOISE_MODE_DISABLE 0 |
|---|
| 482 | |
|---|
| 483 | /* MT6357_AUDDEC_ANA_CON7 */ |
|---|
| 484 | #define MT6357_HP_IVBUF_DEGAIN_SFT 2 |
|---|
| 485 | #define MT6357_HP_IVBUF_DEGAIN_MAX 1 |
|---|
| 486 | |
|---|
| 487 | /* MT6357_AUDDEC_ANA_CON10 */ |
|---|
| 488 | #define MT6357_AUD_IBIAS_PWRDN_VAUDP15_MASK BIT(8) |
|---|
| 489 | #define MT6357_AUD_IBIAS_PWRDN_VAUDP15_DISABLE BIT(8) |
|---|
| 490 | #define MT6357_AUD_IBIAS_PWRDN_VAUDP15_ENABLE 0 |
|---|
| 491 | |
|---|
| 492 | /* MT6357_AUDDEC_ANA_CON11 */ |
|---|
| 493 | #define MT6357_RSTB_ENCODER_VA28_MASK BIT(5) |
|---|
| 494 | #define MT6357_RSTB_ENCODER_VA28_ENABLE BIT(5) |
|---|
| 495 | #define MT6357_RSTB_ENCODER_VA28_DISABLE 0 |
|---|
| 496 | #define MT6357_AUDGLB_PWRDN_VA28_SFT 4 |
|---|
| 497 | #define MT6357_RSTB_DECODER_VA28_MASK BIT(0) |
|---|
| 498 | #define MT6357_RSTB_DECODER_VA28_ENABLE BIT(0) |
|---|
| 499 | #define MT6357_RSTB_DECODER_VA28_DISABLE 0 |
|---|
| 500 | |
|---|
| 501 | /* MT6357_AUDDEC_ANA_CON12 */ |
|---|
| 502 | #define MT6357_VA28REFGEN_EN_VA28_MASK BIT(13) |
|---|
| 503 | #define MT6357_VA28REFGEN_EN_VA28_ENABLE BIT(13) |
|---|
| 504 | #define MT6357_VA28REFGEN_EN_VA28_DISABLE 0 |
|---|
| 505 | #define MT6357_VA33REFGEN_EN_VA18_MASK BIT(12) |
|---|
| 506 | #define MT6357_VA33REFGEN_EN_VA18_ENABLE BIT(12) |
|---|
| 507 | #define MT6357_VA33REFGEN_EN_VA18_DISABLE 0 |
|---|
| 508 | #define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_MASK BIT(10) |
|---|
| 509 | #define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_ENABLE BIT(10) |
|---|
| 510 | #define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_DISABLE 0 |
|---|
| 511 | #define MT6357_LCLDO_ENC_EN_VA28_MASK BIT(8) |
|---|
| 512 | #define MT6357_LCLDO_ENC_EN_VA28_ENABLE BIT(8) |
|---|
| 513 | #define MT6357_LCLDO_ENC_EN_VA28_DISABLE 0 |
|---|
| 514 | #define MT6357_LCLDO_REMOTE_SENSE_VA18_MASK BIT(6) |
|---|
| 515 | #define MT6357_LCLDO_REMOTE_SENSE_VA18_ENABLE BIT(6) |
|---|
| 516 | #define MT6357_LCLDO_REMOTE_SENSE_VA18_DISABLE 0 |
|---|
| 517 | #define MT6357_LCLDO_EN_VA18_MASK BIT(4) |
|---|
| 518 | #define MT6357_LCLDO_EN_VA18_ENABLE BIT(4) |
|---|
| 519 | #define MT6357_LCLDO_EN_VA18_DISABLE 0 |
|---|
| 520 | #define MT6357_HCLDO_REMOTE_SENSE_VA18_MASK BIT(2) |
|---|
| 521 | #define MT6357_HCLDO_REMOTE_SENSE_VA18_ENABLE BIT(2) |
|---|
| 522 | #define MT6357_HCLDO_REMOTE_SENSE_VA18_DISABLE 0 |
|---|
| 523 | #define MT6357_HCLDO_EN_VA18_MASK BIT(0) |
|---|
| 524 | #define MT6357_HCLDO_EN_VA18_ENABLE BIT(0) |
|---|
| 525 | #define MT6357_HCLDO_EN_VA18_DISABLE 0 |
|---|
| 526 | |
|---|
| 527 | /* MT6357_AUDDEC_ANA_CON13 */ |
|---|
| 528 | #define MT6357_NVREG_EN_VAUDP15_MASK BIT(0) |
|---|
| 529 | #define MT6357_NVREG_EN_VAUDP15_ENABLE BIT(0) |
|---|
| 530 | #define MT6357_NVREG_EN_VAUDP15_DISABLE 0 |
|---|
| 531 | |
|---|
| 532 | /* MT6357_AUDDEC_ELR_0 */ |
|---|
| 533 | #define MT6357_AUD_HP_TRIM_EN_VAUDP15_MASK BIT(12) |
|---|
| 534 | #define MT6357_AUD_HP_TRIM_EN_VAUDP15_ENABLE BIT(12) |
|---|
| 535 | #define MT6357_AUD_HP_TRIM_EN_VAUDP15_DISABLE 0 |
|---|
| 536 | |
|---|
| 537 | /* MT6357_ZCD_CON1 */ |
|---|
| 538 | #define MT6357_AUD_LOL_GAIN_MASK GENMASK(4, 0) |
|---|
| 539 | #define MT6357_AUD_LOL_GAIN_SFT 0 |
|---|
| 540 | #define MT6357_AUD_LOR_GAIN_MASK GENMASK(11, 7) |
|---|
| 541 | #define MT6357_AUD_LOR_GAIN_SFT 7 |
|---|
| 542 | #define MT6357_AUD_LO_GAIN_MAX 0x12 |
|---|
| 543 | |
|---|
| 544 | /* MT6357_ZCD_CON2 */ |
|---|
| 545 | #define MT6357_AUD_HPL_GAIN_MASK GENMASK(4, 0) |
|---|
| 546 | #define MT6357_AUD_HPL_GAIN_SFT 0 |
|---|
| 547 | #define MT6357_AUD_HPR_GAIN_MASK GENMASK(11, 7) |
|---|
| 548 | #define MT6357_AUD_HPR_GAIN_SFT 7 |
|---|
| 549 | #define MT6357_AUD_HP_GAIN_MAX 0x12 |
|---|
| 550 | |
|---|
| 551 | /* MT6357_ZCD_CON3 */ |
|---|
| 552 | #define MT6357_AUD_HS_GAIN_MASK GENMASK(4, 0) |
|---|
| 553 | #define MT6357_AUD_HS_GAIN_SFT 0 |
|---|
| 554 | #define MT6357_AUD_HS_GAIN_MAX 0x12 |
|---|
| 555 | |
|---|
| 556 | /* Registers list */ |
|---|
| 557 | /* gpio direction */ |
|---|
| 558 | #define MT6357_GPIO_DIR0 0x0088 |
|---|
| 559 | /* mosi */ |
|---|
| 560 | #define MT6357_GPIO_MODE2 0x00B6 |
|---|
| 561 | #define MT6357_GPIO_MODE2_SET 0x00B8 |
|---|
| 562 | #define MT6357_GPIO_MODE2_CLR 0x00BA |
|---|
| 563 | /* miso */ |
|---|
| 564 | #define MT6357_GPIO_MODE3 0x00BC |
|---|
| 565 | #define MT6357_GPIO_MODE3_SET 0x00BE |
|---|
| 566 | #define MT6357_GPIO_MODE3_CLR 0x00C0 |
|---|
| 567 | |
|---|
| 568 | #define MT6357_DCXO_CW14 0x07AC |
|---|
| 569 | |
|---|
| 570 | #define MT6357_AUD_TOP_CKPDN_CON0 0x208C |
|---|
| 571 | #define MT6357_AUDNCP_CLKDIV_CON0 0x20B4 |
|---|
| 572 | #define MT6357_AUDNCP_CLKDIV_CON1 0x20B6 |
|---|
| 573 | #define MT6357_AUDNCP_CLKDIV_CON2 0x20B8 |
|---|
| 574 | #define MT6357_AUDNCP_CLKDIV_CON3 0x20BA |
|---|
| 575 | #define MT6357_AUDNCP_CLKDIV_CON4 0x20BC |
|---|
| 576 | #define MT6357_AFE_UL_DL_CON0 0x2108 |
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| 577 | #define MT6357_AFE_DL_SRC2_CON0_L 0x210A |
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| 578 | #define MT6357_AFE_UL_SRC_CON0_H 0x210C |
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| 579 | #define MT6357_AFE_UL_SRC_CON0_L 0x210E |
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| 580 | #define MT6357_AFE_TOP_CON0 0x2110 |
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| 581 | #define MT6357_AUDIO_TOP_CON0 0x2112 |
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| 582 | #define MT6357_AFUNC_AUD_CON0 0x2116 |
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| 583 | #define MT6357_AFUNC_AUD_CON2 0x211A |
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| 584 | #define MT6357_AFE_ADDA_MTKAIF_CFG0 0x2134 |
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| 585 | #define MT6357_AFE_SGEN_CFG0 0x2140 |
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| 586 | #define MT6357_AFE_DCCLK_CFG0 0x2146 |
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| 587 | #define MT6357_AFE_DCCLK_CFG1 0x2148 |
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| 588 | #define MT6357_AFE_AUD_PAD_TOP 0x214C |
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| 589 | #define MT6357_AUDENC_ANA_CON0 0x2188 |
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| 590 | #define MT6357_AUDENC_ANA_CON1 0x218A |
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| 591 | #define MT6357_AUDENC_ANA_CON6 0x2194 |
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| 592 | #define MT6357_AUDENC_ANA_CON7 0x2196 |
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| 593 | #define MT6357_AUDENC_ANA_CON8 0x2198 |
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| 594 | #define MT6357_AUDENC_ANA_CON9 0x219A |
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| 595 | #define MT6357_AUDDEC_ANA_CON0 0x2208 |
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| 596 | #define MT6357_AUDDEC_ANA_CON1 0x220A |
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| 597 | #define MT6357_AUDDEC_ANA_CON2 0x220C |
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| 598 | #define MT6357_AUDDEC_ANA_CON3 0x220E |
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| 599 | #define MT6357_AUDDEC_ANA_CON4 0x2210 |
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| 600 | #define MT6357_AUDDEC_ANA_CON6 0x2214 |
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| 601 | #define MT6357_AUDDEC_ANA_CON7 0x2216 |
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| 602 | #define MT6357_AUDDEC_ANA_CON10 0x221C |
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| 603 | #define MT6357_AUDDEC_ANA_CON11 0x221E |
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| 604 | #define MT6357_AUDDEC_ANA_CON12 0x2220 |
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| 605 | #define MT6357_AUDDEC_ANA_CON13 0x2222 |
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| 606 | #define MT6357_AUDDEC_ELR_0 0x2226 |
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| 607 | #define MT6357_ZCD_CON1 0x228A |
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| 608 | #define MT6357_ZCD_CON2 0x228C |
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| 609 | #define MT6357_ZCD_CON3 0x228E |
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| 610 | |
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| 611 | enum { |
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| 612 | DL_GAIN_8DB = 0, |
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| 613 | DL_GAIN_0DB = 8, |
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| 614 | DL_GAIN_N_1DB = 9, |
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| 615 | DL_GAIN_N_10DB = 18, |
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| 616 | DL_GAIN_N_12DB = 20, |
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| 617 | DL_GAIN_N_40DB = 0x1f, |
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| 618 | }; |
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| 619 | |
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| 620 | enum { |
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| 621 | UL_GAIN_0DB = 0, |
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| 622 | UL_GAIN_6DB, |
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| 623 | UL_GAIN_12DB, |
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| 624 | UL_GAIN_18DB, |
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| 625 | UL_GAIN_24DB, |
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| 626 | }; |
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| 627 | |
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| 628 | #define MT6357_DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB) |
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| 629 | #define MT6357_DL_GAIN_REG_LEFT_MASK 0x001f |
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| 630 | #define MT6357_DL_GAIN_REG_LEFT_SHIFT 0 |
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| 631 | #define MT6357_DL_GAIN_REG_RIGHT_MASK 0x0f80 |
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| 632 | #define MT6357_DL_GAIN_REG_RIGHT_SHIFT 7 |
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| 633 | #define MT6357_DL_GAIN_REG_MASK 0x0f9f |
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| 634 | |
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| 635 | #define MT6357_SND_SOC_ADV_MT_FMTS (\ |
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| 636 | SNDRV_PCM_FMTBIT_S16_LE |\ |
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| 637 | SNDRV_PCM_FMTBIT_S16_BE |\ |
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| 638 | SNDRV_PCM_FMTBIT_U16_LE |\ |
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| 639 | SNDRV_PCM_FMTBIT_U16_BE |\ |
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| 640 | SNDRV_PCM_FMTBIT_S24_LE |\ |
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| 641 | SNDRV_PCM_FMTBIT_S24_BE |\ |
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| 642 | SNDRV_PCM_FMTBIT_U24_LE |\ |
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| 643 | SNDRV_PCM_FMTBIT_U24_BE |\ |
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| 644 | SNDRV_PCM_FMTBIT_S32_LE |\ |
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| 645 | SNDRV_PCM_FMTBIT_S32_BE |\ |
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| 646 | SNDRV_PCM_FMTBIT_U32_LE |\ |
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| 647 | SNDRV_PCM_FMTBIT_U32_BE) |
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| 648 | |
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| 649 | #define MT6357_SOC_HIGH_USE_RATE (\ |
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| 650 | SNDRV_PCM_RATE_CONTINUOUS |\ |
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| 651 | SNDRV_PCM_RATE_8000_192000) |
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| 652 | |
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| 653 | /* codec private structure */ |
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| 654 | struct mt6357_priv { |
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| 655 | struct device *dev; |
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| 656 | struct regmap *regmap; |
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| 657 | bool pull_down_needed; |
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| 658 | int hp_channel_number; |
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| 659 | }; |
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| 660 | #endif |
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| 661 | |
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