| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * mt8183-afe-common.h -- Mediatek 8183 audio driver definitions |
| 4 | * |
| 5 | * Copyright (c) 2018 MediaTek Inc. |
| 6 | * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _MT_8183_AFE_COMMON_H_ |
| 10 | #define _MT_8183_AFE_COMMON_H_ |
| 11 | |
| 12 | #include <sound/soc.h> |
| 13 | #include <linux/list.h> |
| 14 | #include <linux/regmap.h> |
| 15 | #include "../common/mtk-base-afe.h" |
| 16 | |
| 17 | enum { |
| 18 | MT8183_MEMIF_DL1, |
| 19 | MT8183_MEMIF_DL2, |
| 20 | MT8183_MEMIF_DL3, |
| 21 | MT8183_MEMIF_VUL12, |
| 22 | MT8183_MEMIF_VUL2, |
| 23 | MT8183_MEMIF_AWB, |
| 24 | MT8183_MEMIF_AWB2, |
| 25 | MT8183_MEMIF_MOD_DAI, |
| 26 | MT8183_MEMIF_HDMI, |
| 27 | MT8183_MEMIF_NUM, |
| 28 | MT8183_DAI_ADDA = MT8183_MEMIF_NUM, |
| 29 | MT8183_DAI_PCM_1, |
| 30 | MT8183_DAI_PCM_2, |
| 31 | MT8183_DAI_I2S_0, |
| 32 | MT8183_DAI_I2S_1, |
| 33 | MT8183_DAI_I2S_2, |
| 34 | MT8183_DAI_I2S_3, |
| 35 | MT8183_DAI_I2S_5, |
| 36 | MT8183_DAI_TDM, |
| 37 | MT8183_DAI_HOSTLESS_LPBK, |
| 38 | MT8183_DAI_HOSTLESS_SPEECH, |
| 39 | MT8183_DAI_NUM, |
| 40 | }; |
| 41 | |
| 42 | enum { |
| 43 | MT8183_IRQ_0, |
| 44 | MT8183_IRQ_1, |
| 45 | MT8183_IRQ_2, |
| 46 | MT8183_IRQ_3, |
| 47 | MT8183_IRQ_4, |
| 48 | MT8183_IRQ_5, |
| 49 | MT8183_IRQ_6, |
| 50 | MT8183_IRQ_7, |
| 51 | MT8183_IRQ_8, /* hw bundle to TDM */ |
| 52 | MT8183_IRQ_11, |
| 53 | MT8183_IRQ_12, |
| 54 | MT8183_IRQ_NUM, |
| 55 | }; |
| 56 | |
| 57 | enum { |
| 58 | MT8183_MTKAIF_PROTOCOL_1 = 0, |
| 59 | MT8183_MTKAIF_PROTOCOL_2, |
| 60 | MT8183_MTKAIF_PROTOCOL_2_CLK_P2, |
| 61 | }; |
| 62 | |
| 63 | /* MCLK */ |
| 64 | enum { |
| 65 | MT8183_I2S0_MCK = 0, |
| 66 | MT8183_I2S1_MCK, |
| 67 | MT8183_I2S2_MCK, |
| 68 | MT8183_I2S3_MCK, |
| 69 | MT8183_I2S4_MCK, |
| 70 | MT8183_I2S4_BCK, |
| 71 | MT8183_I2S5_MCK, |
| 72 | MT8183_MCK_NUM, |
| 73 | }; |
| 74 | |
| 75 | struct clk; |
| 76 | |
| 77 | struct mt8183_afe_private { |
| 78 | struct clk **clk; |
| 79 | |
| 80 | int pm_runtime_bypass_reg_ctl; |
| 81 | |
| 82 | /* dai */ |
| 83 | void *dai_priv[MT8183_DAI_NUM]; |
| 84 | |
| 85 | /* adda */ |
| 86 | int mtkaif_protocol; |
| 87 | int mtkaif_calibration_ok; |
| 88 | int mtkaif_chosen_phase[4]; |
| 89 | int mtkaif_phase_cycle[4]; |
| 90 | int mtkaif_calibration_num_phase; |
| 91 | int mtkaif_dmic; |
| 92 | |
| 93 | /* mck */ |
| 94 | int mck_rate[MT8183_MCK_NUM]; |
| 95 | }; |
| 96 | |
| 97 | unsigned int mt8183_general_rate_transform(struct device *dev, |
| 98 | unsigned int rate); |
| 99 | unsigned int mt8183_rate_transform(struct device *dev, |
| 100 | unsigned int rate, int aud_blk); |
| 101 | |
| 102 | int mt8183_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name, |
| 103 | const char *secondary_i2s_name); |
| 104 | |
| 105 | /* dai register */ |
| 106 | int mt8183_dai_adda_register(struct mtk_base_afe *afe); |
| 107 | int mt8183_dai_pcm_register(struct mtk_base_afe *afe); |
| 108 | int mt8183_dai_i2s_register(struct mtk_base_afe *afe); |
| 109 | int mt8183_dai_tdm_register(struct mtk_base_afe *afe); |
| 110 | int mt8183_dai_hostless_register(struct mtk_base_afe *afe); |
| 111 | #endif |
| 112 | |