1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition
4 *
5 * Copyright (c) 2022 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
9 */
10
11#ifndef _MT8188_AFE_CLK_H_
12#define _MT8188_AFE_CLK_H_
13
14/* APLL */
15#define APLL1_W_NAME "APLL1"
16#define APLL2_W_NAME "APLL2"
17
18enum {
19 /* xtal */
20 MT8188_CLK_XTAL_26M,
21 /* pll */
22 MT8188_CLK_APMIXED_APLL1,
23 MT8188_CLK_APMIXED_APLL2,
24 /* divider */
25 MT8188_CLK_TOP_APLL1_D4,
26 MT8188_CLK_TOP_APLL2_D4,
27 MT8188_CLK_TOP_APLL12_DIV0,
28 MT8188_CLK_TOP_APLL12_DIV1,
29 MT8188_CLK_TOP_APLL12_DIV2,
30 MT8188_CLK_TOP_APLL12_DIV3,
31 MT8188_CLK_TOP_APLL12_DIV4,
32 MT8188_CLK_TOP_APLL12_DIV9,
33 /* mux */
34 MT8188_CLK_TOP_A1SYS_HP_SEL,
35 MT8188_CLK_TOP_A2SYS_SEL,
36 MT8188_CLK_TOP_AUD_IEC_SEL,
37 MT8188_CLK_TOP_AUD_INTBUS_SEL,
38 MT8188_CLK_TOP_AUDIO_H_SEL,
39 MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
40 MT8188_CLK_TOP_DPTX_M_SEL,
41 MT8188_CLK_TOP_I2SO1_M_SEL,
42 MT8188_CLK_TOP_I2SO2_M_SEL,
43 MT8188_CLK_TOP_I2SI1_M_SEL,
44 MT8188_CLK_TOP_I2SI2_M_SEL,
45 /* clock gate */
46 MT8188_CLK_ADSP_AUDIO_26M,
47 MT8188_CLK_AUD_AFE,
48 MT8188_CLK_AUD_APLL1_TUNER,
49 MT8188_CLK_AUD_APLL2_TUNER,
50 MT8188_CLK_AUD_TOP0_SPDF,
51 MT8188_CLK_AUD_APLL,
52 MT8188_CLK_AUD_APLL2,
53 MT8188_CLK_AUD_DAC,
54 MT8188_CLK_AUD_ADC,
55 MT8188_CLK_AUD_DAC_HIRES,
56 MT8188_CLK_AUD_A1SYS_HP,
57 MT8188_CLK_AUD_AFE_DMIC1,
58 MT8188_CLK_AUD_AFE_DMIC2,
59 MT8188_CLK_AUD_AFE_DMIC3,
60 MT8188_CLK_AUD_AFE_DMIC4,
61 MT8188_CLK_AUD_ADC_HIRES,
62 MT8188_CLK_AUD_DMIC_HIRES1,
63 MT8188_CLK_AUD_DMIC_HIRES2,
64 MT8188_CLK_AUD_DMIC_HIRES3,
65 MT8188_CLK_AUD_DMIC_HIRES4,
66 MT8188_CLK_AUD_I2SIN,
67 MT8188_CLK_AUD_TDM_IN,
68 MT8188_CLK_AUD_I2S_OUT,
69 MT8188_CLK_AUD_TDM_OUT,
70 MT8188_CLK_AUD_HDMI_OUT,
71 MT8188_CLK_AUD_ASRC11,
72 MT8188_CLK_AUD_ASRC12,
73 MT8188_CLK_AUD_A1SYS,
74 MT8188_CLK_AUD_A2SYS,
75 MT8188_CLK_AUD_PCMIF,
76 MT8188_CLK_AUD_MEMIF_UL1,
77 MT8188_CLK_AUD_MEMIF_UL2,
78 MT8188_CLK_AUD_MEMIF_UL3,
79 MT8188_CLK_AUD_MEMIF_UL4,
80 MT8188_CLK_AUD_MEMIF_UL5,
81 MT8188_CLK_AUD_MEMIF_UL6,
82 MT8188_CLK_AUD_MEMIF_UL8,
83 MT8188_CLK_AUD_MEMIF_UL9,
84 MT8188_CLK_AUD_MEMIF_UL10,
85 MT8188_CLK_AUD_MEMIF_DL2,
86 MT8188_CLK_AUD_MEMIF_DL3,
87 MT8188_CLK_AUD_MEMIF_DL6,
88 MT8188_CLK_AUD_MEMIF_DL7,
89 MT8188_CLK_AUD_MEMIF_DL8,
90 MT8188_CLK_AUD_MEMIF_DL10,
91 MT8188_CLK_AUD_MEMIF_DL11,
92 MT8188_CLK_NUM,
93};
94
95enum {
96 MT8188_AUD_PLL1,
97 MT8188_AUD_PLL2,
98 MT8188_AUD_PLL3,
99 MT8188_AUD_PLL4,
100 MT8188_AUD_PLL5,
101 MT8188_AUD_PLL_NUM,
102};
103
104enum {
105 MT8188_MCK_SEL_26M,
106 MT8188_MCK_SEL_APLL1,
107 MT8188_MCK_SEL_APLL2,
108 MT8188_MCK_SEL_APLL3,
109 MT8188_MCK_SEL_APLL4,
110 MT8188_MCK_SEL_APLL5,
111 MT8188_MCK_SEL_NUM,
112};
113
114struct mtk_base_afe;
115
116int mt8188_afe_get_mclk_source_clk_id(int sel);
117int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
118int mt8188_afe_get_default_mclk_source_by_rate(int rate);
119int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
120int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
121int mt8188_afe_init_clock(struct mtk_base_afe *afe);
122int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
123void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
124int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
125 unsigned int rate);
126int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
127 struct clk *parent);
128int mt8188_apll1_enable(struct mtk_base_afe *afe);
129int mt8188_apll1_disable(struct mtk_base_afe *afe);
130int mt8188_apll2_enable(struct mtk_base_afe *afe);
131int mt8188_apll2_disable(struct mtk_base_afe *afe);
132int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe);
133int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe);
134int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
135int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
136
137#endif
138

source code of linux/sound/soc/mediatek/mt8188/mt8188-afe-clk.h