1	/* SPDX-License-Identifier: GPL-2.0 */
2	/*
3	* mt8189-reg.h -- Mediatek 8189 audio driver reg definition
4	*
5	* Copyright (c) 2025 MediaTek Inc.
6	* Author: Darren Ye <darren.ye@mediatek.com>
7	*/
8
9	#ifndef _MT8189_REG_H_
10	#define _MT8189_REG_H_
11
12	/* reg bit enum */
13	enum {
14	MT8189_MEMIF_PBUF_SIZE_32_BYTES,
15	MT8189_MEMIF_PBUF_SIZE_64_BYTES,
16	MT8189_MEMIF_PBUF_SIZE_128_BYTES,
17	MT8189_MEMIF_PBUF_SIZE_256_BYTES,
18	MT8189_MEMIF_PBUF_SIZE_NUM,
19	};
20
21	/*****************************************************************************
22	* R E G I S T E R D E F I N I T I O N
23	*****************************************************************************/
24	/* AUDIO_TOP_CON0 */
25	#define PDN_MTKAIFV4_SFT 25
26	#define PDN_MTKAIFV4_MASK 0x1
27	#define PDN_MTKAIFV4_MASK_SFT (0x1 << 25)
28	#define PDN_FM_I2S_SFT 24
29	#define PDN_FM_I2S_MASK 0x1
30	#define PDN_FM_I2S_MASK_SFT (0x1 << 24)
31	#define PDN_HW_GAIN01_SFT 21
32	#define PDN_HW_GAIN01_MASK 0x1
33	#define PDN_HW_GAIN01_MASK_SFT (0x1 << 21)
34	#define PDN_HW_GAIN23_SFT 20
35	#define PDN_HW_GAIN23_MASK 0x1
36	#define PDN_HW_GAIN23_MASK_SFT (0x1 << 20)
37	#define PDN_STF_SFT 19
38	#define PDN_STF_MASK 0x1
39	#define PDN_STF_MASK_SFT (0x1 << 19)
40	#define PDN_CM0_SFT 18
41	#define PDN_CM0_MASK 0x1
42	#define PDN_CM0_MASK_SFT (0x1 << 18)
43	#define PDN_CM1_SFT 17
44	#define PDN_CM1_MASK 0x1
45	#define PDN_CM1_MASK_SFT (0x1 << 17)
46	#define PDN_PCM0_SFT 14
47	#define PDN_PCM0_MASK 0x1
48	#define PDN_PCM0_MASK_SFT (0x1 << 14)
49	#define PDN_DL0_NLE_SFT 11
50	#define PDN_DL0_NLE_MASK 0x1
51	#define PDN_DL0_NLE_MASK_SFT (0x1 << 11)
52	#define PDN_DL0_PREDIS_SFT 10
53	#define PDN_DL0_PREDIS_MASK 0x1
54	#define PDN_DL0_PREDIS_MASK_SFT (0x1 << 10)
55	#define PDN_DL0_DAC_SFT 9
56	#define PDN_DL0_DAC_MASK 0x1
57	#define PDN_DL0_DAC_MASK_SFT (0x1 << 9)
58	#define PDN_DL0_DAC_HIRES_SFT 8
59	#define PDN_DL0_DAC_HIRES_MASK 0x1
60	#define PDN_DL0_DAC_HIRES_MASK_SFT (0x1 << 8)
61	#define PDN_DL0_DAC_TML_SFT 7
62	#define PDN_DL0_DAC_TML_MASK 0x1
63	#define PDN_DL0_DAC_TML_MASK_SFT (0x1 << 7)
64
65	/* AUDIO_TOP_CON1 */
66	#define PDN_UL0_ADC_SFT 23
67	#define PDN_UL0_ADC_MASK 0x1
68	#define PDN_UL0_ADC_MASK_SFT (0x1 << 23)
69	#define PDN_UL0_TML_SFT 22
70	#define PDN_UL0_TML_MASK 0x1
71	#define PDN_UL0_TML_MASK_SFT (0x1 << 22)
72	#define PDN_UL0_ADC_HIRES_SFT 21
73	#define PDN_UL0_ADC_HIRES_MASK 0x1
74	#define PDN_UL0_ADC_HIRES_MASK_SFT (0x1 << 21)
75	#define PDN_UL0_ADC_HIRES_TML_SFT 20
76	#define PDN_UL0_ADC_HIRES_TML_MASK 0x1
77	#define PDN_UL0_ADC_HIRES_TML_MASK_SFT (0x1 << 20)
78	#define PDN_UL1_ADC_SFT 19
79	#define PDN_UL1_ADC_MASK 0x1
80	#define PDN_UL1_ADC_MASK_SFT (0x1 << 19)
81	#define PDN_UL1_TML_SFT 18
82	#define PDN_UL1_TML_MASK 0x1
83	#define PDN_UL1_TML_MASK_SFT (0x1 << 18)
84	#define PDN_UL1_ADC_HIRES_SFT 17
85	#define PDN_UL1_ADC_HIRES_MASK 0x1
86	#define PDN_UL1_ADC_HIRES_MASK_SFT (0x1 << 17)
87	#define PDN_UL1_ADC_HIRES_TML_SFT 16
88	#define PDN_UL1_ADC_HIRES_TML_MASK 0x1
89	#define PDN_UL1_ADC_HIRES_TML_MASK_SFT (0x1 << 16)
90	#define PDN_DMIC0_ADC_SFT 7
91	#define PDN_DMIC0_ADC_MASK 0x1
92	#define PDN_DMIC0_ADC_MASK_SFT (0x1 << 7)
93	#define PDN_DMIC1_ADC_SFT 3
94	#define PDN_DMIC1_ADC_MASK 0x1
95	#define PDN_DMIC1_ADC_MASK_SFT (0x1 << 3)
96
97	/* AUDIO_TOP_CON2 */
98	#define PDN_TDM_OUT_SFT 24
99	#define PDN_TDM_OUT_MASK 0x1
100	#define PDN_TDM_OUT_MASK_SFT (0x1 << 24)
101	#define PDN_ETDM_OUT0_SFT 21
102	#define PDN_ETDM_OUT0_MASK 0x1
103	#define PDN_ETDM_OUT0_MASK_SFT (0x1 << 21)
104	#define PDN_ETDM_OUT1_SFT 20
105	#define PDN_ETDM_OUT1_MASK 0x1
106	#define PDN_ETDM_OUT1_MASK_SFT (0x1 << 20)
107	#define PDN_ETDM_OUT4_SFT 17
108	#define PDN_ETDM_OUT4_MASK 0x1
109	#define PDN_ETDM_OUT4_MASK_SFT (0x1 << 17)
110	#define PDN_ETDM_IN0_SFT 13
111	#define PDN_ETDM_IN0_MASK 0x1
112	#define PDN_ETDM_IN0_MASK_SFT (0x1 << 13)
113	#define PDN_ETDM_IN1_SFT 12
114	#define PDN_ETDM_IN1_MASK 0x1
115	#define PDN_ETDM_IN1_MASK_SFT (0x1 << 12)
116
117	/* AUDIO_TOP_CON3 */
118	#define PDN_CONNSYS_I2S_ASRC_SFT 25
119	#define PDN_CONNSYS_I2S_ASRC_MASK 0x1
120	#define PDN_CONNSYS_I2S_ASRC_MASK_SFT (0x1 << 25)
121	#define PDN_GENERAL0_ASRC_SFT 24
122	#define PDN_GENERAL0_ASRC_MASK 0x1
123	#define PDN_GENERAL0_ASRC_MASK_SFT (0x1 << 24)
124	#define PDN_GENERAL1_ASRC_SFT 23
125	#define PDN_GENERAL1_ASRC_MASK 0x1
126	#define PDN_GENERAL1_ASRC_MASK_SFT (0x1 << 23)
127	#define PDN_GENERAL2_ASRC_SFT 22
128	#define PDN_GENERAL2_ASRC_MASK 0x1
129	#define PDN_GENERAL2_ASRC_MASK_SFT (0x1 << 22)
130	#define PDN_GENERAL3_ASRC_SFT 21
131	#define PDN_GENERAL3_ASRC_MASK 0x1
132	#define PDN_GENERAL3_ASRC_MASK_SFT (0x1 << 21)
133	#define PDN_GENERAL4_ASRC_SFT 20
134	#define PDN_GENERAL4_ASRC_MASK 0x1
135	#define PDN_GENERAL4_ASRC_MASK_SFT (0x1 << 20)
136
137	/* AUDIO_TOP_CON4 */
138	#define PDN_APLL_TUNER1_SFT 13
139	#define PDN_APLL_TUNER1_MASK 0x1
140	#define PDN_APLL_TUNER1_MASK_SFT (0x1 << 13)
141	#define PDN_APLL_TUNER2_SFT 12
142	#define PDN_APLL_TUNER2_MASK 0x1
143	#define PDN_APLL_TUNER2_MASK_SFT (0x1 << 12)
144	#define CG_H208M_CK_SFT 4
145	#define CG_H208M_CK_MASK 0x1
146	#define CG_H208M_CK_MASK_SFT (0x1 << 4)
147	#define CG_APLL2_CK_SFT 3
148	#define CG_APLL2_CK_MASK 0x1
149	#define CG_APLL2_CK_MASK_SFT (0x1 << 3)
150	#define CG_APLL1_CK_SFT 2
151	#define CG_APLL1_CK_MASK 0x1
152	#define CG_APLL1_CK_MASK_SFT (0x1 << 2)
153	#define CG_AUDIO_F26M_CK_SFT 1
154	#define CG_AUDIO_F26M_CK_MASK 0x1
155	#define CG_AUDIO_F26M_CK_MASK_SFT (0x1 << 1)
156	#define CG_AUDIO_HOPPING_CK_SFT 0
157	#define CG_AUDIO_HOPPING_CK_MASK 0x1
158	#define CG_AUDIO_HOPPING_CK_MASK_SFT (0x1 << 0)
159
160	/* AUDIO_ENGEN_CON0 */
161	/* AUDIO_ENGEN_CON0_USER1 */
162	/* AUDIO_ENGEN_CON0_USER2 */
163	#define MULTI_USER_BYPASS_SFT 17
164	#define MULTI_USER_BYPASS_MASK 0x1
165	#define MULTI_USER_BYPASS_MASK_SFT (0x1 << 17)
166	#define MULTI_USER_RST_SFT 16
167	#define MULTI_USER_RST_MASK 0x1
168	#define MULTI_USER_RST_MASK_SFT (0x1 << 16)
169	#define AUDIO_F26M_EN_RST_SFT 8
170	#define AUDIO_F26M_EN_RST_MASK 0x1
171	#define AUDIO_F26M_EN_RST_MASK_SFT (0x1 << 8)
172	#define AUDIO_APLL2_EN_ON_SFT 3
173	#define AUDIO_APLL2_EN_ON_MASK 0x1
174	#define AUDIO_APLL2_EN_ON_MASK_SFT (0x1 << 3)
175	#define AUDIO_APLL1_EN_ON_SFT 2
176	#define AUDIO_APLL1_EN_ON_MASK 0x1
177	#define AUDIO_APLL1_EN_ON_MASK_SFT (0x1 << 2)
178	#define AUDIO_F3P25M_EN_ON_SFT 1
179	#define AUDIO_F3P25M_EN_ON_MASK 0x1
180	#define AUDIO_F3P25M_EN_ON_MASK_SFT (0x1 << 1)
181	#define AUDIO_26M_EN_ON_SFT 0
182	#define AUDIO_26M_EN_ON_MASK 0x1
183	#define AUDIO_26M_EN_ON_MASK_SFT (0x1 << 0)
184
185	/* AFE_SINEGEN_CON0 */
186	#define DAC_EN_SFT 26
187	#define DAC_EN_MASK 0x1
188	#define DAC_EN_MASK_SFT (0x1 << 26)
189	#define TIE_SW_CH2_SFT 25
190	#define TIE_SW_CH2_MASK 0x1
191	#define TIE_SW_CH2_MASK_SFT (0x1 << 25)
192	#define TIE_SW_CH1_SFT 24
193	#define TIE_SW_CH1_MASK 0x1
194	#define TIE_SW_CH1_MASK_SFT (0x1 << 24)
195	#define AMP_DIV_CH2_SFT 20
196	#define AMP_DIV_CH2_MASK 0xf
197	#define AMP_DIV_CH2_MASK_SFT (0xf << 20)
198	#define FREQ_DIV_CH2_SFT 12
199	#define FREQ_DIV_CH2_MASK 0x1f
200	#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)
201	#define AMP_DIV_CH1_SFT 8
202	#define AMP_DIV_CH1_MASK 0xf
203	#define AMP_DIV_CH1_MASK_SFT (0xf << 8)
204	#define FREQ_DIV_CH1_SFT 0
205	#define FREQ_DIV_CH1_MASK 0x1f
206	#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)
207
208	/* AFE_SINEGEN_CON1 */
209	#define SINE_DOMAIN_SFT 20
210	#define SINE_DOMAIN_MASK 0x7
211	#define SINE_DOMAIN_MASK_SFT (0x7 << 20)
212	#define SINE_MODE_SFT 12
213	#define SINE_MODE_MASK 0x1f
214	#define SINE_MODE_MASK_SFT (0x1f << 12)
215	#define INNER_LOOP_BACKI_SEL_SFT 8
216	#define INNER_LOOP_BACKI_SEL_MASK 0x1
217	#define INNER_LOOP_BACKI_SEL_MASK_SFT (0x1 << 8)
218	#define INNER_LOOP_BACK_MODE_SFT 0
219	#define INNER_LOOP_BACK_MODE_MASK 0xff
220	#define INNER_LOOP_BACK_MODE_MASK_SFT (0xff << 0)
221
222	/* AFE_SINEGEN_CON2 */
223	#define TIE_CH1_CONSTANT_SFT 0
224	#define TIE_CH1_CONSTANT_MASK 0xffffffff
225	#define TIE_CH1_CONSTANT_MASK_SFT (0xffffffff << 0)
226
227	/* AFE_SINEGEN_CON3 */
228	#define TIE_CH2_CONSTANT_SFT 0
229	#define TIE_CH2_CONSTANT_MASK 0xffffffff
230	#define TIE_CH2_CONSTANT_MASK_SFT (0xffffffff << 0)
231
232	/* AFE_APLL1_TUNER_CFG */
233	#define UPPER_BOUND_SFT 8
234	#define UPPER_BOUND_MASK 0xff
235	#define UPPER_BOUND_MASK_SFT (0xff << 8)
236	#define APLL_DIV_SFT 4
237	#define APLL_DIV_MASK 0xf
238	#define APLL_DIV_MASK_SFT (0xf << 4)
239	#define XTAL_EN_128FS_SEL_SFT 1
240	#define XTAL_EN_128FS_SEL_MASK 0x3
241	#define XTAL_EN_128FS_SEL_MASK_SFT (0x3 << 1)
242	#define FREQ_TUNER_EN_SFT 0
243	#define FREQ_TUNER_EN_MASK 0x1
244	#define FREQ_TUNER_EN_MASK_SFT (0x1 << 0)
245
246	/* AFE_APLL1_TUNER_MON0 */
247	#define TUNER_MON_SFT 0
248	#define TUNER_MON_MASK 0xffffffff
249	#define TUNER_MON_MASK_SFT (0xffffffff << 0)
250
251	/* AFE_APLL2_TUNER_CFG */
252	#define UPPER_BOUND_SFT 8
253	#define UPPER_BOUND_MASK 0xff
254	#define UPPER_BOUND_MASK_SFT (0xff << 8)
255	#define APLL_DIV_SFT 4
256	#define APLL_DIV_MASK 0xf
257	#define APLL_DIV_MASK_SFT (0xf << 4)
258	#define XTAL_EN_128FS_SEL_SFT 1
259	#define XTAL_EN_128FS_SEL_MASK 0x3
260	#define XTAL_EN_128FS_SEL_MASK_SFT (0x3 << 1)
261	#define FREQ_TUNER_EN_SFT 0
262	#define FREQ_TUNER_EN_MASK 0x1
263	#define FREQ_TUNER_EN_MASK_SFT (0x1 << 0)
264
265	/* AFE_APLL2_TUNER_MON0 */
266	#define TUNER_MON_SFT 0
267	#define TUNER_MON_MASK 0xffffffff
268	#define TUNER_MON_MASK_SFT (0xffffffff << 0)
269
270	/* AUDIO_TOP_RG0 */
271	#define RESERVE_RG_SFT 0
272	#define RESERVE_RG_MASK 0xffffffff
273	#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
274
275	/* AUDIO_TOP_RG1 */
276	#define RESERVE_RG_SFT 0
277	#define RESERVE_RG_MASK 0xffffffff
278	#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
279
280	/* AUDIO_TOP_RG2 */
281	#define RESERVE_RG_SFT 0
282	#define RESERVE_RG_MASK 0xffffffff
283	#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
284
285	/* AUDIO_TOP_RG3 */
286	#define RESERVE_RG_SFT 0
287	#define RESERVE_RG_MASK 0xffffffff
288	#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
289
290	/* AUDIO_TOP_RG4 */
291	#define RESERVE_RG_SFT 0
292	#define RESERVE_RG_MASK 0xffffffff
293	#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
294
295	/* AFE_SPM_CONTROL_REQ */
296	#define AFE_DDREN_REQ_SFT 4
297	#define AFE_DDREN_REQ_MASK 0x1
298	#define AFE_DDREN_REQ_MASK_SFT (0x1 << 4)
299	#define AFE_INFRA_REQ_SFT 3
300	#define AFE_INFRA_REQ_MASK 0x1
301	#define AFE_INFRA_REQ_MASK_SFT (0x1 << 3)
302	#define AFE_VRF18_REQ_SFT 2
303	#define AFE_VRF18_REQ_MASK 0x1
304	#define AFE_VRF18_REQ_MASK_SFT (0x1 << 2)
305	#define AFE_APSRC_REQ_SFT 1
306	#define AFE_APSRC_REQ_MASK 0x1
307	#define AFE_APSRC_REQ_MASK_SFT (0x1 << 1)
308	#define AFE_SRCCLKENA_REQ_SFT 0
309	#define AFE_SRCCLKENA_REQ_MASK 0x1
310	#define AFE_SRCCLKENA_REQ_MASK_SFT (0x1 << 0)
311
312	/* AFE_SPM_CONTROL_ACK */
313	#define SPM_RESOURCE_CONTROL_ACK_SFT 0
314	#define SPM_RESOURCE_CONTROL_ACK_MASK 0xffffffff
315	#define SPM_RESOURCE_CONTROL_ACK_MASK_SFT (0xffffffff << 0)
316
317	/* AUD_TOP_CFG_VCORE_RG */
318	#define AUD_TOP_CFG_SFT 0
319	#define AUD_TOP_CFG_MASK 0xffffffff
320	#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0)
321
322	/* AUDIO_TOP_IP_VERSION */
323	#define AUDIO_TOP_IP_VERSION_SFT 0
324	#define AUDIO_TOP_IP_VERSION_MASK 0xffffffff
325	#define AUDIO_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0)
326
327	/* AUDIO_ENGEN_CON0_MON */
328	#define AUDIO_ENGEN_MON_SFT 0
329	#define AUDIO_ENGEN_MON_MASK 0xffffffff
330	#define AUDIO_ENGEN_MON_MASK_SFT (0xffffffff << 0)
331
332	/* AUD_TOP_CFG_VLP_RG */
333	#define AUD_TOP_CFG_SFT 0
334	#define AUD_TOP_CFG_MASK 0xffffffff
335	#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0)
336
337	/* AUD_TOP_MON_RG */
338	#define AUD_TOP_MON_SFT 0
339	#define AUD_TOP_MON_MASK 0xffffffff
340	#define AUD_TOP_MON_MASK_SFT (0xffffffff << 0)
341
342	/* AUDIO_USE_DEFAULT_DELSEL0 */
343	#define USE_DEFAULT_DELSEL_RG_SFT 0
344	#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff
345	#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0)
346
347	/* AUDIO_USE_DEFAULT_DELSEL1 */
348	#define USE_DEFAULT_DELSEL_RG_SFT 0
349	#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff
350	#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0)
351
352	/* AUDIO_USE_DEFAULT_DELSEL2 */
353	#define USE_DEFAULT_DELSEL_RG_SFT 0
354	#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff
355	#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0)
356
357	/* AFE_CONNSYS_I2S_IPM_VER_MON */
358	#define RG_CONNSYS_I2S_IPM_VER_MON_SFT 0
359	#define RG_CONNSYS_I2S_IPM_VER_MON_MASK 0xffffffff
360	#define RG_CONNSYS_I2S_IPM_VER_MON_MASK_SFT (0xffffffff << 0)
361
362	/* AFE_CONNSYS_I2S_MON_SEL */
363	#define RG_CONNSYS_I2S_MON_SEL_SFT 0
364	#define RG_CONNSYS_I2S_MON_SEL_MASK 0xff
365	#define RG_CONNSYS_I2S_MON_SEL_MASK_SFT (0xff << 0)
366
367	/* AFE_CONNSYS_I2S_MON */
368	#define RG_CONNSYS_I2S_MON_SFT 0
369	#define RG_CONNSYS_I2S_MON_MASK 0xffffffff
370	#define RG_CONNSYS_I2S_MON_MASK_SFT (0xffffffff << 0)
371
372	/* AFE_CONNSYS_I2S_CON */
373	#define I2S_SOFT_RST_SFT 31
374	#define I2S_SOFT_RST_MASK 0x1
375	#define I2S_SOFT_RST_MASK_SFT (0x1 << 31)
376	#define BCK_NEG_EG_LATCH_SFT 30
377	#define BCK_NEG_EG_LATCH_MASK 0x1
378	#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
379	#define BCK_INV_SFT 29
380	#define BCK_INV_MASK 0x1
381	#define BCK_INV_MASK_SFT (0x1 << 29)
382	#define I2SIN_PAD_SEL_SFT 28
383	#define I2SIN_PAD_SEL_MASK 0x1
384	#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
385	#define I2S_LOOPBACK_SFT 20
386	#define I2S_LOOPBACK_MASK 0x1
387	#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
388	#define I2S_HDEN_SFT 12
389	#define I2S_HDEN_MASK 0x1
390	#define I2S_HDEN_MASK_SFT (0x1 << 12)
391	#define I2S_MODE_SFT 8
392	#define I2S_MODE_MASK 0xf
393	#define I2S_MODE_MASK_SFT (0xf << 8)
394	#define I2S_BYPSRC_SFT 6
395	#define I2S_BYPSRC_MASK 0x1
396	#define I2S_BYPSRC_MASK_SFT (0x1 << 6)
397	#define INV_LRCK_SFT 5
398	#define INV_LRCK_MASK 0x1
399	#define INV_LRCK_MASK_SFT (0x1 << 5)
400	#define I2S_FMT_SFT 3
401	#define I2S_FMT_MASK 0x1
402	#define I2S_FMT_MASK_SFT (0x1 << 3)
403	#define I2S_SRC_SFT 2
404	#define I2S_SRC_MASK 0x1
405	#define I2S_SRC_MASK_SFT (0x1 << 2)
406	#define I2S_WLEN_SFT 1
407	#define I2S_WLEN_MASK 0x1
408	#define I2S_WLEN_MASK_SFT (0x1 << 1)
409	#define I2S_EN_SFT 0
410	#define I2S_EN_MASK 0x1
411	#define I2S_EN_MASK_SFT (0x1 << 0)
412
413	/* AFE_PCM0_INTF_CON0 */
414	#define PCM0_HDEN_SFT 26
415	#define PCM0_HDEN_MASK 0x1
416	#define PCM0_HDEN_MASK_SFT (0x1 << 26)
417	#define PCM0_SYNC_DELSEL_SFT 25
418	#define PCM0_SYNC_DELSEL_MASK 0x1
419	#define PCM0_SYNC_DELSEL_MASK_SFT (0x1 << 25)
420	#define PCM0_TX_LR_SWAP_SFT 24
421	#define PCM0_TX_LR_SWAP_MASK 0x1
422	#define PCM0_TX_LR_SWAP_MASK_SFT (0x1 << 24)
423	#define PCM0_SYNC_OUT_INV_SFT 23
424	#define PCM0_SYNC_OUT_INV_MASK 0x1
425	#define PCM0_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
426	#define PCM0_BCLK_OUT_INV_SFT 22
427	#define PCM0_BCLK_OUT_INV_MASK 0x1
428	#define PCM0_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
429	#define PCM0_SYNC_IN_INV_SFT 21
430	#define PCM0_SYNC_IN_INV_MASK 0x1
431	#define PCM0_SYNC_IN_INV_MASK_SFT (0x1 << 21)
432	#define PCM0_BCLK_IN_INV_SFT 20
433	#define PCM0_BCLK_IN_INV_MASK 0x1
434	#define PCM0_BCLK_IN_INV_MASK_SFT (0x1 << 20)
435	#define PCM0_TX_LCH_RPT_SFT 19
436	#define PCM0_TX_LCH_RPT_MASK 0x1
437	#define PCM0_TX_LCH_RPT_MASK_SFT (0x1 << 19)
438	#define PCM0_VBT_16K_MODE_SFT 18
439	#define PCM0_VBT_16K_MODE_MASK 0x1
440	#define PCM0_VBT_16K_MODE_MASK_SFT (0x1 << 18)
441	#define PCM0_BIT_LENGTH_SFT 16
442	#define PCM0_BIT_LENGTH_MASK 0x3
443	#define PCM0_BIT_LENGTH_MASK_SFT (0x3 << 16)
444	#define PCM0_WLEN_SFT 14
445	#define PCM0_WLEN_MASK 0x3
446	#define PCM0_WLEN_MASK_SFT (0x3 << 14)
447	#define PCM0_SYNC_LENGTH_SFT 9
448	#define PCM0_SYNC_LENGTH_MASK 0x1f
449	#define PCM0_SYNC_LENGTH_MASK_SFT (0x1f << 9)
450	#define PCM0_SYNC_TYPE_SFT 8
451	#define PCM0_SYNC_TYPE_MASK 0x1
452	#define PCM0_SYNC_TYPE_MASK_SFT (0x1 << 8)
453	#define PCM0_BYP_ASRC_SFT 7
454	#define PCM0_BYP_ASRC_MASK 0x1
455	#define PCM0_BYP_ASRC_MASK_SFT (0x1 << 7)
456	#define PCM0_SLAVE_SFT 6
457	#define PCM0_SLAVE_MASK 0x1
458	#define PCM0_SLAVE_MASK_SFT (0x1 << 6)
459	#define PCM0_MODE_SFT 3
460	#define PCM0_MODE_MASK 0x7
461	#define PCM0_MODE_MASK_SFT (0x7 << 3)
462	#define PCM0_FMT_SFT 1
463	#define PCM0_FMT_MASK 0x3
464	#define PCM0_FMT_MASK_SFT (0x3 << 1)
465	#define PCM0_EN_SFT 0
466	#define PCM0_EN_MASK 0x1
467	#define PCM0_EN_MASK_SFT (0x1 << 0)
468
469	/* AFE_PCM0_INTF_CON1 */
470	#define PCM0_TX_RX_LOOPBACK_SFT 31
471	#define PCM0_TX_RX_LOOPBACK_MASK 0x1
472	#define PCM0_TX_RX_LOOPBACK_MASK_SFT (0x1 << 31)
473	#define PCM0_BUFFER_LOOPBACK_SFT 30
474	#define PCM0_BUFFER_LOOPBACK_MASK 0x1
475	#define PCM0_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
476	#define PCM0_PARALLEL_LOOPBACK_SFT 29
477	#define PCM0_PARALLEL_LOOPBACK_MASK 0x1
478	#define PCM0_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
479	#define PCM0_SERIAL_LOOPBACK_SFT 28
480	#define PCM0_SERIAL_LOOPBACK_MASK 0x1
481	#define PCM0_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
482	#define PCM0_DAI_LOOPBACK_SFT 27
483	#define PCM0_DAI_LOOPBACK_MASK 0x1
484	#define PCM0_DAI_LOOPBACK_MASK_SFT (0x1 << 27)
485	#define PCM0_I2S_LOOPBACK_SFT 26
486	#define PCM0_I2S_LOOPBACK_MASK 0x1
487	#define PCM0_I2S_LOOPBACK_MASK_SFT (0x1 << 26)
488	#define PCM0_1X_EN_DOMAIN_SFT 23
489	#define PCM0_1X_EN_DOMAIN_MASK 0x7
490	#define PCM0_1X_EN_DOMAIN_MASK_SFT (0x7 << 23)
491	#define PCM0_1X_EN_MODE_SFT 18
492	#define PCM0_1X_EN_MODE_MASK 0x1f
493	#define PCM0_1X_EN_MODE_MASK_SFT (0x1f << 18)
494	#define PCM0_TX3_RCH_DBG_MODE_SFT 17
495	#define PCM0_TX3_RCH_DBG_MODE_MASK 0x1
496	#define PCM0_TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)
497	#define PCM0_PCM1_LOOPBACK_SFT 16
498	#define PCM0_PCM1_LOOPBACK_MASK 0x1
499	#define PCM0_PCM1_LOOPBACK_MASK_SFT (0x1 << 16)
500	#define PCM0_LOOPBACK_CH_SEL_SFT 12
501	#define PCM0_LOOPBACK_CH_SEL_MASK 0x3
502	#define PCM0_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 12)
503	#define PCM0_BT_MODE_SFT 11
504	#define PCM0_BT_MODE_MASK 0x1
505	#define PCM0_BT_MODE_MASK_SFT (0x1 << 11)
506	#define PCM0_EXT_MODEM_SFT 10
507	#define PCM0_EXT_MODEM_MASK 0x1
508	#define PCM0_EXT_MODEM_MASK_SFT (0x1 << 10)
509	#define PCM0_USE_MD3_SFT 9
510	#define PCM0_USE_MD3_MASK 0x1
511	#define PCM0_USE_MD3_MASK_SFT (0x1 << 9)
512	#define PCM0_FIX_VALUE_SEL_SFT 8
513	#define PCM0_FIX_VALUE_SEL_MASK 0x1
514	#define PCM0_FIX_VALUE_SEL_MASK_SFT (0x1 << 8)
515	#define PCM0_TX_FIX_VALUE_SFT 0
516	#define PCM0_TX_FIX_VALUE_MASK 0xff
517	#define PCM0_TX_FIX_VALUE_MASK_SFT (0xff << 0)
518
519	/* AFE_PCM_INTF_MON */
520	#define PCM0_TX_FIFO_OV_SFT 5
521	#define PCM0_TX_FIFO_OV_MASK 0x1
522	#define PCM0_TX_FIFO_OV_MASK_SFT (0x1 << 5)
523	#define PCM0_RX_FIFO_OV_SFT 4
524	#define PCM0_RX_FIFO_OV_MASK 0x1
525	#define PCM0_RX_FIFO_OV_MASK_SFT (0x1 << 4)
526	#define PCM1_TX_FIFO_OV_SFT 3
527	#define PCM1_TX_FIFO_OV_MASK 0x1
528	#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 3)
529	#define PCM1_RX_FIFO_OV_SFT 2
530	#define PCM1_RX_FIFO_OV_MASK 0x1
531	#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 2)
532	#define PCM0_SYNC_GLITCH_SFT 1
533	#define PCM0_SYNC_GLITCH_MASK 0x1
534	#define PCM0_SYNC_GLITCH_MASK_SFT (0x1 << 1)
535	#define PCM1_SYNC_GLITCH_SFT 0
536	#define PCM1_SYNC_GLITCH_MASK 0x1
537	#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 0)
538
539	/* AFE_PCM_TOP_IP_VERSION */
540	#define AFE_PCM_TOP_IP_VERSION_SFT 0
541	#define AFE_PCM_TOP_IP_VERSION_MASK 0xffffffff
542	#define AFE_PCM_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0)
543
544	/* AFE_IRQ_MCU_EN */
545	#define AFE_IRQ_MCU_EN_SFT 0
546	#define AFE_IRQ_MCU_EN_MASK 0xffffffff
547	#define AFE_IRQ_MCU_EN_MASK_SFT (0xffffffff << 0)
548
549	/* AFE_IRQ_MCU_DSP_EN */
550	#define AFE_IRQ_DSP_EN_SFT 0
551	#define AFE_IRQ_DSP_EN_MASK 0xffffffff
552	#define AFE_IRQ_DSP_EN_MASK_SFT (0xffffffff << 0)
553
554	/* AFE_IRQ_MCU_DSP2_EN */
555	#define AFE_IRQ_DSP2_EN_SFT 0
556	#define AFE_IRQ_DSP2_EN_MASK 0xffffffff
557	#define AFE_IRQ_DSP2_EN_MASK_SFT (0xffffffff << 0)
558
559	/* AFE_IRQ_MCU_SCP_EN */
560	#define IRQ31_MCU_SCP_EN_SFT 31
561	#define IRQ30_MCU_SCP_EN_SFT 30
562	#define IRQ29_MCU_SCP_EN_SFT 29
563	#define IRQ28_MCU_SCP_EN_SFT 28
564	#define IRQ27_MCU_SCP_EN_SFT 27
565	#define IRQ26_MCU_SCP_EN_SFT 26
566	#define IRQ25_MCU_SCP_EN_SFT 25
567	#define IRQ24_MCU_SCP_EN_SFT 24
568	#define IRQ23_MCU_SCP_EN_SFT 23
569	#define IRQ22_MCU_SCP_EN_SFT 22
570	#define IRQ21_MCU_SCP_EN_SFT 21
571	#define IRQ20_MCU_SCP_EN_SFT 20
572	#define IRQ19_MCU_SCP_EN_SFT 19
573	#define IRQ18_MCU_SCP_EN_SFT 18
574	#define IRQ17_MCU_SCP_EN_SFT 17
575	#define IRQ16_MCU_SCP_EN_SFT 16
576	#define IRQ15_MCU_SCP_EN_SFT 15
577	#define IRQ14_MCU_SCP_EN_SFT 14
578	#define IRQ13_MCU_SCP_EN_SFT 13
579	#define IRQ12_MCU_SCP_EN_SFT 12
580	#define IRQ11_MCU_SCP_EN_SFT 11
581	#define IRQ10_MCU_SCP_EN_SFT 10
582	#define IRQ9_MCU_SCP_EN_SFT 9
583	#define IRQ8_MCU_SCP_EN_SFT 8
584	#define IRQ7_MCU_SCP_EN_SFT 7
585	#define IRQ6_MCU_SCP_EN_SFT 6
586	#define IRQ5_MCU_SCP_EN_SFT 5
587	#define IRQ4_MCU_SCP_EN_SFT 4
588	#define IRQ3_MCU_SCP_EN_SFT 3
589	#define IRQ2_MCU_SCP_EN_SFT 2
590	#define IRQ1_MCU_SCP_EN_SFT 1
591	#define IRQ0_MCU_SCP_EN_SFT 0
592
593	/* AFE_CUSTOM_IRQ_MCU_EN */
594	#define AFE_CUSTOM_IRQ_MCU_EN_SFT 0
595	#define AFE_CUSTOM_IRQ_MCU_EN_MASK 0xffffffff
596	#define AFE_CUSTOM_IRQ_MCU_EN_MASK_SFT (0xffffffff << 0)
597
598	/* AFE_CUSTOM_IRQ_MCU_DSP_EN */
599	#define AFE_CUSTOM_IRQ_DSP_EN_SFT 0
600	#define AFE_CUSTOM_IRQ_DSP_EN_MASK 0xffffffff
601	#define AFE_CUSTOM_IRQ_DSP_EN_MASK_SFT (0xffffffff << 0)
602
603	/* AFE_CUSTOM_IRQ_MCU_DSP2_EN */
604	#define AFE_CUSTOM_IRQ_DSP2_EN_SFT 0
605	#define AFE_CUSTOM_IRQ_DSP2_EN_MASK 0xffffffff
606	#define AFE_CUSTOM_IRQ_DSP2_EN_MASK_SFT (0xffffffff << 0)
607
608	/* AFE_CUSTOM_IRQ_MCU_SCP_EN */
609	#define AFE_CUSTOM_IRQ_SCP_EN_SFT 0
610	#define AFE_CUSTOM_IRQ_SCP_EN_MASK 0xffffffff
611	#define AFE_CUSTOM_IRQ_SCP_EN_MASK_SFT (0xffffffff << 0)
612
613	/* AFE_IRQ_MCU_STATUS */
614	#define IRQ26_MCU_SFT 26
615	#define IRQ26_MCU_MASK 0x1
616	#define IRQ26_MCU_MASK_SFT (0x1 << 26)
617	#define IRQ25_MCU_SFT 25
618	#define IRQ25_MCU_MASK 0x1
619	#define IRQ25_MCU_MASK_SFT (0x1 << 25)
620	#define IRQ24_MCU_SFT 24
621	#define IRQ24_MCU_MASK 0x1
622	#define IRQ24_MCU_MASK_SFT (0x1 << 24)
623	#define IRQ23_MCU_SFT 23
624	#define IRQ23_MCU_MASK 0x1
625	#define IRQ23_MCU_MASK_SFT (0x1 << 23)
626	#define IRQ22_MCU_SFT 22
627	#define IRQ22_MCU_MASK 0x1
628	#define IRQ22_MCU_MASK_SFT (0x1 << 22)
629	#define IRQ21_MCU_SFT 21
630	#define IRQ21_MCU_MASK 0x1
631	#define IRQ21_MCU_MASK_SFT (0x1 << 21)
632	#define IRQ20_MCU_SFT 20
633	#define IRQ20_MCU_MASK 0x1
634	#define IRQ20_MCU_MASK_SFT (0x1 << 20)
635	#define IRQ19_MCU_SFT 19
636	#define IRQ19_MCU_MASK 0x1
637	#define IRQ19_MCU_MASK_SFT (0x1 << 19)
638	#define IRQ18_MCU_SFT 18
639	#define IRQ18_MCU_MASK 0x1
640	#define IRQ18_MCU_MASK_SFT (0x1 << 18)
641	#define IRQ17_MCU_SFT 17
642	#define IRQ17_MCU_MASK 0x1
643	#define IRQ17_MCU_MASK_SFT (0x1 << 17)
644	#define IRQ16_MCU_SFT 16
645	#define IRQ16_MCU_MASK 0x1
646	#define IRQ16_MCU_MASK_SFT (0x1 << 16)
647	#define IRQ15_MCU_SFT 15
648	#define IRQ15_MCU_MASK 0x1
649	#define IRQ15_MCU_MASK_SFT (0x1 << 15)
650	#define IRQ14_MCU_SFT 14
651	#define IRQ14_MCU_MASK 0x1
652	#define IRQ14_MCU_MASK_SFT (0x1 << 14)
653	#define IRQ13_MCU_SFT 13
654	#define IRQ13_MCU_MASK 0x1
655	#define IRQ13_MCU_MASK_SFT (0x1 << 13)
656	#define IRQ12_MCU_SFT 12
657	#define IRQ12_MCU_MASK 0x1
658	#define IRQ12_MCU_MASK_SFT (0x1 << 12)
659	#define IRQ11_MCU_SFT 11
660	#define IRQ11_MCU_MASK 0x1
661	#define IRQ11_MCU_MASK_SFT (0x1 << 11)
662	#define IRQ10_MCU_SFT 10
663	#define IRQ10_MCU_MASK 0x1
664	#define IRQ10_MCU_MASK_SFT (0x1 << 10)
665	#define IRQ9_MCU_SFT 9
666	#define IRQ9_MCU_MASK 0x1
667	#define IRQ9_MCU_MASK_SFT (0x1 << 9)
668	#define IRQ8_MCU_SFT 8
669	#define IRQ8_MCU_MASK 0x1
670	#define IRQ8_MCU_MASK_SFT (0x1 << 8)
671	#define IRQ7_MCU_SFT 7
672	#define IRQ7_MCU_MASK 0x1
673	#define IRQ7_MCU_MASK_SFT (0x1 << 7)
674	#define IRQ6_MCU_SFT 6
675	#define IRQ6_MCU_MASK 0x1
676	#define IRQ6_MCU_MASK_SFT (0x1 << 6)
677	#define IRQ5_MCU_SFT 5
678	#define IRQ5_MCU_MASK 0x1
679	#define IRQ5_MCU_MASK_SFT (0x1 << 5)
680	#define IRQ4_MCU_SFT 4
681	#define IRQ4_MCU_MASK 0x1
682	#define IRQ4_MCU_MASK_SFT (0x1 << 4)
683	#define IRQ3_MCU_SFT 3
684	#define IRQ3_MCU_MASK 0x1
685	#define IRQ3_MCU_MASK_SFT (0x1 << 3)
686	#define IRQ2_MCU_SFT 2
687	#define IRQ2_MCU_MASK 0x1
688	#define IRQ2_MCU_MASK_SFT (0x1 << 2)
689	#define IRQ1_MCU_SFT 1
690	#define IRQ1_MCU_MASK 0x1
691	#define IRQ1_MCU_MASK_SFT (0x1 << 1)
692	#define IRQ0_MCU_SFT 0
693	#define IRQ0_MCU_MASK 0x1
694	#define IRQ0_MCU_MASK_SFT (0x1 << 0)
695
696	/* AFE_CUSTOM_IRQ_MCU_STATUS */
697	#define CUSTOM_IRQ21_MCU_SFT 21
698	#define CUSTOM_IRQ21_MCU_MASK 0x1
699	#define CUSTOM_IRQ21_MCU_MASK_SFT (0x1 << 21)
700	#define CUSTOM_IRQ20_MCU_SFT 20
701	#define CUSTOM_IRQ20_MCU_MASK 0x1
702	#define CUSTOM_IRQ20_MCU_MASK_SFT (0x1 << 20)
703	#define CUSTOM_IRQ19_MCU_SFT 19
704	#define CUSTOM_IRQ19_MCU_MASK 0x1
705	#define CUSTOM_IRQ19_MCU_MASK_SFT (0x1 << 19)
706	#define CUSTOM_IRQ18_MCU_SFT 18
707	#define CUSTOM_IRQ18_MCU_MASK 0x1
708	#define CUSTOM_IRQ18_MCU_MASK_SFT (0x1 << 18)
709	#define CUSTOM_IRQ17_MCU_SFT 17
710	#define CUSTOM_IRQ17_MCU_MASK 0x1
711	#define CUSTOM_IRQ17_MCU_MASK_SFT (0x1 << 17)
712	#define CUSTOM_IRQ16_MCU_SFT 16
713	#define CUSTOM_IRQ16_MCU_MASK 0x1
714	#define CUSTOM_IRQ16_MCU_MASK_SFT (0x1 << 16)
715	#define CUSTOM_IRQ9_MCU_SFT 9
716	#define CUSTOM_IRQ9_MCU_MASK 0x1
717	#define CUSTOM_IRQ9_MCU_MASK_SFT (0x1 << 9)
718	#define CUSTOM_IRQ8_MCU_SFT 8
719	#define CUSTOM_IRQ8_MCU_MASK 0x1
720	#define CUSTOM_IRQ8_MCU_MASK_SFT (0x1 << 8)
721	#define CUSTOM_IRQ7_MCU_SFT 7
722	#define CUSTOM_IRQ7_MCU_MASK 0x1
723	#define CUSTOM_IRQ7_MCU_MASK_SFT (0x1 << 7)
724	#define CUSTOM_IRQ6_MCU_SFT 6
725	#define CUSTOM_IRQ6_MCU_MASK 0x1
726	#define CUSTOM_IRQ6_MCU_MASK_SFT (0x1 << 6)
727	#define CUSTOM_IRQ5_MCU_SFT 5
728	#define CUSTOM_IRQ5_MCU_MASK 0x1
729	#define CUSTOM_IRQ5_MCU_MASK_SFT (0x1 << 5)
730	#define CUSTOM_IRQ4_MCU_SFT 4
731	#define CUSTOM_IRQ4_MCU_MASK 0x1
732	#define CUSTOM_IRQ4_MCU_MASK_SFT (0x1 << 4)
733	#define CUSTOM_IRQ3_MCU_SFT 3
734	#define CUSTOM_IRQ3_MCU_MASK 0x1
735	#define CUSTOM_IRQ3_MCU_MASK_SFT (0x1 << 3)
736	#define CUSTOM_IRQ2_MCU_SFT 2
737	#define CUSTOM_IRQ2_MCU_MASK 0x1
738	#define CUSTOM_IRQ2_MCU_MASK_SFT (0x1 << 2)
739	#define CUSTOM_IRQ1_MCU_SFT 1
740	#define CUSTOM_IRQ1_MCU_MASK 0x1
741	#define CUSTOM_IRQ1_MCU_MASK_SFT (0x1 << 1)
742	#define CUSTOM_IRQ0_MCU_SFT 0
743	#define CUSTOM_IRQ0_MCU_MASK 0x1
744	#define CUSTOM_IRQ0_MCU_MASK_SFT (0x1 << 0)
745
746	/* AFE_IRQ_MCU_CFG */
747	#define AFE_IRQ_CLR_CFG_SFT 31
748	#define AFE_IRQ_CLR_CFG_MASK 0x1
749	#define AFE_IRQ_CLR_CFG_MASK_SFT (0x1 << 31)
750	#define AFE_IRQ_MISS_FLAG_CLR_CFG_SFT 30
751	#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK 0x1
752	#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
753	#define AFE_IRQ_MCU_CNT_SFT 0
754	#define AFE_IRQ_MCU_CNT_MASK 0xffffff
755	#define AFE_IRQ_MCU_CNT_MASK_SFT (0xffffff << 0)
756
757	/* AFE_IRQ0_MCU_CFG0 */
758	#define AFE_IRQ0_MCU_DOMAIN_SFT 9
759	#define AFE_IRQ0_MCU_DOMAIN_MASK 0x7
760	#define AFE_IRQ0_MCU_DOMAIN_MASK_SFT (0x7 << 9)
761	#define AFE_IRQ0_MCU_FS_SFT 4
762	#define AFE_IRQ0_MCU_FS_MASK 0x1f
763	#define AFE_IRQ0_MCU_FS_MASK_SFT (0x1f << 4)
764	#define AFE_IRQ0_MCU_ON_SFT 0
765	#define AFE_IRQ0_MCU_ON_MASK 0x1
766	#define AFE_IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
767
768	/* AFE_IRQ0_MCU_CFG1 */
769	#define AFE_IRQ0_CLR_CFG_SFT 31
770	#define AFE_IRQ0_CLR_CFG_MASK 0x1
771	#define AFE_IRQ0_CLR_CFG_MASK_SFT (0x1 << 31)
772	#define AFE_IRQ0_MISS_FLAG_CLR_CFG_SFT 30
773	#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK 0x1
774	#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
775	#define AFE_IRQ0_MCU_CNT_SFT 0
776	#define AFE_IRQ0_MCU_CNT_MASK 0xffffff
777	#define AFE_IRQ0_MCU_CNT_MASK_SFT (0xffffff << 0)
778
779	/* AFE_IRQ1_MCU_CFG0 */
780	#define AFE_IRQ1_MCU_DOMAIN_SFT 9
781	#define AFE_IRQ1_MCU_DOMAIN_MASK 0x7
782	#define AFE_IRQ1_MCU_DOMAIN_MASK_SFT (0x7 << 9)
783	#define AFE_IRQ1_MCU_FS_SFT 4
784	#define AFE_IRQ1_MCU_FS_MASK 0x1f
785	#define AFE_IRQ1_MCU_FS_MASK_SFT (0x1f << 4)
786	#define AFE_IRQ1_MCU_ON_SFT 0
787	#define AFE_IRQ1_MCU_ON_MASK 0x1
788	#define AFE_IRQ1_MCU_ON_MASK_SFT (0x1 << 0)
789
790	/* AFE_IRQ1_MCU_CFG1 */
791	#define AFE_IRQ1_CLR_CFG_SFT 31
792	#define AFE_IRQ1_CLR_CFG_MASK 0x1
793	#define AFE_IRQ1_CLR_CFG_MASK_SFT (0x1 << 31)
794	#define AFE_IRQ1_MISS_FLAG_CLR_CFG_SFT 30
795	#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK 0x1
796	#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
797	#define AFE_IRQ1_MCU_CNT_SFT 0
798	#define AFE_IRQ1_MCU_CNT_MASK 0xffffff
799	#define AFE_IRQ1_MCU_CNT_MASK_SFT (0xffffff << 0)
800
801	/* AFE_IRQ2_MCU_CFG0 */
802	#define AFE_IRQ2_MCU_DOMAIN_SFT 9
803	#define AFE_IRQ2_MCU_DOMAIN_MASK 0x7
804	#define AFE_IRQ2_MCU_DOMAIN_MASK_SFT (0x7 << 9)
805	#define AFE_IRQ2_MCU_FS_SFT 4
806	#define AFE_IRQ2_MCU_FS_MASK 0x1f
807	#define AFE_IRQ2_MCU_FS_MASK_SFT (0x1f << 4)
808	#define AFE_IRQ2_MCU_ON_SFT 0
809	#define AFE_IRQ2_MCU_ON_MASK 0x1
810	#define AFE_IRQ2_MCU_ON_MASK_SFT (0x1 << 0)
811
812	/* AFE_IRQ2_MCU_CFG1 */
813	#define AFE_IRQ2_CLR_CFG_SFT 31
814	#define AFE_IRQ2_CLR_CFG_MASK 0x1
815	#define AFE_IRQ2_CLR_CFG_MASK_SFT (0x1 << 31)
816	#define AFE_IRQ2_MISS_FLAG_CLR_CFG_SFT 30
817	#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK 0x1
818	#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
819	#define AFE_IRQ2_MCU_CNT_SFT 0
820	#define AFE_IRQ2_MCU_CNT_MASK 0xffffff
821	#define AFE_IRQ2_MCU_CNT_MASK_SFT (0xffffff << 0)
822
823	/* AFE_IRQ3_MCU_CFG0 */
824	#define AFE_IRQ3_MCU_DOMAIN_SFT 9
825	#define AFE_IRQ3_MCU_DOMAIN_MASK 0x7
826	#define AFE_IRQ3_MCU_DOMAIN_MASK_SFT (0x7 << 9)
827	#define AFE_IRQ3_MCU_FS_SFT 4
828	#define AFE_IRQ3_MCU_FS_MASK 0x1f
829	#define AFE_IRQ3_MCU_FS_MASK_SFT (0x1f << 4)
830	#define AFE_IRQ3_MCU_ON_SFT 0
831	#define AFE_IRQ3_MCU_ON_MASK 0x1
832	#define AFE_IRQ3_MCU_ON_MASK_SFT (0x1 << 0)
833
834	/* AFE_IRQ3_MCU_CFG1 */
835	#define AFE_IRQ3_CLR_CFG_SFT 31
836	#define AFE_IRQ3_CLR_CFG_MASK 0x1
837	#define AFE_IRQ3_CLR_CFG_MASK_SFT (0x1 << 31)
838	#define AFE_IRQ3_MISS_FLAG_CLR_CFG_SFT 30
839	#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK 0x1
840	#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
841	#define AFE_IRQ3_MCU_CNT_SFT 0
842	#define AFE_IRQ3_MCU_CNT_MASK 0xffffff
843	#define AFE_IRQ3_MCU_CNT_MASK_SFT (0xffffff << 0)
844
845	/* AFE_IRQ4_MCU_CFG0 */
846	#define AFE_IRQ4_MCU_DOMAIN_SFT 9
847	#define AFE_IRQ4_MCU_DOMAIN_MASK 0x7
848	#define AFE_IRQ4_MCU_DOMAIN_MASK_SFT (0x7 << 9)
849	#define AFE_IRQ4_MCU_FS_SFT 4
850	#define AFE_IRQ4_MCU_FS_MASK 0x1f
851	#define AFE_IRQ4_MCU_FS_MASK_SFT (0x1f << 4)
852	#define AFE_IRQ4_MCU_ON_SFT 0
853	#define AFE_IRQ4_MCU_ON_MASK 0x1
854	#define AFE_IRQ4_MCU_ON_MASK_SFT (0x1 << 0)
855
856	/* AFE_IRQ4_MCU_CFG1 */
857	#define AFE_IRQ4_CLR_CFG_SFT 31
858	#define AFE_IRQ4_CLR_CFG_MASK 0x1
859	#define AFE_IRQ4_CLR_CFG_MASK_SFT (0x1 << 31)
860	#define AFE_IRQ4_MISS_FLAG_CLR_CFG_SFT 30
861	#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK 0x1
862	#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
863	#define AFE_IRQ4_MCU_CNT_SFT 0
864	#define AFE_IRQ4_MCU_CNT_MASK 0xffffff
865	#define AFE_IRQ4_MCU_CNT_MASK_SFT (0xffffff << 0)
866
867	/* AFE_IRQ5_MCU_CFG0 */
868	#define AFE_IRQ5_MCU_DOMAIN_SFT 9
869	#define AFE_IRQ5_MCU_DOMAIN_MASK 0x7
870	#define AFE_IRQ5_MCU_DOMAIN_MASK_SFT (0x7 << 9)
871	#define AFE_IRQ5_MCU_FS_SFT 4
872	#define AFE_IRQ5_MCU_FS_MASK 0x1f
873	#define AFE_IRQ5_MCU_FS_MASK_SFT (0x1f << 4)
874	#define AFE_IRQ5_MCU_ON_SFT 0
875	#define AFE_IRQ5_MCU_ON_MASK 0x1
876	#define AFE_IRQ5_MCU_ON_MASK_SFT (0x1 << 0)
877
878	/* AFE_IRQ5_MCU_CFG1 */
879	#define AFE_IRQ5_CLR_CFG_SFT 31
880	#define AFE_IRQ5_CLR_CFG_MASK 0x1
881	#define AFE_IRQ5_CLR_CFG_MASK_SFT (0x1 << 31)
882	#define AFE_IRQ5_MISS_FLAG_CLR_CFG_SFT 30
883	#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK 0x1
884	#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
885	#define AFE_IRQ5_MCU_CNT_SFT 0
886	#define AFE_IRQ5_MCU_CNT_MASK 0xffffff
887	#define AFE_IRQ5_MCU_CNT_MASK_SFT (0xffffff << 0)
888
889	/* AFE_IRQ6_MCU_CFG0 */
890	#define AFE_IRQ6_MCU_DOMAIN_SFT 9
891	#define AFE_IRQ6_MCU_DOMAIN_MASK 0x7
892	#define AFE_IRQ6_MCU_DOMAIN_MASK_SFT (0x7 << 9)
893	#define AFE_IRQ6_MCU_FS_SFT 4
894	#define AFE_IRQ6_MCU_FS_MASK 0x1f
895	#define AFE_IRQ6_MCU_FS_MASK_SFT (0x1f << 4)
896	#define AFE_IRQ6_MCU_ON_SFT 0
897	#define AFE_IRQ6_MCU_ON_MASK 0x1
898	#define AFE_IRQ6_MCU_ON_MASK_SFT (0x1 << 0)
899
900	/* AFE_IRQ6_MCU_CFG1 */
901	#define AFE_IRQ6_CLR_CFG_SFT 31
902	#define AFE_IRQ6_CLR_CFG_MASK 0x1
903	#define AFE_IRQ6_CLR_CFG_MASK_SFT (0x1 << 31)
904	#define AFE_IRQ6_MISS_FLAG_CLR_CFG_SFT 30
905	#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK 0x1
906	#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
907	#define AFE_IRQ6_MCU_CNT_SFT 0
908	#define AFE_IRQ6_MCU_CNT_MASK 0xffffff
909	#define AFE_IRQ6_MCU_CNT_MASK_SFT (0xffffff << 0)
910
911	/* AFE_IRQ7_MCU_CFG0 */
912	#define AFE_IRQ7_MCU_DOMAIN_SFT 9
913	#define AFE_IRQ7_MCU_DOMAIN_MASK 0x7
914	#define AFE_IRQ7_MCU_DOMAIN_MASK_SFT (0x7 << 9)
915	#define AFE_IRQ7_MCU_FS_SFT 4
916	#define AFE_IRQ7_MCU_FS_MASK 0x1f
917	#define AFE_IRQ7_MCU_FS_MASK_SFT (0x1f << 4)
918	#define AFE_IRQ7_MCU_ON_SFT 0
919	#define AFE_IRQ7_MCU_ON_MASK 0x1
920	#define AFE_IRQ7_MCU_ON_MASK_SFT (0x1 << 0)
921
922	/* AFE_IRQ7_MCU_CFG1 */
923	#define AFE_IRQ7_CLR_CFG_SFT 31
924	#define AFE_IRQ7_CLR_CFG_MASK 0x1
925	#define AFE_IRQ7_CLR_CFG_MASK_SFT (0x1 << 31)
926	#define AFE_IRQ7_MISS_FLAG_CLR_CFG_SFT 30
927	#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK 0x1
928	#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
929	#define AFE_IRQ7_MCU_CNT_SFT 0
930	#define AFE_IRQ7_MCU_CNT_MASK 0xffffff
931	#define AFE_IRQ7_MCU_CNT_MASK_SFT (0xffffff << 0)
932
933	/* AFE_IRQ8_MCU_CFG0 */
934	#define AFE_IRQ8_MCU_DOMAIN_SFT 9
935	#define AFE_IRQ8_MCU_DOMAIN_MASK 0x7
936	#define AFE_IRQ8_MCU_DOMAIN_MASK_SFT (0x7 << 9)
937	#define AFE_IRQ8_MCU_FS_SFT 4
938	#define AFE_IRQ8_MCU_FS_MASK 0x1f
939	#define AFE_IRQ8_MCU_FS_MASK_SFT (0x1f << 4)
940	#define AFE_IRQ8_MCU_ON_SFT 0
941	#define AFE_IRQ8_MCU_ON_MASK 0x1
942	#define AFE_IRQ8_MCU_ON_MASK_SFT (0x1 << 0)
943
944	/* AFE_IRQ8_MCU_CFG1 */
945	#define AFE_IRQ8_CLR_CFG_SFT 31
946	#define AFE_IRQ8_CLR_CFG_MASK 0x1
947	#define AFE_IRQ8_CLR_CFG_MASK_SFT (0x1 << 31)
948	#define AFE_IRQ8_MISS_FLAG_CLR_CFG_SFT 30
949	#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK 0x1
950	#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
951	#define AFE_IRQ8_MCU_CNT_SFT 0
952	#define AFE_IRQ8_MCU_CNT_MASK 0xffffff
953	#define AFE_IRQ8_MCU_CNT_MASK_SFT (0xffffff << 0)
954
955	/* AFE_IRQ9_MCU_CFG0 */
956	#define AFE_IRQ9_MCU_DOMAIN_SFT 9
957	#define AFE_IRQ9_MCU_DOMAIN_MASK 0x7
958	#define AFE_IRQ9_MCU_DOMAIN_MASK_SFT (0x7 << 9)
959	#define AFE_IRQ9_MCU_FS_SFT 4
960	#define AFE_IRQ9_MCU_FS_MASK 0x1f
961	#define AFE_IRQ9_MCU_FS_MASK_SFT (0x1f << 4)
962	#define AFE_IRQ9_MCU_ON_SFT 0
963	#define AFE_IRQ9_MCU_ON_MASK 0x1
964	#define AFE_IRQ9_MCU_ON_MASK_SFT (0x1 << 0)
965
966	/* AFE_IRQ9_MCU_CFG1 */
967	#define AFE_IRQ9_CLR_CFG_SFT 31
968	#define AFE_IRQ9_CLR_CFG_MASK 0x1
969	#define AFE_IRQ9_CLR_CFG_MASK_SFT (0x1 << 31)
970	#define AFE_IRQ9_MISS_FLAG_CLR_CFG_SFT 30
971	#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK 0x1
972	#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
973	#define AFE_IRQ9_MCU_CNT_SFT 0
974	#define AFE_IRQ9_MCU_CNT_MASK 0xffffff
975	#define AFE_IRQ9_MCU_CNT_MASK_SFT (0xffffff << 0)
976
977	/* AFE_IRQ10_MCU_CFG0 */
978	#define AFE_IRQ10_MCU_DOMAIN_SFT 9
979	#define AFE_IRQ10_MCU_DOMAIN_MASK 0x7
980	#define AFE_IRQ10_MCU_DOMAIN_MASK_SFT (0x7 << 9)
981	#define AFE_IRQ10_MCU_FS_SFT 4
982	#define AFE_IRQ10_MCU_FS_MASK 0x1f
983	#define AFE_IRQ10_MCU_FS_MASK_SFT (0x1f << 4)
984	#define AFE_IRQ10_MCU_ON_SFT 0
985	#define AFE_IRQ10_MCU_ON_MASK 0x1
986	#define AFE_IRQ10_MCU_ON_MASK_SFT (0x1 << 0)
987
988	/* AFE_IRQ10_MCU_CFG1 */
989	#define AFE_IRQ10_CLR_CFG_SFT 31
990	#define AFE_IRQ10_CLR_CFG_MASK 0x1
991	#define AFE_IRQ10_CLR_CFG_MASK_SFT (0x1 << 31)
992	#define AFE_IRQ10_MISS_FLAG_CLR_CFG_SFT 30
993	#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK 0x1
994	#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
995	#define AFE_IRQ10_MCU_CNT_SFT 0
996	#define AFE_IRQ10_MCU_CNT_MASK 0xffffff
997	#define AFE_IRQ10_MCU_CNT_MASK_SFT (0xffffff << 0)
998
999	/* AFE_IRQ11_MCU_CFG0 */
1000	#define AFE_IRQ11_MCU_DOMAIN_SFT 9
1001	#define AFE_IRQ11_MCU_DOMAIN_MASK 0x7
1002	#define AFE_IRQ11_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1003	#define AFE_IRQ11_MCU_FS_SFT 4
1004	#define AFE_IRQ11_MCU_FS_MASK 0x1f
1005	#define AFE_IRQ11_MCU_FS_MASK_SFT (0x1f << 4)
1006	#define AFE_IRQ11_MCU_ON_SFT 0
1007	#define AFE_IRQ11_MCU_ON_MASK 0x1
1008	#define AFE_IRQ11_MCU_ON_MASK_SFT (0x1 << 0)
1009
1010	/* AFE_IRQ11_MCU_CFG1 */
1011	#define AFE_IRQ11_CLR_CFG_SFT 31
1012	#define AFE_IRQ11_CLR_CFG_MASK 0x1
1013	#define AFE_IRQ11_CLR_CFG_MASK_SFT (0x1 << 31)
1014	#define AFE_IRQ11_MISS_FLAG_CLR_CFG_SFT 30
1015	#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK 0x1
1016	#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1017	#define AFE_IRQ11_MCU_CNT_SFT 0
1018	#define AFE_IRQ11_MCU_CNT_MASK 0xffffff
1019	#define AFE_IRQ11_MCU_CNT_MASK_SFT (0xffffff << 0)
1020
1021	/* AFE_IRQ12_MCU_CFG0 */
1022	#define AFE_IRQ12_MCU_DOMAIN_SFT 9
1023	#define AFE_IRQ12_MCU_DOMAIN_MASK 0x7
1024	#define AFE_IRQ12_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1025	#define AFE_IRQ12_MCU_FS_SFT 4
1026	#define AFE_IRQ12_MCU_FS_MASK 0x1f
1027	#define AFE_IRQ12_MCU_FS_MASK_SFT (0x1f << 4)
1028	#define AFE_IRQ12_MCU_ON_SFT 0
1029	#define AFE_IRQ12_MCU_ON_MASK 0x1
1030	#define AFE_IRQ12_MCU_ON_MASK_SFT (0x1 << 0)
1031
1032	/* AFE_IRQ12_MCU_CFG1 */
1033	#define AFE_IRQ12_CLR_CFG_SFT 31
1034	#define AFE_IRQ12_CLR_CFG_MASK 0x1
1035	#define AFE_IRQ12_CLR_CFG_MASK_SFT (0x1 << 31)
1036	#define AFE_IRQ12_MISS_FLAG_CLR_CFG_SFT 30
1037	#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK 0x1
1038	#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1039	#define AFE_IRQ12_MCU_CNT_SFT 0
1040	#define AFE_IRQ12_MCU_CNT_MASK 0xffffff
1041	#define AFE_IRQ12_MCU_CNT_MASK_SFT (0xffffff << 0)
1042
1043	/* AFE_IRQ13_MCU_CFG0 */
1044	#define AFE_IRQ13_MCU_DOMAIN_SFT 9
1045	#define AFE_IRQ13_MCU_DOMAIN_MASK 0x7
1046	#define AFE_IRQ13_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1047	#define AFE_IRQ13_MCU_FS_SFT 4
1048	#define AFE_IRQ13_MCU_FS_MASK 0x1f
1049	#define AFE_IRQ13_MCU_FS_MASK_SFT (0x1f << 4)
1050	#define AFE_IRQ13_MCU_ON_SFT 0
1051	#define AFE_IRQ13_MCU_ON_MASK 0x1
1052	#define AFE_IRQ13_MCU_ON_MASK_SFT (0x1 << 0)
1053
1054	/* AFE_IRQ13_MCU_CFG1 */
1055	#define AFE_IRQ13_CLR_CFG_SFT 31
1056	#define AFE_IRQ13_CLR_CFG_MASK 0x1
1057	#define AFE_IRQ13_CLR_CFG_MASK_SFT (0x1 << 31)
1058	#define AFE_IRQ13_MISS_FLAG_CLR_CFG_SFT 30
1059	#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK 0x1
1060	#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1061	#define AFE_IRQ13_MCU_CNT_SFT 0
1062	#define AFE_IRQ13_MCU_CNT_MASK 0xffffff
1063	#define AFE_IRQ13_MCU_CNT_MASK_SFT (0xffffff << 0)
1064
1065	/* AFE_IRQ14_MCU_CFG0 */
1066	#define AFE_IRQ14_MCU_DOMAIN_SFT 9
1067	#define AFE_IRQ14_MCU_DOMAIN_MASK 0x7
1068	#define AFE_IRQ14_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1069	#define AFE_IRQ14_MCU_FS_SFT 4
1070	#define AFE_IRQ14_MCU_FS_MASK 0x1f
1071	#define AFE_IRQ14_MCU_FS_MASK_SFT (0x1f << 4)
1072	#define AFE_IRQ14_MCU_ON_SFT 0
1073	#define AFE_IRQ14_MCU_ON_MASK 0x1
1074	#define AFE_IRQ14_MCU_ON_MASK_SFT (0x1 << 0)
1075
1076	/* AFE_IRQ14_MCU_CFG1 */
1077	#define AFE_IRQ14_CLR_CFG_SFT 31
1078	#define AFE_IRQ14_CLR_CFG_MASK 0x1
1079	#define AFE_IRQ14_CLR_CFG_MASK_SFT (0x1 << 31)
1080	#define AFE_IRQ14_MISS_FLAG_CLR_CFG_SFT 30
1081	#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK 0x1
1082	#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1083	#define AFE_IRQ14_MCU_CNT_SFT 0
1084	#define AFE_IRQ14_MCU_CNT_MASK 0xffffff
1085	#define AFE_IRQ14_MCU_CNT_MASK_SFT (0xffffff << 0)
1086
1087	/* AFE_IRQ15_MCU_CFG0 */
1088	#define AFE_IRQ15_MCU_DOMAIN_SFT 9
1089	#define AFE_IRQ15_MCU_DOMAIN_MASK 0x7
1090	#define AFE_IRQ15_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1091	#define AFE_IRQ15_MCU_FS_SFT 4
1092	#define AFE_IRQ15_MCU_FS_MASK 0x1f
1093	#define AFE_IRQ15_MCU_FS_MASK_SFT (0x1f << 4)
1094	#define AFE_IRQ15_MCU_ON_SFT 0
1095	#define AFE_IRQ15_MCU_ON_MASK 0x1
1096	#define AFE_IRQ15_MCU_ON_MASK_SFT (0x1 << 0)
1097
1098	/* AFE_IRQ15_MCU_CFG1 */
1099	#define AFE_IRQ15_CLR_CFG_SFT 31
1100	#define AFE_IRQ15_CLR_CFG_MASK 0x1
1101	#define AFE_IRQ15_CLR_CFG_MASK_SFT (0x1 << 31)
1102	#define AFE_IRQ15_MISS_FLAG_CLR_CFG_SFT 30
1103	#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK 0x1
1104	#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1105	#define AFE_IRQ15_MCU_CNT_SFT 0
1106	#define AFE_IRQ15_MCU_CNT_MASK 0xffffff
1107	#define AFE_IRQ15_MCU_CNT_MASK_SFT (0xffffff << 0)
1108
1109	/* AFE_IRQ16_MCU_CFG0 */
1110	#define AFE_IRQ16_MCU_DOMAIN_SFT 9
1111	#define AFE_IRQ16_MCU_DOMAIN_MASK 0x7
1112	#define AFE_IRQ16_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1113	#define AFE_IRQ16_MCU_FS_SFT 4
1114	#define AFE_IRQ16_MCU_FS_MASK 0x1f
1115	#define AFE_IRQ16_MCU_FS_MASK_SFT (0x1f << 4)
1116	#define AFE_IRQ16_MCU_ON_SFT 0
1117	#define AFE_IRQ16_MCU_ON_MASK 0x1
1118	#define AFE_IRQ16_MCU_ON_MASK_SFT (0x1 << 0)
1119
1120	/* AFE_IRQ16_MCU_CFG1 */
1121	#define AFE_IRQ16_CLR_CFG_SFT 31
1122	#define AFE_IRQ16_CLR_CFG_MASK 0x1
1123	#define AFE_IRQ16_CLR_CFG_MASK_SFT (0x1 << 31)
1124	#define AFE_IRQ16_MISS_FLAG_CLR_CFG_SFT 30
1125	#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK 0x1
1126	#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1127	#define AFE_IRQ16_MCU_CNT_SFT 0
1128	#define AFE_IRQ16_MCU_CNT_MASK 0xffffff
1129	#define AFE_IRQ16_MCU_CNT_MASK_SFT (0xffffff << 0)
1130
1131	/* AFE_IRQ17_MCU_CFG0 */
1132	#define AFE_IRQ17_MCU_DOMAIN_SFT 9
1133	#define AFE_IRQ17_MCU_DOMAIN_MASK 0x7
1134	#define AFE_IRQ17_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1135	#define AFE_IRQ17_MCU_FS_SFT 4
1136	#define AFE_IRQ17_MCU_FS_MASK 0x1f
1137	#define AFE_IRQ17_MCU_FS_MASK_SFT (0x1f << 4)
1138	#define AFE_IRQ17_MCU_ON_SFT 0
1139	#define AFE_IRQ17_MCU_ON_MASK 0x1
1140	#define AFE_IRQ17_MCU_ON_MASK_SFT (0x1 << 0)
1141
1142	/* AFE_IRQ17_MCU_CFG1 */
1143	#define AFE_IRQ17_CLR_CFG_SFT 31
1144	#define AFE_IRQ17_CLR_CFG_MASK 0x1
1145	#define AFE_IRQ17_CLR_CFG_MASK_SFT (0x1 << 31)
1146	#define AFE_IRQ17_MISS_FLAG_CLR_CFG_SFT 30
1147	#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK 0x1
1148	#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1149	#define AFE_IRQ17_MCU_CNT_SFT 0
1150	#define AFE_IRQ17_MCU_CNT_MASK 0xffffff
1151	#define AFE_IRQ17_MCU_CNT_MASK_SFT (0xffffff << 0)
1152
1153	/* AFE_IRQ18_MCU_CFG0 */
1154	#define AFE_IRQ18_MCU_DOMAIN_SFT 9
1155	#define AFE_IRQ18_MCU_DOMAIN_MASK 0x7
1156	#define AFE_IRQ18_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1157	#define AFE_IRQ18_MCU_FS_SFT 4
1158	#define AFE_IRQ18_MCU_FS_MASK 0x1f
1159	#define AFE_IRQ18_MCU_FS_MASK_SFT (0x1f << 4)
1160	#define AFE_IRQ18_MCU_ON_SFT 0
1161	#define AFE_IRQ18_MCU_ON_MASK 0x1
1162	#define AFE_IRQ18_MCU_ON_MASK_SFT (0x1 << 0)
1163
1164	/* AFE_IRQ18_MCU_CFG1 */
1165	#define AFE_IRQ18_CLR_CFG_SFT 31
1166	#define AFE_IRQ18_CLR_CFG_MASK 0x1
1167	#define AFE_IRQ18_CLR_CFG_MASK_SFT (0x1 << 31)
1168	#define AFE_IRQ18_MISS_FLAG_CLR_CFG_SFT 30
1169	#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK 0x1
1170	#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1171	#define AFE_IRQ18_MCU_CNT_SFT 0
1172	#define AFE_IRQ18_MCU_CNT_MASK 0xffffff
1173	#define AFE_IRQ18_MCU_CNT_MASK_SFT (0xffffff << 0)
1174
1175	/* AFE_IRQ19_MCU_CFG0 */
1176	#define AFE_IRQ19_MCU_DOMAIN_SFT 9
1177	#define AFE_IRQ19_MCU_DOMAIN_MASK 0x7
1178	#define AFE_IRQ19_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1179	#define AFE_IRQ19_MCU_FS_SFT 4
1180	#define AFE_IRQ19_MCU_FS_MASK 0x1f
1181	#define AFE_IRQ19_MCU_FS_MASK_SFT (0x1f << 4)
1182	#define AFE_IRQ19_MCU_ON_SFT 0
1183	#define AFE_IRQ19_MCU_ON_MASK 0x1
1184	#define AFE_IRQ19_MCU_ON_MASK_SFT (0x1 << 0)
1185
1186	/* AFE_IRQ19_MCU_CFG1 */
1187	#define AFE_IRQ19_CLR_CFG_SFT 31
1188	#define AFE_IRQ19_CLR_CFG_MASK 0x1
1189	#define AFE_IRQ19_CLR_CFG_MASK_SFT (0x1 << 31)
1190	#define AFE_IRQ19_MISS_FLAG_CLR_CFG_SFT 30
1191	#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK 0x1
1192	#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1193	#define AFE_IRQ19_MCU_CNT_SFT 0
1194	#define AFE_IRQ19_MCU_CNT_MASK 0xffffff
1195	#define AFE_IRQ19_MCU_CNT_MASK_SFT (0xffffff << 0)
1196
1197	/* AFE_IRQ20_MCU_CFG0 */
1198	#define AFE_IRQ20_MCU_DOMAIN_SFT 9
1199	#define AFE_IRQ20_MCU_DOMAIN_MASK 0x7
1200	#define AFE_IRQ20_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1201	#define AFE_IRQ20_MCU_FS_SFT 4
1202	#define AFE_IRQ20_MCU_FS_MASK 0x1f
1203	#define AFE_IRQ20_MCU_FS_MASK_SFT (0x1f << 4)
1204	#define AFE_IRQ20_MCU_ON_SFT 0
1205	#define AFE_IRQ20_MCU_ON_MASK 0x1
1206	#define AFE_IRQ20_MCU_ON_MASK_SFT (0x1 << 0)
1207
1208	/* AFE_IRQ20_MCU_CFG1 */
1209	#define AFE_IRQ20_CLR_CFG_SFT 31
1210	#define AFE_IRQ20_CLR_CFG_MASK 0x1
1211	#define AFE_IRQ20_CLR_CFG_MASK_SFT (0x1 << 31)
1212	#define AFE_IRQ20_MISS_FLAG_CLR_CFG_SFT 30
1213	#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK 0x1
1214	#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1215	#define AFE_IRQ20_MCU_CNT_SFT 0
1216	#define AFE_IRQ20_MCU_CNT_MASK 0xffffff
1217	#define AFE_IRQ20_MCU_CNT_MASK_SFT (0xffffff << 0)
1218
1219	/* AFE_IRQ21_MCU_CFG0 */
1220	#define AFE_IRQ21_MCU_DOMAIN_SFT 9
1221	#define AFE_IRQ21_MCU_DOMAIN_MASK 0x7
1222	#define AFE_IRQ21_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1223	#define AFE_IRQ21_MCU_FS_SFT 4
1224	#define AFE_IRQ21_MCU_FS_MASK 0x1f
1225	#define AFE_IRQ21_MCU_FS_MASK_SFT (0x1f << 4)
1226	#define AFE_IRQ21_MCU_ON_SFT 0
1227	#define AFE_IRQ21_MCU_ON_MASK 0x1
1228	#define AFE_IRQ21_MCU_ON_MASK_SFT (0x1 << 0)
1229
1230	/* AFE_IRQ21_MCU_CFG1 */
1231	#define AFE_IRQ21_CLR_CFG_SFT 31
1232	#define AFE_IRQ21_CLR_CFG_MASK 0x1
1233	#define AFE_IRQ21_CLR_CFG_MASK_SFT (0x1 << 31)
1234	#define AFE_IRQ21_MISS_FLAG_CLR_CFG_SFT 30
1235	#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK 0x1
1236	#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1237	#define AFE_IRQ21_MCU_CNT_SFT 0
1238	#define AFE_IRQ21_MCU_CNT_MASK 0xffffff
1239	#define AFE_IRQ21_MCU_CNT_MASK_SFT (0xffffff << 0)
1240
1241	/* AFE_IRQ22_MCU_CFG0 */
1242	#define AFE_IRQ22_MCU_DOMAIN_SFT 9
1243	#define AFE_IRQ22_MCU_DOMAIN_MASK 0x7
1244	#define AFE_IRQ22_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1245	#define AFE_IRQ22_MCU_FS_SFT 4
1246	#define AFE_IRQ22_MCU_FS_MASK 0x1f
1247	#define AFE_IRQ22_MCU_FS_MASK_SFT (0x1f << 4)
1248	#define AFE_IRQ22_MCU_ON_SFT 0
1249	#define AFE_IRQ22_MCU_ON_MASK 0x1
1250	#define AFE_IRQ22_MCU_ON_MASK_SFT (0x1 << 0)
1251
1252	/* AFE_IRQ22_MCU_CFG1 */
1253	#define AFE_IRQ22_CLR_CFG_SFT 31
1254	#define AFE_IRQ22_CLR_CFG_MASK 0x1
1255	#define AFE_IRQ22_CLR_CFG_MASK_SFT (0x1 << 31)
1256	#define AFE_IRQ22_MISS_FLAG_CLR_CFG_SFT 30
1257	#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK 0x1
1258	#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1259	#define AFE_IRQ22_MCU_CNT_SFT 0
1260	#define AFE_IRQ22_MCU_CNT_MASK 0xffffff
1261	#define AFE_IRQ22_MCU_CNT_MASK_SFT (0xffffff << 0)
1262
1263	/* AFE_IRQ23_MCU_CFG0 */
1264	#define AFE_IRQ23_MCU_DOMAIN_SFT 9
1265	#define AFE_IRQ23_MCU_DOMAIN_MASK 0x7
1266	#define AFE_IRQ23_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1267	#define AFE_IRQ23_MCU_FS_SFT 4
1268	#define AFE_IRQ23_MCU_FS_MASK 0x1f
1269	#define AFE_IRQ23_MCU_FS_MASK_SFT (0x1f << 4)
1270	#define AFE_IRQ23_MCU_ON_SFT 0
1271	#define AFE_IRQ23_MCU_ON_MASK 0x1
1272	#define AFE_IRQ23_MCU_ON_MASK_SFT (0x1 << 0)
1273
1274	/* AFE_IRQ23_MCU_CFG1 */
1275	#define AFE_IRQ23_CLR_CFG_SFT 31
1276	#define AFE_IRQ23_CLR_CFG_MASK 0x1
1277	#define AFE_IRQ23_CLR_CFG_MASK_SFT (0x1 << 31)
1278	#define AFE_IRQ23_MISS_FLAG_CLR_CFG_SFT 30
1279	#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK 0x1
1280	#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1281	#define AFE_IRQ23_MCU_CNT_SFT 0
1282	#define AFE_IRQ23_MCU_CNT_MASK 0xffffff
1283	#define AFE_IRQ23_MCU_CNT_MASK_SFT (0xffffff << 0)
1284
1285	/* AFE_IRQ24_MCU_CFG0 */
1286	#define AFE_IRQ24_MCU_DOMAIN_SFT 9
1287	#define AFE_IRQ24_MCU_DOMAIN_MASK 0x7
1288	#define AFE_IRQ24_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1289	#define AFE_IRQ24_MCU_FS_SFT 4
1290	#define AFE_IRQ24_MCU_FS_MASK 0x1f
1291	#define AFE_IRQ24_MCU_FS_MASK_SFT (0x1f << 4)
1292	#define AFE_IRQ24_MCU_ON_SFT 0
1293	#define AFE_IRQ24_MCU_ON_MASK 0x1
1294	#define AFE_IRQ24_MCU_ON_MASK_SFT (0x1 << 0)
1295
1296	/* AFE_IRQ24_MCU_CFG1 */
1297	#define AFE_IRQ24_CLR_CFG_SFT 31
1298	#define AFE_IRQ24_CLR_CFG_MASK 0x1
1299	#define AFE_IRQ24_CLR_CFG_MASK_SFT (0x1 << 31)
1300	#define AFE_IRQ24_MISS_FLAG_CLR_CFG_SFT 30
1301	#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK 0x1
1302	#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1303	#define AFE_IRQ24_MCU_CNT_SFT 0
1304	#define AFE_IRQ24_MCU_CNT_MASK 0xffffff
1305	#define AFE_IRQ24_MCU_CNT_MASK_SFT (0xffffff << 0)
1306
1307	/* AFE_IRQ25_MCU_CFG0 */
1308	#define AFE_IRQ25_MCU_DOMAIN_SFT 9
1309	#define AFE_IRQ25_MCU_DOMAIN_MASK 0x7
1310	#define AFE_IRQ25_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1311	#define AFE_IRQ25_MCU_FS_SFT 4
1312	#define AFE_IRQ25_MCU_FS_MASK 0x1f
1313	#define AFE_IRQ25_MCU_FS_MASK_SFT (0x1f << 4)
1314	#define AFE_IRQ25_MCU_ON_SFT 0
1315	#define AFE_IRQ25_MCU_ON_MASK 0x1
1316	#define AFE_IRQ25_MCU_ON_MASK_SFT (0x1 << 0)
1317
1318	/* AFE_IRQ25_MCU_CFG1 */
1319	#define AFE_IRQ25_CLR_CFG_SFT 31
1320	#define AFE_IRQ25_CLR_CFG_MASK 0x1
1321	#define AFE_IRQ25_CLR_CFG_MASK_SFT (0x1 << 31)
1322	#define AFE_IRQ25_MISS_FLAG_CLR_CFG_SFT 30
1323	#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK 0x1
1324	#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1325	#define AFE_IRQ25_MCU_CNT_SFT 0
1326	#define AFE_IRQ25_MCU_CNT_MASK 0xffffff
1327	#define AFE_IRQ25_MCU_CNT_MASK_SFT (0xffffff << 0)
1328
1329	/* AFE_IRQ26_MCU_CFG0 */
1330	#define AFE_IRQ26_MCU_DOMAIN_SFT 9
1331	#define AFE_IRQ26_MCU_DOMAIN_MASK 0x7
1332	#define AFE_IRQ26_MCU_DOMAIN_MASK_SFT (0x7 << 9)
1333	#define AFE_IRQ26_MCU_FS_SFT 4
1334	#define AFE_IRQ26_MCU_FS_MASK 0x1f
1335	#define AFE_IRQ26_MCU_FS_MASK_SFT (0x1f << 4)
1336	#define AFE_IRQ26_MCU_ON_SFT 0
1337	#define AFE_IRQ26_MCU_ON_MASK 0x1
1338	#define AFE_IRQ26_MCU_ON_MASK_SFT (0x1 << 0)
1339
1340	/* AFE_IRQ26_MCU_CFG1 */
1341	#define AFE_IRQ26_CLR_CFG_SFT 31
1342	#define AFE_IRQ26_CLR_CFG_MASK 0x1
1343	#define AFE_IRQ26_CLR_CFG_MASK_SFT (0x1 << 31)
1344	#define AFE_IRQ26_MISS_FLAG_CLR_CFG_SFT 30
1345	#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK 0x1
1346	#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1347	#define AFE_IRQ26_MCU_CNT_SFT 0
1348	#define AFE_IRQ26_MCU_CNT_MASK 0xffffff
1349	#define AFE_IRQ26_MCU_CNT_MASK_SFT (0xffffff << 0)
1350
1351	/* AFE_CUSTOM_IRQ0_MCU_CFG0 */
1352	#define AFE_CUSTOM_IRQ0_MCU_ON_SFT 0
1353	#define AFE_CUSTOM_IRQ0_MCU_ON_MASK 0x1
1354	#define AFE_CUSTOM_IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
1355
1356	/* AFE_CUSTOM_IRQ0_CNT_MON */
1357	#define AFE_CUSTOM_IRQ0_CNT_MON_SFT 0
1358	#define AFE_CUSTOM_IRQ0_CNT_MON_MASK 0xffffff
1359	#define AFE_CUSTOM_IRQ0_CNT_MON_MASK_SFT (0xffffff << 0)
1360
1361	/* AFE_CUSTOM_IRQ0_MCU_CFG1 */
1362	#define AFE_CUSTOM_IRQ0_CLR_CFG_SFT 31
1363	#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK 0x1
1364	#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK_SFT (0x1 << 31)
1365	#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_SFT 30
1366	#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK 0x1
1367	#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
1368	#define AFE_CUSTOM_IRQ0_MCU_CNT_SFT 0
1369	#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK 0xffffff
1370	#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK_SFT (0xffffff << 0)
1371
1372	/* AFE_IRQ_MCU_MON0 */
1373	#define AFE_IRQ26_MISS_FLAG_SFT 26
1374	#define AFE_IRQ26_MISS_FLAG_MASK 0x1
1375	#define AFE_IRQ26_MISS_FLAG_MASK_SFT (0x1 << 26)
1376	#define AFE_IRQ25_MISS_FLAG_SFT 25
1377	#define AFE_IRQ25_MISS_FLAG_MASK 0x1
1378	#define AFE_IRQ25_MISS_FLAG_MASK_SFT (0x1 << 25)
1379	#define AFE_IRQ24_MISS_FLAG_SFT 24
1380	#define AFE_IRQ24_MISS_FLAG_MASK 0x1
1381	#define AFE_IRQ24_MISS_FLAG_MASK_SFT (0x1 << 24)
1382	#define AFE_IRQ23_MISS_FLAG_SFT 23
1383	#define AFE_IRQ23_MISS_FLAG_MASK 0x1
1384	#define AFE_IRQ23_MISS_FLAG_MASK_SFT (0x1 << 23)
1385	#define AFE_IRQ22_MISS_FLAG_SFT 22
1386	#define AFE_IRQ22_MISS_FLAG_MASK 0x1
1387	#define AFE_IRQ22_MISS_FLAG_MASK_SFT (0x1 << 22)
1388	#define AFE_IRQ21_MISS_FLAG_SFT 21
1389	#define AFE_IRQ21_MISS_FLAG_MASK 0x1
1390	#define AFE_IRQ21_MISS_FLAG_MASK_SFT (0x1 << 21)
1391	#define AFE_IRQ20_MISS_FLAG_SFT 20
1392	#define AFE_IRQ20_MISS_FLAG_MASK 0x1
1393	#define AFE_IRQ20_MISS_FLAG_MASK_SFT (0x1 << 20)
1394	#define AFE_IRQ19_MISS_FLAG_SFT 19
1395	#define AFE_IRQ19_MISS_FLAG_MASK 0x1
1396	#define AFE_IRQ19_MISS_FLAG_MASK_SFT (0x1 << 19)
1397	#define AFE_IRQ18_MISS_FLAG_SFT 18
1398	#define AFE_IRQ18_MISS_FLAG_MASK 0x1
1399	#define AFE_IRQ18_MISS_FLAG_MASK_SFT (0x1 << 18)
1400	#define AFE_IRQ17_MISS_FLAG_SFT 17
1401	#define AFE_IRQ17_MISS_FLAG_MASK 0x1
1402	#define AFE_IRQ17_MISS_FLAG_MASK_SFT (0x1 << 17)
1403	#define AFE_IRQ16_MISS_FLAG_SFT 16
1404	#define AFE_IRQ16_MISS_FLAG_MASK 0x1
1405	#define AFE_IRQ16_MISS_FLAG_MASK_SFT (0x1 << 16)
1406	#define AFE_IRQ15_MISS_FLAG_SFT 15
1407	#define AFE_IRQ15_MISS_FLAG_MASK 0x1
1408	#define AFE_IRQ15_MISS_FLAG_MASK_SFT (0x1 << 15)
1409	#define AFE_IRQ14_MISS_FLAG_SFT 14
1410	#define AFE_IRQ14_MISS_FLAG_MASK 0x1
1411	#define AFE_IRQ14_MISS_FLAG_MASK_SFT (0x1 << 14)
1412	#define AFE_IRQ13_MISS_FLAG_SFT 13
1413	#define AFE_IRQ13_MISS_FLAG_MASK 0x1
1414	#define AFE_IRQ13_MISS_FLAG_MASK_SFT (0x1 << 13)
1415	#define AFE_IRQ12_MISS_FLAG_SFT 12
1416	#define AFE_IRQ12_MISS_FLAG_MASK 0x1
1417	#define AFE_IRQ12_MISS_FLAG_MASK_SFT (0x1 << 12)
1418	#define AFE_IRQ11_MISS_FLAG_SFT 11
1419	#define AFE_IRQ11_MISS_FLAG_MASK 0x1
1420	#define AFE_IRQ11_MISS_FLAG_MASK_SFT (0x1 << 11)
1421	#define AFE_IRQ10_MISS_FLAG_SFT 10
1422	#define AFE_IRQ10_MISS_FLAG_MASK 0x1
1423	#define AFE_IRQ10_MISS_FLAG_MASK_SFT (0x1 << 10)
1424	#define AFE_IRQ9_MISS_FLAG_SFT 9
1425	#define AFE_IRQ9_MISS_FLAG_MASK 0x1
1426	#define AFE_IRQ9_MISS_FLAG_MASK_SFT (0x1 << 9)
1427	#define AFE_IRQ8_MISS_FLAG_SFT 8
1428	#define AFE_IRQ8_MISS_FLAG_MASK 0x1
1429	#define AFE_IRQ8_MISS_FLAG_MASK_SFT (0x1 << 8)
1430	#define AFE_IRQ7_MISS_FLAG_SFT 7
1431	#define AFE_IRQ7_MISS_FLAG_MASK 0x1
1432	#define AFE_IRQ7_MISS_FLAG_MASK_SFT (0x1 << 7)
1433	#define AFE_IRQ6_MISS_FLAG_SFT 6
1434	#define AFE_IRQ6_MISS_FLAG_MASK 0x1
1435	#define AFE_IRQ6_MISS_FLAG_MASK_SFT (0x1 << 6)
1436	#define AFE_IRQ5_MISS_FLAG_SFT 5
1437	#define AFE_IRQ5_MISS_FLAG_MASK 0x1
1438	#define AFE_IRQ5_MISS_FLAG_MASK_SFT (0x1 << 5)
1439	#define AFE_IRQ4_MISS_FLAG_SFT 4
1440	#define AFE_IRQ4_MISS_FLAG_MASK 0x1
1441	#define AFE_IRQ4_MISS_FLAG_MASK_SFT (0x1 << 4)
1442	#define AFE_IRQ3_MISS_FLAG_SFT 3
1443	#define AFE_IRQ3_MISS_FLAG_MASK 0x1
1444	#define AFE_IRQ3_MISS_FLAG_MASK_SFT (0x1 << 3)
1445	#define AFE_IRQ2_MISS_FLAG_SFT 2
1446	#define AFE_IRQ2_MISS_FLAG_MASK 0x1
1447	#define AFE_IRQ2_MISS_FLAG_MASK_SFT (0x1 << 2)
1448	#define AFE_IRQ1_MISS_FLAG_SFT 1
1449	#define AFE_IRQ1_MISS_FLAG_MASK 0x1
1450	#define AFE_IRQ1_MISS_FLAG_MASK_SFT (0x1 << 1)
1451	#define AFE_IRQ0_MISS_FLAG_SFT 0
1452	#define AFE_IRQ0_MISS_FLAG_MASK 0x1
1453	#define AFE_IRQ0_MISS_FLAG_MASK_SFT (0x1 << 0)
1454
1455	/* AFE_IRQ_MCU_MON1 */
1456	#define AFE_CUSTOM_IRQ21_MISS_FLAG_SFT 21
1457	#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK 0x1
1458	#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK_SFT (0x1 << 21)
1459	#define AFE_CUSTOM_IRQ20_MISS_FLAG_SFT 20
1460	#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK 0x1
1461	#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK_SFT (0x1 << 20)
1462	#define AFE_CUSTOM_IRQ19_MISS_FLAG_SFT 19
1463	#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK 0x1
1464	#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK_SFT (0x1 << 19)
1465	#define AFE_CUSTOM_IRQ18_MISS_FLAG_SFT 18
1466	#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK 0x1
1467	#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK_SFT (0x1 << 18)
1468	#define AFE_CUSTOM_IRQ17_MISS_FLAG_SFT 17
1469	#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK 0x1
1470	#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK_SFT (0x1 << 17)
1471	#define AFE_CUSTOM_IRQ16_MISS_FLAG_SFT 16
1472	#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK 0x1
1473	#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK_SFT (0x1 << 16)
1474	#define AFE_CUSTOM_IRQ9_MISS_FLAG_SFT 9
1475	#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK 0x1
1476	#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK_SFT (0x1 << 9)
1477	#define AFE_CUSTOM_IRQ8_MISS_FLAG_SFT 8
1478	#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK 0x1
1479	#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK_SFT (0x1 << 8)
1480	#define AFE_CUSTOM_IRQ7_MISS_FLAG_SFT 7
1481	#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK 0x1
1482	#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK_SFT (0x1 << 7)
1483	#define AFE_CUSTOM_IRQ6_MISS_FLAG_SFT 6
1484	#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK 0x1
1485	#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK_SFT (0x1 << 6)
1486	#define AFE_CUSTOM_IRQ5_MISS_FLAG_SFT 5
1487	#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK 0x1
1488	#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK_SFT (0x1 << 5)
1489	#define AFE_CUSTOM_IRQ4_MISS_FLAG_SFT 4
1490	#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK 0x1
1491	#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK_SFT (0x1 << 4)
1492	#define AFE_CUSTOM_IRQ3_MISS_FLAG_SFT 3
1493	#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK 0x1
1494	#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK_SFT (0x1 << 3)
1495	#define AFE_CUSTOM_IRQ2_MISS_FLAG_SFT 2
1496	#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK 0x1
1497	#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK_SFT (0x1 << 2)
1498	#define AFE_CUSTOM_IRQ1_MISS_FLAG_SFT 1
1499	#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK 0x1
1500	#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK_SFT (0x1 << 1)
1501	#define AFE_CUSTOM_IRQ0_MISS_FLAG_SFT 0
1502	#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK 0x1
1503	#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK_SFT (0x1 << 0)
1504
1505	/* AFE_IRQ_MCU_MON2 */
1506	#define AFE_IRQ_B_R_CNT_SFT 8
1507	#define AFE_IRQ_B_R_CNT_MASK 0xff
1508	#define AFE_IRQ_B_R_CNT_MASK_SFT (0xff << 8)
1509	#define AFE_IRQ_B_F_CNT_SFT 0
1510	#define AFE_IRQ_B_F_CNT_MASK 0xff
1511	#define AFE_IRQ_B_F_CNT_MASK_SFT (0xff << 0)
1512
1513	/* AFE_IRQ0_CNT_MON */
1514	#define AFE_IRQ0_CNT_MON_SFT 0
1515	#define AFE_IRQ0_CNT_MON_MASK 0xffffff
1516	#define AFE_IRQ0_CNT_MON_MASK_SFT (0xffffff << 0)
1517
1518	/* AFE_IRQ1_CNT_MON */
1519	#define AFE_IRQ1_CNT_MON_SFT 0
1520	#define AFE_IRQ1_CNT_MON_MASK 0xffffff
1521	#define AFE_IRQ1_CNT_MON_MASK_SFT (0xffffff << 0)
1522
1523	/* AFE_IRQ2_CNT_MON */
1524	#define AFE_IRQ2_CNT_MON_SFT 0
1525	#define AFE_IRQ2_CNT_MON_MASK 0xffffff
1526	#define AFE_IRQ2_CNT_MON_MASK_SFT (0xffffff << 0)
1527
1528	/* AFE_IRQ3_CNT_MON */
1529	#define AFE_IRQ3_CNT_MON_SFT 0
1530	#define AFE_IRQ3_CNT_MON_MASK 0xffffff
1531	#define AFE_IRQ3_CNT_MON_MASK_SFT (0xffffff << 0)
1532
1533	/* AFE_IRQ4_CNT_MON */
1534	#define AFE_IRQ4_CNT_MON_SFT 0
1535	#define AFE_IRQ4_CNT_MON_MASK 0xffffff
1536	#define AFE_IRQ4_CNT_MON_MASK_SFT (0xffffff << 0)
1537
1538	/* AFE_IRQ5_CNT_MON */
1539	#define AFE_IRQ5_CNT_MON_SFT 0
1540	#define AFE_IRQ5_CNT_MON_MASK 0xffffff
1541	#define AFE_IRQ5_CNT_MON_MASK_SFT (0xffffff << 0)
1542
1543	/* AFE_IRQ6_CNT_MON */
1544	#define AFE_IRQ6_CNT_MON_SFT 0
1545	#define AFE_IRQ6_CNT_MON_MASK 0xffffff
1546	#define AFE_IRQ6_CNT_MON_MASK_SFT (0xffffff << 0)
1547
1548	/* AFE_IRQ7_CNT_MON */
1549	#define AFE_IRQ7_CNT_MON_SFT 0
1550	#define AFE_IRQ7_CNT_MON_MASK 0xffffff
1551	#define AFE_IRQ7_CNT_MON_MASK_SFT (0xffffff << 0)
1552
1553	/* AFE_IRQ8_CNT_MON */
1554	#define AFE_IRQ8_CNT_MON_SFT 0
1555	#define AFE_IRQ8_CNT_MON_MASK 0xffffff
1556	#define AFE_IRQ8_CNT_MON_MASK_SFT (0xffffff << 0)
1557
1558	/* AFE_IRQ9_CNT_MON */
1559	#define AFE_IRQ9_CNT_MON_SFT 0
1560	#define AFE_IRQ9_CNT_MON_MASK 0xffffff
1561	#define AFE_IRQ9_CNT_MON_MASK_SFT (0xffffff << 0)
1562
1563	/* AFE_IRQ10_CNT_MON */
1564	#define AFE_IRQ10_CNT_MON_SFT 0
1565	#define AFE_IRQ10_CNT_MON_MASK 0xffffff
1566	#define AFE_IRQ10_CNT_MON_MASK_SFT (0xffffff << 0)
1567
1568	/* AFE_IRQ11_CNT_MON */
1569	#define AFE_IRQ11_CNT_MON_SFT 0
1570	#define AFE_IRQ11_CNT_MON_MASK 0xffffff
1571	#define AFE_IRQ11_CNT_MON_MASK_SFT (0xffffff << 0)
1572
1573	/* AFE_IRQ12_CNT_MON */
1574	#define AFE_IRQ12_CNT_MON_SFT 0
1575	#define AFE_IRQ12_CNT_MON_MASK 0xffffff
1576	#define AFE_IRQ12_CNT_MON_MASK_SFT (0xffffff << 0)
1577
1578	/* AFE_IRQ13_CNT_MON */
1579	#define AFE_IRQ13_CNT_MON_SFT 0
1580	#define AFE_IRQ13_CNT_MON_MASK 0xffffff
1581	#define AFE_IRQ13_CNT_MON_MASK_SFT (0xffffff << 0)
1582
1583	/* AFE_IRQ14_CNT_MON */
1584	#define AFE_IRQ14_CNT_MON_SFT 0
1585	#define AFE_IRQ14_CNT_MON_MASK 0xffffff
1586	#define AFE_IRQ14_CNT_MON_MASK_SFT (0xffffff << 0)
1587
1588	/* AFE_IRQ15_CNT_MON */
1589	#define AFE_IRQ15_CNT_MON_SFT 0
1590	#define AFE_IRQ15_CNT_MON_MASK 0xffffff
1591	#define AFE_IRQ15_CNT_MON_MASK_SFT (0xffffff << 0)
1592
1593	/* AFE_IRQ16_CNT_MON */
1594	#define AFE_IRQ16_CNT_MON_SFT 0
1595	#define AFE_IRQ16_CNT_MON_MASK 0xffffff
1596	#define AFE_IRQ16_CNT_MON_MASK_SFT (0xffffff << 0)
1597
1598	/* AFE_IRQ17_CNT_MON */
1599	#define AFE_IRQ17_CNT_MON_SFT 0
1600	#define AFE_IRQ17_CNT_MON_MASK 0xffffff
1601	#define AFE_IRQ17_CNT_MON_MASK_SFT (0xffffff << 0)
1602
1603	/* AFE_IRQ18_CNT_MON */
1604	#define AFE_IRQ18_CNT_MON_SFT 0
1605	#define AFE_IRQ18_CNT_MON_MASK 0xffffff
1606	#define AFE_IRQ18_CNT_MON_MASK_SFT (0xffffff << 0)
1607
1608	/* AFE_IRQ19_CNT_MON */
1609	#define AFE_IRQ19_CNT_MON_SFT 0
1610	#define AFE_IRQ19_CNT_MON_MASK 0xffffff
1611	#define AFE_IRQ19_CNT_MON_MASK_SFT (0xffffff << 0)
1612
1613	/* AFE_IRQ20_CNT_MON */
1614	#define AFE_IRQ20_CNT_MON_SFT 0
1615	#define AFE_IRQ20_CNT_MON_MASK 0xffffff
1616	#define AFE_IRQ20_CNT_MON_MASK_SFT (0xffffff << 0)
1617
1618	/* AFE_IRQ21_CNT_MON */
1619	#define AFE_IRQ21_CNT_MON_SFT 0
1620	#define AFE_IRQ21_CNT_MON_MASK 0xffffff
1621	#define AFE_IRQ21_CNT_MON_MASK_SFT (0xffffff << 0)
1622
1623	/* AFE_IRQ22_CNT_MON */
1624	#define AFE_IRQ22_CNT_MON_SFT 0
1625	#define AFE_IRQ22_CNT_MON_MASK 0xffffff
1626	#define AFE_IRQ22_CNT_MON_MASK_SFT (0xffffff << 0)
1627
1628	/* AFE_IRQ23_CNT_MON */
1629	#define AFE_IRQ23_CNT_MON_SFT 0
1630	#define AFE_IRQ23_CNT_MON_MASK 0xffffff
1631	#define AFE_IRQ23_CNT_MON_MASK_SFT (0xffffff << 0)
1632
1633	/* AFE_IRQ24_CNT_MON */
1634	#define AFE_IRQ24_CNT_MON_SFT 0
1635	#define AFE_IRQ24_CNT_MON_MASK 0xffffff
1636	#define AFE_IRQ24_CNT_MON_MASK_SFT (0xffffff << 0)
1637
1638	/* AFE_IRQ25_CNT_MON */
1639	#define AFE_IRQ25_CNT_MON_SFT 0
1640	#define AFE_IRQ25_CNT_MON_MASK 0xffffff
1641	#define AFE_IRQ25_CNT_MON_MASK_SFT (0xffffff << 0)
1642
1643	/* AFE_IRQ26_CNT_MON */
1644	#define AFE_IRQ26_CNT_MON_SFT 0
1645	#define AFE_IRQ26_CNT_MON_MASK 0xffffff
1646	#define AFE_IRQ26_CNT_MON_MASK_SFT (0xffffff << 0)
1647
1648	/* AFE_GAIN0_CON0 */
1649	/* AFE_GAIN1_CON0 */
1650	/* AFE_GAIN2_CON0 */
1651	/* AFE_GAIN3_CON0 */
1652	#define GAIN_TARGET_SYNC_ON_SFT 24
1653	#define GAIN_TARGET_SYNC_ON_MASK 0x1
1654	#define GAIN_TARGET_SYNC_ON_MASK_SFT (0x1 << 24)
1655	#define GAIN_TIMEOUT_SFT 18
1656	#define GAIN_TIMEOUT_MASK 0x3f
1657	#define GAIN_TIMEOUT_MASK_SFT (0x3f << 18)
1658	#define GAIN_TRIG_SFT 17
1659	#define GAIN_TRIG_MASK 0x1
1660	#define GAIN_TRIG_MASK_SFT (0x1 << 17)
1661	#define GAIN_ON_SFT 16
1662	#define GAIN_ON_MASK 0x1
1663	#define GAIN_ON_MASK_SFT (0x1 << 16)
1664	#define GAIN_SAMPLE_PER_STEP_SFT 8
1665	#define GAIN_SAMPLE_PER_STEP_MASK 0xff
1666	#define GAIN_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)
1667	#define GAIN_SEL_DOMAIN_SFT 5
1668	#define GAIN_SEL_DOMAIN_MASK 0x7
1669	#define GAIN_SEL_DOMAIN_MASK_SFT (0x7 << 5)
1670	#define GAIN_SEL_FS_SFT 0
1671	#define GAIN_SEL_FS_MASK 0x1f
1672	#define GAIN_SEL_FS_MASK_SFT (0x1f << 0)
1673
1674	/* AFE_GAIN0_CON1_R */
1675	/* AFE_GAIN1_CON1_R */
1676	/* AFE_GAIN2_CON1_R */
1677	/* AFE_GAIN3_CON1_R */
1678	#define GAIN_TARGET_R_SFT 0
1679	#define GAIN_TARGET_R_MASK 0xffffffff
1680	#define GAIN_TARGET_R_MASK_SFT (0xffffffff << 0)
1681
1682	/* AFE_GAIN0_CON1_L */
1683	/* AFE_GAIN1_CON1_L */
1684	/* AFE_GAIN2_CON1_L */
1685	/* AFE_GAIN3_CON1_L */
1686	#define GAIN_TARGET_L_SFT 0
1687	#define GAIN_TARGET_L_MASK 0xffffffff
1688	#define GAIN_TARGET_L_MASK_SFT (0xffffffff << 0)
1689
1690	/* AFE_GAIN0_CON2 */
1691	/* AFE_GAIN1_CON2 */
1692	/* AFE_GAIN2_CON2 */
1693	/* AFE_GAIN3_CON2 */
1694	#define GAIN_DOWN_STEP_SFT 0
1695	#define GAIN_DOWN_STEP_MASK 0x3fffff
1696	#define GAIN_DOWN_STEP_MASK_SFT (0x3fffff << 0)
1697
1698	/* AFE_GAIN0_CON3 */
1699	/* AFE_GAIN1_CON3 */
1700	/* AFE_GAIN2_CON3 */
1701	/* AFE_GAIN3_CON3 */
1702	#define GAIN_UP_STEP_SFT 0
1703	#define GAIN_UP_STEP_MASK 0x3fffff
1704	#define GAIN_UP_STEP_MASK_SFT (0x3fffff << 0)
1705
1706	/* AFE_GAIN0_CUR_R */
1707	/* AFE_GAIN1_CUR_R */
1708	/* AFE_GAIN2_CUR_R */
1709	/* AFE_GAIN3_CUR_R */
1710	#define AFE_GAIN_CUR_R_SFT 0
1711	#define AFE_GAIN_CUR_R_MASK 0xffffffff
1712	#define AFE_GAIN_CUR_R_MASK_SFT (0xffffffff << 0)
1713
1714	/* AFE_GAIN0_CUR_L */
1715	/* AFE_GAIN1_CUR_L */
1716	/* AFE_GAIN2_CUR_L */
1717	/* AFE_GAIN3_CUR_L */
1718	#define AFE_GAIN_CUR_L_SFT 0
1719	#define AFE_GAIN_CUR_L_MASK 0xffffffff
1720	#define AFE_GAIN_CUR_L_MASK_SFT (0xffffffff << 0)
1721
1722	/* AFE_ADDA_DL_IPM_VER_MON */
1723	#define RG_DL_IPM_VER_MON_SFT 0
1724	#define RG_DL_IPM_VER_MON_MASK 0xffffffff
1725	#define RG_DL_IPM_VER_MON_MASK_SFT (0xffffffff << 0)
1726
1727	/* AFE_ADDA_DL_SRC_CON0 */
1728	#define AFE_DL_INPUT_MODE_CTL_SFT 24
1729	#define AFE_DL_INPUT_MODE_CTL_MASK 0x1f
1730	#define AFE_DL_INPUT_MODE_CTL_MASK_SFT (0x1f << 24)
1731	#define AFE_DL_CH1_SATURATION_EN_CTL_SFT 21
1732	#define AFE_DL_CH1_SATURATION_EN_CTL_MASK 0x1
1733	#define AFE_DL_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 21)
1734	#define AFE_DL_CH2_SATURATION_EN_CTL_SFT 20
1735	#define AFE_DL_CH2_SATURATION_EN_CTL_MASK 0x1
1736	#define AFE_DL_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 20)
1737	#define AFE_DL_OUTPUT_SEL_CTL_SFT 18
1738	#define AFE_DL_OUTPUT_SEL_CTL_MASK 0x3
1739	#define AFE_DL_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 18)
1740	#define AFE_DL_FADEIN_0START_EN_SFT 16
1741	#define AFE_DL_FADEIN_0START_EN_MASK 0x3
1742	#define AFE_DL_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
1743	#define AFE_DL_DISABLE_HW_CG_CTL_SFT 15
1744	#define AFE_DL_DISABLE_HW_CG_CTL_MASK 0x1
1745	#define AFE_DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
1746	#define AFE_DL_MUTE_CH1_OFF_CTL_PRE_SFT 12
1747	#define AFE_DL_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
1748	#define AFE_DL_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
1749	#define AFE_DL_MUTE_CH2_OFF_CTL_PRE_SFT 11
1750	#define AFE_DL_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
1751	#define AFE_DL_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
1752	#define AFE_DL_ARAMPSP_CTL_PRE_SFT 9
1753	#define AFE_DL_ARAMPSP_CTL_PRE_MASK 0x3
1754	#define AFE_DL_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)
1755	#define AFE_DL_VOICE_MODE_CTL_PRE_SFT 5
1756	#define AFE_DL_VOICE_MODE_CTL_PRE_MASK 0x1
1757	#define AFE_DL_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
1758	#define AFE_DL_MUTE_CH1_ON_CTL_PRE_SFT 4
1759	#define AFE_DL_MUTE_CH1_ON_CTL_PRE_MASK 0x1
1760	#define AFE_DL_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
1761	#define AFE_DL_MUTE_CH2_ON_CTL_PRE_SFT 3
1762	#define AFE_DL_MUTE_CH2_ON_CTL_PRE_MASK 0x1
1763	#define AFE_DL_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
1764	#define AFE_DL_GAIN_ON_CTL_PRE_SFT 1
1765	#define AFE_DL_GAIN_ON_CTL_PRE_MASK 0x1
1766	#define AFE_DL_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
1767	#define AFE_DL_SRC_ON_TMP_CTL_PRE_SFT 0
1768	#define AFE_DL_SRC_ON_TMP_CTL_PRE_MASK 0x1
1769	#define AFE_DL_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
1770
1771	/* AFE_ADDA_DL_SRC_CON1 */
1772	#define AFE_DL_GAIN1_CTL_PRE_SFT 16
1773	#define AFE_DL_GAIN1_CTL_PRE_MASK 0xffff
1774	#define AFE_DL_GAIN1_CTL_PRE_MASK_SFT (0xffff << 16)
1775	#define AFE_DL_GAIN2_CTL_PRE_SFT 0
1776	#define AFE_DL_GAIN2_CTL_PRE_MASK 0xffff
1777	#define AFE_DL_GAIN2_CTL_PRE_MASK_SFT (0xffff << 0)
1778
1779	/* AFE_ADDA_DL_SRC_DEBUG_MON0 */
1780	#define AFE_DL_SLT_CNT_FLAG_CTL_SFT 15
1781	#define AFE_DL_SLT_CNT_FLAG_CTL_MASK 0x1
1782	#define AFE_DL_SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 15)
1783	#define AFE_DL_INI_SRAM_FINISH_CTL_SFT 12
1784	#define AFE_DL_INI_SRAM_FINISH_CTL_MASK 0x1
1785	#define AFE_DL_INI_SRAM_FINISH_CTL_MASK_SFT (0x1 << 12)
1786	#define AFE_DL_SLT_COUNTER_CTL_SFT 0
1787	#define AFE_DL_SLT_COUNTER_CTL_MASK 0xfff
1788	#define AFE_DL_SLT_COUNTER_CTL_MASK_SFT (0xfff << 0)
1789
1790	/* AFE_ADDA_DL_PREDIS_CON0 */
1791	#define AFE_DL_PREDIS_ON_CH1_CTL_SFT 31
1792	#define AFE_DL_PREDIS_ON_CH1_CTL_MASK 0x1
1793	#define AFE_DL_PREDIS_ON_CH1_CTL_MASK_SFT (0x1 << 31)
1794	#define AFE_DL_PREDIS_A2_CH1_CTL_SFT 16
1795	#define AFE_DL_PREDIS_A2_CH1_CTL_MASK 0xfff
1796	#define AFE_DL_PREDIS_A2_CH1_CTL_MASK_SFT (0xfff << 16)
1797	#define AFE_DL_PREDIS_A3_CH1_CTL_SFT 0
1798	#define AFE_DL_PREDIS_A3_CH1_CTL_MASK 0xfff
1799	#define AFE_DL_PREDIS_A3_CH1_CTL_MASK_SFT (0xfff << 0)
1800
1801	/* AFE_ADDA_DL_PREDIS_CON1 */
1802	#define AFE_DL_PREDIS_ON_CH2_CTL_SFT 31
1803	#define AFE_DL_PREDIS_ON_CH2_CTL_MASK 0x1
1804	#define AFE_DL_PREDIS_ON_CH2_CTL_MASK_SFT (0x1 << 31)
1805	#define AFE_DL_PREDIS_A2_CH2_CTL_SFT 16
1806	#define AFE_DL_PREDIS_A2_CH2_CTL_MASK 0xfff
1807	#define AFE_DL_PREDIS_A2_CH2_CTL_MASK_SFT (0xfff << 16)
1808	#define AFE_DL_PREDIS_A3_CH2_CTL_SFT 0
1809	#define AFE_DL_PREDIS_A3_CH2_CTL_MASK 0xfff
1810	#define AFE_DL_PREDIS_A3_CH2_CTL_MASK_SFT (0xfff << 0)
1811
1812	/* AFE_ADDA_DL_PREDIS_CON2 */
1813	#define AFE_DL_PREDIS_A4_CH1_CTL_SFT 16
1814	#define AFE_DL_PREDIS_A4_CH1_CTL_MASK 0xfff
1815	#define AFE_DL_PREDIS_A4_CH1_CTL_MASK_SFT (0xfff << 16)
1816	#define AFE_DL_PREDIS_A5_CH1_CTL_SFT 0
1817	#define AFE_DL_PREDIS_A5_CH1_CTL_MASK 0xfff
1818	#define AFE_DL_PREDIS_A5_CH1_CTL_MASK_SFT (0xfff << 0)
1819
1820	/* AFE_ADDA_DL_PREDIS_CON3 */
1821	#define AFE_DL_PREDIS_A4_CH2_CTL_SFT 16
1822	#define AFE_DL_PREDIS_A4_CH2_CTL_MASK 0xfff
1823	#define AFE_DL_PREDIS_A4_CH2_CTL_MASK_SFT (0xfff << 16)
1824	#define AFE_DL_PREDIS_A5_CH2_CTL_SFT 0
1825	#define AFE_DL_PREDIS_A5_CH2_CTL_MASK 0xfff
1826	#define AFE_DL_PREDIS_A5_CH2_CTL_MASK_SFT (0xfff << 0)
1827
1828	/* AFE_ADDA_DL_SDM_DCCOMP_CON */
1829	#define AFE_DL_USE_NEW_2ND_12BIT_SDM_SFT 31
1830	#define AFE_DL_USE_NEW_2ND_12BIT_SDM_MASK 0x1
1831	#define AFE_DL_USE_NEW_2ND_12BIT_SDM_MASK_SFT (0x1 << 31)
1832	#define AFE_DL_USE_NEW_2ND_SDM_SFT 30
1833	#define AFE_DL_USE_NEW_2ND_SDM_MASK 0x1
1834	#define AFE_DL_USE_NEW_2ND_SDM_MASK_SFT (0x1 << 30)
1835	#define AFE_DL_USE_3RD_SDM_SFT 28
1836	#define AFE_DL_USE_3RD_SDM_MASK 0x1
1837	#define AFE_DL_USE_3RD_SDM_MASK_SFT (0x1 << 28)
1838	#define AFE_DL_DCM_AUTO_IDLE_EN_SFT 14
1839	#define AFE_DL_DCM_AUTO_IDLE_EN_MASK 0x1
1840	#define AFE_DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 14)
1841	#define AFE_DL_SRC_DCM_EN_SFT 13
1842	#define AFE_DL_SRC_DCM_EN_MASK 0x1
1843	#define AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 13)
1844	#define AFE_DL_POST_SRC_DCM_EN_SFT 12
1845	#define AFE_DL_POST_SRC_DCM_EN_MASK 0x1
1846	#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 12)
1847	#define AFE_DL_DCCOMP_SYNC_TOGGLE_SFT 11
1848	#define AFE_DL_DCCOMP_SYNC_TOGGLE_MASK 0x1
1849	#define AFE_DL_DCCOMP_SYNC_TOGGLE_MASK_SFT (0x1 << 11)
1850	#define AFE_DL_AUD_SDM_MONO_SFT 9
1851	#define AFE_DL_AUD_SDM_MONO_MASK 0x1
1852	#define AFE_DL_AUD_SDM_MONO_MASK_SFT (0x1 << 9)
1853	#define AFE_DL_AUD_DC_COMP_EN_SFT 8
1854	#define AFE_DL_AUD_DC_COMP_EN_MASK 0x1
1855	#define AFE_DL_AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)
1856	#define AFE_DL_ATTGAIN_CTL_SFT 0
1857	#define AFE_DL_ATTGAIN_CTL_MASK 0x3f
1858	#define AFE_DL_ATTGAIN_CTL_MASK_SFT (0x3f << 0)
1859
1860	/* AFE_ADDA_DL_SDM_TEST */
1861	#define AFE_DL_TRI_AMP_DIV_SFT 12
1862	#define AFE_DL_TRI_AMP_DIV_MASK 0x7
1863	#define AFE_DL_TRI_AMP_DIV_MASK_SFT (0x7 << 12)
1864	#define AFE_DL_TRI_FREQ_DIV_SFT 4
1865	#define AFE_DL_TRI_FREQ_DIV_MASK 0x3f
1866	#define AFE_DL_TRI_FREQ_DIV_MASK_SFT (0x3f << 4)
1867	#define AFE_DL_RG_DL_LEFT_SAT_RSTN_SFT 3
1868	#define AFE_DL_RG_DL_LEFT_SAT_RSTN_MASK 0x1
1869	#define AFE_DL_RG_DL_LEFT_SAT_RSTN_MASK_SFT (0x1 << 3)
1870	#define AFE_DL_RG_DL_RIGHT_SAT_RSTN_SFT 2
1871	#define AFE_DL_RG_DL_RIGHT_SAT_RSTN_MASK 0x1
1872	#define AFE_DL_RG_DL_RIGHT_SAT_RSTN_MASK_SFT (0x1 << 2)
1873	#define AFE_DL_TRI_MUTE_SW_SFT 1
1874	#define AFE_DL_TRI_MUTE_SW_MASK 0x1
1875	#define AFE_DL_TRI_MUTE_SW_MASK_SFT (0x1 << 1)
1876	#define AFE_DL_TRI_DAC_EN_SFT 0
1877	#define AFE_DL_TRI_DAC_EN_MASK 0x1
1878	#define AFE_DL_TRI_DAC_EN_MASK_SFT (0x1 << 0)
1879
1880	/* AFE_ADDA_DL_DC_COMP_CFG0 */
1881	#define AFE_DL_AUD_DC_COMP_LCH_H_SFT 16
1882	#define AFE_DL_AUD_DC_COMP_LCH_H_MASK 0xffff
1883	#define AFE_DL_AUD_DC_COMP_LCH_H_MASK_SFT (0xffff << 16)
1884	#define AFE_DL_AUD_DC_COMP_LCH_L_SFT 0
1885	#define AFE_DL_AUD_DC_COMP_LCH_L_MASK 0xffff
1886	#define AFE_DL_AUD_DC_COMP_LCH_L_MASK_SFT (0xffff << 0)
1887
1888	/* AFE_ADDA_DL_DC_COMP_CFG1 */
1889	#define AFE_DL_AUD_DC_COMP_RCH_H_SFT 16
1890	#define AFE_DL_AUD_DC_COMP_RCH_H_MASK 0xffff
1891	#define AFE_DL_AUD_DC_COMP_RCH_H_MASK_SFT (0xffff << 16)
1892	#define AFE_DL_AUD_DC_COMP_RCH_L_SFT 0
1893	#define AFE_DL_AUD_DC_COMP_RCH_L_MASK 0xffff
1894	#define AFE_DL_AUD_DC_COMP_RCH_L_MASK_SFT (0xffff << 0)
1895
1896	/* AFE_ADDA_DL_SDM_OUT_MON */
1897	#define AFE_DL_SDM_DITHER_MON_SFT 28
1898	#define AFE_DL_SDM_DITHER_MON_MASK 0x3
1899	#define AFE_DL_SDM_DITHER_MON_MASK_SFT (0x3 << 28)
1900	#define AFE_DL_BF_SDM_LEFT_SAT_SFT 21
1901	#define AFE_DL_BF_SDM_LEFT_SAT_MASK 0x1
1902	#define AFE_DL_BF_SDM_LEFT_SAT_MASK_SFT (0x1 << 21)
1903	#define AFE_DL_BF_SDM_RIGHT_SAT_SFT 20
1904	#define AFE_DL_BF_SDM_RIGHT_SAT_MASK 0x1
1905	#define AFE_DL_BF_SDM_RIGHT_SAT_MASK_SFT (0x1 << 20)
1906	#define AFE_DL_3RD_SDM_AUTO_RESET_R_SFT 19
1907	#define AFE_DL_3RD_SDM_AUTO_RESET_R_MASK 0x1
1908	#define AFE_DL_3RD_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 19)
1909	#define AFE_DL_3RD_SDM_AUTO_RESET_L_SFT 18
1910	#define AFE_DL_3RD_SDM_AUTO_RESET_L_MASK 0x1
1911	#define AFE_DL_3RD_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 18)
1912	#define AFE_DL_2ND_SDM_AUTO_RESET_R_SFT 17
1913	#define AFE_DL_2ND_SDM_AUTO_RESET_R_MASK 0x1
1914	#define AFE_DL_2ND_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 17)
1915	#define AFE_DL_2ND_SDM_AUTO_RESET_L_SFT 16
1916	#define AFE_DL_2ND_SDM_AUTO_RESET_L_MASK 0x1
1917	#define AFE_DL_2ND_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 16)
1918	#define AFE_DL_AUD_SDM_OUT_L_SFT 8
1919	#define AFE_DL_AUD_SDM_OUT_L_MASK 0xff
1920	#define AFE_DL_AUD_SDM_OUT_L_MASK_SFT (0xff << 8)
1921	#define AFE_DL_AUD_SDM_OUT_R_SFT 0
1922	#define AFE_DL_AUD_SDM_OUT_R_MASK 0xff
1923	#define AFE_DL_AUD_SDM_OUT_R_MASK_SFT (0xff << 0)
1924
1925	/* AFE_ADDA_DL_SRC_LCH_MON */
1926	#define AFE_DL_ASDM_LEFT_SFT 0
1927	#define AFE_DL_ASDM_LEFT_MASK 0xffffff
1928	#define AFE_DL_ASDM_LEFT_MASK_SFT (0xffffff << 0)
1929
1930	/* AFE_ADDA_DL_SRC_RCH_MON */
1931	#define AFE_DL_ASDM_RIGHT_SFT 0
1932	#define AFE_DL_ASDM_RIGHT_MASK 0xffffff
1933	#define AFE_DL_ASDM_RIGHT_MASK_SFT (0xffffff << 0)
1934
1935	/* AFE_ADDA_DL_SRC_DEBUG */
1936	#define AFE_DL_SLT_CNT_FLAG_RESET_CTL_SFT 12
1937	#define AFE_DL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1
1938	#define AFE_DL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 12)
1939	#define AFE_DL_SLT_CNT_THD_CTL_SFT 0
1940	#define AFE_DL_SLT_CNT_THD_CTL_MASK 0xfff
1941	#define AFE_DL_SLT_CNT_THD_CTL_MASK_SFT (0xfff << 0)
1942
1943	/* AFE_ADDA_DL_SDM_DITHER_CON */
1944	#define AFE_DL_SDM_DITHER_64TAP_EN_SFT 20
1945	#define AFE_DL_SDM_DITHER_64TAP_EN_MASK 0x1
1946	#define AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT (0x1 << 20)
1947	#define AFE_DL_SDM_DITHER_EN_SFT 16
1948	#define AFE_DL_SDM_DITHER_EN_MASK 0x1
1949	#define AFE_DL_SDM_DITHER_EN_MASK_SFT (0x1 << 16)
1950	#define AFE_DL_SDM_DITHER_GAIN_SFT 0
1951	#define AFE_DL_SDM_DITHER_GAIN_MASK 0xff
1952	#define AFE_DL_SDM_DITHER_GAIN_MASK_SFT (0xff << 0)
1953
1954	/* AFE_ADDA_DL_SDM_AUTO_RESET_CON */
1955	#define AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT 31
1956	#define AFE_DL_SDM_AUTO_RESET_TEST_ON_MASK 0x1
1957	#define AFE_DL_SDM_AUTO_RESET_TEST_ON_MASK_SFT (0x1 << 31)
1958	#define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_SFT 24
1959	#define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK 0x1
1960	#define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK_SFT (0x1 << 24)
1961	#define AFE_DL_SDM_AUTO_RESET_COUNT_TH_SFT 0
1962	#define AFE_DL_SDM_AUTO_RESET_COUNT_TH_MASK 0xffffff
1963	#define AFE_DL_SDM_AUTO_RESET_COUNT_TH_MASK_SFT (0xffffff << 0)
1964
1965	/* AFE_ADDA_DL_HBF1_SCF1_CONFIG */
1966	#define AFE_DL_HBF1_SW_CONFIG_SFT 31
1967	#define AFE_DL_HBF1_SW_CONFIG_MASK 0x1
1968	#define AFE_DL_HBF1_SW_CONFIG_MASK_SFT (0x1 << 31)
1969	#define AFE_DL_HBF1_TAPNUM_CONFIG_SFT 16
1970	#define AFE_DL_HBF1_TAPNUM_CONFIG_MASK 0x7f
1971	#define AFE_DL_HBF1_TAPNUM_CONFIG_MASK_SFT (0x7f << 16)
1972	#define AFE_DL_SCF1_SW_CONFIG_SFT 8
1973	#define AFE_DL_SCF1_SW_CONFIG_MASK 0x1
1974	#define AFE_DL_SCF1_SW_CONFIG_MASK_SFT (0x1 << 8)
1975	#define AFE_DL_SCF1_TAPNUM_CONFIG_SFT 0
1976	#define AFE_DL_SCF1_TAPNUM_CONFIG_MASK 0xff
1977	#define AFE_DL_SCF1_TAPNUM_CONFIG_MASK_SFT (0xff << 0)
1978
1979	/* AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG */
1980	#define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_SFT 0
1981	#define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK 0xffffffff
1982	#define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK_SFT (0xffffffff << 0)
1983
1984	/* AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG */
1985	#define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_SFT 0
1986	#define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK 0xffffffff
1987	#define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK_SFT (0xffffffff << 0)
1988
1989	/* AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG */
1990	#define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_SFT 0
1991	#define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK 0xffffffff
1992	#define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK_SFT (0xffffffff << 0)
1993
1994	/* AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG */
1995	#define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_SFT 0
1996	#define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK 0xffffffff
1997	#define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK_SFT (0xffffffff << 0)
1998
1999	/* AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG */
2000	#define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_SFT 0
2001	#define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK 0xffffffff
2002	#define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK_SFT (0xffffffff << 0)
2003
2004	/* AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG */
2005	#define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_SFT 0
2006	#define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK 0xffffffff
2007	#define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK_SFT (0xffffffff << 0)
2008
2009	/* AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG */
2010	#define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_SFT 0
2011	#define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK 0xffffffff
2012	#define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK_SFT (0xffffffff << 0)
2013
2014	/* AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG */
2015	#define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_SFT 0
2016	#define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK 0xffffffff
2017	#define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK_SFT (0xffffffff << 0)
2018
2019	/* AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG */
2020	#define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_SFT 0
2021	#define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK 0xffffffff
2022	#define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK_SFT (0xffffffff << 0)
2023
2024	/* AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG */
2025	#define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_SFT 0
2026	#define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK 0xffffffff
2027	#define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK_SFT (0xffffffff << 0)
2028
2029	/* AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG */
2030	#define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_SFT 0
2031	#define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK 0xffffffff
2032	#define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK_SFT (0xffffffff << 0)
2033
2034	/* AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG */
2035	#define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_SFT 0
2036	#define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK 0xffffffff
2037	#define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK_SFT (0xffffffff << 0)
2038
2039	/* AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG */
2040	#define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_SFT 0
2041	#define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK 0xffffffff
2042	#define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK_SFT (0xffffffff << 0)
2043
2044	/* AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG */
2045	#define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_SFT 0
2046	#define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK 0xffffffff
2047	#define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK_SFT (0xffffffff << 0)
2048
2049	/* AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG */
2050	#define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_SFT 0
2051	#define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK 0xffffffff
2052	#define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK_SFT (0xffffffff << 0)
2053
2054	/* AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG */
2055	#define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_SFT 0
2056	#define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK 0xffffffff
2057	#define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK_SFT (0xffffffff << 0)
2058
2059	/* AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG */
2060	#define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_SFT 0
2061	#define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK 0xffffffff
2062	#define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK_SFT (0xffffffff << 0)
2063
2064	/* AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG */
2065	#define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_SFT 0
2066	#define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK 0xffffffff
2067	#define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK_SFT (0xffffffff << 0)
2068
2069	/* AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG */
2070	#define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_SFT 0
2071	#define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK 0xffffffff
2072	#define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK_SFT (0xffffffff << 0)
2073
2074	/* AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG */
2075	#define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_SFT 0
2076	#define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK 0xffffffff
2077	#define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK_SFT (0xffffffff << 0)
2078
2079	/* AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG */
2080	#define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_SFT 0
2081	#define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK 0xffffffff
2082	#define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK_SFT (0xffffffff << 0)
2083
2084	/* AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG */
2085	#define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_SFT 0
2086	#define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK 0xffffffff
2087	#define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK_SFT (0xffffffff << 0)
2088
2089	/* AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG */
2090	#define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_SFT 0
2091	#define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK 0xffffffff
2092	#define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK_SFT (0xffffffff << 0)
2093
2094	/* AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG */
2095	#define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_SFT 0
2096	#define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK 0xffffffff
2097	#define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK_SFT (0xffffffff << 0)
2098
2099	/* AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG */
2100	#define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_SFT 0
2101	#define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK 0xffffffff
2102	#define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK_SFT (0xffffffff << 0)
2103
2104	/* AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG */
2105	#define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_SFT 0
2106	#define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK 0xffffffff
2107	#define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK_SFT (0xffffffff << 0)
2108
2109	/* AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG */
2110	#define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_SFT 0
2111	#define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK 0xffffffff
2112	#define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK_SFT (0xffffffff << 0)
2113
2114	/* AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG */
2115	#define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_SFT 0
2116	#define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK 0xffffffff
2117	#define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK_SFT (0xffffffff << 0)
2118
2119	/* AFE_DL_NLE_R_CFG0 */
2120	#define RG_NLE_R_GAIN_DIG_TAR_SFT 24
2121	#define RG_NLE_R_GAIN_DIG_TAR_MASK 0x3f
2122	#define RG_NLE_R_GAIN_DIG_TAR_MASK_SFT (0x3f << 24)
2123	#define RG_NLE_R_GAIN_ANA_TAR_SFT 16
2124	#define RG_NLE_R_GAIN_ANA_TAR_MASK 0x3f
2125	#define RG_NLE_R_GAIN_ANA_TAR_MASK_SFT (0x3f << 16)
2126	#define RG_NLE_R_NO_ZCE_SFT 15
2127	#define RG_NLE_R_NO_ZCE_MASK 0x1
2128	#define RG_NLE_R_NO_ZCE_MASK_SFT (0x1 << 15)
2129	#define RG_NLE_R_HP_MODE_SFT 14
2130	#define RG_NLE_R_HP_MODE_MASK 0x1
2131	#define RG_NLE_R_HP_MODE_MASK_SFT (0x1 << 14)
2132	#define RG_NLE_R_GAIN_STEP_SFT 8
2133	#define RG_NLE_R_GAIN_STEP_MASK 0x7
2134	#define RG_NLE_R_GAIN_STEP_MASK_SFT (0x7 << 8)
2135	#define RG_NLE_R_TOGGLE_NUM_SFT 0
2136	#define RG_NLE_R_TOGGLE_NUM_MASK 0x3f
2137	#define RG_NLE_R_TOGGLE_NUM_MASK_SFT (0x3f << 0)
2138
2139	/* AFE_DL_NLE_R_CFG1 */
2140	#define RG_NLE_R_INITIATE_SFT 24
2141	#define RG_NLE_R_INITIATE_MASK 0x1
2142	#define RG_NLE_R_INITIATE_MASK_SFT (0x1 << 24)
2143	#define RG_NLE_R_READY_SFT 16
2144	#define RG_NLE_R_READY_MASK 0x1
2145	#define RG_NLE_R_READY_MASK_SFT (0x1 << 16)
2146	#define RG_NLE_R_TIMEOUT_SCALE_SFT 12
2147	#define RG_NLE_R_TIMEOUT_SCALE_MASK 0x7
2148	#define RG_NLE_R_TIMEOUT_SCALE_MASK_SFT (0x7 << 12)
2149	#define RG_NLE_R_ANC_ON_SFT 11
2150	#define RG_NLE_R_ANC_ON_MASK 0x1
2151	#define RG_NLE_R_ANC_ON_MASK_SFT (0x1 << 11)
2152	#define RG_NLE_R_GTIME_SFT 8
2153	#define RG_NLE_R_GTIME_MASK 0x7
2154	#define RG_NLE_R_GTIME_MASK_SFT (0x7 << 8)
2155	#define RG_NLE_R_ON_SFT 7
2156	#define RG_NLE_R_ON_MASK 0x1
2157	#define RG_NLE_R_ON_MASK_SFT (0x1 << 7)
2158	#define RG_PDN_NLE_CTL_SFT 6
2159	#define RG_PDN_NLE_CTL_MASK 0x1
2160	#define RG_PDN_NLE_CTL_MASK_SFT (0x1 << 6)
2161	#define RG_NLE_R_DELAY_ANA_SFT 0
2162	#define RG_NLE_R_DELAY_ANA_MASK 0x3f
2163	#define RG_NLE_R_DELAY_ANA_MASK_SFT (0x3f << 0)
2164
2165	/* AFE_DL_NLE_L_CFG0 */
2166	#define RG_NLE_L_GAIN_DIG_TAR_SFT 24
2167	#define RG_NLE_L_GAIN_DIG_TAR_MASK 0x3f
2168	#define RG_NLE_L_GAIN_DIG_TAR_MASK_SFT (0x3f << 24)
2169	#define RG_NLE_L_GAIN_ANA_TAR_SFT 16
2170	#define RG_NLE_L_GAIN_ANA_TAR_MASK 0x3f
2171	#define RG_NLE_L_GAIN_ANA_TAR_MASK_SFT (0x3f << 16)
2172	#define RG_NLE_L_NO_ZCE_SFT 15
2173	#define RG_NLE_L_NO_ZCE_MASK 0x1
2174	#define RG_NLE_L_NO_ZCE_MASK_SFT (0x1 << 15)
2175	#define RG_NLE_L_HP_MODE_SFT 14
2176	#define RG_NLE_L_HP_MODE_MASK 0x1
2177	#define RG_NLE_L_HP_MODE_MASK_SFT (0x1 << 14)
2178	#define RG_NLE_L_GAIN_STEP_SFT 8
2179	#define RG_NLE_L_GAIN_STEP_MASK 0x7
2180	#define RG_NLE_L_GAIN_STEP_MASK_SFT (0x7 << 8)
2181	#define RG_NLE_L_TOGGLE_NUM_SFT 0
2182	#define RG_NLE_L_TOGGLE_NUM_MASK 0x3f
2183	#define RG_NLE_L_TOGGLE_NUM_MASK_SFT (0x3f << 0)
2184
2185	/* AFE_DL_NLE_L_CFG1 */
2186	#define RG_NLE_L_INITIATE_SFT 24
2187	#define RG_NLE_L_INITIATE_MASK 0x1
2188	#define RG_NLE_L_INITIATE_MASK_SFT (0x1 << 24)
2189	#define RG_NLE_L_READY_SFT 16
2190	#define RG_NLE_L_READY_MASK 0x1
2191	#define RG_NLE_L_READY_MASK_SFT (0x1 << 16)
2192	#define RG_NLE_L_TIMEOUT_SCALE_SFT 12
2193	#define RG_NLE_L_TIMEOUT_SCALE_MASK 0x7
2194	#define RG_NLE_L_TIMEOUT_SCALE_MASK_SFT (0x7 << 12)
2195	#define RG_NLE_L_ANC_ON_SFT 11
2196	#define RG_NLE_L_ANC_ON_MASK 0x1
2197	#define RG_NLE_L_ANC_ON_MASK_SFT (0x1 << 11)
2198	#define RG_NLE_L_GTIME_SFT 8
2199	#define RG_NLE_L_GTIME_MASK 0x7
2200	#define RG_NLE_L_GTIME_MASK_SFT (0x7 << 8)
2201	#define RG_NLE_L_ON_SFT 7
2202	#define RG_NLE_L_ON_MASK 0x1
2203	#define RG_NLE_L_ON_MASK_SFT (0x1 << 7)
2204	#define RG_PDN_NLE_CTL_SFT 6
2205	#define RG_PDN_NLE_CTL_MASK 0x1
2206	#define RG_PDN_NLE_CTL_MASK_SFT (0x1 << 6)
2207	#define RG_NLE_L_DELAY_ANA_SFT 0
2208	#define RG_NLE_L_DELAY_ANA_MASK 0x3f
2209	#define RG_NLE_L_DELAY_ANA_MASK_SFT (0x3f << 0)
2210
2211	/* AFE_DL_NLE_R_MON0 */
2212	#define NLE_R_GAIN_DIG_CUR_SFT 24
2213	#define NLE_R_GAIN_DIG_CUR_MASK 0x3f
2214	#define NLE_R_GAIN_DIG_CUR_MASK_SFT (0x3f << 24)
2215	#define NLE_R_ANC_MASK_SFT 23
2216	#define NLE_R_ANC_MASK_MASK 0x1
2217	#define NLE_R_ANC_MASK_MASK_SFT (0x1 << 23)
2218	#define NLE_R_GAIN_ANA_CUR_SFT 16
2219	#define NLE_R_GAIN_ANA_CUR_MASK 0x3f
2220	#define NLE_R_GAIN_ANA_CUR_MASK_SFT (0x3f << 16)
2221	#define NLE_R_GAIN_DIG_TAR_CUR_SFT 8
2222	#define NLE_R_GAIN_DIG_TAR_CUR_MASK 0x3f
2223	#define NLE_R_GAIN_DIG_TAR_CUR_MASK_SFT (0x3f << 8)
2224	#define NLE_R_GAIN_ANA_TAR_CUR_SFT 0
2225	#define NLE_R_GAIN_ANA_TAR_CUR_MASK 0x3f
2226	#define NLE_R_GAIN_ANA_TAR_CUR_MASK_SFT (0x3f << 0)
2227
2228	/* AFE_DL_NLE_R_MON1 */
2229	#define NLE_R_STATE_CUR_SFT 28
2230	#define NLE_R_STATE_CUR_MASK 0x7
2231	#define NLE_R_STATE_CUR_MASK_SFT (0x7 << 28)
2232	#define NLE_R_GAIN_STEP_CUR_SFT 24
2233	#define NLE_R_GAIN_STEP_CUR_MASK 0xf
2234	#define NLE_R_GAIN_STEP_CUR_MASK_SFT (0xf << 24)
2235	#define NLE_R_TOGGLE_NUM_CUR_SFT 16
2236	#define NLE_R_TOGGLE_NUM_CUR_MASK 0x3f
2237	#define NLE_R_TOGGLE_NUM_CUR_MASK_SFT (0x3f << 16)
2238	#define NLE_R_DIG_GAIN_TARGETED_SFT 15
2239	#define NLE_R_DIG_GAIN_TARGETED_MASK 0x1
2240	#define NLE_R_DIG_GAIN_TARGETED_MASK_SFT (0x1 << 15)
2241	#define NLE_R_DIG_GAIN_INCREASE_SFT 14
2242	#define NLE_R_DIG_GAIN_INCREASE_MASK 0x1
2243	#define NLE_R_DIG_GAIN_INCREASE_MASK_SFT (0x1 << 14)
2244	#define NLE_R_DIG_GAIN_DECREASE_SFT 13
2245	#define NLE_R_DIG_GAIN_DECREASE_MASK 0x1
2246	#define NLE_R_DIG_GAIN_DECREASE_MASK_SFT (0x1 << 13)
2247	#define NLE_R_ANA_GAIN_TARGETED_SFT 12
2248	#define NLE_R_ANA_GAIN_TARGETED_MASK 0x1
2249	#define NLE_R_ANA_GAIN_TARGETED_MASK_SFT (0x1 << 12)
2250	#define NLE_R_ANA_GAIN_INCREASE_SFT 11
2251	#define NLE_R_ANA_GAIN_INCREASE_MASK 0x1
2252	#define NLE_R_ANA_GAIN_INCREASE_MASK_SFT (0x1 << 11)
2253	#define NLE_R_ANA_GAIN_DECREASE_SFT 10
2254	#define NLE_R_ANA_GAIN_DECREASE_MASK 0x1
2255	#define NLE_R_ANA_GAIN_DECREASE_MASK_SFT (0x1 << 10)
2256	#define NLE_R_TIME_COUNTER_CUR_SFT 0
2257	#define NLE_R_TIME_COUNTER_CUR_MASK 0x1ff
2258	#define NLE_R_TIME_COUNTER_CUR_MASK_SFT (0x1ff << 0)
2259
2260	/* AFE_DL_NLE_R_MON2 */
2261	#define NLE_R_ANA_GAIN_SFT 8
2262	#define NLE_R_ANA_GAIN_MASK 0x1f
2263	#define NLE_R_ANA_GAIN_MASK_SFT (0x1f << 8)
2264	#define NLE_MOSI2_ANA_GAIN_SFT 0
2265	#define NLE_MOSI2_ANA_GAIN_MASK 0x7f
2266	#define NLE_MOSI2_ANA_GAIN_MASK_SFT (0x7f << 0)
2267
2268	/* AFE_DL_NLE_L_MON0 */
2269	#define NLE_L_GAIN_DIG_CUR_SFT 24
2270	#define NLE_L_GAIN_DIG_CUR_MASK 0x3f
2271	#define NLE_L_GAIN_DIG_CUR_MASK_SFT (0x3f << 24)
2272	#define NLE_L_ANC_MASK_SFT 23
2273	#define NLE_L_ANC_MASK_MASK 0x1
2274	#define NLE_L_ANC_MASK_MASK_SFT (0x1 << 23)
2275	#define NLE_L_GAIN_ANA_CUR_SFT 16
2276	#define NLE_L_GAIN_ANA_CUR_MASK 0x3f
2277	#define NLE_L_GAIN_ANA_CUR_MASK_SFT (0x3f << 16)
2278	#define NLE_L_GAIN_DIG_TAR_CUR_SFT 8
2279	#define NLE_L_GAIN_DIG_TAR_CUR_MASK 0x3f
2280	#define NLE_L_GAIN_DIG_TAR_CUR_MASK_SFT (0x3f << 8)
2281	#define NLE_L_GAIN_ANA_TAR_CUR_SFT 0
2282	#define NLE_L_GAIN_ANA_TAR_CUR_MASK 0x3f
2283	#define NLE_L_GAIN_ANA_TAR_CUR_MASK_SFT (0x3f << 0)
2284
2285	/* AFE_DL_NLE_L_MON1 */
2286	#define NLE_L_STATE_CUR_SFT 28
2287	#define NLE_L_STATE_CUR_MASK 0x7
2288	#define NLE_L_STATE_CUR_MASK_SFT (0x7 << 28)
2289	#define NLE_L_GAIN_STEP_CUR_SFT 24
2290	#define NLE_L_GAIN_STEP_CUR_MASK 0xf
2291	#define NLE_L_GAIN_STEP_CUR_MASK_SFT (0xf << 24)
2292	#define NLE_L_TOGGLE_NUM_CUR_SFT 16
2293	#define NLE_L_TOGGLE_NUM_CUR_MASK 0x3f
2294	#define NLE_L_TOGGLE_NUM_CUR_MASK_SFT (0x3f << 16)
2295	#define NLE_L_DIG_GAIN_TARGETED_SFT 15
2296	#define NLE_L_DIG_GAIN_TARGETED_MASK 0x1
2297	#define NLE_L_DIG_GAIN_TARGETED_MASK_SFT (0x1 << 15)
2298	#define NLE_L_DIG_GAIN_INCREASE_SFT 14
2299	#define NLE_L_DIG_GAIN_INCREASE_MASK 0x1
2300	#define NLE_L_DIG_GAIN_INCREASE_MASK_SFT (0x1 << 14)
2301	#define NLE_L_DIG_GAIN_DECREASE_SFT 13
2302	#define NLE_L_DIG_GAIN_DECREASE_MASK 0x1
2303	#define NLE_L_DIG_GAIN_DECREASE_MASK_SFT (0x1 << 13)
2304	#define NLE_L_ANA_GAIN_TARGETED_SFT 12
2305	#define NLE_L_ANA_GAIN_TARGETED_MASK 0x1
2306	#define NLE_L_ANA_GAIN_TARGETED_MASK_SFT (0x1 << 12)
2307	#define NLE_L_ANA_GAIN_INCREASE_SFT 11
2308	#define NLE_L_ANA_GAIN_INCREASE_MASK 0x1
2309	#define NLE_L_ANA_GAIN_INCREASE_MASK_SFT (0x1 << 11)
2310	#define NLE_L_ANA_GAIN_DECREASE_SFT 10
2311	#define NLE_L_ANA_GAIN_DECREASE_MASK 0x1
2312	#define NLE_L_ANA_GAIN_DECREASE_MASK_SFT (0x1 << 10)
2313	#define NLE_L_TIME_COUNTER_CUR_SFT 0
2314	#define NLE_L_TIME_COUNTER_CUR_MASK 0x1ff
2315	#define NLE_L_TIME_COUNTER_CUR_MASK_SFT (0x1ff << 0)
2316
2317	/* AFE_DL_NLE_L_MON2 */
2318	#define NLE_L_ANA_GAIN_SFT 8
2319	#define NLE_L_ANA_GAIN_MASK 0x1f
2320	#define NLE_L_ANA_GAIN_MASK_SFT (0x1f << 8)
2321	#define NLE_MOSI1_ANA_GAIN_SFT 0
2322	#define NLE_MOSI1_ANA_GAIN_MASK 0x7f
2323	#define NLE_MOSI1_ANA_GAIN_MASK_SFT (0x7f << 0)
2324
2325	/* AFE_DL_NLE_GAIN_CFG0 */
2326	#define MISO2_SEL_SFT 4
2327	#define MISO2_SEL_MASK 0x3
2328	#define MISO2_SEL_MASK_SFT (0x3 << 4)
2329	#define MISO1_SEL_SFT 0
2330	#define MISO1_SEL_MASK 0x3
2331	#define MISO1_SEL_MASK_SFT (0x3 << 0)
2332
2333	/* AFE_DEM_IDWA_CON0 */
2334	#define RG_IDWA_SDM_MAV_EN_SFT 31
2335	#define RG_IDWA_SDM_MAV_EN_MASK 0x1
2336	#define RG_IDWA_SDM_MAV_EN_MASK_SFT (0x1 << 31)
2337	#define RG_IDWA_SDM_ADITHON_SFT 30
2338	#define RG_IDWA_SDM_ADITHON_MASK 0x1
2339	#define RG_IDWA_SDM_ADITHON_MASK_SFT (0x1 << 30)
2340	#define RG_IDWA_SDM_ADITHVAL_SFT 28
2341	#define RG_IDWA_SDM_ADITHVAL_MASK 0x3
2342	#define RG_IDWA_SDM_ADITHVAL_MASK_SFT (0x3 << 28)
2343	#define RG_IDWA_SDM_LOOPBACK_SFT 27
2344	#define RG_IDWA_SDM_LOOPBACK_MASK 0x1
2345	#define RG_IDWA_SDM_LOOPBACK_MASK_SFT (0x1 << 27)
2346	#define RG_IDWA_SEL_SFT 26
2347	#define RG_IDWA_SEL_MASK 0x1
2348	#define RG_IDWA_SEL_MASK_SFT (0x1 << 26)
2349	#define RG_IDWA_ON_SFT 25
2350	#define RG_IDWA_ON_MASK 0x1
2351	#define RG_IDWA_ON_MASK_SFT (0x1 << 25)
2352	#define RG_DEM_IN_LR_SWAP_SFT 24
2353	#define RG_DEM_IN_LR_SWAP_MASK 0x1
2354	#define RG_DEM_IN_LR_SWAP_MASK_SFT (0x1 << 24)
2355	#define RG_DEM_IN_L_INV_SFT 23
2356	#define RG_DEM_IN_L_INV_MASK 0x1
2357	#define RG_DEM_IN_L_INV_MASK_SFT (0x1 << 23)
2358	#define RG_DEM_IN_R_EQ_L_SFT 22
2359	#define RG_DEM_IN_R_EQ_L_MASK 0x1
2360	#define RG_DEM_IN_R_EQ_L_MASK_SFT (0x1 << 22)
2361	#define RG_DEM_IN_L_MUTE_SFT 21
2362	#define RG_DEM_IN_L_MUTE_MASK 0x1
2363	#define RG_DEM_IN_L_MUTE_MASK_SFT (0x1 << 21)
2364	#define RG_DEM_IN_R_MUTE_SFT 20
2365	#define RG_DEM_IN_R_MUTE_MASK 0x1
2366	#define RG_DEM_IN_R_MUTE_MASK_SFT (0x1 << 20)
2367	#define RG_DEM_IN_SOURCE_SFT 19
2368	#define RG_DEM_IN_SOURCE_MASK 0x1
2369	#define RG_DEM_IN_SOURCE_MASK_SFT (0x1 << 19)
2370	#define RG_DEM_SPLITTER_TRUNC_RND_SFT 18
2371	#define RG_DEM_SPLITTER_TRUNC_RND_MASK 0x1
2372	#define RG_DEM_SPLITTER_TRUNC_RND_MASK_SFT (0x1 << 18)
2373	#define RG_DEM_SCRAMBLER_CG_EN_SFT 17
2374	#define RG_DEM_SCRAMBLER_CG_EN_MASK 0x1
2375	#define RG_DEM_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 17)
2376	#define RG_DEM_SCRAMBLER_EN_SFT 16
2377	#define RG_DEM_SCRAMBLER_EN_MASK 0x1
2378	#define RG_DEM_SCRAMBLER_EN_MASK_SFT (0x1 << 16)
2379	#define RG_DEM_AUD_SDM_7BIT_SEL_SFT 15
2380	#define RG_DEM_AUD_SDM_7BIT_SEL_MASK 0x1
2381	#define RG_DEM_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 15)
2382	#define RG_DEM_ZERO_PAD_DISABLE_SFT 14
2383	#define RG_DEM_ZERO_PAD_DISABLE_MASK 0x1
2384	#define RG_DEM_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 14)
2385	#define RG_DEM_SPLITTER_TEST_EN_SFT 13
2386	#define RG_DEM_SPLITTER_TEST_EN_MASK 0x1
2387	#define RG_DEM_SPLITTER_TEST_EN_MASK_SFT (0x1 << 13)
2388	#define RG_DEM_IDAC_TEST_EN_SFT 12
2389	#define RG_DEM_IDAC_TEST_EN_MASK 0x1
2390	#define RG_DEM_IDAC_TEST_EN_MASK_SFT (0x1 << 12)
2391	#define RG_DEM_SPLIT_SCRAM_ON_SFT 11
2392	#define RG_DEM_SPLIT_SCRAM_ON_MASK 0x1
2393	#define RG_DEM_SPLIT_SCRAM_ON_MASK_SFT (0x1 << 11)
2394	#define RG_DEM_RAND_EN_SFT 10
2395	#define RG_DEM_RAND_EN_MASK 0x1
2396	#define RG_DEM_RAND_EN_MASK_SFT (0x1 << 10)
2397	#define RG_DEM_SPLITTER2_DITHER_EN_SFT 9
2398	#define RG_DEM_SPLITTER2_DITHER_EN_MASK 0x1
2399	#define RG_DEM_SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)
2400	#define RG_DEM_SPLITTER1_DITHER_EN_SFT 8
2401	#define RG_DEM_SPLITTER1_DITHER_EN_MASK 0x1
2402	#define RG_DEM_SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)
2403	#define RG_DEM_SPLITTER2_DITHER_GAIN_SFT 4
2404	#define RG_DEM_SPLITTER2_DITHER_GAIN_MASK 0xf
2405	#define RG_DEM_SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4)
2406	#define RG_DEM_SPLITTER1_DITHER_GAIN_SFT 0
2407	#define RG_DEM_SPLITTER1_DITHER_GAIN_MASK 0xf
2408	#define RG_DEM_SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0)
2409
2410	/* DEM_RECONSTRUCT_MON */
2411	#define DEM_RECONSTRUCT_L_MON_SFT 8
2412	#define DEM_RECONSTRUCT_L_MON_MASK 0xff
2413	#define DEM_RECONSTRUCT_L_MON_MASK_SFT (0xff << 8)
2414	#define DEM_RECONSTRUCT_R_MON_SFT 0
2415	#define DEM_RECONSTRUCT_R_MON_MASK 0xff
2416	#define DEM_RECONSTRUCT_R_MON_MASK_SFT (0xff << 0)
2417
2418	/* AFE_STF_CON0 */
2419	#define SLT_CNT_FLAG_RESET_SFT 28
2420	#define SLT_CNT_FLAG_RESET_MASK 0x1
2421	#define SLT_CNT_FLAG_RESET_MASK_SFT (0x1 << 28)
2422	#define SLT_CNT_THD_SFT 16
2423	#define SLT_CNT_THD_MASK 0xfff
2424	#define SLT_CNT_THD_MASK_SFT (0xfff << 16)
2425	#define SIDE_TONE_HALF_TAP_NUM_SFT 4
2426	#define SIDE_TONE_HALF_TAP_NUM_MASK 0x7f
2427	#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x7f << 4)
2428	#define SIDE_TONE_ODD_MODE_SFT 1
2429	#define SIDE_TONE_ODD_MODE_MASK 0x1
2430	#define SIDE_TONE_ODD_MODE_MASK_SFT (0x1 << 1)
2431	#define SIDE_TONE_ON_SFT 0
2432	#define SIDE_TONE_ON_MASK 0x1
2433	#define SIDE_TONE_ON_MASK_SFT (0x1 << 0)
2434
2435	/* AFE_STF_CON1 */
2436	#define SIDE_TONE_IN_EN_SEL_DOMAIN_SFT 5
2437	#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK 0x7
2438	#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK_SFT (0x7 << 5)
2439	#define SIDE_TONE_IN_EN_SEL_FS_SFT 0
2440	#define SIDE_TONE_IN_EN_SEL_FS_MASK 0x1f
2441	#define SIDE_TONE_IN_EN_SEL_FS_MASK_SFT (0x1f << 0)
2442
2443	/* AFE_STF_COEFF */
2444	#define SIDE_TONE_COEFFICIENT_R_W_SEL_SFT 24
2445	#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK 0x1
2446	#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK_SFT (0x1 << 24)
2447	#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16
2448	#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f
2449	#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)
2450	#define SIDE_TONE_COEFFICIENT_SFT 0
2451	#define SIDE_TONE_COEFFICIENT_MASK 0xffff
2452	#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)
2453
2454	/* AFE_STF_GAIN */
2455	#define SIDE_TONE_POSITIVE_GAIN_SFT 16
2456	#define SIDE_TONE_POSITIVE_GAIN_MASK 0x7
2457	#define SIDE_TONE_POSITIVE_GAIN_MASK_SFT (0x7 << 16)
2458	#define SIDE_TONE_GAIN_SFT 0
2459	#define SIDE_TONE_GAIN_MASK 0xffff
2460	#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)
2461
2462	/* AFE_STF_MON */
2463	#define SIDE_TONE_R_RDY_SFT 30
2464	#define SIDE_TONE_R_RDY_MASK 0x1
2465	#define SIDE_TONE_R_RDY_MASK_SFT (0x1 << 30)
2466	#define SIDE_TONE_W_RDY_SFT 29
2467	#define SIDE_TONE_W_RDY_MASK 0x1
2468	#define SIDE_TONE_W_RDY_MASK_SFT (0x1 << 29)
2469	#define SLT_CNT_FLAG_SFT 28
2470	#define SLT_CNT_FLAG_MASK 0x1
2471	#define SLT_CNT_FLAG_MASK_SFT (0x1 << 28)
2472	#define SLT_CNT_SFT 16
2473	#define SLT_CNT_MASK 0xfff
2474	#define SLT_CNT_MASK_SFT (0xfff << 16)
2475	#define SIDE_TONE_COEFF_SFT 0
2476	#define SIDE_TONE_COEFF_MASK 0xffff
2477	#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)
2478
2479	/* AFE_STF_IP_VERSION */
2480	#define SIDE_TONE_IP_VERSION_SFT 0
2481	#define SIDE_TONE_IP_VERSION_MASK 0xffffffff
2482	#define SIDE_TONE_IP_VERSION_MASK_SFT (0xffffffff << 0)
2483
2484	/* AFE_CM_REG */
2485	#define AFE_CM_UPDATE_CNT_SFT 16
2486	#define AFE_CM_UPDATE_CNT_MASK 0x7fff
2487	#define AFE_CM_UPDATE_CNT_MASK_SFT (0x7fff << 16)
2488	#define AFE_CM_1X_EN_SEL_FS_SFT 8
2489	#define AFE_CM_1X_EN_SEL_FS_MASK 0x1f
2490	#define AFE_CM_1X_EN_SEL_FS_MASK_SFT (0x1f << 8)
2491	#define AFE_CM_CH_NUM_SFT 2
2492	#define AFE_CM_CH_NUM_MASK 0x1f
2493	#define AFE_CM_CH_NUM_MASK_SFT (0x1f << 2)
2494	#define AFE_CM_BYTE_SWAP_SFT 1
2495	#define AFE_CM_BYTE_SWAP_MASK 0x1
2496	#define AFE_CM_BYTE_SWAP_MASK_SFT (0x1 << 1)
2497	#define AFE_CM_BYPASS_MODE_SFT 31
2498	#define AFE_CM_BYPASS_MODE_MASK 0x1
2499	#define AFE_CM_BYPASS_MODE_MASK_SFT (0x1 << 31)
2500
2501	/* AFE_CM0_CON0 */
2502	#define AFE_CM0_BYPASS_MODE_SFT 31
2503	#define AFE_CM0_BYPASS_MODE_MASK 0x1
2504	#define AFE_CM0_BYPASS_MODE_MASK_SFT (0x1 << 31)
2505	#define AFE_CM0_UPDATE_CNT_SFT 16
2506	#define AFE_CM0_UPDATE_CNT_MASK 0x7fff
2507	#define AFE_CM0_UPDATE_CNT_MASK_SFT (0x7fff << 16)
2508	#define AFE_CM0_1X_EN_SEL_DOMAIN_SFT 13
2509	#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK 0x7
2510	#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13)
2511	#define AFE_CM0_1X_EN_SEL_FS_SFT 8
2512	#define AFE_CM0_1X_EN_SEL_FS_MASK 0x1f
2513	#define AFE_CM0_1X_EN_SEL_FS_MASK_SFT (0x1f << 8)
2514	#define AFE_CM0_OUTPUT_MUX_SFT 7
2515	#define AFE_CM0_OUTPUT_MUX_MASK 0x1
2516	#define AFE_CM0_OUTPUT_MUX_MASK_SFT (0x1 << 7)
2517	#define AFE_CM0_CH_NUM_SFT 2
2518	#define AFE_CM0_CH_NUM_MASK 0x1f
2519	#define AFE_CM0_CH_NUM_MASK_SFT (0x1f << 2)
2520	#define AFE_CM0_BYTE_SWAP_SFT 1
2521	#define AFE_CM0_BYTE_SWAP_MASK 0x1
2522	#define AFE_CM0_BYTE_SWAP_MASK_SFT (0x1 << 1)
2523	#define AFE_CM0_ON_SFT 0
2524	#define AFE_CM0_ON_MASK 0x1
2525	#define AFE_CM0_ON_MASK_SFT (0x1 << 0)
2526
2527	/* AFE_CM0_MON */
2528	#define AFE_CM0_BYPASS_MODE_MON_SFT 31
2529	#define AFE_CM0_BYPASS_MODE_MON_MASK 0x1
2530	#define AFE_CM0_BYPASS_MODE_MON_MASK_SFT (0x1 << 31)
2531	#define AFE_CM0_OUTPUT_CNT_MON_SFT 16
2532	#define AFE_CM0_OUTPUT_CNT_MON_MASK 0x7fff
2533	#define AFE_CM0_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16)
2534	#define AFE_CM0_CUR_CHSET_MON_SFT 5
2535	#define AFE_CM0_CUR_CHSET_MON_MASK 0xf
2536	#define AFE_CM0_CUR_CHSET_MON_MASK_SFT (0xf << 5)
2537	#define AFE_CM0_ODD_FLAG_MON_SFT 4
2538	#define AFE_CM0_ODD_FLAG_MON_MASK 0x1
2539	#define AFE_CM0_ODD_FLAG_MON_MASK_SFT (0x1 << 4)
2540	#define AFE_CM0_BYTE_SWAP_MON_SFT 1
2541	#define AFE_CM0_BYTE_SWAP_MON_MASK 0x1
2542	#define AFE_CM0_BYTE_SWAP_MON_MASK_SFT (0x1 << 1)
2543	#define AFE_CM0_ON_MON_SFT 0
2544	#define AFE_CM0_ON_MON_MASK 0x1
2545	#define AFE_CM0_ON_MON_MASK_SFT (0x1 << 0)
2546
2547	/* AFE_CM0_IP_VERSION */
2548	#define AFE_CM0_IP_VERSION_SFT 0
2549	#define AFE_CM0_IP_VERSION_MASK 0xffffffff
2550	#define AFE_CM0_IP_VERSION_MASK_SFT (0xffffffff << 0)
2551
2552	/* AFE_CM1_CON0 */
2553	#define AFE_CM1_BYPASS_MODE_SFT 31
2554	#define AFE_CM1_BYPASS_MODE_MASK 0x1
2555	#define AFE_CM1_BYPASS_MODE_MASK_SFT (0x1 << 31)
2556	#define AFE_CM1_UPDATE_CNT_SFT 16
2557	#define AFE_CM1_UPDATE_CNT_MASK 0x7fff
2558	#define AFE_CM1_UPDATE_CNT_MASK_SFT (0x7fff << 16)
2559	#define AFE_CM1_1X_EN_SEL_DOMAIN_SFT 13
2560	#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK 0x7
2561	#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13)
2562	#define AFE_CM1_1X_EN_SEL_FS_SFT 8
2563	#define AFE_CM1_1X_EN_SEL_FS_MASK 0x1f
2564	#define AFE_CM1_1X_EN_SEL_FS_MASK_SFT (0x1f << 8)
2565	#define AFE_CM1_OUTPUT_MUX_SFT 7
2566	#define AFE_CM1_OUTPUT_MUX_MASK 0x1
2567	#define AFE_CM1_OUTPUT_MUX_MASK_SFT (0x1 << 7)
2568	#define AFE_CM1_CH_NUM_SFT 2
2569	#define AFE_CM1_CH_NUM_MASK 0x1f
2570	#define AFE_CM1_CH_NUM_MASK_SFT (0x1f << 2)
2571	#define AFE_CM1_BYTE_SWAP_SFT 1
2572	#define AFE_CM1_BYTE_SWAP_MASK 0x1
2573	#define AFE_CM1_BYTE_SWAP_MASK_SFT (0x1 << 1)
2574	#define AFE_CM1_ON_SFT 0
2575	#define AFE_CM1_ON_MASK 0x1
2576	#define AFE_CM1_ON_MASK_SFT (0x1 << 0)
2577
2578	/* AFE_CM1_MON */
2579	#define AFE_CM1_BYPASS_MODE_MON_SFT 31
2580	#define AFE_CM1_BYPASS_MODE_MON_MASK 0x1
2581	#define AFE_CM1_BYPASS_MODE_MON_MASK_SFT (0x1 << 31)
2582	#define AFE_CM1_OUTPUT_CNT_MON_SFT 16
2583	#define AFE_CM1_OUTPUT_CNT_MON_MASK 0x7fff
2584	#define AFE_CM1_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16)
2585	#define AFE_CM1_CUR_CHSET_MON_SFT 5
2586	#define AFE_CM1_CUR_CHSET_MON_MASK 0xf
2587	#define AFE_CM1_CUR_CHSET_MON_MASK_SFT (0xf << 5)
2588	#define AFE_CM1_ODD_FLAG_MON_SFT 4
2589	#define AFE_CM1_ODD_FLAG_MON_MASK 0x1
2590	#define AFE_CM1_ODD_FLAG_MON_MASK_SFT (0x1 << 4)
2591	#define AFE_CM1_BYTE_SWAP_MON_SFT 1
2592	#define AFE_CM1_BYTE_SWAP_MON_MASK 0x1
2593	#define AFE_CM1_BYTE_SWAP_MON_MASK_SFT (0x1 << 1)
2594	#define AFE_CM1_ON_MON_SFT 0
2595	#define AFE_CM1_ON_MON_MASK 0x1
2596	#define AFE_CM1_ON_MON_MASK_SFT (0x1 << 0)
2597
2598	/* AFE_CM1_IP_VERSION */
2599	#define AFE_CM1_IP_VERSION_SFT 0
2600	#define AFE_CM1_IP_VERSION_MASK 0xffffffff
2601	#define AFE_CM1_IP_VERSION_MASK_SFT (0xffffffff << 0)
2602
2603	/* AFE_ADDA_UL0_SRC_CON0 */
2604	#define ULCF_CFG_EN_CTL_SFT 31
2605	#define ULCF_CFG_EN_CTL_MASK 0x1
2606	#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
2607	#define UL_DMIC_PHASE_SEL_CH1_SFT 27
2608	#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7
2609	#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)
2610	#define UL_DMIC_PHASE_SEL_CH2_SFT 24
2611	#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7
2612	#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)
2613	#define UL_DMIC_TWO_WIRE_CTL_SFT 23
2614	#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1
2615	#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23)
2616	#define UL_MODE_3P25M_CH2_CTL_SFT 22
2617	#define UL_MODE_3P25M_CH2_CTL_MASK 0x1
2618	#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
2619	#define UL_MODE_3P25M_CH1_CTL_SFT 21
2620	#define UL_MODE_3P25M_CH1_CTL_MASK 0x1
2621	#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
2622	#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
2623	#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
2624	#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
2625	#define UL_AP_DMIC_ON_SFT 16
2626	#define UL_AP_DMIC_ON_MASK 0x1
2627	#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)
2628	#define DMIC_LOW_POWER_MODE_CTL_SFT 14
2629	#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
2630	#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
2631	#define UL_DISABLE_HW_CG_CTL_SFT 12
2632	#define UL_DISABLE_HW_CG_CTL_MASK 0x1
2633	#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
2634	#define AMIC_26M_SEL_CTL_SFT 11
2635	#define AMIC_26M_SEL_CTL_MASK 0x1
2636	#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11)
2637	#define UL_IIR_ON_TMP_CTL_SFT 10
2638	#define UL_IIR_ON_TMP_CTL_MASK 0x1
2639	#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
2640	#define UL_IIRMODE_CTL_SFT 7
2641	#define UL_IIRMODE_CTL_MASK 0x7
2642	#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
2643	#define DIGMIC_4P33M_SEL_SFT 6
2644	#define DIGMIC_4P33M_SEL_MASK 0x1
2645	#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)
2646	#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
2647	#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
2648	#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
2649	#define AMIC_6P5M_SEL_CTL_SFT 4
2650	#define AMIC_6P5M_SEL_CTL_MASK 0x1
2651	#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4)
2652	#define AMIC_1P625M_SEL_CTL_SFT 3
2653	#define AMIC_1P625M_SEL_CTL_MASK 0x1
2654	#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3)
2655	#define UL_LOOP_BACK_MODE_CTL_SFT 2
2656	#define UL_LOOP_BACK_MODE_CTL_MASK 0x1
2657	#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
2658	#define UL_SDM_3_LEVEL_CTL_SFT 1
2659	#define UL_SDM_3_LEVEL_CTL_MASK 0x1
2660	#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
2661	#define UL_SRC_ON_TMP_CTL_SFT 0
2662	#define UL_SRC_ON_TMP_CTL_MASK 0x1
2663	#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
2664
2665	/* AFE_ADDA_UL0_SRC_CON1 */
2666	#define ADDA_UL_GAIN_VALUE_SFT 16
2667	#define ADDA_UL_GAIN_VALUE_MASK 0xffff
2668	#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16)
2669	#define ADDA_UL_POSTIVEGAIN_SFT 12
2670	#define ADDA_UL_POSTIVEGAIN_MASK 0x7
2671	#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12)
2672	#define ADDA_UL_ODDTAP_MODE_SFT 11
2673	#define ADDA_UL_ODDTAP_MODE_MASK 0x1
2674	#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11)
2675	#define ADDA_UL_HALF_TAP_NUM_SFT 5
2676	#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f
2677	#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5)
2678	#define FIFO_SOFT_RST_SFT 4
2679	#define FIFO_SOFT_RST_MASK 0x1
2680	#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
2681	#define FIFO_SOFT_RST_EN_SFT 3
2682	#define FIFO_SOFT_RST_EN_MASK 0x1
2683	#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3)
2684	#define LR_SWAP_SFT 2
2685	#define LR_SWAP_MASK 0x1
2686	#define LR_SWAP_MASK_SFT (0x1 << 2)
2687	#define GAIN_MODE_SFT 0
2688	#define GAIN_MODE_MASK 0x3
2689	#define GAIN_MODE_MASK_SFT (0x3 << 0)
2690
2691	/* AFE_ADDA_UL0_SRC_CON2 */
2692	#define C_DAC_EN_CTL_SFT 27
2693	#define C_DAC_EN_CTL_MASK 0x1
2694	#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
2695	#define C_MUTE_SW_CTL_SFT 26
2696	#define C_MUTE_SW_CTL_MASK 0x1
2697	#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
2698	#define C_AMP_DIV_CH2_CTL_SFT 21
2699	#define C_AMP_DIV_CH2_CTL_MASK 0x7
2700	#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
2701	#define C_FREQ_DIV_CH2_CTL_SFT 16
2702	#define C_FREQ_DIV_CH2_CTL_MASK 0x1f
2703	#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
2704	#define C_SINE_MODE_CH2_CTL_SFT 12
2705	#define C_SINE_MODE_CH2_CTL_MASK 0xf
2706	#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
2707	#define C_AMP_DIV_CH1_CTL_SFT 9
2708	#define C_AMP_DIV_CH1_CTL_MASK 0x7
2709	#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
2710	#define C_FREQ_DIV_CH1_CTL_SFT 4
2711	#define C_FREQ_DIV_CH1_CTL_MASK 0x1f
2712	#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
2713	#define C_SINE_MODE_CH1_CTL_SFT 0
2714	#define C_SINE_MODE_CH1_CTL_MASK 0xf
2715	#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
2716
2717	/* AFE_ADDA_UL0_SRC_DEBUG */
2718	#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16
2719	#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1
2720	#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16)
2721	#define FIFO_DIGMIC_TESTIN_SFT 12
2722	#define FIFO_DIGMIC_TESTIN_MASK 0x3
2723	#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12)
2724	#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11
2725	#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
2726	#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11)
2727	#define SLT_CNT_THD_CTL_SFT 0
2728	#define SLT_CNT_THD_CTL_MASK 0x7ff
2729	#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0)
2730
2731	/* AFE_ADDA_UL0_SRC_DEBUG_MON0 */
2732	#define SLT_CNT_FLAG_CTL_SFT 16
2733	#define SLT_CNT_FLAG_CTL_MASK 0x1
2734	#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16)
2735	#define SLT_COUNTER_CTL_SFT 0
2736	#define SLT_COUNTER_CTL_MASK 0x7ff
2737	#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0)
2738
2739	/* AFE_ADDA_UL0_SRC_MON1 */
2740	#define UL_VOICE_MODE_CTL_SFT 29
2741	#define UL_VOICE_MODE_CTL_MASK 0x7
2742	#define UL_VOICE_MODE_CTL_MASK_SFT (0x7 << 29)
2743	#define DATA_COMB_IN_CH2_SFT 24
2744	#define DATA_COMB_IN_CH2_MASK 0x1f
2745	#define DATA_COMB_IN_CH2_MASK_SFT (0x1f << 24)
2746	#define DATA_COMB_OUT_CH2_SFT 0
2747	#define DATA_COMB_OUT_CH2_MASK 0xffffff
2748	#define DATA_COMB_OUT_CH2_MASK_SFT (0xffffff << 0)
2749
2750	/* AFE_ADDA_UL0_IIR_COEF_02_01 */
2751	#define ADDA_IIR_COEF_02_01_SFT 0
2752	#define ADDA_IIR_COEF_02_01_MASK 0xffffffff
2753	#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0)
2754
2755	/* AFE_ADDA_UL0_IIR_COEF_04_03 */
2756	#define ADDA_IIR_COEF_04_03_SFT 0
2757	#define ADDA_IIR_COEF_04_03_MASK 0xffffffff
2758	#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0)
2759
2760	/* AFE_ADDA_UL0_IIR_COEF_06_05 */
2761	#define ADDA_IIR_COEF_06_05_SFT 0
2762	#define ADDA_IIR_COEF_06_05_MASK 0xffffffff
2763	#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0)
2764
2765	/* AFE_ADDA_UL0_IIR_COEF_08_07 */
2766	#define ADDA_IIR_COEF_08_07_SFT 0
2767	#define ADDA_IIR_COEF_08_07_MASK 0xffffffff
2768	#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0)
2769
2770	/* AFE_ADDA_UL0_IIR_COEF_10_09 */
2771	#define ADDA_IIR_COEF_10_09_SFT 0
2772	#define ADDA_IIR_COEF_10_09_MASK 0xffffffff
2773	#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0)
2774
2775	/* AFE_ADDA_UL0_ULCF_CFG_02_01 */
2776	#define ADDA_ULCF_CFG_02_01_SFT 0
2777	#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff
2778	#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0)
2779
2780	/* AFE_ADDA_UL0_ULCF_CFG_04_03 */
2781	#define ADDA_ULCF_CFG_04_03_SFT 0
2782	#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff
2783	#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0)
2784
2785	/* AFE_ADDA_UL0_ULCF_CFG_06_05 */
2786	#define ADDA_ULCF_CFG_06_05_SFT 0
2787	#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff
2788	#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0)
2789
2790	/* AFE_ADDA_UL0_ULCF_CFG_08_07 */
2791	#define ADDA_ULCF_CFG_08_07_SFT 0
2792	#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff
2793	#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0)
2794
2795	/* AFE_ADDA_UL0_ULCF_CFG_10_09 */
2796	#define ADDA_ULCF_CFG_10_09_SFT 0
2797	#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff
2798	#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0)
2799
2800	/* AFE_ADDA_UL0_ULCF_CFG_12_11 */
2801	#define ADDA_ULCF_CFG_12_11_SFT 0
2802	#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff
2803	#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0)
2804
2805	/* AFE_ADDA_UL0_ULCF_CFG_14_13 */
2806	#define ADDA_ULCF_CFG_14_13_SFT 0
2807	#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff
2808	#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0)
2809
2810	/* AFE_ADDA_UL0_ULCF_CFG_16_15 */
2811	#define ADDA_ULCF_CFG_16_15_SFT 0
2812	#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff
2813	#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0)
2814
2815	/* AFE_ADDA_UL0_ULCF_CFG_18_17 */
2816	#define ADDA_ULCF_CFG_18_17_SFT 0
2817	#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff
2818	#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0)
2819
2820	/* AFE_ADDA_UL0_ULCF_CFG_20_19 */
2821	#define ADDA_ULCF_CFG_20_19_SFT 0
2822	#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff
2823	#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0)
2824
2825	/* AFE_ADDA_UL0_ULCF_CFG_22_21 */
2826	#define ADDA_ULCF_CFG_22_21_SFT 0
2827	#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff
2828	#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0)
2829
2830	/* AFE_ADDA_UL0_ULCF_CFG_24_23 */
2831	#define ADDA_ULCF_CFG_24_23_SFT 0
2832	#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff
2833	#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0)
2834
2835	/* AFE_ADDA_UL0_ULCF_CFG_26_25 */
2836	#define ADDA_ULCF_CFG_26_25_SFT 0
2837	#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff
2838	#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0)
2839
2840	/* AFE_ADDA_UL0_ULCF_CFG_28_27 */
2841	#define ADDA_ULCF_CFG_28_27_SFT 0
2842	#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff
2843	#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0)
2844
2845	/* AFE_ADDA_UL0_ULCF_CFG_30_29 */
2846	#define ADDA_ULCF_CFG_30_29_SFT 0
2847	#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff
2848	#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0)
2849
2850	/* AFE_ADDA_UL0_ULCF_CFG_32_31 */
2851	#define ADDA_ULCF_CFG_32_31_SFT 0
2852	#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff
2853	#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0)
2854
2855	/* AFE_ADDA_UL0_IP_VERSION */
2856	#define ADDA_ULCF_IP_VERSION_SFT 0
2857	#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff
2858	#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0)
2859
2860	/* AFE_ADDA_UL1_SRC_CON0 */
2861	#define ULCF_CFG_EN_CTL_SFT 31
2862	#define ULCF_CFG_EN_CTL_MASK 0x1
2863	#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
2864	#define UL_DMIC_PHASE_SEL_CH1_SFT 27
2865	#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7
2866	#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)
2867	#define UL_DMIC_PHASE_SEL_CH2_SFT 24
2868	#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7
2869	#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)
2870	#define UL_DMIC_TWO_WIRE_CTL_SFT 23
2871	#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1
2872	#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23)
2873	#define UL_MODE_3P25M_CH2_CTL_SFT 22
2874	#define UL_MODE_3P25M_CH2_CTL_MASK 0x1
2875	#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
2876	#define UL_MODE_3P25M_CH1_CTL_SFT 21
2877	#define UL_MODE_3P25M_CH1_CTL_MASK 0x1
2878	#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
2879	#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
2880	#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
2881	#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
2882	#define UL_AP_DMIC_ON_SFT 16
2883	#define UL_AP_DMIC_ON_MASK 0x1
2884	#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)
2885	#define DMIC_LOW_POWER_MODE_CTL_SFT 14
2886	#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
2887	#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
2888	#define UL_DISABLE_HW_CG_CTL_SFT 12
2889	#define UL_DISABLE_HW_CG_CTL_MASK 0x1
2890	#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
2891	#define AMIC_26M_SEL_CTL_SFT 11
2892	#define AMIC_26M_SEL_CTL_MASK 0x1
2893	#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11)
2894	#define UL_IIR_ON_TMP_CTL_SFT 10
2895	#define UL_IIR_ON_TMP_CTL_MASK 0x1
2896	#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
2897	#define UL_IIRMODE_CTL_SFT 7
2898	#define UL_IIRMODE_CTL_MASK 0x7
2899	#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
2900	#define DIGMIC_4P33M_SEL_SFT 6
2901	#define DIGMIC_4P33M_SEL_MASK 0x1
2902	#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)
2903	#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
2904	#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
2905	#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
2906	#define AMIC_6P5M_SEL_CTL_SFT 4
2907	#define AMIC_6P5M_SEL_CTL_MASK 0x1
2908	#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4)
2909	#define AMIC_1P625M_SEL_CTL_SFT 3
2910	#define AMIC_1P625M_SEL_CTL_MASK 0x1
2911	#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3)
2912	#define UL_LOOP_BACK_MODE_CTL_SFT 2
2913	#define UL_LOOP_BACK_MODE_CTL_MASK 0x1
2914	#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
2915	#define UL_SDM_3_LEVEL_CTL_SFT 1
2916	#define UL_SDM_3_LEVEL_CTL_MASK 0x1
2917	#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
2918	#define UL_SRC_ON_TMP_CTL_SFT 0
2919	#define UL_SRC_ON_TMP_CTL_MASK 0x1
2920	#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
2921
2922	/* AFE_ADDA_UL1_SRC_CON1 */
2923	#define ADDA_UL_GAIN_VALUE_SFT 16
2924	#define ADDA_UL_GAIN_VALUE_MASK 0xffff
2925	#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16)
2926	#define ADDA_UL_POSTIVEGAIN_SFT 12
2927	#define ADDA_UL_POSTIVEGAIN_MASK 0x7
2928	#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12)
2929	#define ADDA_UL_ODDTAP_MODE_SFT 11
2930	#define ADDA_UL_ODDTAP_MODE_MASK 0x1
2931	#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11)
2932	#define ADDA_UL_HALF_TAP_NUM_SFT 5
2933	#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f
2934	#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5)
2935	#define FIFO_SOFT_RST_SFT 4
2936	#define FIFO_SOFT_RST_MASK 0x1
2937	#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
2938	#define FIFO_SOFT_RST_EN_SFT 3
2939	#define FIFO_SOFT_RST_EN_MASK 0x1
2940	#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3)
2941	#define LR_SWAP_SFT 2
2942	#define LR_SWAP_MASK 0x1
2943	#define LR_SWAP_MASK_SFT (0x1 << 2)
2944	#define GAIN_MODE_SFT 0
2945	#define GAIN_MODE_MASK 0x3
2946	#define GAIN_MODE_MASK_SFT (0x3 << 0)
2947
2948	/* AFE_ADDA_UL1_SRC_CON2 */
2949	#define C_DAC_EN_CTL_SFT 27
2950	#define C_DAC_EN_CTL_MASK 0x1
2951	#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
2952	#define C_MUTE_SW_CTL_SFT 26
2953	#define C_MUTE_SW_CTL_MASK 0x1
2954	#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
2955	#define C_AMP_DIV_CH2_CTL_SFT 21
2956	#define C_AMP_DIV_CH2_CTL_MASK 0x7
2957	#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
2958	#define C_FREQ_DIV_CH2_CTL_SFT 16
2959	#define C_FREQ_DIV_CH2_CTL_MASK 0x1f
2960	#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
2961	#define C_SINE_MODE_CH2_CTL_SFT 12
2962	#define C_SINE_MODE_CH2_CTL_MASK 0xf
2963	#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
2964	#define C_AMP_DIV_CH1_CTL_SFT 9
2965	#define C_AMP_DIV_CH1_CTL_MASK 0x7
2966	#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
2967	#define C_FREQ_DIV_CH1_CTL_SFT 4
2968	#define C_FREQ_DIV_CH1_CTL_MASK 0x1f
2969	#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
2970	#define C_SINE_MODE_CH1_CTL_SFT 0
2971	#define C_SINE_MODE_CH1_CTL_MASK 0xf
2972	#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
2973
2974	/* AFE_ADDA_UL1_SRC_DEBUG */
2975	#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16
2976	#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1
2977	#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16)
2978	#define FIFO_DIGMIC_TESTIN_SFT 12
2979	#define FIFO_DIGMIC_TESTIN_MASK 0x3
2980	#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12)
2981	#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11
2982	#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
2983	#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11)
2984	#define SLT_CNT_THD_CTL_SFT 0
2985	#define SLT_CNT_THD_CTL_MASK 0x7ff
2986	#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0)
2987
2988	/* AFE_ADDA_UL1_SRC_DEBUG_MON0 */
2989	#define SLT_CNT_FLAG_CTL_SFT 16
2990	#define SLT_CNT_FLAG_CTL_MASK 0x1
2991	#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16)
2992	#define SLT_COUNTER_CTL_SFT 0
2993	#define SLT_COUNTER_CTL_MASK 0x7ff
2994	#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0)
2995
2996	/* AFE_ADDA_UL1_SRC_MON1 */
2997	#define UL_VOICE_MODE_CTL_SFT 29
2998	#define UL_VOICE_MODE_CTL_MASK 0x7
2999	#define UL_VOICE_MODE_CTL_MASK_SFT (0x7 << 29)
3000	#define DATA_COMB_IN_CH2_SFT 24
3001	#define DATA_COMB_IN_CH2_MASK 0x1f
3002	#define DATA_COMB_IN_CH2_MASK_SFT (0x1f << 24)
3003	#define DATA_COMB_OUT_CH2_SFT 0
3004	#define DATA_COMB_OUT_CH2_MASK 0xffffff
3005	#define DATA_COMB_OUT_CH2_MASK_SFT (0xffffff << 0)
3006
3007	/* AFE_ADDA_UL1_IIR_COEF_02_01 */
3008	#define ADDA_IIR_COEF_02_01_SFT 0
3009	#define ADDA_IIR_COEF_02_01_MASK 0xffffffff
3010	#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0)
3011
3012	/* AFE_ADDA_UL1_IIR_COEF_04_03 */
3013	#define ADDA_IIR_COEF_04_03_SFT 0
3014	#define ADDA_IIR_COEF_04_03_MASK 0xffffffff
3015	#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0)
3016
3017	/* AFE_ADDA_UL1_IIR_COEF_06_05 */
3018	#define ADDA_IIR_COEF_06_05_SFT 0
3019	#define ADDA_IIR_COEF_06_05_MASK 0xffffffff
3020	#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0)
3021
3022	/* AFE_ADDA_UL1_IIR_COEF_08_07 */
3023	#define ADDA_IIR_COEF_08_07_SFT 0
3024	#define ADDA_IIR_COEF_08_07_MASK 0xffffffff
3025	#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0)
3026
3027	/* AFE_ADDA_UL1_IIR_COEF_10_09 */
3028	#define ADDA_IIR_COEF_10_09_SFT 0
3029	#define ADDA_IIR_COEF_10_09_MASK 0xffffffff
3030	#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0)
3031
3032	/* AFE_ADDA_UL1_ULCF_CFG_02_01 */
3033	#define ADDA_ULCF_CFG_02_01_SFT 0
3034	#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff
3035	#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0)
3036
3037	/* AFE_ADDA_UL1_ULCF_CFG_04_03 */
3038	#define ADDA_ULCF_CFG_04_03_SFT 0
3039	#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff
3040	#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0)
3041
3042	/* AFE_ADDA_UL1_ULCF_CFG_06_05 */
3043	#define ADDA_ULCF_CFG_06_05_SFT 0
3044	#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff
3045	#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0)
3046
3047	/* AFE_ADDA_UL1_ULCF_CFG_08_07 */
3048	#define ADDA_ULCF_CFG_08_07_SFT 0
3049	#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff
3050	#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0)
3051
3052	/* AFE_ADDA_UL1_ULCF_CFG_10_09 */
3053	#define ADDA_ULCF_CFG_10_09_SFT 0
3054	#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff
3055	#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0)
3056
3057	/* AFE_ADDA_UL1_ULCF_CFG_12_11 */
3058	#define ADDA_ULCF_CFG_12_11_SFT 0
3059	#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff
3060	#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0)
3061
3062	/* AFE_ADDA_UL1_ULCF_CFG_14_13 */
3063	#define ADDA_ULCF_CFG_14_13_SFT 0
3064	#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff
3065	#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0)
3066
3067	/* AFE_ADDA_UL1_ULCF_CFG_16_15 */
3068	#define ADDA_ULCF_CFG_16_15_SFT 0
3069	#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff
3070	#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0)
3071
3072	/* AFE_ADDA_UL1_ULCF_CFG_18_17 */
3073	#define ADDA_ULCF_CFG_18_17_SFT 0
3074	#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff
3075	#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0)
3076
3077	/* AFE_ADDA_UL1_ULCF_CFG_20_19 */
3078	#define ADDA_ULCF_CFG_20_19_SFT 0
3079	#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff
3080	#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0)
3081
3082	/* AFE_ADDA_UL1_ULCF_CFG_22_21 */
3083	#define ADDA_ULCF_CFG_22_21_SFT 0
3084	#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff
3085	#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0)
3086
3087	/* AFE_ADDA_UL1_ULCF_CFG_24_23 */
3088	#define ADDA_ULCF_CFG_24_23_SFT 0
3089	#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff
3090	#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0)
3091
3092	/* AFE_ADDA_UL1_ULCF_CFG_26_25 */
3093	#define ADDA_ULCF_CFG_26_25_SFT 0
3094	#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff
3095	#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0)
3096
3097	/* AFE_ADDA_UL1_ULCF_CFG_28_27 */
3098	#define ADDA_ULCF_CFG_28_27_SFT 0
3099	#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff
3100	#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0)
3101
3102	/* AFE_ADDA_UL1_ULCF_CFG_30_29 */
3103	#define ADDA_ULCF_CFG_30_29_SFT 0
3104	#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff
3105	#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0)
3106
3107	/* AFE_ADDA_UL1_ULCF_CFG_32_31 */
3108	#define ADDA_ULCF_CFG_32_31_SFT 0
3109	#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff
3110	#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0)
3111
3112	/* AFE_ADDA_UL1_IP_VERSION */
3113	#define ADDA_ULCF_IP_VERSION_SFT 0
3114	#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff
3115	#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0)
3116
3117	/* AFE_ADDA_PROXIMITY_CON0 */
3118	#define PROXIMITY_CH1_ON_SFT 12
3119	#define PROXIMITY_CH1_ON_MASK 0x1
3120	#define PROXIMITY_CH1_ON_MASK_SFT (0x1 << 12)
3121	#define PROXIMITY_CH1_SEL_SFT 8
3122	#define PROXIMITY_CH1_SEL_MASK 0xf
3123	#define PROXIMITY_CH1_SEL_MASK_SFT (0xf << 8)
3124	#define PROXIMITY_CH2_ON_SFT 4
3125	#define PROXIMITY_CH2_ON_MASK 0x1
3126	#define PROXIMITY_CH2_ON_MASK_SFT (0x1 << 4)
3127	#define PROXIMITY_CH2_SEL_SFT 0
3128	#define PROXIMITY_CH2_SEL_MASK 0xf
3129	#define PROXIMITY_CH2_SEL_MASK_SFT (0xf << 0)
3130
3131	/* AFE_ADDA_ULSRC_PHASE_CON0 */
3132	#define DMIC1_PHASE_FCLK_SEL_SFT 30
3133	#define DMIC1_PHASE_FCLK_SEL_MASK 0x3
3134	#define DMIC1_PHASE_FCLK_SEL_MASK_SFT (0x3 << 30)
3135	#define DMIC0_PHASE_FCLK_SEL_SFT 28
3136	#define DMIC0_PHASE_FCLK_SEL_MASK 0x3
3137	#define DMIC0_PHASE_FCLK_SEL_MASK_SFT (0x3 << 28)
3138	#define UL3_PHASE_FCLK_SEL_SFT 26
3139	#define UL3_PHASE_FCLK_SEL_MASK 0x3
3140	#define UL3_PHASE_FCLK_SEL_MASK_SFT (0x3 << 26)
3141	#define UL2_PHASE_FCLK_SEL_SFT 24
3142	#define UL2_PHASE_FCLK_SEL_MASK 0x3
3143	#define UL2_PHASE_FCLK_SEL_MASK_SFT (0x3 << 24)
3144	#define UL1_PHASE_FCLK_SEL_SFT 22
3145	#define UL1_PHASE_FCLK_SEL_MASK 0x3
3146	#define UL1_PHASE_FCLK_SEL_MASK_SFT (0x3 << 22)
3147	#define UL0_PHASE_FCLK_SEL_SFT 20
3148	#define UL0_PHASE_FCLK_SEL_MASK 0x3
3149	#define UL0_PHASE_FCLK_SEL_MASK_SFT (0x3 << 20)
3150	#define UL_PHASE_SYNC_FCLK_2_ON_SFT 18
3151	#define UL_PHASE_SYNC_FCLK_2_ON_MASK 0x1
3152	#define UL_PHASE_SYNC_FCLK_2_ON_MASK_SFT (0x1 << 18)
3153	#define UL_PHASE_SYNC_FCLK_1_ON_SFT 17
3154	#define UL_PHASE_SYNC_FCLK_1_ON_MASK 0x1
3155	#define UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT (0x1 << 17)
3156	#define UL_PHASE_SYNC_FCLK_0_ON_SFT 16
3157	#define UL_PHASE_SYNC_FCLK_0_ON_MASK 0x1
3158	#define UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT (0x1 << 16)
3159	#define DMIC1_PHASE_HCLK_SEL_SFT 14
3160	#define DMIC1_PHASE_HCLK_SEL_MASK 0x3
3161	#define DMIC1_PHASE_HCLK_SEL_MASK_SFT (0x3 << 14)
3162	#define DMIC0_PHASE_HCLK_SEL_SFT 12
3163	#define DMIC0_PHASE_HCLK_SEL_MASK 0x3
3164	#define DMIC0_PHASE_HCLK_SEL_MASK_SFT (0x3 << 12)
3165	#define UL3_PHASE_HCLK_SEL_SFT 10
3166	#define UL3_PHASE_HCLK_SEL_MASK 0x3
3167	#define UL3_PHASE_HCLK_SEL_MASK_SFT (0x3 << 10)
3168	#define UL2_PHASE_HCLK_SEL_SFT 8
3169	#define UL2_PHASE_HCLK_SEL_MASK 0x3
3170	#define UL2_PHASE_HCLK_SEL_MASK_SFT (0x3 << 8)
3171	#define UL1_PHASE_HCLK_SEL_SFT 6
3172	#define UL1_PHASE_HCLK_SEL_MASK 0x3
3173	#define UL1_PHASE_HCLK_SEL_MASK_SFT (0x3 << 6)
3174	#define UL0_PHASE_HCLK_SEL_SFT 4
3175	#define UL0_PHASE_HCLK_SEL_MASK 0x3
3176	#define UL0_PHASE_HCLK_SEL_MASK_SFT (0x3 << 4)
3177	#define UL_PHASE_SYNC_HCLK_2_ON_SFT 2
3178	#define UL_PHASE_SYNC_HCLK_2_ON_MASK 0x1
3179	#define UL_PHASE_SYNC_HCLK_2_ON_MASK_SFT (0x1 << 2)
3180	#define UL_PHASE_SYNC_HCLK_1_ON_SFT 1
3181	#define UL_PHASE_SYNC_HCLK_1_ON_MASK 0x1
3182	#define UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT (0x1 << 1)
3183	#define UL_PHASE_SYNC_HCLK_0_ON_SFT 0
3184	#define UL_PHASE_SYNC_HCLK_0_ON_MASK 0x1
3185	#define UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT (0x1 << 0)
3186
3187	/* AFE_ADDA_ULSRC_PHASE_CON1 */
3188	#define DMIC_CLK_PHASE_SYNC_SET_SFT 31
3189	#define DMIC_CLK_PHASE_SYNC_SET_MASK 0x1
3190	#define DMIC_CLK_PHASE_SYNC_SET_MASK_SFT (0x1 << 31)
3191	#define DMIC1_PHASE_SYNC_FCLK_SET_SFT 11
3192	#define DMIC1_PHASE_SYNC_FCLK_SET_MASK 0x1
3193	#define DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 11)
3194	#define DMIC1_PHASE_SYNC_HCLK_SET_SFT 10
3195	#define DMIC1_PHASE_SYNC_HCLK_SET_MASK 0x1
3196	#define DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 10)
3197	#define DMIC0_PHASE_SYNC_FCLK_SET_SFT 9
3198	#define DMIC0_PHASE_SYNC_FCLK_SET_MASK 0x1
3199	#define DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 9)
3200	#define DMIC0_PHASE_SYNC_HCLK_SET_SFT 8
3201	#define DMIC0_PHASE_SYNC_HCLK_SET_MASK 0x1
3202	#define DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 8)
3203	#define UL3_PHASE_SYNC_FCLK_SET_SFT 7
3204	#define UL3_PHASE_SYNC_FCLK_SET_MASK 0x1
3205	#define UL3_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 7)
3206	#define UL3_PHASE_SYNC_HCLK_SET_SFT 6
3207	#define UL3_PHASE_SYNC_HCLK_SET_MASK 0x1
3208	#define UL3_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 6)
3209	#define UL2_PHASE_SYNC_FCLK_SET_SFT 5
3210	#define UL2_PHASE_SYNC_FCLK_SET_MASK 0x1
3211	#define UL2_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 5)
3212	#define UL2_PHASE_SYNC_HCLK_SET_SFT 4
3213	#define UL2_PHASE_SYNC_HCLK_SET_MASK 0x1
3214	#define UL2_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 4)
3215	#define UL1_PHASE_SYNC_FCLK_SET_SFT 3
3216	#define UL1_PHASE_SYNC_FCLK_SET_MASK 0x1
3217	#define UL1_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 3)
3218	#define UL1_PHASE_SYNC_HCLK_SET_SFT 2
3219	#define UL1_PHASE_SYNC_HCLK_SET_MASK 0x1
3220	#define UL1_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 2)
3221	#define UL0_PHASE_SYNC_FCLK_SET_SFT 1
3222	#define UL0_PHASE_SYNC_FCLK_SET_MASK 0x1
3223	#define UL0_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 1)
3224	#define UL0_PHASE_SYNC_HCLK_SET_SFT 0
3225	#define UL0_PHASE_SYNC_HCLK_SET_MASK 0x1
3226	#define UL0_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 0)
3227
3228	/* AFE_ADDA_ULSRC_PHASE_CON2 */
3229	#define DMIC1_PHASE_SYNC_1X_EN_SEL_SFT 26
3230	#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK 0x3
3231	#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 26)
3232	#define DMIC0_PHASE_SYNC_1X_EN_SEL_SFT 24
3233	#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK 0x3
3234	#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 24)
3235	#define UL3_PHASE_SYNC_1X_EN_SEL_SFT 22
3236	#define UL3_PHASE_SYNC_1X_EN_SEL_MASK 0x3
3237	#define UL3_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 22)
3238	#define UL2_PHASE_SYNC_1X_EN_SEL_SFT 20
3239	#define UL2_PHASE_SYNC_1X_EN_SEL_MASK 0x3
3240	#define UL2_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 20)
3241	#define UL1_PHASE_SYNC_1X_EN_SEL_SFT 18
3242	#define UL1_PHASE_SYNC_1X_EN_SEL_MASK 0x3
3243	#define UL1_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 18)
3244	#define UL0_PHASE_SYNC_1X_EN_SEL_SFT 16
3245	#define UL0_PHASE_SYNC_1X_EN_SEL_MASK 0x3
3246	#define UL0_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 16)
3247	#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_SFT 5
3248	#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK 0x1
3249	#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK_SFT (0x1 << 5)
3250	#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_SFT 4
3251	#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK 0x1
3252	#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK_SFT (0x1 << 4)
3253	#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_SFT 3
3254	#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK 0x1
3255	#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK_SFT (0x1 << 3)
3256	#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_SFT 2
3257	#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK 0x1
3258	#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK_SFT (0x1 << 2)
3259	#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_SFT 1
3260	#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK 0x1
3261	#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK_SFT (0x1 << 1)
3262	#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_SFT 0
3263	#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK 0x1
3264	#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK_SFT (0x1 << 0)
3265
3266	/* AFE_ADDA_ULSRC_PHASE_CON3 */
3267	#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_SFT 26
3268	#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
3269	#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 26)
3270	#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_SFT 24
3271	#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
3272	#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 24)
3273	#define UL3_PHASE_SYNC_SOFT_RST_SEL_SFT 22
3274	#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
3275	#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 22)
3276	#define UL2_PHASE_SYNC_SOFT_RST_SEL_SFT 20
3277	#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
3278	#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 20)
3279	#define UL1_PHASE_SYNC_SOFT_RST_SEL_SFT 18
3280	#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
3281	#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 18)
3282	#define UL0_PHASE_SYNC_SOFT_RST_SEL_SFT 16
3283	#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
3284	#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 16)
3285	#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_SFT 13
3286	#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
3287	#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 13)
3288	#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_SFT 12
3289	#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
3290	#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 12)
3291	#define UL3_PHASE_SYNC_CH1_FIFO_SEL_SFT 11
3292	#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
3293	#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 11)
3294	#define UL2_PHASE_SYNC_CH1_FIFO_SEL_SFT 10
3295	#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
3296	#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 10)
3297	#define UL1_PHASE_SYNC_CH1_FIFO_SEL_SFT 9
3298	#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
3299	#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 9)
3300	#define UL0_PHASE_SYNC_CH1_FIFO_SEL_SFT 8
3301	#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
3302	#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 8)
3303	#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_SFT 5
3304	#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK 0x1
3305	#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK_SFT (0x1 << 5)
3306	#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_SFT 4
3307	#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK 0x1
3308	#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK_SFT (0x1 << 4)
3309	#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_SFT 3
3310	#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK 0x1
3311	#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK_SFT (0x1 << 3)
3312	#define UL_PHASE_SYNC_SOFT_RST_2_ON_SFT 2
3313	#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK 0x1
3314	#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK_SFT (0x1 << 2)
3315	#define UL_PHASE_SYNC_SOFT_RST_1_ON_SFT 1
3316	#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK 0x1
3317	#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK_SFT (0x1 << 1)
3318	#define UL_PHASE_SYNC_SOFT_RST_0_ON_SFT 0
3319	#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK 0x1
3320	#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK_SFT (0x1 << 0)
3321
3322	/* AFE_MTKAIF_IPM_VER_MON */
3323	#define RG_MTKAIF_IPM_VER_MON_SFT 0
3324	#define RG_MTKAIF_IPM_VER_MON_MASK 0xffffffff
3325	#define RG_MTKAIF_IPM_VER_MON_MASK_SFT (0xffffffff << 0)
3326
3327	/* AFE_MTKAIF_MON_SEL */
3328	#define RG_MTKAIF_MON_SEL_SFT 0
3329	#define RG_MTKAIF_MON_SEL_MASK 0xff
3330	#define RG_MTKAIF_MON_SEL_MASK_SFT (0xff << 0)
3331
3332	/* AFE_MTKAIF_MON */
3333	#define RG_MTKAIF_MON_SFT 0
3334	#define RG_MTKAIF_MON_MASK 0xffffffff
3335	#define RG_MTKAIF_MON_MASK_SFT (0xffffffff << 0)
3336
3337	/* AFE_MTKAIF0_CFG0 */
3338	#define RG_MTKAIF0_RXIF_CLKINV_SFT 31
3339	#define RG_MTKAIF0_RXIF_CLKINV_MASK 0x1
3340	#define RG_MTKAIF0_RXIF_CLKINV_MASK_SFT (0x1 << 31)
3341	#define RG_MTKAIF0_RXIF_BYPASS_SRC_SFT 17
3342	#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK 0x1
3343	#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
3344	#define RG_MTKAIF0_RXIF_PROTOCOL2_SFT 16
3345	#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK 0x1
3346	#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
3347	#define RG_MTKAIF0_TXIF_NLE_DEBUG_SFT 8
3348	#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK 0x1
3349	#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK_SFT (0x1 << 8)
3350	#define RG_MTKAIF0_TXIF_BYPASS_SRC_SFT 5
3351	#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK 0x1
3352	#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
3353	#define RG_MTKAIF0_TXIF_PROTOCOL2_SFT 4
3354	#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK 0x1
3355	#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
3356	#define RG_MTKAIF0_TXIF_8TO5_SFT 2
3357	#define RG_MTKAIF0_TXIF_8TO5_MASK 0x1
3358	#define RG_MTKAIF0_TXIF_8TO5_MASK_SFT (0x1 << 2)
3359	#define RG_MTKAIF0_RXIF_8TO5_SFT 1
3360	#define RG_MTKAIF0_RXIF_8TO5_MASK 0x1
3361	#define RG_MTKAIF0_RXIF_8TO5_MASK_SFT (0x1 << 1)
3362	#define RG_MTKAIF0_TX2RX_LOOPBACK1_SFT 0
3363	#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK 0x1
3364	#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK_SFT (0x1 << 0)
3365
3366	/* AFE_MTKAIF0_TX_CFG0 */
3367	#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_SFT 23
3368	#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK 0x1
3369	#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK_SFT (0x1 << 23)
3370	#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_SFT 20
3371	#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK 0x7
3372	#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK_SFT (0x7 << 20)
3373	#define RG_MTKAIF0_TXIF_FIFO_SWAP_SFT 15
3374	#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK 0x1
3375	#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK_SFT (0x1 << 15)
3376	#define RG_MTKAIF0_TXIF_FIFO_RSP_SFT 12
3377	#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK 0x7
3378	#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK_SFT (0x7 << 12)
3379	#define RG_MTKAIF0_TXIF_SYNC_WORD1_SFT 4
3380	#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK 0x7
3381	#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK_SFT (0x7 << 4)
3382	#define RG_MTKAIF0_TXIF_SYNC_WORD0_SFT 0
3383	#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK 0x7
3384	#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK_SFT (0x7 << 0)
3385
3386	/* AFE_MTKAIF0_RX_CFG0 */
3387	#define RG_MTKAIF0_RXIF_VOICE_MODE_SFT 20
3388	#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK 0xf
3389	#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK_SFT (0xf << 20)
3390	#define RG_MTKAIF0_RXIF_DETECT_ON_SFT 16
3391	#define RG_MTKAIF0_RXIF_DETECT_ON_MASK 0x1
3392	#define RG_MTKAIF0_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)
3393	#define RG_MTKAIF0_RXIF_DATA_BIT_SFT 8
3394	#define RG_MTKAIF0_RXIF_DATA_BIT_MASK 0x7
3395	#define RG_MTKAIF0_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
3396	#define RG_MTKAIF0_RXIF_FIFO_RSP_SFT 4
3397	#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK 0x7
3398	#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
3399	#define RG_MTKAIF0_RXIF_DATA_MODE_SFT 0
3400	#define RG_MTKAIF0_RXIF_DATA_MODE_MASK 0x1
3401	#define RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
3402
3403	/* AFE_MTKAIF0_RX_CFG1 */
3404	#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_SFT 28
3405	#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
3406	#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 28)
3407	#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_SFT 16
3408	#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK 0xfff
3409	#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 16)
3410	#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_SFT 12
3411	#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
3412	#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
3413	#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
3414	#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
3415	#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
3416	#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_SFT 4
3417	#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK 0xf
3418	#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
3419
3420	/* AFE_MTKAIF0_RX_CFG2 */
3421	#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_SFT 27
3422	#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
3423	#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 27)
3424	#define RG_MTKAIF0_RXIF_SYNC_WORD1_SFT 24
3425	#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK 0x7
3426	#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK_SFT (0x7 << 24)
3427	#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_SFT 23
3428	#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK 0x1
3429	#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK_SFT (0x1 << 23)
3430	#define RG_MTKAIF0_RXIF_SYNC_WORD0_SFT 20
3431	#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK 0x7
3432	#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK_SFT (0x7 << 20)
3433	#define RG_MTKAIF0_RXIF_DELAY_CYCLE_SFT 12
3434	#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK 0xf
3435	#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)
3436	#define RG_MTKAIF0_RXIF_DELAY_DATA_SFT 8
3437	#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK 0x1
3438	#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
3439
3440	/* AFE_MTKAIF1_CFG0 */
3441	#define RG_MTKAIF1_RXIF_CLKINV_ADC_SFT 31
3442	#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK 0x1
3443	#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)
3444	#define RG_MTKAIF1_RXIF_BYPASS_SRC_SFT 17
3445	#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK 0x1
3446	#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
3447	#define RG_MTKAIF1_RXIF_PROTOCOL2_SFT 16
3448	#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK 0x1
3449	#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
3450	#define RG_MTKAIF1_TXIF_NLE_DEBUG_SFT 8
3451	#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK 0x1
3452	#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK_SFT (0x1 << 8)
3453	#define RG_MTKAIF1_TXIF_BYPASS_SRC_SFT 5
3454	#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK 0x1
3455	#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
3456	#define RG_MTKAIF1_TXIF_PROTOCOL2_SFT 4
3457	#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK 0x1
3458	#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
3459	#define RG_MTKAIF1_TXIF_8TO5_SFT 2
3460	#define RG_MTKAIF1_TXIF_8TO5_MASK 0x1
3461	#define RG_MTKAIF1_TXIF_8TO5_MASK_SFT (0x1 << 2)
3462	#define RG_MTKAIF1_RXIF_8TO5_SFT 1
3463	#define RG_MTKAIF1_RXIF_8TO5_MASK 0x1
3464	#define RG_MTKAIF1_RXIF_8TO5_MASK_SFT (0x1 << 1)
3465	#define RG_MTKAIF1_IF_LOOPBACK1_SFT 0
3466	#define RG_MTKAIF1_IF_LOOPBACK1_MASK 0x1
3467	#define RG_MTKAIF1_IF_LOOPBACK1_MASK_SFT (0x1 << 0)
3468
3469	/* AFE_MTKAIF1_TX_CFG0 */
3470	#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_SFT 23
3471	#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK 0x1
3472	#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK_SFT (0x1 << 23)
3473	#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_SFT 20
3474	#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK 0x7
3475	#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK_SFT (0x7 << 20)
3476	#define RG_MTKAIF1_TXIF_FIFO_SWAP_SFT 15
3477	#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK 0x1
3478	#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK_SFT (0x1 << 15)
3479	#define RG_MTKAIF1_TXIF_FIFO_RSP_SFT 12
3480	#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK 0x7
3481	#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK_SFT (0x7 << 12)
3482	#define RG_MTKAIF1_TXIF_SYNC_WORD1_SFT 4
3483	#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK 0x7
3484	#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK_SFT (0x7 << 4)
3485	#define RG_MTKAIF1_TXIF_SYNC_WORD0_SFT 0
3486	#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK 0x7
3487	#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK_SFT (0x7 << 0)
3488
3489	/* AFE_MTKAIF1_RX_CFG0 */
3490	#define RG_MTKAIF1_RXIF_VOICE_MODE_SFT 20
3491	#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK 0xf
3492	#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK_SFT (0xf << 20)
3493	#define RG_MTKAIF1_RXIF_DETECT_ON_SFT 16
3494	#define RG_MTKAIF1_RXIF_DETECT_ON_MASK 0x1
3495	#define RG_MTKAIF1_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)
3496	#define RG_MTKAIF1_RXIF_DATA_BIT_SFT 8
3497	#define RG_MTKAIF1_RXIF_DATA_BIT_MASK 0x7
3498	#define RG_MTKAIF1_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
3499	#define RG_MTKAIF1_RXIF_FIFO_RSP_SFT 4
3500	#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK 0x7
3501	#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
3502	#define RG_MTKAIF1_RXIF_DATA_MODE_SFT 0
3503	#define RG_MTKAIF1_RXIF_DATA_MODE_MASK 0x1
3504	#define RG_MTKAIF1_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
3505
3506	/* AFE_MTKAIF1_RX_CFG1 */
3507	#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_SFT 28
3508	#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
3509	#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 28)
3510	#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_SFT 16
3511	#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK 0xfff
3512	#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 16)
3513	#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_SFT 12
3514	#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
3515	#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
3516	#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
3517	#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
3518	#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
3519	#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_SFT 4
3520	#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK 0xf
3521	#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
3522
3523	/* AFE_MTKAIF1_RX_CFG2 */
3524	#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_SFT 27
3525	#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
3526	#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 27)
3527	#define RG_MTKAIF1_RXIF_SYNC_WORD1_SFT 24
3528	#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK 0x7
3529	#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK_SFT (0x7 << 24)
3530	#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_SFT 23
3531	#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK 0x1
3532	#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK_SFT (0x1 << 23)
3533	#define RG_MTKAIF1_RXIF_SYNC_WORD0_SFT 20
3534	#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK 0x7
3535	#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK_SFT (0x7 << 20)
3536	#define RG_MTKAIF1_RXIF_DELAY_CYCLE_SFT 12
3537	#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK 0xf
3538	#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)
3539	#define RG_MTKAIF1_RXIF_DELAY_DATA_SFT 8
3540	#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK 0x1
3541	#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
3542
3543	/* AFE_AUD_PAD_TOP_CFG0 */
3544	#define AUD_PAD_TOP_FIFO_RSP_SFT 4
3545	#define AUD_PAD_TOP_FIFO_RSP_MASK 0xf
3546	#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT (0xf << 4)
3547	#define RG_RX_PROTOCOL2_SFT 3
3548	#define RG_RX_PROTOCOL2_MASK 0x1
3549	#define RG_RX_PROTOCOL2_MASK_SFT (0x1 << 3)
3550	#define RG_RX_FIFO_ON_SFT 0
3551	#define RG_RX_FIFO_ON_MASK 0x1
3552	#define RG_RX_FIFO_ON_MASK_SFT (0x1 << 0)
3553
3554	/* AFE_AUD_PAD_TOP_MON */
3555	#define AUD_PAD_TOP_MON_SFT 0
3556	#define AUD_PAD_TOP_MON_MASK 0xffff
3557	#define AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
3558
3559	/* AFE_ADDA_MTKAIFV4_TX_CFG0 */
3560	#define MTKAIFV4_TXIF_EN_SEL_SFT 12
3561	#define MTKAIFV4_TXIF_EN_SEL_MASK 0x1
3562	#define MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 12)
3563	#define MTKAIFV4_TXIF_V4_SFT 11
3564	#define MTKAIFV4_TXIF_V4_MASK 0x1
3565	#define MTKAIFV4_TXIF_V4_MASK_SFT (0x1 << 11)
3566	#define MTKAIFV4_ADDA6_OUT_EN_SEL_SFT 10
3567	#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK 0x1
3568	#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT (0x1 << 10)
3569	#define MTKAIFV4_ADDA_OUT_EN_SEL_SFT 9
3570	#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK 0x1
3571	#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT (0x1 << 9)
3572	#define MTKAIFV4_TXIF_INPUT_MODE_SFT 4
3573	#define MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f
3574	#define MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
3575	#define MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1
3576	#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1
3577	#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
3578	#define MTKAIFV4_TXIF_AFE_ON_SFT 0
3579	#define MTKAIFV4_TXIF_AFE_ON_MASK 0x1
3580	#define MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0)
3581
3582	/* AFE_ADDA6_MTKAIFV4_TX_CFG0 */
3583	#define ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT 12
3584	#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK 0x1
3585	#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 12)
3586	#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT 4
3587	#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f
3588	#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
3589	#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1
3590	#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1
3591	#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
3592	#define ADDA6_MTKAIFV4_TXIF_AFE_ON_SFT 0
3593	#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK 0x1
3594	#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0)
3595
3596	/* AFE_ADDA_MTKAIFV4_RX_CFG0 */
3597	#define MTKAIFV4_RXIF_CLKINV_SFT 31
3598	#define MTKAIFV4_RXIF_CLKINV_MASK 0x1
3599	#define MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 31)
3600	#define MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 28
3601	#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1
3602	#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 28)
3603	#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_SFT 19
3604	#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK 0x1
3605	#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK_SFT (0x1 << 19)
3606	#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT 18
3607	#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK 0x1
3608	#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT (0x1 << 18)
3609	#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT 17
3610	#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK 0x1
3611	#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT (0x1 << 17)
3612	#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT 16
3613	#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK 0x1
3614	#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT (0x1 << 16)
3615	#define MTKAIFV4_RXIF_EN_SEL_SFT 12
3616	#define MTKAIFV4_RXIF_EN_SEL_MASK 0x1
3617	#define MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 12)
3618	#define MTKAIFV4_RXIF_INPUT_MODE_SFT 4
3619	#define MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f
3620	#define MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
3621	#define MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1
3622	#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1
3623	#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
3624	#define MTKAIFV4_RXIF_AFE_ON_SFT 0
3625	#define MTKAIFV4_RXIF_AFE_ON_MASK 0x1
3626	#define MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0)
3627
3628	/* AFE_ADDA_MTKAIFV4_RX_CFG1 */
3629	#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT 17
3630	#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK 0xfff
3631	#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 17)
3632	#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 12
3633	#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f
3634	#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 12)
3635	#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT 8
3636	#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK 0xf
3637	#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
3638	#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4
3639	#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf
3640	#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
3641	#define MTKAIFV4_RXIF_FIFO_RSP_SFT 1
3642	#define MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7
3643	#define MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1)
3644	#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0
3645	#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1
3646	#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0)
3647
3648	/* AFE_ADDA6_MTKAIFV4_RX_CFG0 */
3649	#define ADDA6_MTKAIFV4_RXIF_CLKINV_SFT 31
3650	#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK 0x1
3651	#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 31)
3652	#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 28
3653	#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1
3654	#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 28)
3655	#define ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT 12
3656	#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK 0x1
3657	#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 12)
3658	#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT 4
3659	#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f
3660	#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
3661	#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1
3662	#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1
3663	#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
3664	#define ADDA6_MTKAIFV4_RXIF_AFE_ON_SFT 0
3665	#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK 0x1
3666	#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0)
3667
3668	/* AFE_ADDA6_MTKAIFV4_RX_CFG1 */
3669	#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT 17
3670	#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK 0xfff
3671	#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 17)
3672	#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 12
3673	#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f
3674	#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 12)
3675	#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT 8
3676	#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK 0xf
3677	#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
3678	#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4
3679	#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf
3680	#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
3681	#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_SFT 1
3682	#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7
3683	#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1)
3684	#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0
3685	#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1
3686	#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0)
3687
3688	/* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG */
3689	#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_SFT 16
3690	#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK 0xffff
3691	#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT (0xffff << 16)
3692	#define ADDA_MTKAIFV4_TXIF_SYNCWORD_SFT 0
3693	#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK 0xffff
3694	#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT (0xffff << 0)
3695
3696	/* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG */
3697	#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_SFT 16
3698	#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK 0xffff
3699	#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT (0xffff << 16)
3700	#define ADDA_MTKAIFV4_RXIF_SYNCWORD_SFT 0
3701	#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK 0xffff
3702	#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT (0xffff << 0)
3703
3704	/* AFE_ADDA_MTKAIFV4_MON0 */
3705	#define MTKAIFV4_TXIF_SDATA_OUT_SFT 23
3706	#define MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1
3707	#define MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 23)
3708	#define MTKAIFV4_RXIF_SDATA_IN_SFT 22
3709	#define MTKAIFV4_RXIF_SDATA_IN_MASK 0x1
3710	#define MTKAIFV4_RXIF_SDATA_IN_MASK_SFT (0x1 << 22)
3711	#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 21
3712	#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
3713	#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 21)
3714	#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_SFT 0
3715	#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK 0xfff
3716	#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xfff << 0)
3717
3718	/* AFE_ADDA_MTKAIFV4_MON1 */
3719	#define MTKAIFV4_RXIF_OUT_CH4_SFT 24
3720	#define MTKAIFV4_RXIF_OUT_CH4_MASK 0xff
3721	#define MTKAIFV4_RXIF_OUT_CH4_MASK_SFT (0xff << 24)
3722	#define MTKAIFV4_RXIF_OUT_CH3_SFT 16
3723	#define MTKAIFV4_RXIF_OUT_CH3_MASK 0xff
3724	#define MTKAIFV4_RXIF_OUT_CH3_MASK_SFT (0xff << 16)
3725	#define MTKAIFV4_RXIF_OUT_CH2_SFT 8
3726	#define MTKAIFV4_RXIF_OUT_CH2_MASK 0xff
3727	#define MTKAIFV4_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
3728	#define MTKAIFV4_RXIF_OUT_CH1_SFT 0
3729	#define MTKAIFV4_RXIF_OUT_CH1_MASK 0xff
3730	#define MTKAIFV4_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
3731
3732	/* AFE_ADDA6_MTKAIFV4_MON0 */
3733	#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_SFT 23
3734	#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1
3735	#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 23)
3736	#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_SFT 22
3737	#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK 0x1
3738	#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK_SFT (0x1 << 22)
3739	#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 21
3740	#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
3741	#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 21)
3742	#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_SFT 0
3743	#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK 0xfff
3744	#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xfff << 0)
3745
3746	/* ETDM_IN0_CON0 */
3747	/* ETDM_IN1_CON0 */
3748	#define REG_ETDM_IN_EN_SFT 0
3749	#define REG_ETDM_IN_EN_MASK 0x1
3750	#define REG_ETDM_IN_EN_MASK_SFT (0x1 << 0)
3751	#define REG_SYNC_MODE_SFT 1
3752	#define REG_SYNC_MODE_MASK 0x1
3753	#define REG_SYNC_MODE_MASK_SFT (0x1 << 1)
3754	#define REG_LSB_FIRST_SFT 3
3755	#define REG_LSB_FIRST_MASK 0x1
3756	#define REG_LSB_FIRST_MASK_SFT (0x1 << 3)
3757	#define REG_SOFT_RST_SFT 4
3758	#define REG_SOFT_RST_MASK 0x1
3759	#define REG_SOFT_RST_MASK_SFT (0x1 << 4)
3760	#define REG_SLAVE_MODE_SFT 5
3761	#define REG_SLAVE_MODE_MASK 0x1
3762	#define REG_SLAVE_MODE_MASK_SFT (0x1 << 5)
3763	#define REG_FMT_SFT 6
3764	#define REG_FMT_MASK 0x7
3765	#define REG_FMT_MASK_SFT (0x7 << 6)
3766	#define REG_LRCK_EDGE_SEL_SFT 10
3767	#define REG_LRCK_EDGE_SEL_MASK 0x1
3768	#define REG_LRCK_EDGE_SEL_MASK_SFT (0x1 << 10)
3769	#define REG_BIT_LENGTH_SFT 11
3770	#define REG_BIT_LENGTH_MASK 0x1f
3771	#define REG_BIT_LENGTH_MASK_SFT (0x1f << 11)
3772	#define REG_WORD_LENGTH_SFT 16
3773	#define REG_WORD_LENGTH_MASK 0x1f
3774	#define REG_WORD_LENGTH_MASK_SFT (0x1f << 16)
3775	#define REG_CH_NUM_SFT 23
3776	#define REG_CH_NUM_MASK 0x1f
3777	#define REG_CH_NUM_MASK_SFT (0x1f << 23)
3778	#define REG_RELATCH_1X_EN_DOMAIN_SEL_SFT 28
3779	#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK 0x7
3780	#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK_SFT (0x7 << 28)
3781	#define REG_VALID_TOGETHER_SFT 31
3782	#define REG_VALID_TOGETHER_MASK 0x1
3783	#define REG_VALID_TOGETHER_MASK_SFT (0x1 << 31)
3784
3785	/* ETDM_IN0_CON1 */
3786	/* ETDM_IN1_CON1 */
3787	#define REG_INITIAL_COUNT_SFT 0
3788	#define REG_INITIAL_COUNT_MASK 0x1f
3789	#define REG_INITIAL_COUNT_MASK_SFT (0x1f << 0)
3790	#define REG_INITIAL_POINT_SFT 5
3791	#define REG_INITIAL_POINT_MASK 0x1f
3792	#define REG_INITIAL_POINT_MASK_SFT (0x1f << 5)
3793	#define REG_LRCK_AUTO_OFF_SFT 10
3794	#define REG_LRCK_AUTO_OFF_MASK 0x1
3795	#define REG_LRCK_AUTO_OFF_MASK_SFT (0x1 << 10)
3796	#define REG_BCK_AUTO_OFF_SFT 11
3797	#define REG_BCK_AUTO_OFF_MASK 0x1
3798	#define REG_BCK_AUTO_OFF_MASK_SFT (0x1 << 11)
3799	#define REG_INITIAL_LRCK_SFT 13
3800	#define REG_INITIAL_LRCK_MASK 0x1
3801	#define REG_INITIAL_LRCK_MASK_SFT (0x1 << 13)
3802	#define REG_NO_ALIGN_1X_EN_SFT 14
3803	#define REG_NO_ALIGN_1X_EN_MASK 0x1
3804	#define REG_NO_ALIGN_1X_EN_MASK_SFT (0x1 << 14)
3805	#define REG_LRCK_RESET_SFT 15
3806	#define REG_LRCK_RESET_MASK 0x1
3807	#define REG_LRCK_RESET_MASK_SFT (0x1 << 15)
3808	#define PINMUX_MCLK_CTRL_OE_SFT 16
3809	#define PINMUX_MCLK_CTRL_OE_MASK 0x1
3810	#define PINMUX_MCLK_CTRL_OE_MASK_SFT (0x1 << 16)
3811	#define REG_OUTPUT_CR_EN_SFT 18
3812	#define REG_OUTPUT_CR_EN_MASK 0x1
3813	#define REG_OUTPUT_CR_EN_MASK_SFT (0x1 << 18)
3814	#define REG_LR_ALIGN_SFT 19
3815	#define REG_LR_ALIGN_MASK 0x1
3816	#define REG_LR_ALIGN_MASK_SFT (0x1 << 19)
3817	#define REG_LRCK_WIDTH_SFT 20
3818	#define REG_LRCK_WIDTH_MASK 0x3ff
3819	#define REG_LRCK_WIDTH_MASK_SFT (0x3ff << 20)
3820	#define REG_DIRECT_INPUT_MASTER_BCK_SFT 30
3821	#define REG_DIRECT_INPUT_MASTER_BCK_MASK 0x1
3822	#define REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT (0x1 << 30)
3823	#define REG_LRCK_AUTO_MODE_SFT 31
3824	#define REG_LRCK_AUTO_MODE_MASK 0x1
3825	#define REG_LRCK_AUTO_MODE_MASK_SFT (0x1 << 31)
3826
3827	/* ETDM_IN0_CON2 */
3828	/* ETDM_IN1_CON2 */
3829	#define REG_UPDATE_POINT_SFT 0
3830	#define REG_UPDATE_POINT_MASK 0x1f
3831	#define REG_UPDATE_POINT_MASK_SFT (0x1f << 0)
3832	#define REG_UPDATE_GAP_SFT 5
3833	#define REG_UPDATE_GAP_MASK 0x1f
3834	#define REG_UPDATE_GAP_MASK_SFT (0x1f << 5)
3835	#define REG_CLOCK_SOURCE_SEL_SFT 10
3836	#define REG_CLOCK_SOURCE_SEL_MASK 0x7
3837	#define REG_CLOCK_SOURCE_SEL_MASK_SFT (0x7 << 10)
3838	#define REG_CK_EN_SEL_AUTO_SFT 14
3839	#define REG_CK_EN_SEL_AUTO_MASK 0x1
3840	#define REG_CK_EN_SEL_AUTO_MASK_SFT (0x1 << 14)
3841	#define REG_MULTI_IP_TOTAL_CHNUM_SFT 15
3842	#define REG_MULTI_IP_TOTAL_CHNUM_MASK 0x1f
3843	#define REG_MULTI_IP_TOTAL_CHNUM_MASK_SFT (0x1f << 15)
3844	#define REG_MASK_AUTO_SFT 20
3845	#define REG_MASK_AUTO_MASK 0x1
3846	#define REG_MASK_AUTO_MASK_SFT (0x1 << 20)
3847	#define REG_MASK_NUM_SFT 21
3848	#define REG_MASK_NUM_MASK 0x1f
3849	#define REG_MASK_NUM_MASK_SFT (0x1f << 21)
3850	#define REG_UPDATE_POINT_AUTO_SFT 26
3851	#define REG_UPDATE_POINT_AUTO_MASK 0x1
3852	#define REG_UPDATE_POINT_AUTO_MASK_SFT (0x1 << 26)
3853	#define REG_SDATA_DELAY_0P5T_EN_SFT 27
3854	#define REG_SDATA_DELAY_0P5T_EN_MASK 0x1
3855	#define REG_SDATA_DELAY_0P5T_EN_MASK_SFT (0x1 << 27)
3856	#define REG_SDATA_DELAY_BCK_INV_SFT 28
3857	#define REG_SDATA_DELAY_BCK_INV_MASK 0x1
3858	#define REG_SDATA_DELAY_BCK_INV_MASK_SFT (0x1 << 28)
3859	#define REG_LRCK_DELAY_0P5T_EN_SFT 29
3860	#define REG_LRCK_DELAY_0P5T_EN_MASK 0x1
3861	#define REG_LRCK_DELAY_0P5T_EN_MASK_SFT (0x1 << 29)
3862	#define REG_LRCK_DELAY_BCK_INV_SFT 30
3863	#define REG_LRCK_DELAY_BCK_INV_MASK 0x1
3864	#define REG_LRCK_DELAY_BCK_INV_MASK_SFT (0x1 << 30)
3865	#define REG_MULTI_IP_MODE_SFT 31
3866	#define REG_MULTI_IP_MODE_MASK 0x1
3867	#define REG_MULTI_IP_MODE_MASK_SFT (0x1 << 31)
3868
3869	/* ETDM_IN0_CON3 */
3870	/* ETDM_IN1_CON3 */
3871	#define REG_DISABLE_OUT_SFT 0
3872	#define REG_DISABLE_OUT_MASK 0xffff
3873	#define REG_DISABLE_OUT_MASK_SFT (0xffff << 0)
3874	#define REG_RJ_DATA_RIGHT_ALIGN_SFT 16
3875	#define REG_RJ_DATA_RIGHT_ALIGN_MASK 0x1
3876	#define REG_RJ_DATA_RIGHT_ALIGN_MASK_SFT (0x1 << 16)
3877	#define REG_MONITOR_SEL_SFT 17
3878	#define REG_MONITOR_SEL_MASK 0x3
3879	#define REG_MONITOR_SEL_MASK_SFT (0x3 << 17)
3880	#define REG_CNT_UPPER_LIMIT_SFT 19
3881	#define REG_CNT_UPPER_LIMIT_MASK 0x3f
3882	#define REG_CNT_UPPER_LIMIT_MASK_SFT (0x3f << 19)
3883	#define REG_COMPACT_SAMPLE_END_DIS_SFT 25
3884	#define REG_COMPACT_SAMPLE_END_DIS_MASK 0x1
3885	#define REG_COMPACT_SAMPLE_END_DIS_MASK_SFT (0x1 << 25)
3886	#define REG_FS_TIMING_SEL_SFT 26
3887	#define REG_FS_TIMING_SEL_MASK 0x1f
3888	#define REG_FS_TIMING_SEL_MASK_SFT (0x1f << 26)
3889	#define REG_SAMPLE_END_MODE_SFT 31
3890	#define REG_SAMPLE_END_MODE_MASK 0x1
3891	#define REG_SAMPLE_END_MODE_MASK_SFT (0x1 << 31)
3892
3893	/* ETDM_IN0_CON4 */
3894	/* ETDM_IN1_CON4 */
3895	#define REG_ALWAYS_OPEN_1X_EN_SFT 31
3896	#define REG_ALWAYS_OPEN_1X_EN_MASK 0x1
3897	#define REG_ALWAYS_OPEN_1X_EN_MASK_SFT (0x1 << 31)
3898	#define REG_WAIT_LAST_SAMPLE_SFT 30
3899	#define REG_WAIT_LAST_SAMPLE_MASK 0x1
3900	#define REG_WAIT_LAST_SAMPLE_MASK_SFT (0x1 << 30)
3901	#define REG_SAMPLE_END_POINT_SFT 25
3902	#define REG_SAMPLE_END_POINT_MASK 0x1f
3903	#define REG_SAMPLE_END_POINT_MASK_SFT (0x1f << 25)
3904	#define REG_RELATCH_1X_EN_SEL_SFT 20
3905	#define REG_RELATCH_1X_EN_SEL_MASK 0x1f
3906	#define REG_RELATCH_1X_EN_SEL_MASK_SFT (0x1f << 20)
3907	#define REG_MASTER_WS_INV_SFT 19
3908	#define REG_MASTER_WS_INV_MASK 0x1
3909	#define REG_MASTER_WS_INV_MASK_SFT (0x1 << 19)
3910	#define REG_MASTER_BCK_INV_SFT 18
3911	#define REG_MASTER_BCK_INV_MASK 0x1
3912	#define REG_MASTER_BCK_INV_MASK_SFT (0x1 << 18)
3913	#define REG_SLAVE_LRCK_INV_SFT 17
3914	#define REG_SLAVE_LRCK_INV_MASK 0x1
3915	#define REG_SLAVE_LRCK_INV_MASK_SFT (0x1 << 17)
3916	#define REG_SLAVE_BCK_INV_SFT 16
3917	#define REG_SLAVE_BCK_INV_MASK 0x1
3918	#define REG_SLAVE_BCK_INV_MASK_SFT (0x1 << 16)
3919	#define REG_REPACK_CHNUM_SFT 12
3920	#define REG_REPACK_CHNUM_MASK 0xf
3921	#define REG_REPACK_CHNUM_MASK_SFT (0xf << 12)
3922	#define REG_ASYNC_RESET_SFT 11
3923	#define REG_ASYNC_RESET_MASK 0x1
3924	#define REG_ASYNC_RESET_MASK_SFT (0x1 << 11)
3925	#define REG_REPACK_WORD_LENGTH_SFT 9
3926	#define REG_REPACK_WORD_LENGTH_MASK 0x3
3927	#define REG_REPACK_WORD_LENGTH_MASK_SFT (0x3 << 9)
3928	#define REG_REPACK_AUTO_MODE_SFT 8
3929	#define REG_REPACK_AUTO_MODE_MASK 0x1
3930	#define REG_REPACK_AUTO_MODE_MASK_SFT (0x1 << 8)
3931	#define REG_REPACK_MODE_SFT 0
3932	#define REG_REPACK_MODE_MASK 0x3f
3933	#define REG_REPACK_MODE_MASK_SFT (0x3f << 0)
3934
3935	/* ETDM_IN0_CON5 */
3936	/* ETDM_IN1_CON5 */
3937	#define REG_LR_SWAP_SFT 16
3938	#define REG_LR_SWAP_MASK 0xffff
3939	#define REG_LR_SWAP_MASK_SFT (0xffff << 16)
3940	#define REG_ODD_FLAG_EN_SFT 0
3941	#define REG_ODD_FLAG_EN_MASK 0xffff
3942	#define REG_ODD_FLAG_EN_MASK_SFT (0xffff << 0)
3943
3944	/* ETDM_IN0_CON6 */
3945	/* ETDM_IN1_CON6 */
3946	#define LCH_DATA_REG_SFT 0
3947	#define LCH_DATA_REG_MASK 0xffffffff
3948	#define LCH_DATA_REG_MASK_SFT (0xffffffff << 0)
3949
3950	/* ETDM_IN0_CON7 */
3951	/* ETDM_IN1_CON7 */
3952	#define RCH_DATA_REG_SFT 0
3953	#define RCH_DATA_REG_MASK 0xffffffff
3954	#define RCH_DATA_REG_MASK_SFT (0xffffffff << 0)
3955
3956	/* ETDM_IN0_CON8 */
3957	/* ETDM_IN1_CON8 */
3958	#define REG_AFIFO_THRESHOLD_SFT 29
3959	#define REG_AFIFO_THRESHOLD_MASK 0x3
3960	#define REG_AFIFO_THRESHOLD_MASK_SFT (0x3 << 29)
3961	#define REG_CK_EN_SEL_MANUAL_SFT 16
3962	#define REG_CK_EN_SEL_MANUAL_MASK 0x3ff
3963	#define REG_CK_EN_SEL_MANUAL_MASK_SFT (0x3ff << 16)
3964	#define REG_AFIFO_SW_RESET_SFT 15
3965	#define REG_AFIFO_SW_RESET_MASK 0x1
3966	#define REG_AFIFO_SW_RESET_MASK_SFT (0x1 << 15)
3967	#define REG_AFIFO_RESET_SEL_SFT 14
3968	#define REG_AFIFO_RESET_SEL_MASK 0x1
3969	#define REG_AFIFO_RESET_SEL_MASK_SFT (0x1 << 14)
3970	#define REG_AFIFO_AUTO_RESET_DIS_SFT 9
3971	#define REG_AFIFO_AUTO_RESET_DIS_MASK 0x1
3972	#define REG_AFIFO_AUTO_RESET_DIS_MASK_SFT (0x1 << 9)
3973	#define REG_ETDM_USE_AFIFO_SFT 8
3974	#define REG_ETDM_USE_AFIFO_MASK 0x1
3975	#define REG_ETDM_USE_AFIFO_MASK_SFT (0x1 << 8)
3976	#define REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 5
3977	#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK 0x7
3978	#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT (0x7 << 5)
3979	#define REG_AFIFO_MODE_SFT 0
3980	#define REG_AFIFO_MODE_MASK 0x1f
3981	#define REG_AFIFO_MODE_MASK_SFT (0x1f << 0)
3982
3983	/* ETDM_IN0_CON9 */
3984	/* ETDM_IN1_CON9 */
3985	#define REG_OUT2LATCH_TIME_SFT 10
3986	#define REG_OUT2LATCH_TIME_MASK 0x1f
3987	#define REG_OUT2LATCH_TIME_MASK_SFT (0x1f << 10)
3988	#define REG_ALMOST_END_BIT_COUNT_SFT 5
3989	#define REG_ALMOST_END_BIT_COUNT_MASK 0x1f
3990	#define REG_ALMOST_END_BIT_COUNT_MASK_SFT (0x1f << 5)
3991	#define REG_ALMOST_END_CH_COUNT_SFT 0
3992	#define REG_ALMOST_END_CH_COUNT_MASK 0x1f
3993	#define REG_ALMOST_END_CH_COUNT_MASK_SFT (0x1f << 0)
3994
3995	/* ETDM_IN0_MON */
3996	/* ETDM_IN1_MON */
3997	#define LRCK_INV_SFT 30
3998	#define LRCK_INV_MASK 0x1
3999	#define LRCK_INV_MASK_SFT (0x1 << 30)
4000	#define EN_SYNC_OUT_SFT 29
4001	#define EN_SYNC_OUT_MASK 0x1
4002	#define EN_SYNC_OUT_MASK_SFT (0x1 << 29)
4003	#define HOPPING_EN_SYNC_OUT_PRE_SFT 28
4004	#define HOPPING_EN_SYNC_OUT_PRE_MASK 0x1
4005	#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT (0x1 << 28)
4006	#define WFULL_SFT 27
4007	#define WFULL_MASK 0x1
4008	#define WFULL_MASK_SFT (0x1 << 27)
4009	#define REMPTY_SFT 26
4010	#define REMPTY_MASK 0x1
4011	#define REMPTY_MASK_SFT (0x1 << 26)
4012	#define ETDM_2X_CK_EN_SFT 25
4013	#define ETDM_2X_CK_EN_MASK 0x1
4014	#define ETDM_2X_CK_EN_MASK_SFT (0x1 << 25)
4015	#define ETDM_1X_CK_EN_SFT 24
4016	#define ETDM_1X_CK_EN_MASK 0x1
4017	#define ETDM_1X_CK_EN_MASK_SFT (0x1 << 24)
4018	#define SDATA0_SFT 23
4019	#define SDATA0_MASK 0x1
4020	#define SDATA0_MASK_SFT (0x1 << 23)
4021	#define CURRENT_STATUS_SFT 21
4022	#define CURRENT_STATUS_MASK 0x3
4023	#define CURRENT_STATUS_MASK_SFT (0x3 << 21)
4024	#define BIT_POINT_SFT 16
4025	#define BIT_POINT_MASK 0x1f
4026	#define BIT_POINT_MASK_SFT (0x1f << 16)
4027	#define BIT_CH_COUNT_SFT 10
4028	#define BIT_CH_COUNT_MASK 0x3f
4029	#define BIT_CH_COUNT_MASK_SFT (0x3f << 10)
4030	#define BIT_COUNT_SFT 5
4031	#define BIT_COUNT_MASK 0x1f
4032	#define BIT_COUNT_MASK_SFT (0x1f << 5)
4033	#define CH_COUNT_SFT 0
4034	#define CH_COUNT_MASK 0x1f
4035	#define CH_COUNT_MASK_SFT (0x1f << 0)
4036
4037	/* ETDM_OUT0_CON0 */
4038	/* ETDM_OUT1_CON0 */
4039	/* ETDM_OUT4_CON0 */
4040	#define OUT_REG_ETDM_OUT_EN_SFT 0
4041	#define OUT_REG_ETDM_OUT_EN_MASK 0x1
4042	#define OUT_REG_ETDM_OUT_EN_MASK_SFT (0x1 << 0)
4043	#define OUT_REG_SYNC_MODE_SFT 1
4044	#define OUT_REG_SYNC_MODE_MASK 0x1
4045	#define OUT_REG_SYNC_MODE_MASK_SFT (0x1 << 1)
4046	#define OUT_REG_LSB_FIRST_SFT 3
4047	#define OUT_REG_LSB_FIRST_MASK 0x1
4048	#define OUT_REG_LSB_FIRST_MASK_SFT (0x1 << 3)
4049	#define OUT_REG_SOFT_RST_SFT 4
4050	#define OUT_REG_SOFT_RST_MASK 0x1
4051	#define OUT_REG_SOFT_RST_MASK_SFT (0x1 << 4)
4052	#define OUT_REG_SLAVE_MODE_SFT 5
4053	#define OUT_REG_SLAVE_MODE_MASK 0x1
4054	#define OUT_REG_SLAVE_MODE_MASK_SFT (0x1 << 5)
4055	#define OUT_REG_FMT_SFT 6
4056	#define OUT_REG_FMT_MASK 0x7
4057	#define OUT_REG_FMT_MASK_SFT (0x7 << 6)
4058	#define OUT_REG_LRCK_EDGE_SEL_SFT 10
4059	#define OUT_REG_LRCK_EDGE_SEL_MASK 0x1
4060	#define OUT_REG_LRCK_EDGE_SEL_MASK_SFT (0x1 << 10)
4061	#define OUT_REG_BIT_LENGTH_SFT 11
4062	#define OUT_REG_BIT_LENGTH_MASK 0x1f
4063	#define OUT_REG_BIT_LENGTH_MASK_SFT (0x1f << 11)
4064	#define OUT_REG_WORD_LENGTH_SFT 16
4065	#define OUT_REG_WORD_LENGTH_MASK 0x1f
4066	#define OUT_REG_WORD_LENGTH_MASK_SFT (0x1f << 16)
4067	#define OUT_REG_CH_NUM_SFT 23
4068	#define OUT_REG_CH_NUM_MASK 0x1f
4069	#define OUT_REG_CH_NUM_MASK_SFT (0x1f << 23)
4070	#define OUT_REG_RELATCH_DOMAIN_SEL_SFT 28
4071	#define OUT_REG_RELATCH_DOMAIN_SEL_MASK 0x7
4072	#define OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT (0x7 << 28)
4073	#define OUT_REG_VALID_TOGETHER_SFT 31
4074	#define OUT_REG_VALID_TOGETHER_MASK 0x1
4075	#define OUT_REG_VALID_TOGETHER_MASK_SFT (0x1 << 31)
4076
4077	/* ETDM_OUT0_CON1 */
4078	/* ETDM_OUT1_CON1 */
4079	/* ETDM_OUT4_CON1 */
4080	#define OUT_REG_INITIAL_COUNT_SFT 0
4081	#define OUT_REG_INITIAL_COUNT_MASK 0x1f
4082	#define OUT_REG_INITIAL_COUNT_MASK_SFT (0x1f << 0)
4083	#define OUT_REG_INITIAL_POINT_SFT 5
4084	#define OUT_REG_INITIAL_POINT_MASK 0x1f
4085	#define OUT_REG_INITIAL_POINT_MASK_SFT (0x1f << 5)
4086	#define OUT_REG_LRCK_AUTO_OFF_SFT 10
4087	#define OUT_REG_LRCK_AUTO_OFF_MASK 0x1
4088	#define OUT_REG_LRCK_AUTO_OFF_MASK_SFT (0x1 << 10)
4089	#define OUT_REG_BCK_AUTO_OFF_SFT 11
4090	#define OUT_REG_BCK_AUTO_OFF_MASK 0x1
4091	#define OUT_REG_BCK_AUTO_OFF_MASK_SFT (0x1 << 11)
4092	#define OUT_REG_INITIAL_LRCK_SFT 13
4093	#define OUT_REG_INITIAL_LRCK_MASK 0x1
4094	#define OUT_REG_INITIAL_LRCK_MASK_SFT (0x1 << 13)
4095	#define OUT_REG_NO_ALIGN_1X_EN_SFT 14
4096	#define OUT_REG_NO_ALIGN_1X_EN_MASK 0x1
4097	#define OUT_REG_NO_ALIGN_1X_EN_MASK_SFT (0x1 << 14)
4098	#define OUT_REG_LRCK_RESET_SFT 15
4099	#define OUT_REG_LRCK_RESET_MASK 0x1
4100	#define OUT_REG_LRCK_RESET_MASK_SFT (0x1 << 15)
4101	#define OUT_PINMUX_MCLK_CTRL_OE_SFT 16
4102	#define OUT_PINMUX_MCLK_CTRL_OE_MASK 0x1
4103	#define OUT_PINMUX_MCLK_CTRL_OE_MASK_SFT (0x1 << 16)
4104	#define OUT_REG_OUTPUT_CR_EN_SFT 18
4105	#define OUT_REG_OUTPUT_CR_EN_MASK 0x1
4106	#define OUT_REG_OUTPUT_CR_EN_MASK_SFT (0x1 << 18)
4107	#define OUT_REG_LRCK_WIDTH_SFT 19
4108	#define OUT_REG_LRCK_WIDTH_MASK 0x3ff
4109	#define OUT_REG_LRCK_WIDTH_MASK_SFT (0x3ff << 19)
4110	#define OUT_REG_LRCK_AUTO_MODE_SFT 29
4111	#define OUT_REG_LRCK_AUTO_MODE_MASK 0x1
4112	#define OUT_REG_LRCK_AUTO_MODE_MASK_SFT (0x1 << 29)
4113	#define OUT_REG_DIRECT_INPUT_MASTER_BCK_SFT 30
4114	#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK 0x1
4115	#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT (0x1 << 30)
4116	#define OUT_REG_16B_COMPACT_MODE_SFT 31
4117	#define OUT_REG_16B_COMPACT_MODE_MASK 0x1
4118	#define OUT_REG_16B_COMPACT_MODE_MASK_SFT (0x1 << 31)
4119
4120	/* ETDM_OUT0_CON2 */
4121	/* ETDM_OUT1_CON2 */
4122	/* ETDM_OUT4_CON2 */
4123	#define OUT_REG_IN2LATCH_TIME_SFT 0
4124	#define OUT_REG_IN2LATCH_TIME_MASK 0x1f
4125	#define OUT_REG_IN2LATCH_TIME_MASK_SFT (0x1f << 0)
4126	#define OUT_REG_MASK_NUM_SFT 5
4127	#define OUT_REG_MASK_NUM_MASK 0x1f
4128	#define OUT_REG_MASK_NUM_MASK_SFT (0x1f << 5)
4129	#define OUT_REG_MASK_AUTO_SFT 10
4130	#define OUT_REG_MASK_AUTO_MASK 0x1
4131	#define OUT_REG_MASK_AUTO_MASK_SFT (0x1 << 10)
4132	#define OUT_REG_SDATA_SHIFT_SFT 11
4133	#define OUT_REG_SDATA_SHIFT_MASK 0x3
4134	#define OUT_REG_SDATA_SHIFT_MASK_SFT (0x3 << 11)
4135	#define OUT_REG_ALMOST_END_BIT_COUNT_SFT 13
4136	#define OUT_REG_ALMOST_END_BIT_COUNT_MASK 0x1f
4137	#define OUT_REG_ALMOST_END_BIT_COUNT_MASK_SFT (0x1f << 13)
4138	#define OUT_REG_SDATA_CON_SFT 18
4139	#define OUT_REG_SDATA_CON_MASK 0x3
4140	#define OUT_REG_SDATA_CON_MASK_SFT (0x3 << 18)
4141	#define OUT_REG_REDUNDANT_0_SFT 20
4142	#define OUT_REG_REDUNDANT_0_MASK 0x1
4143	#define OUT_REG_REDUNDANT_0_MASK_SFT (0x1 << 20)
4144	#define OUT_REG_SDATA_AUTO_OFF_SFT 21
4145	#define OUT_REG_SDATA_AUTO_OFF_MASK 0x1
4146	#define OUT_REG_SDATA_AUTO_OFF_MASK_SFT (0x1 << 21)
4147	#define OUT_REG_BCK_OFF_TIME_SFT 22
4148	#define OUT_REG_BCK_OFF_TIME_MASK 0x3
4149	#define OUT_REG_BCK_OFF_TIME_MASK_SFT (0x3 << 22)
4150	#define OUT_REG_MONITOR_SEL_SFT 24
4151	#define OUT_REG_MONITOR_SEL_MASK 0x3
4152	#define OUT_REG_MONITOR_SEL_MASK_SFT (0x3 << 24)
4153	#define OUT_REG_SHIFT_AUTO_SFT 26
4154	#define OUT_REG_SHIFT_AUTO_MASK 0x1
4155	#define OUT_REG_SHIFT_AUTO_MASK_SFT (0x1 << 26)
4156	#define OUT_REG_SDATA_DELAY_0P5T_EN_SFT 27
4157	#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK 0x1
4158	#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK_SFT (0x1 << 27)
4159	#define OUT_REG_SDATA_DELAY_BCK_INV_SFT 28
4160	#define OUT_REG_SDATA_DELAY_BCK_INV_MASK 0x1
4161	#define OUT_REG_SDATA_DELAY_BCK_INV_MASK_SFT (0x1 << 28)
4162	#define OUT_REG_LRCK_DELAY_0P5T_EN_SFT 29
4163	#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK 0x1
4164	#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK_SFT (0x1 << 29)
4165	#define OUT_REG_LRCK_DELAY_BCK_INV_SFT 30
4166	#define OUT_REG_LRCK_DELAY_BCK_INV_MASK 0x1
4167	#define OUT_REG_LRCK_DELAY_BCK_INV_MASK_SFT (0x1 << 30)
4168	#define OUT_REG_OFF_CR_EN_SFT 31
4169	#define OUT_REG_OFF_CR_EN_MASK 0x1
4170	#define OUT_REG_OFF_CR_EN_MASK_SFT (0x1 << 31)
4171
4172	/* ETDM_OUT0_CON3 */
4173	/* ETDM_OUT1_CON3 */
4174	/* ETDM_OUT4_CON3 */
4175	#define OUT_REG_START_CH_PAIR0_SFT 0
4176	#define OUT_REG_START_CH_PAIR0_MASK 0xf
4177	#define OUT_REG_START_CH_PAIR0_MASK_SFT (0xf << 0)
4178	#define OUT_REG_START_CH_PAIR1_SFT 4
4179	#define OUT_REG_START_CH_PAIR1_MASK 0xf
4180	#define OUT_REG_START_CH_PAIR1_MASK_SFT (0xf << 4)
4181	#define OUT_REG_START_CH_PAIR2_SFT 8
4182	#define OUT_REG_START_CH_PAIR2_MASK 0xf
4183	#define OUT_REG_START_CH_PAIR2_MASK_SFT (0xf << 8)
4184	#define OUT_REG_START_CH_PAIR3_SFT 12
4185	#define OUT_REG_START_CH_PAIR3_MASK 0xf
4186	#define OUT_REG_START_CH_PAIR3_MASK_SFT (0xf << 12)
4187	#define OUT_REG_START_CH_PAIR4_SFT 16
4188	#define OUT_REG_START_CH_PAIR4_MASK 0xf
4189	#define OUT_REG_START_CH_PAIR4_MASK_SFT (0xf << 16)
4190	#define OUT_REG_START_CH_PAIR5_SFT 20
4191	#define OUT_REG_START_CH_PAIR5_MASK 0xf
4192	#define OUT_REG_START_CH_PAIR5_MASK_SFT (0xf << 20)
4193	#define OUT_REG_START_CH_PAIR6_SFT 24
4194	#define OUT_REG_START_CH_PAIR6_MASK 0xf
4195	#define OUT_REG_START_CH_PAIR6_MASK_SFT (0xf << 24)
4196	#define OUT_REG_START_CH_PAIR7_SFT 28
4197	#define OUT_REG_START_CH_PAIR7_MASK 0xf
4198	#define OUT_REG_START_CH_PAIR7_MASK_SFT (0xf << 28)
4199
4200	/* ETDM_OUT0_CON4 */
4201	/* ETDM_OUT1_CON4 */
4202	/* ETDM_OUT4_CON4 */
4203	#define OUT_REG_FS_TIMING_SEL_SFT 0
4204	#define OUT_REG_FS_TIMING_SEL_MASK 0x1f
4205	#define OUT_REG_FS_TIMING_SEL_MASK_SFT (0x1f << 0)
4206	#define OUT_REG_CLOCK_SOURCE_SEL_SFT 6
4207	#define OUT_REG_CLOCK_SOURCE_SEL_MASK 0x7
4208	#define OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT (0x7 << 6)
4209	#define OUT_REG_CK_EN_SEL_AUTO_SFT 10
4210	#define OUT_REG_CK_EN_SEL_AUTO_MASK 0x1
4211	#define OUT_REG_CK_EN_SEL_AUTO_MASK_SFT (0x1 << 10)
4212	#define OUT_REG_ASYNC_RESET_SFT 11
4213	#define OUT_REG_ASYNC_RESET_MASK 0x1
4214	#define OUT_REG_ASYNC_RESET_MASK_SFT (0x1 << 11)
4215	#define OUT_REG_CK_EN_SEL_MANUAL_SFT 14
4216	#define OUT_REG_CK_EN_SEL_MANUAL_MASK 0x3ff
4217	#define OUT_REG_CK_EN_SEL_MANUAL_MASK_SFT (0x3ff << 14)
4218	#define OUT_REG_RELATCH_EN_SEL_SFT 24
4219	#define OUT_REG_RELATCH_EN_SEL_MASK 0x1f
4220	#define OUT_REG_RELATCH_EN_SEL_MASK_SFT (0x1f << 24)
4221	#define OUT_REG_WAIT_LAST_SAMPLE_SFT 30
4222	#define OUT_REG_WAIT_LAST_SAMPLE_MASK 0x1
4223	#define OUT_REG_WAIT_LAST_SAMPLE_MASK_SFT (0x1 << 30)
4224	#define OUT_REG_ALWAYS_OPEN_1X_EN_SFT 31
4225	#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK 0x1
4226	#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK_SFT (0x1 << 31)
4227
4228	/* ETDM_OUT0_CON5 */
4229	/* ETDM_OUT1_CON5 */
4230	/* ETDM_OUT4_CON5 */
4231	#define OUT_REG_REPACK_BITNUM_SFT 0
4232	#define OUT_REG_REPACK_BITNUM_MASK 0x3
4233	#define OUT_REG_REPACK_BITNUM_MASK_SFT (0x3 << 0)
4234	#define OUT_REG_REPACK_CHNUM_SFT 2
4235	#define OUT_REG_REPACK_CHNUM_MASK 0xf
4236	#define OUT_REG_REPACK_CHNUM_MASK_SFT (0xf << 2)
4237	#define OUT_REG_SLAVE_BCK_INV_SFT 7
4238	#define OUT_REG_SLAVE_BCK_INV_MASK 0x1
4239	#define OUT_REG_SLAVE_BCK_INV_MASK_SFT (0x1 << 7)
4240	#define OUT_REG_SLAVE_LRCK_INV_SFT 8
4241	#define OUT_REG_SLAVE_LRCK_INV_MASK 0x1
4242	#define OUT_REG_SLAVE_LRCK_INV_MASK_SFT (0x1 << 8)
4243	#define OUT_REG_MASTER_BCK_INV_SFT 9
4244	#define OUT_REG_MASTER_BCK_INV_MASK 0x1
4245	#define OUT_REG_MASTER_BCK_INV_MASK_SFT (0x1 << 9)
4246	#define OUT_REG_MASTER_WS_INV_SFT 10
4247	#define OUT_REG_MASTER_WS_INV_MASK 0x1
4248	#define OUT_REG_MASTER_WS_INV_MASK_SFT (0x1 << 10)
4249	#define OUT_REG_REPACK_24B_MSB_ALIGN_SFT 11
4250	#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK 0x1
4251	#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK_SFT (0x1 << 11)
4252	#define OUT_REG_LR_SWAP_SFT 16
4253	#define OUT_REG_LR_SWAP_MASK 0xffff
4254	#define OUT_REG_LR_SWAP_MASK_SFT (0xffff << 16)
4255
4256	/* ETDM_OUT0_CON6 */
4257	/* ETDM_OUT1_CON6 */
4258	/* ETDM_OUT4_CON6 */
4259	#define OUT_LCH_DATA_REG_SFT 0
4260	#define OUT_LCH_DATA_REG_MASK 0xffffffff
4261	#define OUT_LCH_DATA_REG_MASK_SFT (0xffffffff << 0)
4262
4263	/* ETDM_OUT0_CON7 */
4264	/* ETDM_OUT1_CON7 */
4265	/* ETDM_OUT4_CON7 */
4266	#define OUT_RCH_DATA_REG_SFT 0
4267	#define OUT_RCH_DATA_REG_MASK 0xffffffff
4268	#define OUT_RCH_DATA_REG_MASK_SFT (0xffffffff << 0)
4269
4270	/* ETDM_OUT0_CON8 */
4271	/* ETDM_OUT1_CON8 */
4272	/* ETDM_OUT4_CON8 */
4273	#define OUT_REG_START_CH_PAIR8_SFT 0
4274	#define OUT_REG_START_CH_PAIR8_MASK 0xf
4275	#define OUT_REG_START_CH_PAIR8_MASK_SFT (0xf << 0)
4276	#define OUT_REG_START_CH_PAIR9_SFT 4
4277	#define OUT_REG_START_CH_PAIR9_MASK 0xf
4278	#define OUT_REG_START_CH_PAIR9_MASK_SFT (0xf << 4)
4279	#define OUT_REG_START_CH_PAIR10_SFT 8
4280	#define OUT_REG_START_CH_PAIR10_MASK 0xf
4281	#define OUT_REG_START_CH_PAIR10_MASK_SFT (0xf << 8)
4282	#define OUT_REG_START_CH_PAIR11_SFT 12
4283	#define OUT_REG_START_CH_PAIR11_MASK 0xf
4284	#define OUT_REG_START_CH_PAIR11_MASK_SFT (0xf << 12)
4285	#define OUT_REG_START_CH_PAIR12_SFT 16
4286	#define OUT_REG_START_CH_PAIR12_MASK 0xf
4287	#define OUT_REG_START_CH_PAIR12_MASK_SFT (0xf << 16)
4288	#define OUT_REG_START_CH_PAIR13_SFT 20
4289	#define OUT_REG_START_CH_PAIR13_MASK 0xf
4290	#define OUT_REG_START_CH_PAIR13_MASK_SFT (0xf << 20)
4291	#define OUT_REG_START_CH_PAIR14_SFT 24
4292	#define OUT_REG_START_CH_PAIR14_MASK 0xf
4293	#define OUT_REG_START_CH_PAIR14_MASK_SFT (0xf << 24)
4294	#define OUT_REG_START_CH_PAIR15_SFT 28
4295	#define OUT_REG_START_CH_PAIR15_MASK 0xf
4296	#define OUT_REG_START_CH_PAIR15_MASK_SFT (0xf << 28)
4297
4298	/* ETDM_OUT0_CON9 */
4299	/* ETDM_OUT1_CON9 */
4300	/* ETDM_OUT4_CON9 */
4301	#define OUT_REG_AFIFO_THRESHOLD_SFT 29
4302	#define OUT_REG_AFIFO_THRESHOLD_MASK 0x3
4303	#define OUT_REG_AFIFO_THRESHOLD_MASK_SFT (0x3 << 29)
4304	#define OUT_REG_AFIFO_SW_RESET_SFT 15
4305	#define OUT_REG_AFIFO_SW_RESET_MASK 0x1
4306	#define OUT_REG_AFIFO_SW_RESET_MASK_SFT (0x1 << 15)
4307	#define OUT_REG_AFIFO_RESET_SEL_SFT 14
4308	#define OUT_REG_AFIFO_RESET_SEL_MASK 0x1
4309	#define OUT_REG_AFIFO_RESET_SEL_MASK_SFT (0x1 << 14)
4310	#define OUT_REG_AFIFO_AUTO_RESET_DIS_SFT 9
4311	#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK 0x1
4312	#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK_SFT (0x1 << 9)
4313	#define OUT_REG_ETDM_USE_AFIFO_SFT 8
4314	#define OUT_REG_ETDM_USE_AFIFO_MASK 0x1
4315	#define OUT_REG_ETDM_USE_AFIFO_MASK_SFT (0x1 << 8)
4316	#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 5
4317	#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK 0x7
4318	#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT (0x7 << 5)
4319	#define OUT_REG_AFIFO_MODE_SFT 0
4320	#define OUT_REG_AFIFO_MODE_MASK 0x1f
4321	#define OUT_REG_AFIFO_MODE_MASK_SFT (0x1f << 0)
4322
4323	/* ETDM_OUT0_MON */
4324	/* ETDM_OUT1_MON */
4325	/* ETDM_OUT4_MON */
4326	#define LRCK_INV_SFT 30
4327	#define LRCK_INV_MASK 0x1
4328	#define LRCK_INV_MASK_SFT (0x1 << 30)
4329	#define EN_SYNC_OUT_SFT 29
4330	#define EN_SYNC_OUT_MASK 0x1
4331	#define EN_SYNC_OUT_MASK_SFT (0x1 << 29)
4332	#define HOPPING_EN_SYNC_OUT_PRE_SFT 28
4333	#define HOPPING_EN_SYNC_OUT_PRE_MASK 0x1
4334	#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT (0x1 << 28)
4335	#define ETDM_2X_CK_EN_SFT 25
4336	#define ETDM_2X_CK_EN_MASK 0x1
4337	#define ETDM_2X_CK_EN_MASK_SFT (0x1 << 25)
4338	#define ETDM_1X_CK_EN_SFT 24
4339	#define ETDM_1X_CK_EN_MASK 0x1
4340	#define ETDM_1X_CK_EN_MASK_SFT (0x1 << 24)
4341	#define SDATA0_SFT 23
4342	#define SDATA0_MASK 0x1
4343	#define SDATA0_MASK_SFT (0x1 << 23)
4344	#define CURRENT_STATUS_SFT 21
4345	#define CURRENT_STATUS_MASK 0x3
4346	#define CURRENT_STATUS_MASK_SFT (0x3 << 21)
4347	#define BIT_POINT_SFT 16
4348	#define BIT_POINT_MASK 0x1f
4349	#define BIT_POINT_MASK_SFT (0x1f << 16)
4350	#define BIT_CH_COUNT_SFT 10
4351	#define BIT_CH_COUNT_MASK 0x3f
4352	#define BIT_CH_COUNT_MASK_SFT (0x3f << 10)
4353	#define BIT_COUNT_SFT 5
4354	#define BIT_COUNT_MASK 0x1f
4355	#define BIT_COUNT_MASK_SFT (0x1f << 5)
4356	#define CH_COUNT_SFT 0
4357	#define CH_COUNT_MASK 0x1f
4358	#define CH_COUNT_MASK_SFT (0x1f << 0)
4359
4360	/* ETDM_0_3_COWORK_CON0 */
4361	#define ETDM_OUT0_DATA_SEL_SFT 0
4362	#define ETDM_OUT0_DATA_SEL_MASK 0xf
4363	#define ETDM_OUT0_DATA_SEL_MASK_SFT (0xf << 0)
4364	#define ETDM_OUT0_SYNC_SEL_SFT 4
4365	#define ETDM_OUT0_SYNC_SEL_MASK 0xf
4366	#define ETDM_OUT0_SYNC_SEL_MASK_SFT (0xf << 4)
4367	#define ETDM_OUT0_SLAVE_SEL_SFT 8
4368	#define ETDM_OUT0_SLAVE_SEL_MASK 0xf
4369	#define ETDM_OUT0_SLAVE_SEL_MASK_SFT (0xf << 8)
4370	#define ETDM_OUT1_DATA_SEL_SFT 12
4371	#define ETDM_OUT1_DATA_SEL_MASK 0xf
4372	#define ETDM_OUT1_DATA_SEL_MASK_SFT (0xf << 12)
4373	#define ETDM_OUT1_SYNC_SEL_SFT 16
4374	#define ETDM_OUT1_SYNC_SEL_MASK 0xf
4375	#define ETDM_OUT1_SYNC_SEL_MASK_SFT (0xf << 16)
4376	#define ETDM_OUT1_SLAVE_SEL_SFT 20
4377	#define ETDM_OUT1_SLAVE_SEL_MASK 0xf
4378	#define ETDM_OUT1_SLAVE_SEL_MASK_SFT (0xf << 20)
4379	#define ETDM_IN0_SLAVE_SEL_SFT 24
4380	#define ETDM_IN0_SLAVE_SEL_MASK 0xf
4381	#define ETDM_IN0_SLAVE_SEL_MASK_SFT (0xf << 24)
4382	#define ETDM_IN0_SYNC_SEL_SFT 28
4383	#define ETDM_IN0_SYNC_SEL_MASK 0xf
4384	#define ETDM_IN0_SYNC_SEL_MASK_SFT (0xf << 28)
4385
4386	/* ETDM_0_3_COWORK_CON1 */
4387	#define ETDM_IN0_SDATA0_SEL_SFT 0
4388	#define ETDM_IN0_SDATA0_SEL_MASK 0xf
4389	#define ETDM_IN0_SDATA0_SEL_MASK_SFT (0xf << 0)
4390	#define ETDM_IN0_SDATA1_15_SEL_SFT 4
4391	#define ETDM_IN0_SDATA1_15_SEL_MASK 0xf
4392	#define ETDM_IN0_SDATA1_15_SEL_MASK_SFT (0xf << 4)
4393	#define ETDM_IN1_SLAVE_SEL_SFT 8
4394	#define ETDM_IN1_SLAVE_SEL_MASK 0xf
4395	#define ETDM_IN1_SLAVE_SEL_MASK_SFT (0xf << 8)
4396	#define ETDM_IN1_SYNC_SEL_SFT 12
4397	#define ETDM_IN1_SYNC_SEL_MASK 0xf
4398	#define ETDM_IN1_SYNC_SEL_MASK_SFT (0xf << 12)
4399	#define ETDM_IN1_SDATA0_SEL_SFT 16
4400	#define ETDM_IN1_SDATA0_SEL_MASK 0xf
4401	#define ETDM_IN1_SDATA0_SEL_MASK_SFT (0xf << 16)
4402	#define ETDM_IN1_SDATA1_15_SEL_SFT 20
4403	#define ETDM_IN1_SDATA1_15_SEL_MASK 0xf
4404	#define ETDM_IN1_SDATA1_15_SEL_MASK_SFT (0xf << 20)
4405
4406	/* ETDM_4_7_COWORK_CON0 */
4407	#define ETDM_OUT4_DATA_SEL_SFT 0
4408	#define ETDM_OUT4_DATA_SEL_MASK 0xf
4409	#define ETDM_OUT4_DATA_SEL_MASK_SFT (0xf << 0)
4410	#define ETDM_OUT4_SYNC_SEL_SFT 4
4411	#define ETDM_OUT4_SYNC_SEL_MASK 0xf
4412	#define ETDM_OUT4_SYNC_SEL_MASK_SFT (0xf << 4)
4413	#define ETDM_OUT4_SLAVE_SEL_SFT 8
4414	#define ETDM_OUT4_SLAVE_SEL_MASK 0xf
4415	#define ETDM_OUT4_SLAVE_SEL_MASK_SFT (0xf << 8)
4416
4417	/* AFE_DPTX_CON */
4418	#define DPTX_CHANNEL_ENABLE_SFT 8
4419	#define DPTX_CHANNEL_ENABLE_MASK 0xff
4420	#define DPTX_CHANNEL_ENABLE_MASK_SFT (0xff << 8)
4421	#define DPTX_REGISTER_MONITOR_SELECT_SFT 3
4422	#define DPTX_REGISTER_MONITOR_SELECT_MASK 0xf
4423	#define DPTX_REGISTER_MONITOR_SELECT_MASK_SFT (0xf << 3)
4424	#define DPTX_16BIT_SFT 2
4425	#define DPTX_16BIT_MASK 0x1
4426	#define DPTX_16BIT_MASK_SFT (0x1 << 2)
4427	#define DPTX_CHANNEL_NUMBER_SFT 1
4428	#define DPTX_CHANNEL_NUMBER_MASK 0x1
4429	#define DPTX_CHANNEL_NUMBER_MASK_SFT (0x1 << 1)
4430	#define DPTX_ON_SFT 0
4431	#define DPTX_ON_MASK 0x1
4432	#define DPTX_ON_MASK_SFT (0x1 << 0)
4433
4434	/* AFE_DPTX_MON */
4435	#define AFE_DPTX_MON0_SFT 0
4436	#define AFE_DPTX_MON0_MASK 0xffffffff
4437	#define AFE_DPTX_MON0_MASK_SFT (0xffffffff << 0)
4438
4439	/* AFE_TDM_CON1 */
4440	#define TDM_EN_SFT 0
4441	#define TDM_EN_MASK 0x1
4442	#define TDM_EN_MASK_SFT (0x1 << 0)
4443	#define BCK_INVERSE_SFT 1
4444	#define BCK_INVERSE_MASK 0x1
4445	#define BCK_INVERSE_MASK_SFT (0x1 << 1)
4446	#define LRCK_INVERSE_SFT 2
4447	#define LRCK_INVERSE_MASK 0x1
4448	#define LRCK_INVERSE_MASK_SFT (0x1 << 2)
4449	#define DELAY_DATA_SFT 3
4450	#define DELAY_DATA_MASK 0x1
4451	#define DELAY_DATA_MASK_SFT (0x1 << 3)
4452	#define LEFT_ALIGN_SFT 4
4453	#define LEFT_ALIGN_MASK 0x1
4454	#define LEFT_ALIGN_MASK_SFT (0x1 << 4)
4455	#define TDM_LRCK_D0P5T_SFT 5
4456	#define TDM_LRCK_D0P5T_MASK 0x1
4457	#define TDM_LRCK_D0P5T_MASK_SFT (0x1 << 5)
4458	#define TDM_SDATA_D0P5T_SFT 6
4459	#define TDM_SDATA_D0P5T_MASK 0x1
4460	#define TDM_SDATA_D0P5T_MASK_SFT (0x1 << 6)
4461	#define WLEN_SFT 8
4462	#define WLEN_MASK 0x3
4463	#define WLEN_MASK_SFT (0x3 << 8)
4464	#define CHANNEL_NUM_SFT 10
4465	#define CHANNEL_NUM_MASK 0x3
4466	#define CHANNEL_NUM_MASK_SFT (0x3 << 10)
4467	#define CHANNEL_BCK_CYCLES_SFT 12
4468	#define CHANNEL_BCK_CYCLES_MASK 0x3
4469	#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12)
4470	#define HDMI_CLK_INV_SEL_SFT 15
4471	#define HDMI_CLK_INV_SEL_MASK 0x1
4472	#define HDMI_CLK_INV_SEL_MASK_SFT (0x1 << 15)
4473	#define DAC_BIT_NUM_SFT 16
4474	#define DAC_BIT_NUM_MASK 0x1f
4475	#define DAC_BIT_NUM_MASK_SFT (0x1f << 16)
4476	#define LRCK_TDM_WIDTH_SFT 24
4477	#define LRCK_TDM_WIDTH_MASK 0xff
4478	#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24)
4479
4480	/* AFE_TDM_CON2 */
4481	#define ST_CH_PAIR_SOUT0_SFT 0
4482	#define ST_CH_PAIR_SOUT0_MASK 0x7
4483	#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0)
4484	#define ST_CH_PAIR_SOUT1_SFT 4
4485	#define ST_CH_PAIR_SOUT1_MASK 0x7
4486	#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4)
4487	#define ST_CH_PAIR_SOUT2_SFT 8
4488	#define ST_CH_PAIR_SOUT2_MASK 0x7
4489	#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8)
4490	#define ST_CH_PAIR_SOUT3_SFT 12
4491	#define ST_CH_PAIR_SOUT3_MASK 0x7
4492	#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12)
4493	#define TDM_FIX_VALUE_SEL_SFT 16
4494	#define TDM_FIX_VALUE_SEL_MASK 0x1
4495	#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)
4496	#define TDM_I2S_LOOPBACK_SFT 20
4497	#define TDM_I2S_LOOPBACK_MASK 0x1
4498	#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)
4499	#define TDM_I2S_LOOPBACK_CH_SFT 21
4500	#define TDM_I2S_LOOPBACK_CH_MASK 0x3
4501	#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21)
4502	#define TDM_USE_SINEGEN_INPUT_SFT 23
4503	#define TDM_USE_SINEGEN_INPUT_MASK 0x1
4504	#define TDM_USE_SINEGEN_INPUT_MASK_SFT (0x1 << 23)
4505	#define TDM_FIX_VALUE_SFT 24
4506	#define TDM_FIX_VALUE_MASK 0xff
4507	#define TDM_FIX_VALUE_MASK_SFT (0xff << 24)
4508
4509	/* AFE_TDM_CON3 */
4510	#define TDM_OUT_SEL_DOMAIN_SFT 29
4511	#define TDM_OUT_SEL_DOMAIN_MASK 0x7
4512	#define TDM_OUT_SEL_DOMAIN_MASK_SFT (0x7 << 29)
4513	#define TDM_OUT_SEL_FS_SFT 24
4514	#define TDM_OUT_SEL_FS_MASK 0x1f
4515	#define TDM_OUT_SEL_FS_MASK_SFT (0x1f << 24)
4516	#define TDM_OUT_MON_SEL_SFT 3
4517	#define TDM_OUT_MON_SEL_MASK 0x1
4518	#define TDM_OUT_MON_SEL_MASK_SFT (0x1 << 3)
4519	#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_SFT 2
4520	#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
4521	#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 2)
4522	#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_SFT 1
4523	#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK 0x1
4524	#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 1)
4525	#define TDM_UPDATE_EN_SEL_SFT 0
4526	#define TDM_UPDATE_EN_SEL_MASK 0x1
4527	#define TDM_UPDATE_EN_SEL_MASK_SFT (0x1 << 0)
4528
4529	/* AFE_TDM_OUT_MON */
4530	#define AFE_TDM_OUT_MON_SFT 0
4531	#define AFE_TDM_OUT_MON_MASK 0xffffffff
4532	#define AFE_TDM_OUT_MON_MASK_SFT (0xffffffff << 0)
4533
4534	/* AFE_HDMI_CONN0 */
4535	#define HDMI_O_7_SFT 21
4536	#define HDMI_O_7_MASK 0x7
4537	#define HDMI_O_7_MASK_SFT (0x7 << 21)
4538	#define HDMI_O_6_SFT 18
4539	#define HDMI_O_6_MASK 0x7
4540	#define HDMI_O_6_MASK_SFT (0x7 << 18)
4541	#define HDMI_O_5_SFT 15
4542	#define HDMI_O_5_MASK 0x7
4543	#define HDMI_O_5_MASK_SFT (0x7 << 15)
4544	#define HDMI_O_4_SFT 12
4545	#define HDMI_O_4_MASK 0x7
4546	#define HDMI_O_4_MASK_SFT (0x7 << 12)
4547	#define HDMI_O_3_SFT 9
4548	#define HDMI_O_3_MASK 0x7
4549	#define HDMI_O_3_MASK_SFT (0x7 << 9)
4550	#define HDMI_O_2_SFT 6
4551	#define HDMI_O_2_MASK 0x7
4552	#define HDMI_O_2_MASK_SFT (0x7 << 6)
4553	#define HDMI_O_1_SFT 3
4554	#define HDMI_O_1_MASK 0x7
4555	#define HDMI_O_1_MASK_SFT (0x7 << 3)
4556	#define HDMI_O_0_SFT 0
4557	#define HDMI_O_0_MASK 0x7
4558	#define HDMI_O_0_MASK_SFT (0x7 << 0)
4559
4560	/* AFE_TDM_TOP_IP_VERSION */
4561	#define AFE_TDM_TOP_IP_VERSION_SFT 0
4562	#define AFE_TDM_TOP_IP_VERSION_MASK 0xffffffff
4563	#define AFE_TDM_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0)
4564
4565	/* AFE_HDMI_OUT_BASE_MSB */
4566	#define AFE_HDMI_OUT_BASE_MSB_SFT 0
4567	#define AFE_HDMI_OUT_BASE_MSB_MASK 0x1ff
4568	#define AFE_HDMI_OUT_BASE_MSB_MASK_SFT (0x1ff << 0)
4569
4570	/* AFE_HDMI_OUT_BASE */
4571	#define AFE_HDMI_OUT_BASE_SFT 4
4572	#define AFE_HDMI_OUT_BASE_MASK 0xfffffff
4573	#define AFE_HDMI_OUT_BASE_MASK_SFT (0xfffffff << 4)
4574
4575	/* AFE_HDMI_OUT_CUR_MSB */
4576	#define AFE_HDMI_OUT_CUR_MSB_SFT 0
4577	#define AFE_HDMI_OUT_CUR_MSB_MASK 0x1ff
4578	#define AFE_HDMI_OUT_CUR_MSB_MASK_SFT (0x1ff << 0)
4579
4580	/* AFE_HDMI_OUT_CUR */
4581	#define AFE_HDMI_OUT_CUR_SFT 0
4582	#define AFE_HDMI_OUT_CUR_MASK 0xffffffff
4583	#define AFE_HDMI_OUT_CUR_MASK_SFT (0xffffffff << 0)
4584
4585	/* AFE_HDMI_OUT_END_MSB */
4586	#define AFE_HDMI_OUT_END_MSB_SFT 0
4587	#define AFE_HDMI_OUT_END_MSB_MASK 0x1ff
4588	#define AFE_HDMI_OUT_END_MSB_MASK_SFT (0x1ff << 0)
4589
4590	/* AFE_HDMI_OUT_END */
4591	#define AFE_HDMI_OUT_END_SFT 4
4592	#define AFE_HDMI_OUT_END_MASK 0xfffffff
4593	#define AFE_HDMI_OUT_END_MASK_SFT (0xfffffff << 4)
4594	#define AFE_HDMI_OUT_END_LSB_SFT 0
4595	#define AFE_HDMI_OUT_END_LSB_MASK 0xf
4596	#define AFE_HDMI_OUT_END_LSB_MASK_SFT (0xf << 0)
4597
4598	/* AFE_HDMI_OUT_CON0 */
4599	#define HDMI_OUT_ON_SFT 28
4600	#define HDMI_OUT_ON_MASK 0x1
4601	#define HDMI_OUT_ON_MASK_SFT (0x1 << 28)
4602	#define HDMI_CH_NUM_SFT 24
4603	#define HDMI_CH_NUM_MASK 0xf
4604	#define HDMI_CH_NUM_MASK_SFT (0xf << 24)
4605	#define HDMI_OUT_ONE_HEART_SEL_SFT 22
4606	#define HDMI_OUT_ONE_HEART_SEL_MASK 0x3
4607	#define HDMI_OUT_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
4608	#define HDMI_OUT_MINLEN_SFT 20
4609	#define HDMI_OUT_MINLEN_MASK 0x3
4610	#define HDMI_OUT_MINLEN_MASK_SFT (0x3 << 20)
4611	#define HDMI_OUT_MAXLEN_SFT 16
4612	#define HDMI_OUT_MAXLEN_MASK 0x3
4613	#define HDMI_OUT_MAXLEN_MASK_SFT (0x3 << 16)
4614	#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_SFT 15
4615	#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK 0x1
4616	#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
4617	#define HDMI_OUT_PBUF_SIZE_SFT 12
4618	#define HDMI_OUT_PBUF_SIZE_MASK 0x3
4619	#define HDMI_OUT_PBUF_SIZE_MASK_SFT (0x3 << 12)
4620	#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_SFT 7
4621	#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK 0x1
4622	#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK_SFT (0x1 << 7)
4623	#define HDMI_OUT_NORMAL_MODE_SFT 5
4624	#define HDMI_OUT_NORMAL_MODE_MASK 0x1
4625	#define HDMI_OUT_NORMAL_MODE_MASK_SFT (0x1 << 5)
4626	#define HDMI_OUT_HALIGN_SFT 4
4627	#define HDMI_OUT_HALIGN_MASK 0x1
4628	#define HDMI_OUT_HALIGN_MASK_SFT (0x1 << 4)
4629	#define HDMI_OUT_HD_MODE_SFT 0
4630	#define HDMI_OUT_HD_MODE_MASK 0x3
4631	#define HDMI_OUT_HD_MODE_MASK_SFT (0x3 << 0)
4632
4633	/* AFE_CBIP_CFG0 */
4634	#define CBIP_TOP_SLV_MUX_WAY_EN_SFT 16
4635	#define CBIP_TOP_SLV_MUX_WAY_EN_MASK 0xffff
4636	#define CBIP_TOP_SLV_MUX_WAY_EN_MASK_SFT (0xffff << 16)
4637	#define RESERVED_04_SFT 15
4638	#define RESERVED_04_MASK 0x1
4639	#define RESERVED_04_MASK_SFT (0x1 << 15)
4640	#define CBIP_ASYNC_MST_RG_FIFO_THRE_SFT 13
4641	#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK 0x3
4642	#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK_SFT (0x3 << 13)
4643	#define CBIP_ASYNC_MST_POSTWRITE_DIS_SFT 12
4644	#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK 0x1
4645	#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK_SFT (0x1 << 12)
4646	#define RESERVED_03_SFT 11
4647	#define RESERVED_03_MASK 0x1
4648	#define RESERVED_03_MASK_SFT (0x1 << 11)
4649	#define CBIP_ASYNC_SLV_RG_FIFO_THRE_SFT 9
4650	#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK 0x3
4651	#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK_SFT (0x3 << 9)
4652	#define CBIP_ASYNC_SLV_POSTWRITE_DIS_SFT 8
4653	#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK 0x1
4654	#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK_SFT (0x1 << 8)
4655	#define AUDIOSYS_BUSY_SFT 7
4656	#define AUDIOSYS_BUSY_MASK 0x1
4657	#define AUDIOSYS_BUSY_MASK_SFT (0x1 << 7)
4658	#define CBIP_SLV_DECODER_ERR_FLAG_EN_SFT 6
4659	#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK 0x1
4660	#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK_SFT (0x1 << 6)
4661	#define CBIP_SLV_DECODER_SLAVE_WAY_EN_SFT 5
4662	#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK 0x1
4663	#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK_SFT (0x1 << 5)
4664	#define APB_R2T_SFT 3
4665	#define APB_R2T_MASK 0x1
4666	#define APB_R2T_MASK_SFT (0x1 << 3)
4667	#define APB_W2T_SFT 2
4668	#define APB_W2T_MASK 0x1
4669	#define APB_W2T_MASK_SFT (0x1 << 2)
4670	#define AHB_IDLE_EN_INT_SFT 1
4671	#define AHB_IDLE_EN_INT_MASK 0x1
4672	#define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 1)
4673	#define AHB_IDLE_EN_EXT_SFT 0
4674	#define AHB_IDLE_EN_EXT_MASK 0x1
4675	#define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 0)
4676
4677	/* AFE_CBIP_SLV_DECODER_MON0 */
4678	#define CBIP_SLV_DECODER_ERR_DOMAIN_SFT 4
4679	#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK 0x1
4680	#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK_SFT (0x1 << 4)
4681	#define CBIP_SLV_DECODER_ERR_ID_SFT 3
4682	#define CBIP_SLV_DECODER_ERR_ID_MASK 0x1
4683	#define CBIP_SLV_DECODER_ERR_ID_MASK_SFT (0x1 << 3)
4684	#define CBIP_SLV_DECODER_ERR_RW_SFT 2
4685	#define CBIP_SLV_DECODER_ERR_RW_MASK 0x1
4686	#define CBIP_SLV_DECODER_ERR_RW_MASK_SFT (0x1 << 2)
4687	#define CBIP_SLV_DECODER_ERR_DECERR_SFT 1
4688	#define CBIP_SLV_DECODER_ERR_DECERR_MASK 0x1
4689	#define CBIP_SLV_DECODER_ERR_DECERR_MASK_SFT (0x1 << 1)
4690	#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_SFT 0
4691	#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK 0x1
4692	#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK_SFT (0x1 << 0)
4693
4694	/* AFE_CBIP_SLV_DECODER_MON1 */
4695	#define CBIP_SLV_DECODER_ERR_ADDR_SFT 0
4696	#define CBIP_SLV_DECODER_ERR_ADDR_MASK 0xffffffff
4697	#define CBIP_SLV_DECODER_ERR_ADDR_MASK_SFT (0xffffffff << 0)
4698
4699	/* AFE_CBIP_SLV_MUX_MON_CFG */
4700	#define CBIP_SLV_MUX_ERR_FLAG_EN_SFT 3
4701	#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK 0x1
4702	#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK_SFT (0x1 << 3)
4703	#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_SFT 2
4704	#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK 0x1
4705	#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK_SFT (0x1 << 2)
4706	#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_SFT 0
4707	#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK 0x3
4708	#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK_SFT (0x3 << 0)
4709
4710	/* AFE_CBIP_SLV_MUX_MON0 */
4711	#define CBIP_SLV_MUX_ERR_DOMAIN_SFT 8
4712	#define CBIP_SLV_MUX_ERR_DOMAIN_MASK 0x1
4713	#define CBIP_SLV_MUX_ERR_DOMAIN_MASK_SFT (0x1 << 8)
4714	#define CBIP_SLV_MUX_ERR_ID_SFT 7
4715	#define CBIP_SLV_MUX_ERR_ID_MASK 0x1
4716	#define CBIP_SLV_MUX_ERR_ID_MASK_SFT (0x1 << 7)
4717	#define CBIP_SLV_MUX_ERR_RD_SFT 6
4718	#define CBIP_SLV_MUX_ERR_RD_MASK 0x1
4719	#define CBIP_SLV_MUX_ERR_RD_MASK_SFT (0x1 << 6)
4720	#define CBIP_SLV_MUX_ERR_WR_SFT 5
4721	#define CBIP_SLV_MUX_ERR_WR_MASK 0x1
4722	#define CBIP_SLV_MUX_ERR_WR_MASK_SFT (0x1 << 5)
4723	#define CBIP_SLV_MUX_ERR_EN_SLV_SFT 4
4724	#define CBIP_SLV_MUX_ERR_EN_SLV_MASK 0x1
4725	#define CBIP_SLV_MUX_ERR_EN_SLV_MASK_SFT (0x1 << 4)
4726	#define CBIP_SLV_MUX_ERR_EN_MST_SFT 2
4727	#define CBIP_SLV_MUX_ERR_EN_MST_MASK 0x3
4728	#define CBIP_SLV_MUX_ERR_EN_MST_MASK_SFT (0x3 << 2)
4729	#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_SFT 0
4730	#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK 0x3
4731	#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK_SFT (0x3 << 0)
4732
4733	/* AFE_CBIP_SLV_MUX_MON1 */
4734	#define CBIP_SLV_MUX_ERR_ADDR_SFT 0
4735	#define CBIP_SLV_MUX_ERR_ADDR_MASK 0xffffffff
4736	#define CBIP_SLV_MUX_ERR_ADDR_MASK_SFT (0xffffffff << 0)
4737
4738	/* AFE_MEMIF_CON0 */
4739	#define CPU_COMPACT_MODE_SFT 2
4740	#define CPU_COMPACT_MODE_MASK 0x1
4741	#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 2)
4742	#define CPU_HD_ALIGN_SFT 1
4743	#define CPU_HD_ALIGN_MASK 0x1
4744	#define CPU_HD_ALIGN_MASK_SFT (0x1 << 1)
4745	#define SYSRAM_SIGN_SFT 0
4746	#define SYSRAM_SIGN_MASK 0x1
4747	#define SYSRAM_SIGN_MASK_SFT (0x1 << 0)
4748
4749	/* AFE_MEMIF_ONE_HEART */
4750	#define DL_ONE_HEART_ON_2_SFT 2
4751	#define DL_ONE_HEART_ON_2_MASK 0x1
4752	#define DL_ONE_HEART_ON_2_MASK_SFT (0x1 << 2)
4753	#define DL_ONE_HEART_ON_1_SFT 1
4754	#define DL_ONE_HEART_ON_1_MASK 0x1
4755	#define DL_ONE_HEART_ON_1_MASK_SFT (0x1 << 1)
4756	#define DL_ONE_HEART_ON_0_SFT 0
4757	#define DL_ONE_HEART_ON_0_MASK 0x1
4758	#define DL_ONE_HEART_ON_0_MASK_SFT (0x1 << 0)
4759
4760	/* AFE_DL0_BASE_MSB */
4761	#define DL0_BASE_ADDR_MSB_SFT 0
4762	#define DL0_BASE_ADDR_MSB_MASK 0x1ff
4763	#define DL0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
4764
4765	/* AFE_DL0_BASE */
4766	#define DL0_BASE_ADDR_SFT 4
4767	#define DL0_BASE_ADDR_MASK 0xfffffff
4768	#define DL0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
4769
4770	/* AFE_DL0_CUR_MSB */
4771	#define DL0_CUR_PTR_MSB_SFT 0
4772	#define DL0_CUR_PTR_MSB_MASK 0x1ff
4773	#define DL0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
4774
4775	/* AFE_DL0_CUR */
4776	#define DL0_CUR_PTR_SFT 0
4777	#define DL0_CUR_PTR_MASK 0xffffffff
4778	#define DL0_CUR_PTR_MASK_SFT (0xffffffff << 0)
4779
4780	/* AFE_DL0_END_MSB */
4781	#define DL0_END_ADDR_MSB_SFT 0
4782	#define DL0_END_ADDR_MSB_MASK 0x1ff
4783	#define DL0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
4784
4785	/* AFE_DL0_END */
4786	#define DL0_END_ADDR_SFT 4
4787	#define DL0_END_ADDR_MASK 0xfffffff
4788	#define DL0_END_ADDR_MASK_SFT (0xfffffff << 4)
4789
4790	/* AFE_DL0_RCH_MON */
4791	#define DL0_RCH_DATA_SFT 0
4792	#define DL0_RCH_DATA_MASK 0xffffffff
4793	#define DL0_RCH_DATA_MASK_SFT (0xffffffff << 0)
4794
4795	/* AFE_DL0_LCH_MON */
4796	#define DL0_LCH_DATA_SFT 0
4797	#define DL0_LCH_DATA_MASK 0xffffffff
4798	#define DL0_LCH_DATA_MASK_SFT (0xffffffff << 0)
4799
4800	/* AFE_DL0_CON0 */
4801	#define DL0_ON_SFT 28
4802	#define DL0_ON_MASK 0x1
4803	#define DL0_ON_MASK_SFT (0x1 << 28)
4804	#define DL0_ONE_HEART_SEL_SFT 22
4805	#define DL0_ONE_HEART_SEL_MASK 0x3
4806	#define DL0_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
4807	#define DL0_MINLEN_SFT 20
4808	#define DL0_MINLEN_MASK 0x3
4809	#define DL0_MINLEN_MASK_SFT (0x3 << 20)
4810	#define DL0_MAXLEN_SFT 16
4811	#define DL0_MAXLEN_MASK 0x3
4812	#define DL0_MAXLEN_MASK_SFT (0x3 << 16)
4813	#define DL0_SEL_DOMAIN_SFT 13
4814	#define DL0_SEL_DOMAIN_MASK 0x7
4815	#define DL0_SEL_DOMAIN_MASK_SFT (0x7 << 13)
4816	#define DL0_SEL_FS_SFT 8
4817	#define DL0_SEL_FS_MASK 0x1f
4818	#define DL0_SEL_FS_MASK_SFT (0x1f << 8)
4819	#define DL0_SW_CLEAR_BUF_EMPTY_SFT 7
4820	#define DL0_SW_CLEAR_BUF_EMPTY_MASK 0x1
4821	#define DL0_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
4822	#define DL0_PBUF_SIZE_SFT 5
4823	#define DL0_PBUF_SIZE_MASK 0x3
4824	#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5)
4825	#define DL0_MONO_SFT 4
4826	#define DL0_MONO_MASK 0x1
4827	#define DL0_MONO_MASK_SFT (0x1 << 4)
4828	#define DL0_NORMAL_MODE_SFT 3
4829	#define DL0_NORMAL_MODE_MASK 0x1
4830	#define DL0_NORMAL_MODE_MASK_SFT (0x1 << 3)
4831	#define DL0_HALIGN_SFT 2
4832	#define DL0_HALIGN_MASK 0x1
4833	#define DL0_HALIGN_MASK_SFT (0x1 << 2)
4834	#define DL0_HD_MODE_SFT 0
4835	#define DL0_HD_MODE_MASK 0x3
4836	#define DL0_HD_MODE_MASK_SFT (0x3 << 0)
4837
4838	/* AFE_DL0_MON0 */
4839	#define RESERVED_01_SFT 20
4840	#define RESERVED_01_MASK 0xfff
4841	#define RESERVED_01_MASK_SFT (0xfff << 20)
4842	#define MEM_REQ_PENDING_SFT 19
4843	#define MEM_REQ_PENDING_MASK 0x1
4844	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
4845	#define BUF_EMPTY_SFT 18
4846	#define BUF_EMPTY_MASK 0x1
4847	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
4848	#define ENABLE_SYNC_MEM_SFT 17
4849	#define ENABLE_SYNC_MEM_MASK 0x1
4850	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
4851	#define ENABLE_SYNC_AGENT_SFT 16
4852	#define ENABLE_SYNC_AGENT_MASK 0x1
4853	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
4854	#define RESERVED_02_SFT 6
4855	#define RESERVED_02_MASK 0x3ff
4856	#define RESERVED_02_MASK_SFT (0x3ff << 6)
4857	#define MEM_ADDR_DIFF_SFT 0
4858	#define MEM_ADDR_DIFF_MASK 0x3f
4859	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
4860
4861	/* AFE_DL1_BASE_MSB */
4862	#define DL1_BASE_ADDR_MSB_SFT 0
4863	#define DL1_BASE_ADDR_MSB_MASK 0x1ff
4864	#define DL1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
4865
4866	/* AFE_DL1_BASE */
4867	#define DL1_BASE_ADDR_SFT 4
4868	#define DL1_BASE_ADDR_MASK 0xfffffff
4869	#define DL1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
4870
4871	/* AFE_DL1_CUR_MSB */
4872	#define DL1_CUR_PTR_MSB_SFT 0
4873	#define DL1_CUR_PTR_MSB_MASK 0x1ff
4874	#define DL1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
4875
4876	/* AFE_DL1_CUR */
4877	#define DL1_CUR_PTR_SFT 0
4878	#define DL1_CUR_PTR_MASK 0xffffffff
4879	#define DL1_CUR_PTR_MASK_SFT (0xffffffff << 0)
4880
4881	/* AFE_DL1_END_MSB */
4882	#define DL1_END_ADDR_MSB_SFT 0
4883	#define DL1_END_ADDR_MSB_MASK 0x1ff
4884	#define DL1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
4885
4886	/* AFE_DL1_END */
4887	#define DL1_END_ADDR_SFT 4
4888	#define DL1_END_ADDR_MASK 0xfffffff
4889	#define DL1_END_ADDR_MASK_SFT (0xfffffff << 4)
4890
4891	/* AFE_DL1_RCH_MON */
4892	#define DL1_RCH_DATA_SFT 0
4893	#define DL1_RCH_DATA_MASK 0xffffffff
4894	#define DL1_RCH_DATA_MASK_SFT (0xffffffff << 0)
4895
4896	/* AFE_DL1_LCH_MON */
4897	#define DL1_LCH_DATA_SFT 0
4898	#define DL1_LCH_DATA_MASK 0xffffffff
4899	#define DL1_LCH_DATA_MASK_SFT (0xffffffff << 0)
4900
4901	/* AFE_DL1_CON0 */
4902	#define DL1_ON_SFT 28
4903	#define DL1_ON_MASK 0x1
4904	#define DL1_ON_MASK_SFT (0x1 << 28)
4905	#define DL1_ONE_HEART_SEL_SFT 22
4906	#define DL1_ONE_HEART_SEL_MASK 0x3
4907	#define DL1_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
4908	#define DL1_MINLEN_SFT 20
4909	#define DL1_MINLEN_MASK 0x3
4910	#define DL1_MINLEN_MASK_SFT (0x3 << 20)
4911	#define DL1_MAXLEN_SFT 16
4912	#define DL1_MAXLEN_MASK 0x3
4913	#define DL1_MAXLEN_MASK_SFT (0x3 << 16)
4914	#define DL1_SEL_DOMAIN_SFT 13
4915	#define DL1_SEL_DOMAIN_MASK 0x7
4916	#define DL1_SEL_DOMAIN_MASK_SFT (0x7 << 13)
4917	#define DL1_SEL_FS_SFT 8
4918	#define DL1_SEL_FS_MASK 0x1f
4919	#define DL1_SEL_FS_MASK_SFT (0x1f << 8)
4920	#define DL1_SW_CLEAR_BUF_EMPTY_SFT 7
4921	#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1
4922	#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
4923	#define DL1_PBUF_SIZE_SFT 5
4924	#define DL1_PBUF_SIZE_MASK 0x3
4925	#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 5)
4926	#define DL1_MONO_SFT 4
4927	#define DL1_MONO_MASK 0x1
4928	#define DL1_MONO_MASK_SFT (0x1 << 4)
4929	#define DL1_NORMAL_MODE_SFT 3
4930	#define DL1_NORMAL_MODE_MASK 0x1
4931	#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 3)
4932	#define DL1_HALIGN_SFT 2
4933	#define DL1_HALIGN_MASK 0x1
4934	#define DL1_HALIGN_MASK_SFT (0x1 << 2)
4935	#define DL1_HD_MODE_SFT 0
4936	#define DL1_HD_MODE_MASK 0x3
4937	#define DL1_HD_MODE_MASK_SFT (0x3 << 0)
4938
4939	/* AFE_DL1_MON0 */
4940	#define RESERVED_01_SFT 20
4941	#define RESERVED_01_MASK 0xfff
4942	#define RESERVED_01_MASK_SFT (0xfff << 20)
4943	#define MEM_REQ_PENDING_SFT 19
4944	#define MEM_REQ_PENDING_MASK 0x1
4945	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
4946	#define BUF_EMPTY_SFT 18
4947	#define BUF_EMPTY_MASK 0x1
4948	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
4949	#define ENABLE_SYNC_MEM_SFT 17
4950	#define ENABLE_SYNC_MEM_MASK 0x1
4951	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
4952	#define ENABLE_SYNC_AGENT_SFT 16
4953	#define ENABLE_SYNC_AGENT_MASK 0x1
4954	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
4955	#define RESERVED_02_SFT 6
4956	#define RESERVED_02_MASK 0x3ff
4957	#define RESERVED_02_MASK_SFT (0x3ff << 6)
4958	#define MEM_ADDR_DIFF_SFT 0
4959	#define MEM_ADDR_DIFF_MASK 0x3f
4960	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
4961
4962	/* AFE_DL2_BASE_MSB */
4963	#define DL2_BASE__ADDR_MSB_SFT 0
4964	#define DL2_BASE__ADDR_MSB_MASK 0x1ff
4965	#define DL2_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
4966
4967	/* AFE_DL2_BASE */
4968	#define DL2_BASE_ADDR_SFT 4
4969	#define DL2_BASE_ADDR_MASK 0xfffffff
4970	#define DL2_BASE_ADDR_MASK_SFT (0xfffffff << 4)
4971
4972	/* AFE_DL2_CUR_MSB */
4973	#define DL2_CUR_PTR_MSB_SFT 0
4974	#define DL2_CUR_PTR_MSB_MASK 0x1ff
4975	#define DL2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
4976
4977	/* AFE_DL2_CUR */
4978	#define DL2_CUR_PTR_SFT 0
4979	#define DL2_CUR_PTR_MASK 0xffffffff
4980	#define DL2_CUR_PTR_MASK_SFT (0xffffffff << 0)
4981
4982	/* AFE_DL2_END_MSB */
4983	#define DL2_END_ADDR_MSB_SFT 0
4984	#define DL2_END_ADDR_MSB_MASK 0x1ff
4985	#define DL2_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
4986
4987	/* AFE_DL2_END */
4988	#define DL2_END_ADDR_SFT 4
4989	#define DL2_END_ADDR_MASK 0xfffffff
4990	#define DL2_END_ADDR_MASK_SFT (0xfffffff << 4)
4991
4992	/* AFE_DL2_RCH_MON */
4993	#define DL2_RCH_DATA_SFT 0
4994	#define DL2_RCH_DATA_MASK 0xffffffff
4995	#define DL2_RCH_DATA_MASK_SFT (0xffffffff << 0)
4996
4997	/* AFE_DL2_LCH_MON */
4998	#define DL2_LCH_DATA_SFT 0
4999	#define DL2_LCH_DATA_MASK 0xffffffff
5000	#define DL2_LCH_DATA_MASK_SFT (0xffffffff << 0)
5001
5002	/* AFE_DL2_CON0 */
5003	#define DL2_ON_SFT 28
5004	#define DL2_ON_MASK 0x1
5005	#define DL2_ON_MASK_SFT (0x1 << 28)
5006	#define DL2_ONE_HEART_SEL_SFT 22
5007	#define DL2_ONE_HEART_SEL_MASK 0x3
5008	#define DL2_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5009	#define DL2_MINLEN_SFT 20
5010	#define DL2_MINLEN_MASK 0x3
5011	#define DL2_MINLEN_MASK_SFT (0x3 << 20)
5012	#define DL2_MAXLEN_SFT 16
5013	#define DL2_MAXLEN_MASK 0x3
5014	#define DL2_MAXLEN_MASK_SFT (0x3 << 16)
5015	#define DL2_SEL_DOMAIN_SFT 13
5016	#define DL2_SEL_DOMAIN_MASK 0x7
5017	#define DL2_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5018	#define DL2_SEL_FS_SFT 8
5019	#define DL2_SEL_FS_MASK 0x1f
5020	#define DL2_SEL_FS_MASK_SFT (0x1f << 8)
5021	#define DL2_SW_CLEAR_BUF_EMPTY_SFT 7
5022	#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1
5023	#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5024	#define DL2_PBUF_SIZE_SFT 5
5025	#define DL2_PBUF_SIZE_MASK 0x3
5026	#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 5)
5027	#define DL2_MONO_SFT 4
5028	#define DL2_MONO_MASK 0x1
5029	#define DL2_MONO_MASK_SFT (0x1 << 4)
5030	#define DL2_NORMAL_MODE_SFT 3
5031	#define DL2_NORMAL_MODE_MASK 0x1
5032	#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 3)
5033	#define DL2_HALIGN_SFT 2
5034	#define DL2_HALIGN_MASK 0x1
5035	#define DL2_HALIGN_MASK_SFT (0x1 << 2)
5036	#define DL2_HD_MODE_SFT 0
5037	#define DL2_HD_MODE_MASK 0x3
5038	#define DL2_HD_MODE_MASK_SFT (0x3 << 0)
5039
5040	/* AFE_DL2_MON0 */
5041	#define RESERVED_01_SFT 20
5042	#define RESERVED_01_MASK 0xfff
5043	#define RESERVED_01_MASK_SFT (0xfff << 20)
5044	#define MEM_REQ_PENDING_SFT 19
5045	#define MEM_REQ_PENDING_MASK 0x1
5046	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5047	#define BUF_EMPTY_SFT 18
5048	#define BUF_EMPTY_MASK 0x1
5049	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5050	#define ENABLE_SYNC_MEM_SFT 17
5051	#define ENABLE_SYNC_MEM_MASK 0x1
5052	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5053	#define ENABLE_SYNC_AGENT_SFT 16
5054	#define ENABLE_SYNC_AGENT_MASK 0x1
5055	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5056	#define RESERVED_02_SFT 6
5057	#define RESERVED_02_MASK 0x3ff
5058	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5059	#define MEM_ADDR_DIFF_SFT 0
5060	#define MEM_ADDR_DIFF_MASK 0x3f
5061	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5062
5063	/* AFE_DL3_BASE_MSB */
5064	#define DL3_BASE__ADDR_MSB_SFT 0
5065	#define DL3_BASE__ADDR_MSB_MASK 0x1ff
5066	#define DL3_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5067
5068	/* AFE_DL3_BASE */
5069	#define DL3_BASE_ADDR_SFT 4
5070	#define DL3_BASE_ADDR_MASK 0xfffffff
5071	#define DL3_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5072
5073	/* AFE_DL3_CUR_MSB */
5074	#define DL3_CUR_PTR_MSB_SFT 0
5075	#define DL3_CUR_PTR_MSB_MASK 0x1ff
5076	#define DL3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5077
5078	/* AFE_DL3_CUR */
5079	#define DL3_CUR_PTR_SFT 0
5080	#define DL3_CUR_PTR_MASK 0xffffffff
5081	#define DL3_CUR_PTR_MASK_SFT (0xffffffff << 0)
5082
5083	/* AFE_DL3_END_MSB */
5084	#define DL3_END_ADDR_MSB_SFT 0
5085	#define DL3_END_ADDR_MSB_MASK 0x1ff
5086	#define DL3_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5087
5088	/* AFE_DL3_END */
5089	#define DL3_END_ADDR_SFT 4
5090	#define DL3_END_ADDR_MASK 0xfffffff
5091	#define DL3_END_ADDR_MASK_SFT (0xfffffff << 4)
5092
5093	/* AFE_DL3_RCH_MON */
5094	#define DL3_RCH_DATA_SFT 0
5095	#define DL3_RCH_DATA_MASK 0xffffffff
5096	#define DL3_RCH_DATA_MASK_SFT (0xffffffff << 0)
5097
5098	/* AFE_DL3_LCH_MON */
5099	#define DL3_LCH_DATA_SFT 0
5100	#define DL3_LCH_DATA_MASK 0xffffffff
5101	#define DL3_LCH_DATA_MASK_SFT (0xffffffff << 0)
5102
5103	/* AFE_DL3_CON0 */
5104	#define DL3_ON_SFT 28
5105	#define DL3_ON_MASK 0x1
5106	#define DL3_ON_MASK_SFT (0x1 << 28)
5107	#define DL3_ONE_HEART_SEL_SFT 22
5108	#define DL3_ONE_HEART_SEL_MASK 0x3
5109	#define DL3_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5110	#define DL3_MINLEN_SFT 20
5111	#define DL3_MINLEN_MASK 0x3
5112	#define DL3_MINLEN_MASK_SFT (0x3 << 20)
5113	#define DL3_MAXLEN_SFT 16
5114	#define DL3_MAXLEN_MASK 0x3
5115	#define DL3_MAXLEN_MASK_SFT (0x3 << 16)
5116	#define DL3_SEL_DOMAIN_SFT 13
5117	#define DL3_SEL_DOMAIN_MASK 0x7
5118	#define DL3_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5119	#define DL3_SEL_FS_SFT 8
5120	#define DL3_SEL_FS_MASK 0x1f
5121	#define DL3_SEL_FS_MASK_SFT (0x1f << 8)
5122	#define DL3_SW_CLEAR_BUF_EMPTY_SFT 7
5123	#define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1
5124	#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5125	#define DL3_PBUF_SIZE_SFT 5
5126	#define DL3_PBUF_SIZE_MASK 0x3
5127	#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 5)
5128	#define DL3_MONO_SFT 4
5129	#define DL3_MONO_MASK 0x1
5130	#define DL3_MONO_MASK_SFT (0x1 << 4)
5131	#define DL3_NORMAL_MODE_SFT 3
5132	#define DL3_NORMAL_MODE_MASK 0x1
5133	#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 3)
5134	#define DL3_HALIGN_SFT 2
5135	#define DL3_HALIGN_MASK 0x1
5136	#define DL3_HALIGN_MASK_SFT (0x1 << 2)
5137	#define DL3_HD_MODE_SFT 0
5138	#define DL3_HD_MODE_MASK 0x3
5139	#define DL3_HD_MODE_MASK_SFT (0x3 << 0)
5140
5141	/* AFE_DL3_MON0 */
5142	#define RESERVED_01_SFT 20
5143	#define RESERVED_01_MASK 0xfff
5144	#define RESERVED_01_MASK_SFT (0xfff << 20)
5145	#define MEM_REQ_PENDING_SFT 19
5146	#define MEM_REQ_PENDING_MASK 0x1
5147	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5148	#define BUF_EMPTY_SFT 18
5149	#define BUF_EMPTY_MASK 0x1
5150	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5151	#define ENABLE_SYNC_MEM_SFT 17
5152	#define ENABLE_SYNC_MEM_MASK 0x1
5153	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5154	#define ENABLE_SYNC_AGENT_SFT 16
5155	#define ENABLE_SYNC_AGENT_MASK 0x1
5156	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5157	#define RESERVED_02_SFT 6
5158	#define RESERVED_02_MASK 0x3ff
5159	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5160	#define MEM_ADDR_DIFF_SFT 0
5161	#define MEM_ADDR_DIFF_MASK 0x3f
5162	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5163
5164	/* AFE_DL4_BASE_MSB */
5165	#define DL4_BASE__ADDR_MSB_SFT 0
5166	#define DL4_BASE__ADDR_MSB_MASK 0x1ff
5167	#define DL4_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5168
5169	/* AFE_DL4_BASE */
5170	#define DL4_BASE_ADDR_SFT 4
5171	#define DL4_BASE_ADDR_MASK 0xfffffff
5172	#define DL4_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5173
5174	/* AFE_DL4_CUR_MSB */
5175	#define DL4_CUR_PTR_MSB_SFT 0
5176	#define DL4_CUR_PTR_MSB_MASK 0x1ff
5177	#define DL4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5178
5179	/* AFE_DL4_CUR */
5180	#define DL4_CUR_PTR_SFT 0
5181	#define DL4_CUR_PTR_MASK 0xffffffff
5182	#define DL4_CUR_PTR_MASK_SFT (0xffffffff << 0)
5183
5184	/* AFE_DL4_END_MSB */
5185	#define DL4_END_ADDR_MSB_SFT 0
5186	#define DL4_END_ADDR_MSB_MASK 0x1ff
5187	#define DL4_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5188
5189	/* AFE_DL4_END */
5190	#define DL4_END_ADDR_SFT 4
5191	#define DL4_END_ADDR_MASK 0xfffffff
5192	#define DL4_END_ADDR_MASK_SFT (0xfffffff << 4)
5193
5194	/* AFE_DL4_RCH_MON */
5195	#define DL4_RCH_DATA_SFT 0
5196	#define DL4_RCH_DATA_MASK 0xffffffff
5197	#define DL4_RCH_DATA_MASK_SFT (0xffffffff << 0)
5198
5199	/* AFE_DL4_LCH_MON */
5200	#define DL4_LCH_DATA_SFT 0
5201	#define DL4_LCH_DATA_MASK 0xffffffff
5202	#define DL4_LCH_DATA_MASK_SFT (0xffffffff << 0)
5203
5204	/* AFE_DL4_CON0 */
5205	#define DL4_ON_SFT 28
5206	#define DL4_ON_MASK 0x1
5207	#define DL4_ON_MASK_SFT (0x1 << 28)
5208	#define DL4_ONE_HEART_SEL_SFT 22
5209	#define DL4_ONE_HEART_SEL_MASK 0x3
5210	#define DL4_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5211	#define DL4_MINLEN_SFT 20
5212	#define DL4_MINLEN_MASK 0x3
5213	#define DL4_MINLEN_MASK_SFT (0x3 << 20)
5214	#define DL4_MAXLEN_SFT 16
5215	#define DL4_MAXLEN_MASK 0x3
5216	#define DL4_MAXLEN_MASK_SFT (0x3 << 16)
5217	#define DL4_SEL_DOMAIN_SFT 13
5218	#define DL4_SEL_DOMAIN_MASK 0x7
5219	#define DL4_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5220	#define DL4_SEL_FS_SFT 8
5221	#define DL4_SEL_FS_MASK 0x1f
5222	#define DL4_SEL_FS_MASK_SFT (0x1f << 8)
5223	#define DL4_SW_CLEAR_BUF_EMPTY_SFT 7
5224	#define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1
5225	#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5226	#define DL4_PBUF_SIZE_SFT 5
5227	#define DL4_PBUF_SIZE_MASK 0x3
5228	#define DL4_PBUF_SIZE_MASK_SFT (0x3 << 5)
5229	#define DL4_MONO_SFT 4
5230	#define DL4_MONO_MASK 0x1
5231	#define DL4_MONO_MASK_SFT (0x1 << 4)
5232	#define DL4_NORMAL_MODE_SFT 3
5233	#define DL4_NORMAL_MODE_MASK 0x1
5234	#define DL4_NORMAL_MODE_MASK_SFT (0x1 << 3)
5235	#define DL4_HALIGN_SFT 2
5236	#define DL4_HALIGN_MASK 0x1
5237	#define DL4_HALIGN_MASK_SFT (0x1 << 2)
5238	#define DL4_HD_MODE_SFT 0
5239	#define DL4_HD_MODE_MASK 0x3
5240	#define DL4_HD_MODE_MASK_SFT (0x3 << 0)
5241
5242	/* AFE_DL4_MON0 */
5243	#define RESERVED_01_SFT 20
5244	#define RESERVED_01_MASK 0xfff
5245	#define RESERVED_01_MASK_SFT (0xfff << 20)
5246	#define MEM_REQ_PENDING_SFT 19
5247	#define MEM_REQ_PENDING_MASK 0x1
5248	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5249	#define BUF_EMPTY_SFT 18
5250	#define BUF_EMPTY_MASK 0x1
5251	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5252	#define ENABLE_SYNC_MEM_SFT 17
5253	#define ENABLE_SYNC_MEM_MASK 0x1
5254	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5255	#define ENABLE_SYNC_AGENT_SFT 16
5256	#define ENABLE_SYNC_AGENT_MASK 0x1
5257	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5258	#define RESERVED_02_SFT 6
5259	#define RESERVED_02_MASK 0x3ff
5260	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5261	#define MEM_ADDR_DIFF_SFT 0
5262	#define MEM_ADDR_DIFF_MASK 0x3f
5263	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5264
5265	/* AFE_DL5_BASE_MSB */
5266	#define DL5_BASE__ADDR_MSB_SFT 0
5267	#define DL5_BASE__ADDR_MSB_MASK 0x1ff
5268	#define DL5_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5269
5270	/* AFE_DL5_BASE */
5271	#define DL5_BASE_ADDR_SFT 4
5272	#define DL5_BASE_ADDR_MASK 0xfffffff
5273	#define DL5_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5274
5275	/* AFE_DL5_CUR_MSB */
5276	#define DL5_CUR_PTR_MSB_SFT 0
5277	#define DL5_CUR_PTR_MSB_MASK 0x1ff
5278	#define DL5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5279
5280	/* AFE_DL5_CUR */
5281	#define DL5_CUR_PTR_SFT 0
5282	#define DL5_CUR_PTR_MASK 0xffffffff
5283	#define DL5_CUR_PTR_MASK_SFT (0xffffffff << 0)
5284
5285	/* AFE_DL5_END_MSB */
5286	#define DL5_END_ADDR_MSB_SFT 0
5287	#define DL5_END_ADDR_MSB_MASK 0x1ff
5288	#define DL5_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5289
5290	/* AFE_DL5_END */
5291	#define DL5_END_ADDR_SFT 4
5292	#define DL5_END_ADDR_MASK 0xfffffff
5293	#define DL5_END_ADDR_MASK_SFT (0xfffffff << 4)
5294
5295	/* AFE_DL5_RCH_MON */
5296	#define DL5_RCH_DATA_SFT 0
5297	#define DL5_RCH_DATA_MASK 0xffffffff
5298	#define DL5_RCH_DATA_MASK_SFT (0xffffffff << 0)
5299
5300	/* AFE_DL5_LCH_MON */
5301	#define DL5_LCH_DATA_SFT 0
5302	#define DL5_LCH_DATA_MASK 0xffffffff
5303	#define DL5_LCH_DATA_MASK_SFT (0xffffffff << 0)
5304
5305	/* AFE_DL5_CON0 */
5306	#define DL5_ON_SFT 28
5307	#define DL5_ON_MASK 0x1
5308	#define DL5_ON_MASK_SFT (0x1 << 28)
5309	#define DL5_ONE_HEART_SEL_SFT 22
5310	#define DL5_ONE_HEART_SEL_MASK 0x3
5311	#define DL5_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5312	#define DL5_MINLEN_SFT 20
5313	#define DL5_MINLEN_MASK 0x3
5314	#define DL5_MINLEN_MASK_SFT (0x3 << 20)
5315	#define DL5_MAXLEN_SFT 16
5316	#define DL5_MAXLEN_MASK 0x3
5317	#define DL5_MAXLEN_MASK_SFT (0x3 << 16)
5318	#define DL5_SEL_DOMAIN_SFT 13
5319	#define DL5_SEL_DOMAIN_MASK 0x7
5320	#define DL5_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5321	#define DL5_SEL_FS_SFT 8
5322	#define DL5_SEL_FS_MASK 0x1f
5323	#define DL5_SEL_FS_MASK_SFT (0x1f << 8)
5324	#define DL5_SW_CLEAR_BUF_EMPTY_SFT 7
5325	#define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1
5326	#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5327	#define DL5_PBUF_SIZE_SFT 5
5328	#define DL5_PBUF_SIZE_MASK 0x3
5329	#define DL5_PBUF_SIZE_MASK_SFT (0x3 << 5)
5330	#define DL5_MONO_SFT 4
5331	#define DL5_MONO_MASK 0x1
5332	#define DL5_MONO_MASK_SFT (0x1 << 4)
5333	#define DL5_NORMAL_MODE_SFT 3
5334	#define DL5_NORMAL_MODE_MASK 0x1
5335	#define DL5_NORMAL_MODE_MASK_SFT (0x1 << 3)
5336	#define DL5_HALIGN_SFT 2
5337	#define DL5_HALIGN_MASK 0x1
5338	#define DL5_HALIGN_MASK_SFT (0x1 << 2)
5339	#define DL5_HD_MODE_SFT 0
5340	#define DL5_HD_MODE_MASK 0x3
5341	#define DL5_HD_MODE_MASK_SFT (0x3 << 0)
5342
5343	/* AFE_DL5_MON0 */
5344	#define RESERVED_01_SFT 20
5345	#define RESERVED_01_MASK 0xfff
5346	#define RESERVED_01_MASK_SFT (0xfff << 20)
5347	#define MEM_REQ_PENDING_SFT 19
5348	#define MEM_REQ_PENDING_MASK 0x1
5349	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5350	#define BUF_EMPTY_SFT 18
5351	#define BUF_EMPTY_MASK 0x1
5352	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5353	#define ENABLE_SYNC_MEM_SFT 17
5354	#define ENABLE_SYNC_MEM_MASK 0x1
5355	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5356	#define ENABLE_SYNC_AGENT_SFT 16
5357	#define ENABLE_SYNC_AGENT_MASK 0x1
5358	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5359	#define RESERVED_02_SFT 6
5360	#define RESERVED_02_MASK 0x3ff
5361	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5362	#define MEM_ADDR_DIFF_SFT 0
5363	#define MEM_ADDR_DIFF_MASK 0x3f
5364	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5365
5366	/* AFE_DL6_BASE_MSB */
5367	#define DL6_BASE__ADDR_MSB_SFT 0
5368	#define DL6_BASE__ADDR_MSB_MASK 0x1ff
5369	#define DL6_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5370
5371	/* AFE_DL6_BASE */
5372	#define DL6_BASE_ADDR_SFT 4
5373	#define DL6_BASE_ADDR_MASK 0xfffffff
5374	#define DL6_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5375
5376	/* AFE_DL6_CUR_MSB */
5377	#define DL6_CUR_PTR_MSB_SFT 0
5378	#define DL6_CUR_PTR_MSB_MASK 0x1ff
5379	#define DL6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5380
5381	/* AFE_DL6_CUR */
5382	#define DL6_CUR_PTR_SFT 0
5383	#define DL6_CUR_PTR_MASK 0xffffffff
5384	#define DL6_CUR_PTR_MASK_SFT (0xffffffff << 0)
5385
5386	/* AFE_DL6_END_MSB */
5387	#define DL6_END_ADDR_MSB_SFT 0
5388	#define DL6_END_ADDR_MSB_MASK 0x1ff
5389	#define DL6_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5390
5391	/* AFE_DL6_END */
5392	#define DL6_END_ADDR_SFT 4
5393	#define DL6_END_ADDR_MASK 0xfffffff
5394	#define DL6_END_ADDR_MASK_SFT (0xfffffff << 4)
5395
5396	/* AFE_DL6_RCH_MON */
5397	#define DL6_RCH_DATA_SFT 0
5398	#define DL6_RCH_DATA_MASK 0xffffffff
5399	#define DL6_RCH_DATA_MASK_SFT (0xffffffff << 0)
5400
5401	/* AFE_DL6_LCH_MON */
5402	#define DL6_LCH_DATA_SFT 0
5403	#define DL6_LCH_DATA_MASK 0xffffffff
5404	#define DL6_LCH_DATA_MASK_SFT (0xffffffff << 0)
5405
5406	/* AFE_DL6_CON0 */
5407	#define DL6_ON_SFT 28
5408	#define DL6_ON_MASK 0x1
5409	#define DL6_ON_MASK_SFT (0x1 << 28)
5410	#define DL6_ONE_HEART_SEL_SFT 22
5411	#define DL6_ONE_HEART_SEL_MASK 0x3
5412	#define DL6_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5413	#define DL6_MINLEN_SFT 20
5414	#define DL6_MINLEN_MASK 0x3
5415	#define DL6_MINLEN_MASK_SFT (0x3 << 20)
5416	#define DL6_MAXLEN_SFT 16
5417	#define DL6_MAXLEN_MASK 0x3
5418	#define DL6_MAXLEN_MASK_SFT (0x3 << 16)
5419	#define DL6_SEL_DOMAIN_SFT 13
5420	#define DL6_SEL_DOMAIN_MASK 0x7
5421	#define DL6_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5422	#define DL6_SEL_FS_SFT 8
5423	#define DL6_SEL_FS_MASK 0x1f
5424	#define DL6_SEL_FS_MASK_SFT (0x1f << 8)
5425	#define DL6_SW_CLEAR_BUF_EMPTY_SFT 7
5426	#define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1
5427	#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5428	#define DL6_PBUF_SIZE_SFT 5
5429	#define DL6_PBUF_SIZE_MASK 0x3
5430	#define DL6_PBUF_SIZE_MASK_SFT (0x3 << 5)
5431	#define DL6_MONO_SFT 4
5432	#define DL6_MONO_MASK 0x1
5433	#define DL6_MONO_MASK_SFT (0x1 << 4)
5434	#define DL6_NORMAL_MODE_SFT 3
5435	#define DL6_NORMAL_MODE_MASK 0x1
5436	#define DL6_NORMAL_MODE_MASK_SFT (0x1 << 3)
5437	#define DL6_HALIGN_SFT 2
5438	#define DL6_HALIGN_MASK 0x1
5439	#define DL6_HALIGN_MASK_SFT (0x1 << 2)
5440	#define DL6_HD_MODE_SFT 0
5441	#define DL6_HD_MODE_MASK 0x3
5442	#define DL6_HD_MODE_MASK_SFT (0x3 << 0)
5443
5444	/* AFE_DL6_MON0 */
5445	#define RESERVED_01_SFT 20
5446	#define RESERVED_01_MASK 0xfff
5447	#define RESERVED_01_MASK_SFT (0xfff << 20)
5448	#define MEM_REQ_PENDING_SFT 19
5449	#define MEM_REQ_PENDING_MASK 0x1
5450	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5451	#define BUF_EMPTY_SFT 18
5452	#define BUF_EMPTY_MASK 0x1
5453	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5454	#define ENABLE_SYNC_MEM_SFT 17
5455	#define ENABLE_SYNC_MEM_MASK 0x1
5456	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5457	#define ENABLE_SYNC_AGENT_SFT 16
5458	#define ENABLE_SYNC_AGENT_MASK 0x1
5459	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5460	#define RESERVED_02_SFT 6
5461	#define RESERVED_02_MASK 0x3ff
5462	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5463	#define MEM_ADDR_DIFF_SFT 0
5464	#define MEM_ADDR_DIFF_MASK 0x3f
5465	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5466
5467	/* AFE_DL7_BASE_MSB */
5468	#define DL7_BASE__ADDR_MSB_SFT 0
5469	#define DL7_BASE__ADDR_MSB_MASK 0x1ff
5470	#define DL7_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5471
5472	/* AFE_DL7_BASE */
5473	#define DL7_BASE_ADDR_SFT 4
5474	#define DL7_BASE_ADDR_MASK 0xfffffff
5475	#define DL7_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5476
5477	/* AFE_DL7_CUR_MSB */
5478	#define DL7_CUR_PTR_MSB_SFT 0
5479	#define DL7_CUR_PTR_MSB_MASK 0x1ff
5480	#define DL7_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5481
5482	/* AFE_DL7_CUR */
5483	#define DL7_CUR_PTR_SFT 0
5484	#define DL7_CUR_PTR_MASK 0xffffffff
5485	#define DL7_CUR_PTR_MASK_SFT (0xffffffff << 0)
5486
5487	/* AFE_DL7_END_MSB */
5488	#define DL7_END_ADDR_MSB_SFT 0
5489	#define DL7_END_ADDR_MSB_MASK 0x1ff
5490	#define DL7_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5491
5492	/* AFE_DL7_END */
5493	#define DL7_END_ADDR_SFT 4
5494	#define DL7_END_ADDR_MASK 0xfffffff
5495	#define DL7_END_ADDR_MASK_SFT (0xfffffff << 4)
5496
5497	/* AFE_DL7_RCH_MON */
5498	#define DL7_RCH_DATA_SFT 0
5499	#define DL7_RCH_DATA_MASK 0xffffffff
5500	#define DL7_RCH_DATA_MASK_SFT (0xffffffff << 0)
5501
5502	/* AFE_DL7_LCH_MON */
5503	#define DL7_LCH_DATA_SFT 0
5504	#define DL7_LCH_DATA_MASK 0xffffffff
5505	#define DL7_LCH_DATA_MASK_SFT (0xffffffff << 0)
5506
5507	/* AFE_DL7_CON0 */
5508	#define DL7_ON_SFT 28
5509	#define DL7_ON_MASK 0x1
5510	#define DL7_ON_MASK_SFT (0x1 << 28)
5511	#define DL7_ONE_HEART_SEL_SFT 22
5512	#define DL7_ONE_HEART_SEL_MASK 0x3
5513	#define DL7_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5514	#define DL7_MINLEN_SFT 20
5515	#define DL7_MINLEN_MASK 0x3
5516	#define DL7_MINLEN_MASK_SFT (0x3 << 20)
5517	#define DL7_MAXLEN_SFT 16
5518	#define DL7_MAXLEN_MASK 0x3
5519	#define DL7_MAXLEN_MASK_SFT (0x3 << 16)
5520	#define DL7_SEL_DOMAIN_SFT 13
5521	#define DL7_SEL_DOMAIN_MASK 0x7
5522	#define DL7_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5523	#define DL7_SEL_FS_SFT 8
5524	#define DL7_SEL_FS_MASK 0x1f
5525	#define DL7_SEL_FS_MASK_SFT (0x1f << 8)
5526	#define DL7_SW_CLEAR_BUF_EMPTY_SFT 7
5527	#define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1
5528	#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5529	#define DL7_PBUF_SIZE_SFT 5
5530	#define DL7_PBUF_SIZE_MASK 0x3
5531	#define DL7_PBUF_SIZE_MASK_SFT (0x3 << 5)
5532	#define DL7_MONO_SFT 4
5533	#define DL7_MONO_MASK 0x1
5534	#define DL7_MONO_MASK_SFT (0x1 << 4)
5535	#define DL7_NORMAL_MODE_SFT 3
5536	#define DL7_NORMAL_MODE_MASK 0x1
5537	#define DL7_NORMAL_MODE_MASK_SFT (0x1 << 3)
5538	#define DL7_HALIGN_SFT 2
5539	#define DL7_HALIGN_MASK 0x1
5540	#define DL7_HALIGN_MASK_SFT (0x1 << 2)
5541	#define DL7_HD_MODE_SFT 0
5542	#define DL7_HD_MODE_MASK 0x3
5543	#define DL7_HD_MODE_MASK_SFT (0x3 << 0)
5544
5545	/* AFE_DL7_MON0 */
5546	#define RESERVED_01_SFT 20
5547	#define RESERVED_01_MASK 0xfff
5548	#define RESERVED_01_MASK_SFT (0xfff << 20)
5549	#define MEM_REQ_PENDING_SFT 19
5550	#define MEM_REQ_PENDING_MASK 0x1
5551	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5552	#define BUF_EMPTY_SFT 18
5553	#define BUF_EMPTY_MASK 0x1
5554	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5555	#define ENABLE_SYNC_MEM_SFT 17
5556	#define ENABLE_SYNC_MEM_MASK 0x1
5557	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5558	#define ENABLE_SYNC_AGENT_SFT 16
5559	#define ENABLE_SYNC_AGENT_MASK 0x1
5560	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5561	#define RESERVED_02_SFT 6
5562	#define RESERVED_02_MASK 0x3ff
5563	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5564	#define MEM_ADDR_DIFF_SFT 0
5565	#define MEM_ADDR_DIFF_MASK 0x3f
5566	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5567
5568	/* AFE_DL8_BASE_MSB */
5569	#define DL8_BASE__ADDR_MSB_SFT 0
5570	#define DL8_BASE__ADDR_MSB_MASK 0x1ff
5571	#define DL8_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5572
5573	/* AFE_DL8_BASE */
5574	#define DL8_BASE_ADDR_SFT 4
5575	#define DL8_BASE_ADDR_MASK 0xfffffff
5576	#define DL8_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5577
5578	/* AFE_DL8_CUR_MSB */
5579	#define DL8_CUR_PTR_MSB_SFT 0
5580	#define DL8_CUR_PTR_MSB_MASK 0x1ff
5581	#define DL8_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5582
5583	/* AFE_DL8_CUR */
5584	#define DL8_CUR_PTR_SFT 0
5585	#define DL8_CUR_PTR_MASK 0xffffffff
5586	#define DL8_CUR_PTR_MASK_SFT (0xffffffff << 0)
5587
5588	/* AFE_DL8_END_MSB */
5589	#define DL8_END_ADDR_MSB_SFT 0
5590	#define DL8_END_ADDR_MSB_MASK 0x1ff
5591	#define DL8_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5592
5593	/* AFE_DL8_END */
5594	#define DL8_END_ADDR_SFT 4
5595	#define DL8_END_ADDR_MASK 0xfffffff
5596	#define DL8_END_ADDR_MASK_SFT (0xfffffff << 4)
5597
5598	/* AFE_DL8_RCH_MON */
5599	#define DL8_RCH_DATA_SFT 0
5600	#define DL8_RCH_DATA_MASK 0xffffffff
5601	#define DL8_RCH_DATA_MASK_SFT (0xffffffff << 0)
5602
5603	/* AFE_DL8_LCH_MON */
5604	#define DL8_LCH_DATA_SFT 0
5605	#define DL8_LCH_DATA_MASK 0xffffffff
5606	#define DL8_LCH_DATA_MASK_SFT (0xffffffff << 0)
5607
5608	/* AFE_DL8_CON0 */
5609	#define DL8_ON_SFT 28
5610	#define DL8_ON_MASK 0x1
5611	#define DL8_ON_MASK_SFT (0x1 << 28)
5612	#define DL8_ONE_HEART_SEL_SFT 22
5613	#define DL8_ONE_HEART_SEL_MASK 0x3
5614	#define DL8_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5615	#define DL8_MINLEN_SFT 20
5616	#define DL8_MINLEN_MASK 0x3
5617	#define DL8_MINLEN_MASK_SFT (0x3 << 20)
5618	#define DL8_MAXLEN_SFT 16
5619	#define DL8_MAXLEN_MASK 0x3
5620	#define DL8_MAXLEN_MASK_SFT (0x3 << 16)
5621	#define DL8_SEL_DOMAIN_SFT 13
5622	#define DL8_SEL_DOMAIN_MASK 0x7
5623	#define DL8_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5624	#define DL8_SEL_FS_SFT 8
5625	#define DL8_SEL_FS_MASK 0x1f
5626	#define DL8_SEL_FS_MASK_SFT (0x1f << 8)
5627	#define DL8_SW_CLEAR_BUF_EMPTY_SFT 7
5628	#define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1
5629	#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5630	#define DL8_PBUF_SIZE_SFT 5
5631	#define DL8_PBUF_SIZE_MASK 0x3
5632	#define DL8_PBUF_SIZE_MASK_SFT (0x3 << 5)
5633	#define DL8_MONO_SFT 4
5634	#define DL8_MONO_MASK 0x1
5635	#define DL8_MONO_MASK_SFT (0x1 << 4)
5636	#define DL8_NORMAL_MODE_SFT 3
5637	#define DL8_NORMAL_MODE_MASK 0x1
5638	#define DL8_NORMAL_MODE_MASK_SFT (0x1 << 3)
5639	#define DL8_HALIGN_SFT 2
5640	#define DL8_HALIGN_MASK 0x1
5641	#define DL8_HALIGN_MASK_SFT (0x1 << 2)
5642	#define DL8_HD_MODE_SFT 0
5643	#define DL8_HD_MODE_MASK 0x3
5644	#define DL8_HD_MODE_MASK_SFT (0x3 << 0)
5645
5646	/* AFE_DL8_MON0 */
5647	#define RESERVED_01_SFT 20
5648	#define RESERVED_01_MASK 0xfff
5649	#define RESERVED_01_MASK_SFT (0xfff << 20)
5650	#define MEM_REQ_PENDING_SFT 19
5651	#define MEM_REQ_PENDING_MASK 0x1
5652	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
5653	#define BUF_EMPTY_SFT 18
5654	#define BUF_EMPTY_MASK 0x1
5655	#define BUF_EMPTY_MASK_SFT (0x1 << 18)
5656	#define ENABLE_SYNC_MEM_SFT 17
5657	#define ENABLE_SYNC_MEM_MASK 0x1
5658	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
5659	#define ENABLE_SYNC_AGENT_SFT 16
5660	#define ENABLE_SYNC_AGENT_MASK 0x1
5661	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
5662	#define RESERVED_02_SFT 6
5663	#define RESERVED_02_MASK 0x3ff
5664	#define RESERVED_02_MASK_SFT (0x3ff << 6)
5665	#define MEM_ADDR_DIFF_SFT 0
5666	#define MEM_ADDR_DIFF_MASK 0x3f
5667	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
5668
5669	/* AFE_DL_24CH_BASE_MSB */
5670	#define DL_24CH_BASE__ADDR_MSB_SFT 0
5671	#define DL_24CH_BASE__ADDR_MSB_MASK 0x1ff
5672	#define DL_24CH_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5673
5674	/* AFE_DL_24CH_BASE */
5675	#define DL_24CH_BASE_ADDR_SFT 4
5676	#define DL_24CH_BASE_ADDR_MASK 0xfffffff
5677	#define DL_24CH_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5678
5679	/* AFE_DL_24CH_CUR_MSB */
5680	#define DL_24CH_CUR_PTR_MSB_SFT 0
5681	#define DL_24CH_CUR_PTR_MSB_MASK 0x1ff
5682	#define DL_24CH_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5683
5684	/* AFE_DL_24CH_CUR */
5685	#define DL_24CH_CUR_PTR_SFT 0
5686	#define DL_24CH_CUR_PTR_MASK 0xffffffff
5687	#define DL_24CH_CUR_PTR_MASK_SFT (0xffffffff << 0)
5688
5689	/* AFE_DL_24CH_END_MSB */
5690	#define DL_24CH_END_ADDR_MSB_SFT 0
5691	#define DL_24CH_END_ADDR_MSB_MASK 0x1ff
5692	#define DL_24CH_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5693
5694	/* AFE_DL_24CH_END */
5695	#define DL_24CH_END_ADDR_SFT 4
5696	#define DL_24CH_END_ADDR_MASK 0xfffffff
5697	#define DL_24CH_END_ADDR_MASK_SFT (0xfffffff << 4)
5698
5699	/* AFE_DL_24CH_CON0 */
5700	#define DL_24CH_ON_SFT 31
5701	#define DL_24CH_ON_MASK 0x1
5702	#define DL_24CH_ON_MASK_SFT (0x1 << 31)
5703	#define DL_24CH_NUM_SFT 24
5704	#define DL_24CH_NUM_MASK 0x3f
5705	#define DL_24CH_NUM_MASK_SFT (0x3f << 24)
5706	#define DL_24CH_ONE_HEART_SEL_SFT 22
5707	#define DL_24CH_ONE_HEART_SEL_MASK 0x3
5708	#define DL_24CH_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5709	#define DL_24CH_MINLEN_SFT 20
5710	#define DL_24CH_MINLEN_MASK 0x3
5711	#define DL_24CH_MINLEN_MASK_SFT (0x3 << 20)
5712	#define DL_24CH_MAXLEN_SFT 16
5713	#define DL_24CH_MAXLEN_MASK 0x3
5714	#define DL_24CH_MAXLEN_MASK_SFT (0x3 << 16)
5715	#define DL_24CH_SEL_DOMAIN_SFT 13
5716	#define DL_24CH_SEL_DOMAIN_MASK 0x7
5717	#define DL_24CH_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5718	#define DL_24CH_SEL_FS_SFT 8
5719	#define DL_24CH_SEL_FS_MASK 0x1f
5720	#define DL_24CH_SEL_FS_MASK_SFT (0x1f << 8)
5721	#define DL_24CH_BUF_EMPTY_CLR_SFT 7
5722	#define DL_24CH_BUF_EMPTY_CLR_MASK 0x1
5723	#define DL_24CH_BUF_EMPTY_CLR_MASK_SFT (0x1 << 7)
5724	#define DL_24CH_PBUF_SIZE_SFT 5
5725	#define DL_24CH_PBUF_SIZE_MASK 0x3
5726	#define DL_24CH_PBUF_SIZE_MASK_SFT (0x3 << 5)
5727	#define DL_24CH_HANG_CLR_SFT 4
5728	#define DL_24CH_HANG_CLR_MASK 0x1
5729	#define DL_24CH_HANG_CLR_MASK_SFT (0x1 << 4)
5730	#define DL_24CH_NORMAL_MODE_SFT 3
5731	#define DL_24CH_NORMAL_MODE_MASK 0x1
5732	#define DL_24CH_NORMAL_MODE_MASK_SFT (0x1 << 3)
5733	#define DL_24CH_HALIGN_SFT 2
5734	#define DL_24CH_HALIGN_MASK 0x1
5735	#define DL_24CH_HALIGN_MASK_SFT (0x1 << 2)
5736	#define DL_24CH_HD_MODE_SFT 0
5737	#define DL_24CH_HD_MODE_MASK 0x3
5738	#define DL_24CH_HD_MODE_MASK_SFT (0x3 << 0)
5739
5740	/* AFE_DL23_BASE_MSB */
5741	#define DL23_BASE__ADDR_MSB_SFT 0
5742	#define DL23_BASE__ADDR_MSB_MASK 0x1ff
5743	#define DL23_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5744
5745	/* AFE_DL23_BASE */
5746	#define DL23_BASE_ADDR_SFT 4
5747	#define DL23_BASE_ADDR_MASK 0xfffffff
5748	#define DL23_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5749
5750	/* AFE_DL23_CUR_MSB */
5751	#define DL23_CUR_PTR_MSB_SFT 0
5752	#define DL23_CUR_PTR_MSB_MASK 0x1ff
5753	#define DL23_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5754
5755	/* AFE_DL23_CUR */
5756	#define DL23_CUR_PTR_SFT 0
5757	#define DL23_CUR_PTR_MASK 0xffffffff
5758	#define DL23_CUR_PTR_MASK_SFT (0xffffffff << 0)
5759
5760	/* AFE_DL23_END_MSB */
5761	#define DL23_END_ADDR_MSB_SFT 0
5762	#define DL23_END_ADDR_MSB_MASK 0x1ff
5763	#define DL23_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5764
5765	/* AFE_DL23_END */
5766	#define DL23_END_ADDR_SFT 4
5767	#define DL23_END_ADDR_MASK 0xfffffff
5768	#define DL23_END_ADDR_MASK_SFT (0xfffffff << 4)
5769
5770	/* AFE_DL23_RCH_MON */
5771	#define DL23_RCH_DATA_SFT 0
5772	#define DL23_RCH_DATA_MASK 0xffffffff
5773	#define DL23_RCH_DATA_MASK_SFT (0xffffffff << 0)
5774
5775	/* AFE_DL23_LCH_MON */
5776	#define DL23_LCH_DATA_SFT 0
5777	#define DL23_LCH_DATA_MASK 0xffffffff
5778	#define DL23_LCH_DATA_MASK_SFT (0xffffffff << 0)
5779
5780	/* AFE_DL23_CON0 */
5781	#define DL23_ON_SFT 28
5782	#define DL23_ON_MASK 0x1
5783	#define DL23_ON_MASK_SFT (0x1 << 28)
5784	#define DL23_ONE_HEART_SEL_SFT 22
5785	#define DL23_ONE_HEART_SEL_MASK 0x3
5786	#define DL23_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5787	#define DL23_MINLEN_SFT 20
5788	#define DL23_MINLEN_MASK 0x3
5789	#define DL23_MINLEN_MASK_SFT (0x3 << 20)
5790	#define DL23_MAXLEN_SFT 16
5791	#define DL23_MAXLEN_MASK 0x3
5792	#define DL23_MAXLEN_MASK_SFT (0x3 << 16)
5793	#define DL23_SEL_DOMAIN_SFT 13
5794	#define DL23_SEL_DOMAIN_MASK 0x7
5795	#define DL23_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5796	#define DL23_SEL_FS_SFT 8
5797	#define DL23_SEL_FS_MASK 0x1f
5798	#define DL23_SEL_FS_MASK_SFT (0x1f << 8)
5799	#define DL23_SW_CLEAR_BUF_EMPTY_SFT 7
5800	#define DL23_SW_CLEAR_BUF_EMPTY_MASK 0x1
5801	#define DL23_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5802	#define DL23_PBUF_SIZE_SFT 5
5803	#define DL23_PBUF_SIZE_MASK 0x3
5804	#define DL23_PBUF_SIZE_MASK_SFT (0x3 << 5)
5805	#define DL23_MONO_SFT 4
5806	#define DL23_MONO_MASK 0x1
5807	#define DL23_MONO_MASK_SFT (0x1 << 4)
5808	#define DL23_NORMAL_MODE_SFT 3
5809	#define DL23_NORMAL_MODE_MASK 0x1
5810	#define DL23_NORMAL_MODE_MASK_SFT (0x1 << 3)
5811	#define DL23_HALIGN_SFT 2
5812	#define DL23_HALIGN_MASK 0x1
5813	#define DL23_HALIGN_MASK_SFT (0x1 << 2)
5814	#define DL23_HD_MODE_SFT 0
5815	#define DL23_HD_MODE_MASK 0x3
5816	#define DL23_HD_MODE_MASK_SFT (0x3 << 0)
5817
5818	/* AFE_DL24_BASE_MSB */
5819	#define DL24_BASE__ADDR_MSB_SFT 0
5820	#define DL24_BASE__ADDR_MSB_MASK 0x1ff
5821	#define DL24_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5822
5823	/* AFE_DL24_BASE */
5824	#define DL24_BASE_ADDR_SFT 4
5825	#define DL24_BASE_ADDR_MASK 0xfffffff
5826	#define DL24_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5827
5828	/* AFE_DL24_CUR_MSB */
5829	#define DL24_CUR_PTR_MSB_SFT 0
5830	#define DL24_CUR_PTR_MSB_MASK 0x1ff
5831	#define DL24_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5832
5833	/* AFE_DL24_CUR */
5834	#define DL24_CUR_PTR_SFT 0
5835	#define DL24_CUR_PTR_MASK 0xffffffff
5836	#define DL24_CUR_PTR_MASK_SFT (0xffffffff << 0)
5837
5838	/* AFE_DL24_END_MSB */
5839	#define DL24_END_ADDR_MSB_SFT 0
5840	#define DL24_END_ADDR_MSB_MASK 0x1ff
5841	#define DL24_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5842
5843	/* AFE_DL24_END */
5844	#define DL24_END_ADDR_SFT 4
5845	#define DL24_END_ADDR_MASK 0xfffffff
5846	#define DL24_END_ADDR_MASK_SFT (0xfffffff << 4)
5847
5848	/* AFE_DL24_RCH_MON */
5849	#define DL24_RCH_DATA_SFT 0
5850	#define DL24_RCH_DATA_MASK 0xffffffff
5851	#define DL24_RCH_DATA_MASK_SFT (0xffffffff << 0)
5852
5853	/* AFE_DL24_LCH_MON */
5854	#define DL24_LCH_DATA_SFT 0
5855	#define DL24_LCH_DATA_MASK 0xffffffff
5856	#define DL24_LCH_DATA_MASK_SFT (0xffffffff << 0)
5857
5858	/* AFE_DL24_CON0 */
5859	#define DL24_ON_SFT 28
5860	#define DL24_ON_MASK 0x1
5861	#define DL24_ON_MASK_SFT (0x1 << 28)
5862	#define DL24_ONE_HEART_SEL_SFT 22
5863	#define DL24_ONE_HEART_SEL_MASK 0x3
5864	#define DL24_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5865	#define DL24_MINLEN_SFT 20
5866	#define DL24_MINLEN_MASK 0x3
5867	#define DL24_MINLEN_MASK_SFT (0x3 << 20)
5868	#define DL24_MAXLEN_SFT 16
5869	#define DL24_MAXLEN_MASK 0x3
5870	#define DL24_MAXLEN_MASK_SFT (0x3 << 16)
5871	#define DL24_SEL_DOMAIN_SFT 13
5872	#define DL24_SEL_DOMAIN_MASK 0x7
5873	#define DL24_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5874	#define DL24_SEL_FS_SFT 8
5875	#define DL24_SEL_FS_MASK 0x1f
5876	#define DL24_SEL_FS_MASK_SFT (0x1f << 8)
5877	#define DL24_SW_CLEAR_BUF_EMPTY_SFT 7
5878	#define DL24_SW_CLEAR_BUF_EMPTY_MASK 0x1
5879	#define DL24_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5880	#define DL24_PBUF_SIZE_SFT 5
5881	#define DL24_PBUF_SIZE_MASK 0x3
5882	#define DL24_PBUF_SIZE_MASK_SFT (0x3 << 5)
5883	#define DL24_MONO_SFT 4
5884	#define DL24_MONO_MASK 0x1
5885	#define DL24_MONO_MASK_SFT (0x1 << 4)
5886	#define DL24_NORMAL_MODE_SFT 3
5887	#define DL24_NORMAL_MODE_MASK 0x1
5888	#define DL24_NORMAL_MODE_MASK_SFT (0x1 << 3)
5889	#define DL24_HALIGN_SFT 2
5890	#define DL24_HALIGN_MASK 0x1
5891	#define DL24_HALIGN_MASK_SFT (0x1 << 2)
5892	#define DL24_HD_MODE_SFT 0
5893	#define DL24_HD_MODE_MASK 0x3
5894	#define DL24_HD_MODE_MASK_SFT (0x3 << 0)
5895
5896	/* AFE_DL25_BASE_MSB */
5897	#define DL25_BASE__ADDR_MSB_SFT 0
5898	#define DL25_BASE__ADDR_MSB_MASK 0x1ff
5899	#define DL25_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
5900
5901	/* AFE_DL25_BASE */
5902	#define DL25_BASE_ADDR_SFT 4
5903	#define DL25_BASE_ADDR_MASK 0xfffffff
5904	#define DL25_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5905
5906	/* AFE_DL25_CUR_MSB */
5907	#define DL25_CUR_PTR_MSB_SFT 0
5908	#define DL25_CUR_PTR_MSB_MASK 0x1ff
5909	#define DL25_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5910
5911	/* AFE_DL25_CUR */
5912	#define DL25_CUR_PTR_SFT 0
5913	#define DL25_CUR_PTR_MASK 0xffffffff
5914	#define DL25_CUR_PTR_MASK_SFT (0xffffffff << 0)
5915
5916	/* AFE_DL25_END_MSB */
5917	#define DL25_END_ADDR_MSB_SFT 0
5918	#define DL25_END_ADDR_MSB_MASK 0x1ff
5919	#define DL25_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5920
5921	/* AFE_DL25_END */
5922	#define DL25_END_ADDR_SFT 4
5923	#define DL25_END_ADDR_MASK 0xfffffff
5924	#define DL25_END_ADDR_MASK_SFT (0xfffffff << 4)
5925
5926	/* AFE_DL25_RCH_MON */
5927	#define DL25_RCH_DATA_SFT 0
5928	#define DL25_RCH_DATA_MASK 0xffffffff
5929	#define DL25_RCH_DATA_MASK_SFT (0xffffffff << 0)
5930
5931	/* AFE_DL25_LCH_MON */
5932	#define DL25_LCH_DATA_SFT 0
5933	#define DL25_LCH_DATA_MASK 0xffffffff
5934	#define DL25_LCH_DATA_MASK_SFT (0xffffffff << 0)
5935
5936	/* AFE_DL25_CON0 */
5937	#define DL25_ON_SFT 28
5938	#define DL25_ON_MASK 0x1
5939	#define DL25_ON_MASK_SFT (0x1 << 28)
5940	#define DL25_ONE_HEART_SEL_SFT 22
5941	#define DL25_ONE_HEART_SEL_MASK 0x3
5942	#define DL25_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
5943	#define DL25_MINLEN_SFT 20
5944	#define DL25_MINLEN_MASK 0x3
5945	#define DL25_MINLEN_MASK_SFT (0x3 << 20)
5946	#define DL25_MAXLEN_SFT 16
5947	#define DL25_MAXLEN_MASK 0x3
5948	#define DL25_MAXLEN_MASK_SFT (0x3 << 16)
5949	#define DL25_SEL_DOMAIN_SFT 13
5950	#define DL25_SEL_DOMAIN_MASK 0x7
5951	#define DL25_SEL_DOMAIN_MASK_SFT (0x7 << 13)
5952	#define DL25_SEL_FS_SFT 8
5953	#define DL25_SEL_FS_MASK 0x1f
5954	#define DL25_SEL_FS_MASK_SFT (0x1f << 8)
5955	#define DL25_SW_CLEAR_BUF_EMPTY_SFT 7
5956	#define DL25_SW_CLEAR_BUF_EMPTY_MASK 0x1
5957	#define DL25_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
5958	#define DL25_PBUF_SIZE_SFT 5
5959	#define DL25_PBUF_SIZE_MASK 0x3
5960	#define DL25_PBUF_SIZE_MASK_SFT (0x3 << 5)
5961	#define DL25_MONO_SFT 4
5962	#define DL25_MONO_MASK 0x1
5963	#define DL25_MONO_MASK_SFT (0x1 << 4)
5964	#define DL25_NORMAL_MODE_SFT 3
5965	#define DL25_NORMAL_MODE_MASK 0x1
5966	#define DL25_NORMAL_MODE_MASK_SFT (0x1 << 3)
5967	#define DL25_HALIGN_SFT 2
5968	#define DL25_HALIGN_MASK 0x1
5969	#define DL25_HALIGN_MASK_SFT (0x1 << 2)
5970	#define DL25_HD_MODE_SFT 0
5971	#define DL25_HD_MODE_MASK 0x3
5972	#define DL25_HD_MODE_MASK_SFT (0x3 << 0)
5973
5974	/* AFE_VUL0_BASE_MSB */
5975	#define VUL0_BASE_ADDR_MSB_SFT 0
5976	#define VUL0_BASE_ADDR_MSB_MASK 0x1ff
5977	#define VUL0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
5978
5979	/* AFE_VUL0_BASE */
5980	#define VUL0_BASE_ADDR_SFT 4
5981	#define VUL0_BASE_ADDR_MASK 0xfffffff
5982	#define VUL0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
5983
5984	/* AFE_VUL0_CUR_MSB */
5985	#define VUL0_CUR_PTR_MSB_SFT 0
5986	#define VUL0_CUR_PTR_MSB_MASK 0x1ff
5987	#define VUL0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
5988
5989	/* AFE_VUL0_CUR */
5990	#define VUL0_CUR_PTR_SFT 0
5991	#define VUL0_CUR_PTR_MASK 0xffffffff
5992	#define VUL0_CUR_PTR_MASK_SFT (0xffffffff << 0)
5993
5994	/* AFE_VUL0_END_MSB */
5995	#define VUL0_END_ADDR_MSB_SFT 0
5996	#define VUL0_END_ADDR_MSB_MASK 0x1ff
5997	#define VUL0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
5998
5999	/* AFE_VUL0_END */
6000	#define VUL0_END_ADDR_SFT 4
6001	#define VUL0_END_ADDR_MASK 0xfffffff
6002	#define VUL0_END_ADDR_MASK_SFT (0xfffffff << 4)
6003
6004	/* AFE_VUL0_RCH_MON */
6005	#define VUL0_RCH_DATA_SFT 0
6006	#define VUL0_RCH_DATA_MASK 0xffffffff
6007	#define VUL0_RCH_DATA_MASK_SFT (0xffffffff << 0)
6008
6009	/* AFE_VUL0_LCH_MON */
6010	#define VUL0_LCH_DATA_SFT 0
6011	#define VUL0_LCH_DATA_MASK 0xffffffff
6012	#define VUL0_LCH_DATA_MASK_SFT (0xffffffff << 0)
6013
6014	/* AFE_VUL0_CON0 */
6015	#define VUL0_ON_SFT 28
6016	#define VUL0_ON_MASK 0x1
6017	#define VUL0_ON_MASK_SFT (0x1 << 28)
6018	#define VUL0_MINLEN_SFT 20
6019	#define VUL0_MINLEN_MASK 0x3
6020	#define VUL0_MINLEN_MASK_SFT (0x3 << 20)
6021	#define VUL0_MAXLEN_SFT 16
6022	#define VUL0_MAXLEN_MASK 0x3
6023	#define VUL0_MAXLEN_MASK_SFT (0x3 << 16)
6024	#define VUL0_SEL_DOMAIN_SFT 13
6025	#define VUL0_SEL_DOMAIN_MASK 0x7
6026	#define VUL0_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6027	#define VUL0_SEL_FS_SFT 8
6028	#define VUL0_SEL_FS_MASK 0x1f
6029	#define VUL0_SEL_FS_MASK_SFT (0x1f << 8)
6030	#define VUL0_SW_CLEAR_BUF_FULL_SFT 7
6031	#define VUL0_SW_CLEAR_BUF_FULL_MASK 0x1
6032	#define VUL0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6033	#define VUL0_WR_SIGN_SFT 6
6034	#define VUL0_WR_SIGN_MASK 0x1
6035	#define VUL0_WR_SIGN_MASK_SFT (0x1 << 6)
6036	#define VUL0_R_MONO_SFT 5
6037	#define VUL0_R_MONO_MASK 0x1
6038	#define VUL0_R_MONO_MASK_SFT (0x1 << 5)
6039	#define VUL0_MONO_SFT 4
6040	#define VUL0_MONO_MASK 0x1
6041	#define VUL0_MONO_MASK_SFT (0x1 << 4)
6042	#define VUL0_NORMAL_MODE_SFT 3
6043	#define VUL0_NORMAL_MODE_MASK 0x1
6044	#define VUL0_NORMAL_MODE_MASK_SFT (0x1 << 3)
6045	#define VUL0_HALIGN_SFT 2
6046	#define VUL0_HALIGN_MASK 0x1
6047	#define VUL0_HALIGN_MASK_SFT (0x1 << 2)
6048	#define VUL0_HD_MODE_SFT 0
6049	#define VUL0_HD_MODE_MASK 0x3
6050	#define VUL0_HD_MODE_MASK_SFT (0x3 << 0)
6051
6052	/* AFE_VUL1_BASE_MSB */
6053	#define VUL1_BASE_ADDR_MSB_SFT 0
6054	#define VUL1_BASE_ADDR_MSB_MASK 0x1ff
6055	#define VUL1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6056
6057	/* AFE_VUL1_BASE */
6058	#define VUL1_BASE_ADDR_SFT 4
6059	#define VUL1_BASE_ADDR_MASK 0xfffffff
6060	#define VUL1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6061
6062	/* AFE_VUL1_CUR_MSB */
6063	#define VUL1_CUR_PTR_MSB_SFT 0
6064	#define VUL1_CUR_PTR_MSB_MASK 0x1ff
6065	#define VUL1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6066
6067	/* AFE_VUL1_CUR */
6068	#define VUL1_CUR_PTR_SFT 0
6069	#define VUL1_CUR_PTR_MASK 0xffffffff
6070	#define VUL1_CUR_PTR_MASK_SFT (0xffffffff << 0)
6071
6072	/* AFE_VUL1_END_MSB */
6073	#define VUL1_END_ADDR_MSB_SFT 0
6074	#define VUL1_END_ADDR_MSB_MASK 0x1ff
6075	#define VUL1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6076
6077	/* AFE_VUL1_END */
6078	#define VUL1_END_ADDR_SFT 4
6079	#define VUL1_END_ADDR_MASK 0xfffffff
6080	#define VUL1_END_ADDR_MASK_SFT (0xfffffff << 4)
6081
6082	/* AFE_VUL1_RCH_MON */
6083	#define VUL1_RCH_DATA_SFT 0
6084	#define VUL1_RCH_DATA_MASK 0xffffffff
6085	#define VUL1_RCH_DATA_MASK_SFT (0xffffffff << 0)
6086
6087	/* AFE_VUL1_LCH_MON */
6088	#define VUL1_LCH_DATA_SFT 0
6089	#define VUL1_LCH_DATA_MASK 0xffffffff
6090	#define VUL1_LCH_DATA_MASK_SFT (0xffffffff << 0)
6091
6092	/* AFE_VUL1_CON0 */
6093	#define VUL1_ON_SFT 28
6094	#define VUL1_ON_MASK 0x1
6095	#define VUL1_ON_MASK_SFT (0x1 << 28)
6096	#define VUL1_MINLEN_SFT 20
6097	#define VUL1_MINLEN_MASK 0x3
6098	#define VUL1_MINLEN_MASK_SFT (0x3 << 20)
6099	#define VUL1_MAXLEN_SFT 16
6100	#define VUL1_MAXLEN_MASK 0x3
6101	#define VUL1_MAXLEN_MASK_SFT (0x3 << 16)
6102	#define VUL1_SEL_DOMAIN_SFT 13
6103	#define VUL1_SEL_DOMAIN_MASK 0x7
6104	#define VUL1_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6105	#define VUL1_SEL_FS_SFT 8
6106	#define VUL1_SEL_FS_MASK 0x1f
6107	#define VUL1_SEL_FS_MASK_SFT (0x1f << 8)
6108	#define VUL1_SW_CLEAR_BUF_FULL_SFT 7
6109	#define VUL1_SW_CLEAR_BUF_FULL_MASK 0x1
6110	#define VUL1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6111	#define VUL1_WR_SIGN_SFT 6
6112	#define VUL1_WR_SIGN_MASK 0x1
6113	#define VUL1_WR_SIGN_MASK_SFT (0x1 << 6)
6114	#define VUL1_R_MONO_SFT 5
6115	#define VUL1_R_MONO_MASK 0x1
6116	#define VUL1_R_MONO_MASK_SFT (0x1 << 5)
6117	#define VUL1_MONO_SFT 4
6118	#define VUL1_MONO_MASK 0x1
6119	#define VUL1_MONO_MASK_SFT (0x1 << 4)
6120	#define VUL1_NORMAL_MODE_SFT 3
6121	#define VUL1_NORMAL_MODE_MASK 0x1
6122	#define VUL1_NORMAL_MODE_MASK_SFT (0x1 << 3)
6123	#define VUL1_HALIGN_SFT 2
6124	#define VUL1_HALIGN_MASK 0x1
6125	#define VUL1_HALIGN_MASK_SFT (0x1 << 2)
6126	#define VUL1_HD_MODE_SFT 0
6127	#define VUL1_HD_MODE_MASK 0x3
6128	#define VUL1_HD_MODE_MASK_SFT (0x3 << 0)
6129
6130	/* AFE_VUL1_MON0 */
6131	#define MEM_HW_WEN_SFT 20
6132	#define MEM_HW_WEN_MASK 0xf
6133	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6134	#define MEM_REQ_PENDING_SFT 19
6135	#define MEM_REQ_PENDING_MASK 0x1
6136	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6137	#define BUF_FULL_SFT 18
6138	#define BUF_FULL_MASK 0x1
6139	#define BUF_FULL_MASK_SFT (0x1 << 18)
6140	#define ENABLE_SYNC_MEM_SFT 17
6141	#define ENABLE_SYNC_MEM_MASK 0x1
6142	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6143	#define ENABLE_SYNC_AGENT_SFT 16
6144	#define ENABLE_SYNC_AGENT_MASK 0x1
6145	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6146	#define RESERVED_02_SFT 6
6147	#define RESERVED_02_MASK 0x3ff
6148	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6149	#define MEM_ADDR_DIFF_SFT 0
6150	#define MEM_ADDR_DIFF_MASK 0x3f
6151	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6152
6153	/* AFE_VUL2_BASE_MSB */
6154	#define VUL2_BASE_ADDR_MSB_SFT 0
6155	#define VUL2_BASE_ADDR_MSB_MASK 0x1ff
6156	#define VUL2_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6157
6158	/* AFE_VUL2_BASE */
6159	#define VUL2_BASE_ADDR_SFT 4
6160	#define VUL2_BASE_ADDR_MASK 0xfffffff
6161	#define VUL2_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6162
6163	/* AFE_VUL2_CUR_MSB */
6164	#define VUL2_CUR_PTR_MSB_SFT 0
6165	#define VUL2_CUR_PTR_MSB_MASK 0x1ff
6166	#define VUL2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6167
6168	/* AFE_VUL2_CUR */
6169	#define VUL2_CUR_PTR_SFT 0
6170	#define VUL2_CUR_PTR_MASK 0xffffffff
6171	#define VUL2_CUR_PTR_MASK_SFT (0xffffffff << 0)
6172
6173	/* AFE_VUL2_END_MSB */
6174	#define VUL2_END_ADDR_MSB_SFT 0
6175	#define VUL2_END_ADDR_MSB_MASK 0x1ff
6176	#define VUL2_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6177
6178	/* AFE_VUL2_END */
6179	#define VUL2_END_ADDR_SFT 4
6180	#define VUL2_END_ADDR_MASK 0xfffffff
6181	#define VUL2_END_ADDR_MASK_SFT (0xfffffff << 4)
6182
6183	/* AFE_VUL2_RCH_MON */
6184	#define VUL2_RCH_DATA_SFT 0
6185	#define VUL2_RCH_DATA_MASK 0xffffffff
6186	#define VUL2_RCH_DATA_MASK_SFT (0xffffffff << 0)
6187
6188	/* AFE_VUL2_LCH_MON */
6189	#define VUL2_LCH_DATA_SFT 0
6190	#define VUL2_LCH_DATA_MASK 0xffffffff
6191	#define VUL2_LCH_DATA_MASK_SFT (0xffffffff << 0)
6192
6193	/* AFE_VUL2_CON0 */
6194	#define VUL2_ON_SFT 28
6195	#define VUL2_ON_MASK 0x1
6196	#define VUL2_ON_MASK_SFT (0x1 << 28)
6197	#define VUL2_MINLEN_SFT 20
6198	#define VUL2_MINLEN_MASK 0x3
6199	#define VUL2_MINLEN_MASK_SFT (0x3 << 20)
6200	#define VUL2_MAXLEN_SFT 16
6201	#define VUL2_MAXLEN_MASK 0x3
6202	#define VUL2_MAXLEN_MASK_SFT (0x3 << 16)
6203	#define VUL2_SEL_DOMAIN_SFT 13
6204	#define VUL2_SEL_DOMAIN_MASK 0x7
6205	#define VUL2_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6206	#define VUL2_SEL_FS_SFT 8
6207	#define VUL2_SEL_FS_MASK 0x1f
6208	#define VUL2_SEL_FS_MASK_SFT (0x1f << 8)
6209	#define VUL2_SW_CLEAR_BUF_FULL_SFT 7
6210	#define VUL2_SW_CLEAR_BUF_FULL_MASK 0x1
6211	#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6212	#define VUL2_WR_SIGN_SFT 6
6213	#define VUL2_WR_SIGN_MASK 0x1
6214	#define VUL2_WR_SIGN_MASK_SFT (0x1 << 6)
6215	#define VUL2_R_MONO_SFT 5
6216	#define VUL2_R_MONO_MASK 0x1
6217	#define VUL2_R_MONO_MASK_SFT (0x1 << 5)
6218	#define VUL2_MONO_SFT 4
6219	#define VUL2_MONO_MASK 0x1
6220	#define VUL2_MONO_MASK_SFT (0x1 << 4)
6221	#define VUL2_NORMAL_MODE_SFT 3
6222	#define VUL2_NORMAL_MODE_MASK 0x1
6223	#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 3)
6224	#define VUL2_HALIGN_SFT 2
6225	#define VUL2_HALIGN_MASK 0x1
6226	#define VUL2_HALIGN_MASK_SFT (0x1 << 2)
6227	#define VUL2_HD_MODE_SFT 0
6228	#define VUL2_HD_MODE_MASK 0x3
6229	#define VUL2_HD_MODE_MASK_SFT (0x3 << 0)
6230
6231	/* AFE_VUL2_MON0 */
6232	#define MEM_HW_WEN_SFT 20
6233	#define MEM_HW_WEN_MASK 0xf
6234	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6235	#define MEM_REQ_PENDING_SFT 19
6236	#define MEM_REQ_PENDING_MASK 0x1
6237	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6238	#define BUF_FULL_SFT 18
6239	#define BUF_FULL_MASK 0x1
6240	#define BUF_FULL_MASK_SFT (0x1 << 18)
6241	#define ENABLE_SYNC_MEM_SFT 17
6242	#define ENABLE_SYNC_MEM_MASK 0x1
6243	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6244	#define ENABLE_SYNC_AGENT_SFT 16
6245	#define ENABLE_SYNC_AGENT_MASK 0x1
6246	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6247	#define RESERVED_02_SFT 6
6248	#define RESERVED_02_MASK 0x3ff
6249	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6250	#define MEM_ADDR_DIFF_SFT 0
6251	#define MEM_ADDR_DIFF_MASK 0x3f
6252	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6253
6254	/* AFE_VUL3_BASE_MSB */
6255	#define VUL3_BASE_ADDR_MSB_SFT 0
6256	#define VUL3_BASE_ADDR_MSB_MASK 0x1ff
6257	#define VUL3_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6258
6259	/* AFE_VUL3_BASE */
6260	#define VUL3_BASE_ADDR_SFT 4
6261	#define VUL3_BASE_ADDR_MASK 0xfffffff
6262	#define VUL3_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6263
6264	/* AFE_VUL3_CUR_MSB */
6265	#define VUL3_CUR_PTR_MSB_SFT 0
6266	#define VUL3_CUR_PTR_MSB_MASK 0x1ff
6267	#define VUL3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6268
6269	/* AFE_VUL3_CUR */
6270	#define VUL3_CUR_PTR_SFT 0
6271	#define VUL3_CUR_PTR_MASK 0xffffffff
6272	#define VUL3_CUR_PTR_MASK_SFT (0xffffffff << 0)
6273
6274	/* AFE_VUL3_END_MSB */
6275	#define VUL3_END_ADDR_MSB_SFT 0
6276	#define VUL3_END_ADDR_MSB_MASK 0x1ff
6277	#define VUL3_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6278
6279	/* AFE_VUL3_END */
6280	#define VUL3_END_ADDR_SFT 4
6281	#define VUL3_END_ADDR_MASK 0xfffffff
6282	#define VUL3_END_ADDR_MASK_SFT (0xfffffff << 4)
6283
6284	/* AFE_VUL3_RCH_MON */
6285	#define VUL3_RCH_DATA_SFT 0
6286	#define VUL3_RCH_DATA_MASK 0xffffffff
6287	#define VUL3_RCH_DATA_MASK_SFT (0xffffffff << 0)
6288
6289	/* AFE_VUL3_LCH_MON */
6290	#define VUL3_LCH_DATA_SFT 0
6291	#define VUL3_LCH_DATA_MASK 0xffffffff
6292	#define VUL3_LCH_DATA_MASK_SFT (0xffffffff << 0)
6293
6294	/* AFE_VUL3_CON0 */
6295	#define VUL3_ON_SFT 28
6296	#define VUL3_ON_MASK 0x1
6297	#define VUL3_ON_MASK_SFT (0x1 << 28)
6298	#define VUL3_MINLEN_SFT 20
6299	#define VUL3_MINLEN_MASK 0x3
6300	#define VUL3_MINLEN_MASK_SFT (0x3 << 20)
6301	#define VUL3_MAXLEN_SFT 16
6302	#define VUL3_MAXLEN_MASK 0x3
6303	#define VUL3_MAXLEN_MASK_SFT (0x3 << 16)
6304	#define VUL3_SEL_DOMAIN_SFT 13
6305	#define VUL3_SEL_DOMAIN_MASK 0x7
6306	#define VUL3_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6307	#define VUL3_SEL_FS_SFT 8
6308	#define VUL3_SEL_FS_MASK 0x1f
6309	#define VUL3_SEL_FS_MASK_SFT (0x1f << 8)
6310	#define VUL3_SW_CLEAR_BUF_FULL_SFT 7
6311	#define VUL3_SW_CLEAR_BUF_FULL_MASK 0x1
6312	#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6313	#define VUL3_WR_SIGN_SFT 6
6314	#define VUL3_WR_SIGN_MASK 0x1
6315	#define VUL3_WR_SIGN_MASK_SFT (0x1 << 6)
6316	#define VUL3_R_MONO_SFT 5
6317	#define VUL3_R_MONO_MASK 0x1
6318	#define VUL3_R_MONO_MASK_SFT (0x1 << 5)
6319	#define VUL3_MONO_SFT 4
6320	#define VUL3_MONO_MASK 0x1
6321	#define VUL3_MONO_MASK_SFT (0x1 << 4)
6322	#define VUL3_NORMAL_MODE_SFT 3
6323	#define VUL3_NORMAL_MODE_MASK 0x1
6324	#define VUL3_NORMAL_MODE_MASK_SFT (0x1 << 3)
6325	#define VUL3_HALIGN_SFT 2
6326	#define VUL3_HALIGN_MASK 0x1
6327	#define VUL3_HALIGN_MASK_SFT (0x1 << 2)
6328	#define VUL3_HD_MODE_SFT 0
6329	#define VUL3_HD_MODE_MASK 0x3
6330	#define VUL3_HD_MODE_MASK_SFT (0x3 << 0)
6331
6332	/* AFE_VUL3_MON0 */
6333	#define MEM_HW_WEN_SFT 20
6334	#define MEM_HW_WEN_MASK 0xf
6335	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6336	#define MEM_REQ_PENDING_SFT 19
6337	#define MEM_REQ_PENDING_MASK 0x1
6338	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6339	#define BUF_FULL_SFT 18
6340	#define BUF_FULL_MASK 0x1
6341	#define BUF_FULL_MASK_SFT (0x1 << 18)
6342	#define ENABLE_SYNC_MEM_SFT 17
6343	#define ENABLE_SYNC_MEM_MASK 0x1
6344	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6345	#define ENABLE_SYNC_AGENT_SFT 16
6346	#define ENABLE_SYNC_AGENT_MASK 0x1
6347	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6348	#define RESERVED_02_SFT 6
6349	#define RESERVED_02_MASK 0x3ff
6350	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6351	#define MEM_ADDR_DIFF_SFT 0
6352	#define MEM_ADDR_DIFF_MASK 0x3f
6353	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6354
6355	/* AFE_VUL4_BASE_MSB */
6356	#define VUL4_BASE_ADDR_MSB_SFT 0
6357	#define VUL4_BASE_ADDR_MSB_MASK 0x1ff
6358	#define VUL4_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6359
6360	/* AFE_VUL4_BASE */
6361	#define VUL4_BASE_ADDR_SFT 4
6362	#define VUL4_BASE_ADDR_MASK 0xfffffff
6363	#define VUL4_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6364
6365	/* AFE_VUL4_CUR_MSB */
6366	#define VUL4_CUR_PTR_MSB_SFT 0
6367	#define VUL4_CUR_PTR_MSB_MASK 0x1ff
6368	#define VUL4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6369
6370	/* AFE_VUL4_CUR */
6371	#define VUL4_CUR_PTR_SFT 0
6372	#define VUL4_CUR_PTR_MASK 0xffffffff
6373	#define VUL4_CUR_PTR_MASK_SFT (0xffffffff << 0)
6374
6375	/* AFE_VUL4_END_MSB */
6376	#define VUL4_END_ADDR_MSB_SFT 0
6377	#define VUL4_END_ADDR_MSB_MASK 0x1ff
6378	#define VUL4_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6379
6380	/* AFE_VUL4_END */
6381	#define VUL4_END_ADDR_SFT 4
6382	#define VUL4_END_ADDR_MASK 0xfffffff
6383	#define VUL4_END_ADDR_MASK_SFT (0xfffffff << 4)
6384
6385	/* AFE_VUL4_RCH_MON */
6386	#define VUL4_RCH_DATA_SFT 0
6387	#define VUL4_RCH_DATA_MASK 0xffffffff
6388	#define VUL4_RCH_DATA_MASK_SFT (0xffffffff << 0)
6389
6390	/* AFE_VUL4_LCH_MON */
6391	#define VUL4_LCH_DATA_SFT 0
6392	#define VUL4_LCH_DATA_MASK 0xffffffff
6393	#define VUL4_LCH_DATA_MASK_SFT (0xffffffff << 0)
6394
6395	/* AFE_VUL4_CON0 */
6396	#define VUL4_ON_SFT 28
6397	#define VUL4_ON_MASK 0x1
6398	#define VUL4_ON_MASK_SFT (0x1 << 28)
6399	#define VUL4_MINLEN_SFT 20
6400	#define VUL4_MINLEN_MASK 0x3
6401	#define VUL4_MINLEN_MASK_SFT (0x3 << 20)
6402	#define VUL4_MAXLEN_SFT 16
6403	#define VUL4_MAXLEN_MASK 0x3
6404	#define VUL4_MAXLEN_MASK_SFT (0x3 << 16)
6405	#define VUL4_SEL_DOMAIN_SFT 13
6406	#define VUL4_SEL_DOMAIN_MASK 0x7
6407	#define VUL4_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6408	#define VUL4_SEL_FS_SFT 8
6409	#define VUL4_SEL_FS_MASK 0x1f
6410	#define VUL4_SEL_FS_MASK_SFT (0x1f << 8)
6411	#define VUL4_SW_CLEAR_BUF_FULL_SFT 7
6412	#define VUL4_SW_CLEAR_BUF_FULL_MASK 0x1
6413	#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6414	#define VUL4_WR_SIGN_SFT 6
6415	#define VUL4_WR_SIGN_MASK 0x1
6416	#define VUL4_WR_SIGN_MASK_SFT (0x1 << 6)
6417	#define VUL4_R_MONO_SFT 5
6418	#define VUL4_R_MONO_MASK 0x1
6419	#define VUL4_R_MONO_MASK_SFT (0x1 << 5)
6420	#define VUL4_MONO_SFT 4
6421	#define VUL4_MONO_MASK 0x1
6422	#define VUL4_MONO_MASK_SFT (0x1 << 4)
6423	#define VUL4_NORMAL_MODE_SFT 3
6424	#define VUL4_NORMAL_MODE_MASK 0x1
6425	#define VUL4_NORMAL_MODE_MASK_SFT (0x1 << 3)
6426	#define VUL4_HALIGN_SFT 2
6427	#define VUL4_HALIGN_MASK 0x1
6428	#define VUL4_HALIGN_MASK_SFT (0x1 << 2)
6429	#define VUL4_HD_MODE_SFT 0
6430	#define VUL4_HD_MODE_MASK 0x3
6431	#define VUL4_HD_MODE_MASK_SFT (0x3 << 0)
6432
6433	/* AFE_VUL4_MON0 */
6434	#define MEM_HW_WEN_SFT 20
6435	#define MEM_HW_WEN_MASK 0xf
6436	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6437	#define MEM_REQ_PENDING_SFT 19
6438	#define MEM_REQ_PENDING_MASK 0x1
6439	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6440	#define BUF_FULL_SFT 18
6441	#define BUF_FULL_MASK 0x1
6442	#define BUF_FULL_MASK_SFT (0x1 << 18)
6443	#define ENABLE_SYNC_MEM_SFT 17
6444	#define ENABLE_SYNC_MEM_MASK 0x1
6445	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6446	#define ENABLE_SYNC_AGENT_SFT 16
6447	#define ENABLE_SYNC_AGENT_MASK 0x1
6448	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6449	#define RESERVED_02_SFT 6
6450	#define RESERVED_02_MASK 0x3ff
6451	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6452	#define MEM_ADDR_DIFF_SFT 0
6453	#define MEM_ADDR_DIFF_MASK 0x3f
6454	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6455
6456	/* AFE_VUL5_BASE_MSB */
6457	#define VUL5_BASE_ADDR_MSB_SFT 0
6458	#define VUL5_BASE_ADDR_MSB_MASK 0x1ff
6459	#define VUL5_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6460
6461	/* AFE_VUL5_BASE */
6462	#define VUL5_BASE_ADDR_SFT 4
6463	#define VUL5_BASE_ADDR_MASK 0xfffffff
6464	#define VUL5_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6465
6466	/* AFE_VUL5_CUR_MSB */
6467	#define VUL5_CUR_PTR_MSB_SFT 0
6468	#define VUL5_CUR_PTR_MSB_MASK 0x1ff
6469	#define VUL5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6470
6471	/* AFE_VUL5_CUR */
6472	#define VUL5_CUR_PTR_SFT 0
6473	#define VUL5_CUR_PTR_MASK 0xffffffff
6474	#define VUL5_CUR_PTR_MASK_SFT (0xffffffff << 0)
6475
6476	/* AFE_VUL5_END_MSB */
6477	#define VUL5_END_ADDR_MSB_SFT 0
6478	#define VUL5_END_ADDR_MSB_MASK 0x1ff
6479	#define VUL5_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6480
6481	/* AFE_VUL5_END */
6482	#define VUL5_END_ADDR_SFT 4
6483	#define VUL5_END_ADDR_MASK 0xfffffff
6484	#define VUL5_END_ADDR_MASK_SFT (0xfffffff << 4)
6485
6486	/* AFE_VUL5_RCH_MON */
6487	#define VUL5_RCH_DATA_SFT 0
6488	#define VUL5_RCH_DATA_MASK 0xffffffff
6489	#define VUL5_RCH_DATA_MASK_SFT (0xffffffff << 0)
6490
6491	/* AFE_VUL5_LCH_MON */
6492	#define VUL5_LCH_DATA_SFT 0
6493	#define VUL5_LCH_DATA_MASK 0xffffffff
6494	#define VUL5_LCH_DATA_MASK_SFT (0xffffffff << 0)
6495
6496	/* AFE_VUL5_CON0 */
6497	#define VUL5_ON_SFT 28
6498	#define VUL5_ON_MASK 0x1
6499	#define VUL5_ON_MASK_SFT (0x1 << 28)
6500	#define VUL5_MINLEN_SFT 20
6501	#define VUL5_MINLEN_MASK 0x3
6502	#define VUL5_MINLEN_MASK_SFT (0x3 << 20)
6503	#define VUL5_MAXLEN_SFT 16
6504	#define VUL5_MAXLEN_MASK 0x3
6505	#define VUL5_MAXLEN_MASK_SFT (0x3 << 16)
6506	#define VUL5_SEL_DOMAIN_SFT 13
6507	#define VUL5_SEL_DOMAIN_MASK 0x7
6508	#define VUL5_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6509	#define VUL5_SEL_FS_SFT 8
6510	#define VUL5_SEL_FS_MASK 0x1f
6511	#define VUL5_SEL_FS_MASK_SFT (0x1f << 8)
6512	#define VUL5_SW_CLEAR_BUF_FULL_SFT 7
6513	#define VUL5_SW_CLEAR_BUF_FULL_MASK 0x1
6514	#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6515	#define VUL5_WR_SIGN_SFT 6
6516	#define VUL5_WR_SIGN_MASK 0x1
6517	#define VUL5_WR_SIGN_MASK_SFT (0x1 << 6)
6518	#define VUL5_R_MONO_SFT 5
6519	#define VUL5_R_MONO_MASK 0x1
6520	#define VUL5_R_MONO_MASK_SFT (0x1 << 5)
6521	#define VUL5_MONO_SFT 4
6522	#define VUL5_MONO_MASK 0x1
6523	#define VUL5_MONO_MASK_SFT (0x1 << 4)
6524	#define VUL5_NORMAL_MODE_SFT 3
6525	#define VUL5_NORMAL_MODE_MASK 0x1
6526	#define VUL5_NORMAL_MODE_MASK_SFT (0x1 << 3)
6527	#define VUL5_HALIGN_SFT 2
6528	#define VUL5_HALIGN_MASK 0x1
6529	#define VUL5_HALIGN_MASK_SFT (0x1 << 2)
6530	#define VUL5_HD_MODE_SFT 0
6531	#define VUL5_HD_MODE_MASK 0x3
6532	#define VUL5_HD_MODE_MASK_SFT (0x3 << 0)
6533
6534	/* AFE_VUL5_MON0 */
6535	#define MEM_HW_WEN_SFT 20
6536	#define MEM_HW_WEN_MASK 0xf
6537	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6538	#define MEM_REQ_PENDING_SFT 19
6539	#define MEM_REQ_PENDING_MASK 0x1
6540	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6541	#define BUF_FULL_SFT 18
6542	#define BUF_FULL_MASK 0x1
6543	#define BUF_FULL_MASK_SFT (0x1 << 18)
6544	#define ENABLE_SYNC_MEM_SFT 17
6545	#define ENABLE_SYNC_MEM_MASK 0x1
6546	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6547	#define ENABLE_SYNC_AGENT_SFT 16
6548	#define ENABLE_SYNC_AGENT_MASK 0x1
6549	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6550	#define RESERVED_02_SFT 6
6551	#define RESERVED_02_MASK 0x3ff
6552	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6553	#define MEM_ADDR_DIFF_SFT 0
6554	#define MEM_ADDR_DIFF_MASK 0x3f
6555	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6556
6557	/* AFE_VUL6_BASE_MSB */
6558	#define VUL6_BASE_ADDR_MSB_SFT 0
6559	#define VUL6_BASE_ADDR_MSB_MASK 0x1ff
6560	#define VUL6_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6561
6562	/* AFE_VUL6_BASE */
6563	#define VUL6_BASE_ADDR_SFT 4
6564	#define VUL6_BASE_ADDR_MASK 0xfffffff
6565	#define VUL6_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6566
6567	/* AFE_VUL6_CUR_MSB */
6568	#define VUL6_CUR_PTR_MSB_SFT 0
6569	#define VUL6_CUR_PTR_MSB_MASK 0x1ff
6570	#define VUL6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6571
6572	/* AFE_VUL6_CUR */
6573	#define VUL6_CUR_PTR_SFT 0
6574	#define VUL6_CUR_PTR_MASK 0xffffffff
6575	#define VUL6_CUR_PTR_MASK_SFT (0xffffffff << 0)
6576
6577	/* AFE_VUL6_END_MSB */
6578	#define VUL6_END_ADDR_MSB_SFT 0
6579	#define VUL6_END_ADDR_MSB_MASK 0x1ff
6580	#define VUL6_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6581
6582	/* AFE_VUL6_END */
6583	#define VUL6_END_ADDR_SFT 4
6584	#define VUL6_END_ADDR_MASK 0xfffffff
6585	#define VUL6_END_ADDR_MASK_SFT (0xfffffff << 4)
6586
6587	/* AFE_VUL6_RCH_MON */
6588	#define VUL6_RCH_DATA_SFT 0
6589	#define VUL6_RCH_DATA_MASK 0xffffffff
6590	#define VUL6_RCH_DATA_MASK_SFT (0xffffffff << 0)
6591
6592	/* AFE_VUL6_LCH_MON */
6593	#define VUL6_LCH_DATA_SFT 0
6594	#define VUL6_LCH_DATA_MASK 0xffffffff
6595	#define VUL6_LCH_DATA_MASK_SFT (0xffffffff << 0)
6596
6597	/* AFE_VUL6_CON0 */
6598	#define VUL6_ON_SFT 28
6599	#define VUL6_ON_MASK 0x1
6600	#define VUL6_ON_MASK_SFT (0x1 << 28)
6601	#define VUL6_MINLEN_SFT 20
6602	#define VUL6_MINLEN_MASK 0x3
6603	#define VUL6_MINLEN_MASK_SFT (0x3 << 20)
6604	#define VUL6_MAXLEN_SFT 16
6605	#define VUL6_MAXLEN_MASK 0x3
6606	#define VUL6_MAXLEN_MASK_SFT (0x3 << 16)
6607	#define VUL6_SEL_DOMAIN_SFT 13
6608	#define VUL6_SEL_DOMAIN_MASK 0x7
6609	#define VUL6_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6610	#define VUL6_SEL_FS_SFT 8
6611	#define VUL6_SEL_FS_MASK 0x1f
6612	#define VUL6_SEL_FS_MASK_SFT (0x1f << 8)
6613	#define VUL6_SW_CLEAR_BUF_FULL_SFT 7
6614	#define VUL6_SW_CLEAR_BUF_FULL_MASK 0x1
6615	#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6616	#define VUL6_WR_SIGN_SFT 6
6617	#define VUL6_WR_SIGN_MASK 0x1
6618	#define VUL6_WR_SIGN_MASK_SFT (0x1 << 6)
6619	#define VUL6_R_MONO_SFT 5
6620	#define VUL6_R_MONO_MASK 0x1
6621	#define VUL6_R_MONO_MASK_SFT (0x1 << 5)
6622	#define VUL6_MONO_SFT 4
6623	#define VUL6_MONO_MASK 0x1
6624	#define VUL6_MONO_MASK_SFT (0x1 << 4)
6625	#define VUL6_NORMAL_MODE_SFT 3
6626	#define VUL6_NORMAL_MODE_MASK 0x1
6627	#define VUL6_NORMAL_MODE_MASK_SFT (0x1 << 3)
6628	#define VUL6_HALIGN_SFT 2
6629	#define VUL6_HALIGN_MASK 0x1
6630	#define VUL6_HALIGN_MASK_SFT (0x1 << 2)
6631	#define VUL6_HD_MODE_SFT 0
6632	#define VUL6_HD_MODE_MASK 0x3
6633	#define VUL6_HD_MODE_MASK_SFT (0x3 << 0)
6634
6635	/* AFE_VUL6_MON0 */
6636	#define MEM_HW_WEN_SFT 20
6637	#define MEM_HW_WEN_MASK 0xf
6638	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6639	#define MEM_REQ_PENDING_SFT 19
6640	#define MEM_REQ_PENDING_MASK 0x1
6641	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6642	#define BUF_FULL_SFT 18
6643	#define BUF_FULL_MASK 0x1
6644	#define BUF_FULL_MASK_SFT (0x1 << 18)
6645	#define ENABLE_SYNC_MEM_SFT 17
6646	#define ENABLE_SYNC_MEM_MASK 0x1
6647	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6648	#define ENABLE_SYNC_AGENT_SFT 16
6649	#define ENABLE_SYNC_AGENT_MASK 0x1
6650	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6651	#define RESERVED_02_SFT 6
6652	#define RESERVED_02_MASK 0x3ff
6653	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6654	#define MEM_ADDR_DIFF_SFT 0
6655	#define MEM_ADDR_DIFF_MASK 0x3f
6656	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6657
6658	/* AFE_VUL7_BASE_MSB */
6659	#define VUL7_BASE_ADDR_MSB_SFT 0
6660	#define VUL7_BASE_ADDR_MSB_MASK 0x1ff
6661	#define VUL7_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6662
6663	/* AFE_VUL7_BASE */
6664	#define VUL7_BASE_ADDR_SFT 4
6665	#define VUL7_BASE_ADDR_MASK 0xfffffff
6666	#define VUL7_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6667
6668	/* AFE_VUL7_CUR_MSB */
6669	#define VUL7_CUR_PTR_MSB_SFT 0
6670	#define VUL7_CUR_PTR_MSB_MASK 0x1ff
6671	#define VUL7_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6672
6673	/* AFE_VUL7_CUR */
6674	#define VUL7_CUR_PTR_SFT 0
6675	#define VUL7_CUR_PTR_MASK 0xffffffff
6676	#define VUL7_CUR_PTR_MASK_SFT (0xffffffff << 0)
6677
6678	/* AFE_VUL7_END_MSB */
6679	#define VUL7_END_ADDR_MSB_SFT 0
6680	#define VUL7_END_ADDR_MSB_MASK 0x1ff
6681	#define VUL7_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6682
6683	/* AFE_VUL7_END */
6684	#define VUL7_END_ADDR_SFT 4
6685	#define VUL7_END_ADDR_MASK 0xfffffff
6686	#define VUL7_END_ADDR_MASK_SFT (0xfffffff << 4)
6687
6688	/* AFE_VUL7_RCH_MON */
6689	#define VUL7_RCH_DATA_SFT 0
6690	#define VUL7_RCH_DATA_MASK 0xffffffff
6691	#define VUL7_RCH_DATA_MASK_SFT (0xffffffff << 0)
6692
6693	/* AFE_VUL7_LCH_MON */
6694	#define VUL7_LCH_DATA_SFT 0
6695	#define VUL7_LCH_DATA_MASK 0xffffffff
6696	#define VUL7_LCH_DATA_MASK_SFT (0xffffffff << 0)
6697
6698	/* AFE_VUL7_CON0 */
6699	#define VUL7_ON_SFT 28
6700	#define VUL7_ON_MASK 0x1
6701	#define VUL7_ON_MASK_SFT (0x1 << 28)
6702	#define VUL7_MINLEN_SFT 20
6703	#define VUL7_MINLEN_MASK 0x3
6704	#define VUL7_MINLEN_MASK_SFT (0x3 << 20)
6705	#define VUL7_MAXLEN_SFT 16
6706	#define VUL7_MAXLEN_MASK 0x3
6707	#define VUL7_MAXLEN_MASK_SFT (0x3 << 16)
6708	#define VUL7_SEL_DOMAIN_SFT 13
6709	#define VUL7_SEL_DOMAIN_MASK 0x7
6710	#define VUL7_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6711	#define VUL7_SEL_FS_SFT 8
6712	#define VUL7_SEL_FS_MASK 0x1f
6713	#define VUL7_SEL_FS_MASK_SFT (0x1f << 8)
6714	#define VUL7_SW_CLEAR_BUF_FULL_SFT 7
6715	#define VUL7_SW_CLEAR_BUF_FULL_MASK 0x1
6716	#define VUL7_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6717	#define VUL7_WR_SIGN_SFT 6
6718	#define VUL7_WR_SIGN_MASK 0x1
6719	#define VUL7_WR_SIGN_MASK_SFT (0x1 << 6)
6720	#define VUL7_R_MONO_SFT 5
6721	#define VUL7_R_MONO_MASK 0x1
6722	#define VUL7_R_MONO_MASK_SFT (0x1 << 5)
6723	#define VUL7_MONO_SFT 4
6724	#define VUL7_MONO_MASK 0x1
6725	#define VUL7_MONO_MASK_SFT (0x1 << 4)
6726	#define VUL7_NORMAL_MODE_SFT 3
6727	#define VUL7_NORMAL_MODE_MASK 0x1
6728	#define VUL7_NORMAL_MODE_MASK_SFT (0x1 << 3)
6729	#define VUL7_HALIGN_SFT 2
6730	#define VUL7_HALIGN_MASK 0x1
6731	#define VUL7_HALIGN_MASK_SFT (0x1 << 2)
6732	#define VUL7_HD_MODE_SFT 0
6733	#define VUL7_HD_MODE_MASK 0x3
6734	#define VUL7_HD_MODE_MASK_SFT (0x3 << 0)
6735
6736	/* AFE_VUL7_MON0 */
6737	#define MEM_HW_WEN_SFT 20
6738	#define MEM_HW_WEN_MASK 0xf
6739	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6740	#define MEM_REQ_PENDING_SFT 19
6741	#define MEM_REQ_PENDING_MASK 0x1
6742	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6743	#define BUF_FULL_SFT 18
6744	#define BUF_FULL_MASK 0x1
6745	#define BUF_FULL_MASK_SFT (0x1 << 18)
6746	#define ENABLE_SYNC_MEM_SFT 17
6747	#define ENABLE_SYNC_MEM_MASK 0x1
6748	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6749	#define ENABLE_SYNC_AGENT_SFT 16
6750	#define ENABLE_SYNC_AGENT_MASK 0x1
6751	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6752	#define RESERVED_02_SFT 6
6753	#define RESERVED_02_MASK 0x3ff
6754	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6755	#define MEM_ADDR_DIFF_SFT 0
6756	#define MEM_ADDR_DIFF_MASK 0x3f
6757	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6758
6759	/* AFE_VUL8_BASE_MSB */
6760	#define VUL8_BASE_ADDR_MSB_SFT 0
6761	#define VUL8_BASE_ADDR_MSB_MASK 0x1ff
6762	#define VUL8_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6763
6764	/* AFE_VUL8_BASE */
6765	#define VUL8_BASE_ADDR_SFT 4
6766	#define VUL8_BASE_ADDR_MASK 0xfffffff
6767	#define VUL8_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6768
6769	/* AFE_VUL8_CUR_MSB */
6770	#define VUL8_CUR_PTR_MSB_SFT 0
6771	#define VUL8_CUR_PTR_MSB_MASK 0x1ff
6772	#define VUL8_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6773
6774	/* AFE_VUL8_CUR */
6775	#define VUL8_CUR_PTR_SFT 0
6776	#define VUL8_CUR_PTR_MASK 0xffffffff
6777	#define VUL8_CUR_PTR_MASK_SFT (0xffffffff << 0)
6778
6779	/* AFE_VUL8_END_MSB */
6780	#define VUL8_END_ADDR_MSB_SFT 0
6781	#define VUL8_END_ADDR_MSB_MASK 0x1ff
6782	#define VUL8_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6783
6784	/* AFE_VUL8_END */
6785	#define VUL8_END_ADDR_SFT 4
6786	#define VUL8_END_ADDR_MASK 0xfffffff
6787	#define VUL8_END_ADDR_MASK_SFT (0xfffffff << 4)
6788
6789	/* AFE_VUL8_RCH_MON */
6790	#define VUL8_RCH_DATA_SFT 0
6791	#define VUL8_RCH_DATA_MASK 0xffffffff
6792	#define VUL8_RCH_DATA_MASK_SFT (0xffffffff << 0)
6793
6794	/* AFE_VUL8_LCH_MON */
6795	#define VUL8_LCH_DATA_SFT 0
6796	#define VUL8_LCH_DATA_MASK 0xffffffff
6797	#define VUL8_LCH_DATA_MASK_SFT (0xffffffff << 0)
6798
6799	/* AFE_VUL8_CON0 */
6800	#define VUL8_ON_SFT 28
6801	#define VUL8_ON_MASK 0x1
6802	#define VUL8_ON_MASK_SFT (0x1 << 28)
6803	#define VUL8_MINLEN_SFT 20
6804	#define VUL8_MINLEN_MASK 0x3
6805	#define VUL8_MINLEN_MASK_SFT (0x3 << 20)
6806	#define VUL8_MAXLEN_SFT 16
6807	#define VUL8_MAXLEN_MASK 0x3
6808	#define VUL8_MAXLEN_MASK_SFT (0x3 << 16)
6809	#define VUL8_SEL_DOMAIN_SFT 13
6810	#define VUL8_SEL_DOMAIN_MASK 0x7
6811	#define VUL8_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6812	#define VUL8_SEL_FS_SFT 8
6813	#define VUL8_SEL_FS_MASK 0x1f
6814	#define VUL8_SEL_FS_MASK_SFT (0x1f << 8)
6815	#define VUL8_SW_CLEAR_BUF_FULL_SFT 7
6816	#define VUL8_SW_CLEAR_BUF_FULL_MASK 0x1
6817	#define VUL8_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6818	#define VUL8_WR_SIGN_SFT 6
6819	#define VUL8_WR_SIGN_MASK 0x1
6820	#define VUL8_WR_SIGN_MASK_SFT (0x1 << 6)
6821	#define VUL8_R_MONO_SFT 5
6822	#define VUL8_R_MONO_MASK 0x1
6823	#define VUL8_R_MONO_MASK_SFT (0x1 << 5)
6824	#define VUL8_MONO_SFT 4
6825	#define VUL8_MONO_MASK 0x1
6826	#define VUL8_MONO_MASK_SFT (0x1 << 4)
6827	#define VUL8_NORMAL_MODE_SFT 3
6828	#define VUL8_NORMAL_MODE_MASK 0x1
6829	#define VUL8_NORMAL_MODE_MASK_SFT (0x1 << 3)
6830	#define VUL8_HALIGN_SFT 2
6831	#define VUL8_HALIGN_MASK 0x1
6832	#define VUL8_HALIGN_MASK_SFT (0x1 << 2)
6833	#define VUL8_HD_MODE_SFT 0
6834	#define VUL8_HD_MODE_MASK 0x3
6835	#define VUL8_HD_MODE_MASK_SFT (0x3 << 0)
6836
6837	/* AFE_VUL8_MON0 */
6838	#define MEM_HW_WEN_SFT 20
6839	#define MEM_HW_WEN_MASK 0xf
6840	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6841	#define MEM_REQ_PENDING_SFT 19
6842	#define MEM_REQ_PENDING_MASK 0x1
6843	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6844	#define BUF_FULL_SFT 18
6845	#define BUF_FULL_MASK 0x1
6846	#define BUF_FULL_MASK_SFT (0x1 << 18)
6847	#define ENABLE_SYNC_MEM_SFT 17
6848	#define ENABLE_SYNC_MEM_MASK 0x1
6849	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6850	#define ENABLE_SYNC_AGENT_SFT 16
6851	#define ENABLE_SYNC_AGENT_MASK 0x1
6852	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6853	#define RESERVED_02_SFT 6
6854	#define RESERVED_02_MASK 0x3ff
6855	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6856	#define MEM_ADDR_DIFF_SFT 0
6857	#define MEM_ADDR_DIFF_MASK 0x3f
6858	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6859
6860	/* AFE_VUL9_BASE_MSB */
6861	#define VUL9_BASE_ADDR_MSB_SFT 0
6862	#define VUL9_BASE_ADDR_MSB_MASK 0x1ff
6863	#define VUL9_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6864
6865	/* AFE_VUL9_BASE */
6866	#define VUL9_BASE_ADDR_SFT 4
6867	#define VUL9_BASE_ADDR_MASK 0xfffffff
6868	#define VUL9_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6869
6870	/* AFE_VUL9_CUR_MSB */
6871	#define VUL9_CUR_PTR_MSB_SFT 0
6872	#define VUL9_CUR_PTR_MSB_MASK 0x1ff
6873	#define VUL9_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6874
6875	/* AFE_VUL9_CUR */
6876	#define VUL9_CUR_PTR_SFT 0
6877	#define VUL9_CUR_PTR_MASK 0xffffffff
6878	#define VUL9_CUR_PTR_MASK_SFT (0xffffffff << 0)
6879
6880	/* AFE_VUL9_END_MSB */
6881	#define VUL9_END_ADDR_MSB_SFT 0
6882	#define VUL9_END_ADDR_MSB_MASK 0x1ff
6883	#define VUL9_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6884
6885	/* AFE_VUL9_END */
6886	#define VUL9_END_ADDR_SFT 4
6887	#define VUL9_END_ADDR_MASK 0xfffffff
6888	#define VUL9_END_ADDR_MASK_SFT (0xfffffff << 4)
6889
6890	/* AFE_VUL9_RCH_MON */
6891	#define VUL9_RCH_DATA_SFT 0
6892	#define VUL9_RCH_DATA_MASK 0xffffffff
6893	#define VUL9_RCH_DATA_MASK_SFT (0xffffffff << 0)
6894
6895	/* AFE_VUL9_LCH_MON */
6896	#define VUL9_LCH_DATA_SFT 0
6897	#define VUL9_LCH_DATA_MASK 0xffffffff
6898	#define VUL9_LCH_DATA_MASK_SFT (0xffffffff << 0)
6899
6900	/* AFE_VUL9_CON0 */
6901	#define VUL9_ON_SFT 28
6902	#define VUL9_ON_MASK 0x1
6903	#define VUL9_ON_MASK_SFT (0x1 << 28)
6904	#define VUL9_MINLEN_SFT 20
6905	#define VUL9_MINLEN_MASK 0x3
6906	#define VUL9_MINLEN_MASK_SFT (0x3 << 20)
6907	#define VUL9_MAXLEN_SFT 16
6908	#define VUL9_MAXLEN_MASK 0x3
6909	#define VUL9_MAXLEN_MASK_SFT (0x3 << 16)
6910	#define VUL9_SEL_DOMAIN_SFT 13
6911	#define VUL9_SEL_DOMAIN_MASK 0x7
6912	#define VUL9_SEL_DOMAIN_MASK_SFT (0x7 << 13)
6913	#define VUL9_SEL_FS_SFT 8
6914	#define VUL9_SEL_FS_MASK 0x1f
6915	#define VUL9_SEL_FS_MASK_SFT (0x1f << 8)
6916	#define VUL9_SW_CLEAR_BUF_FULL_SFT 7
6917	#define VUL9_SW_CLEAR_BUF_FULL_MASK 0x1
6918	#define VUL9_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
6919	#define VUL9_WR_SIGN_SFT 6
6920	#define VUL9_WR_SIGN_MASK 0x1
6921	#define VUL9_WR_SIGN_MASK_SFT (0x1 << 6)
6922	#define VUL9_R_MONO_SFT 5
6923	#define VUL9_R_MONO_MASK 0x1
6924	#define VUL9_R_MONO_MASK_SFT (0x1 << 5)
6925	#define VUL9_MONO_SFT 4
6926	#define VUL9_MONO_MASK 0x1
6927	#define VUL9_MONO_MASK_SFT (0x1 << 4)
6928	#define VUL9_NORMAL_MODE_SFT 3
6929	#define VUL9_NORMAL_MODE_MASK 0x1
6930	#define VUL9_NORMAL_MODE_MASK_SFT (0x1 << 3)
6931	#define VUL9_HALIGN_SFT 2
6932	#define VUL9_HALIGN_MASK 0x1
6933	#define VUL9_HALIGN_MASK_SFT (0x1 << 2)
6934	#define VUL9_HD_MODE_SFT 0
6935	#define VUL9_HD_MODE_MASK 0x3
6936	#define VUL9_HD_MODE_MASK_SFT (0x3 << 0)
6937
6938	/* AFE_VUL9_MON0 */
6939	#define MEM_HW_WEN_SFT 20
6940	#define MEM_HW_WEN_MASK 0xf
6941	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
6942	#define MEM_REQ_PENDING_SFT 19
6943	#define MEM_REQ_PENDING_MASK 0x1
6944	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
6945	#define BUF_FULL_SFT 18
6946	#define BUF_FULL_MASK 0x1
6947	#define BUF_FULL_MASK_SFT (0x1 << 18)
6948	#define ENABLE_SYNC_MEM_SFT 17
6949	#define ENABLE_SYNC_MEM_MASK 0x1
6950	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
6951	#define ENABLE_SYNC_AGENT_SFT 16
6952	#define ENABLE_SYNC_AGENT_MASK 0x1
6953	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
6954	#define RESERVED_02_SFT 6
6955	#define RESERVED_02_MASK 0x3ff
6956	#define RESERVED_02_MASK_SFT (0x3ff << 6)
6957	#define MEM_ADDR_DIFF_SFT 0
6958	#define MEM_ADDR_DIFF_MASK 0x3f
6959	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
6960
6961	/* AFE_VUL10_BASE_MSB */
6962	#define VUL10_BASE_ADDR_MSB_SFT 0
6963	#define VUL10_BASE_ADDR_MSB_MASK 0x1ff
6964	#define VUL10_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
6965
6966	/* AFE_VUL10_BASE */
6967	#define VUL10_BASE_ADDR_SFT 4
6968	#define VUL10_BASE_ADDR_MASK 0xfffffff
6969	#define VUL10_BASE_ADDR_MASK_SFT (0xfffffff << 4)
6970
6971	/* AFE_VUL10_CUR_MSB */
6972	#define VUL10_CUR_PTR_MSB_SFT 0
6973	#define VUL10_CUR_PTR_MSB_MASK 0x1ff
6974	#define VUL10_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
6975
6976	/* AFE_VUL10_CUR */
6977	#define VUL10_CUR_PTR_SFT 0
6978	#define VUL10_CUR_PTR_MASK 0xffffffff
6979	#define VUL10_CUR_PTR_MASK_SFT (0xffffffff << 0)
6980
6981	/* AFE_VUL10_END_MSB */
6982	#define VUL10_END_ADDR_MSB_SFT 0
6983	#define VUL10_END_ADDR_MSB_MASK 0x1ff
6984	#define VUL10_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
6985
6986	/* AFE_VUL10_END */
6987	#define VUL10_END_ADDR_SFT 4
6988	#define VUL10_END_ADDR_MASK 0xfffffff
6989	#define VUL10_END_ADDR_MASK_SFT (0xfffffff << 4)
6990
6991	/* AFE_VUL10_RCH_MON */
6992	#define VUL10_RCH_DATA_SFT 0
6993	#define VUL10_RCH_DATA_MASK 0xffffffff
6994	#define VUL10_RCH_DATA_MASK_SFT (0xffffffff << 0)
6995
6996	/* AFE_VUL10_LCH_MON */
6997	#define VUL10_LCH_DATA_SFT 0
6998	#define VUL10_LCH_DATA_MASK 0xffffffff
6999	#define VUL10_LCH_DATA_MASK_SFT (0xffffffff << 0)
7000
7001	/* AFE_VUL10_CON0 */
7002	#define VUL10_ON_SFT 28
7003	#define VUL10_ON_MASK 0x1
7004	#define VUL10_ON_MASK_SFT (0x1 << 28)
7005	#define VUL10_MINLEN_SFT 20
7006	#define VUL10_MINLEN_MASK 0x3
7007	#define VUL10_MINLEN_MASK_SFT (0x3 << 20)
7008	#define VUL10_MAXLEN_SFT 16
7009	#define VUL10_MAXLEN_MASK 0x3
7010	#define VUL10_MAXLEN_MASK_SFT (0x3 << 16)
7011	#define VUL10_SEL_DOMAIN_SFT 13
7012	#define VUL10_SEL_DOMAIN_MASK 0x7
7013	#define VUL10_SEL_DOMAIN_MASK_SFT (0x7 << 13)
7014	#define VUL10_SEL_FS_SFT 8
7015	#define VUL10_SEL_FS_MASK 0x1f
7016	#define VUL10_SEL_FS_MASK_SFT (0x1f << 8)
7017	#define VUL10_SW_CLEAR_BUF_FULL_SFT 7
7018	#define VUL10_SW_CLEAR_BUF_FULL_MASK 0x1
7019	#define VUL10_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
7020	#define VUL10_WR_SIGN_SFT 6
7021	#define VUL10_WR_SIGN_MASK 0x1
7022	#define VUL10_WR_SIGN_MASK_SFT (0x1 << 6)
7023	#define VUL10_R_MONO_SFT 5
7024	#define VUL10_R_MONO_MASK 0x1
7025	#define VUL10_R_MONO_MASK_SFT (0x1 << 5)
7026	#define VUL10_MONO_SFT 4
7027	#define VUL10_MONO_MASK 0x1
7028	#define VUL10_MONO_MASK_SFT (0x1 << 4)
7029	#define VUL10_NORMAL_MODE_SFT 3
7030	#define VUL10_NORMAL_MODE_MASK 0x1
7031	#define VUL10_NORMAL_MODE_MASK_SFT (0x1 << 3)
7032	#define VUL10_HALIGN_SFT 2
7033	#define VUL10_HALIGN_MASK 0x1
7034	#define VUL10_HALIGN_MASK_SFT (0x1 << 2)
7035	#define VUL10_HD_MODE_SFT 0
7036	#define VUL10_HD_MODE_MASK 0x3
7037	#define VUL10_HD_MODE_MASK_SFT (0x3 << 0)
7038
7039	/* AFE_VUL10_MON0 */
7040	#define MEM_HW_WEN_SFT 20
7041	#define MEM_HW_WEN_MASK 0xf
7042	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
7043	#define MEM_REQ_PENDING_SFT 19
7044	#define MEM_REQ_PENDING_MASK 0x1
7045	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
7046	#define BUF_FULL_SFT 18
7047	#define BUF_FULL_MASK 0x1
7048	#define BUF_FULL_MASK_SFT (0x1 << 18)
7049	#define ENABLE_SYNC_MEM_SFT 17
7050	#define ENABLE_SYNC_MEM_MASK 0x1
7051	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
7052	#define ENABLE_SYNC_AGENT_SFT 16
7053	#define ENABLE_SYNC_AGENT_MASK 0x1
7054	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
7055	#define RESERVED_02_SFT 6
7056	#define RESERVED_02_MASK 0x3ff
7057	#define RESERVED_02_MASK_SFT (0x3ff << 6)
7058	#define MEM_ADDR_DIFF_SFT 0
7059	#define MEM_ADDR_DIFF_MASK 0x3f
7060	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
7061
7062	/* AFE_VUL24_BASE_MSB */
7063	#define VUL24_BASE_ADDR_MSB_SFT 0
7064	#define VUL24_BASE_ADDR_MSB_MASK 0x1ff
7065	#define VUL24_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
7066
7067	/* AFE_VUL24_BASE */
7068	#define VUL24_BASE_ADDR_SFT 4
7069	#define VUL24_BASE_ADDR_MASK 0xfffffff
7070	#define VUL24_BASE_ADDR_MASK_SFT (0xfffffff << 4)
7071
7072	/* AFE_VUL24_CUR_MSB */
7073	#define VUL24_CUR_PTR_MSB_SFT 0
7074	#define VUL24_CUR_PTR_MSB_MASK 0x1ff
7075	#define VUL24_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
7076
7077	/* AFE_VUL24_CUR */
7078	#define VUL24_CUR_PTR_SFT 0
7079	#define VUL24_CUR_PTR_MASK 0xffffffff
7080	#define VUL24_CUR_PTR_MASK_SFT (0xffffffff << 0)
7081
7082	/* AFE_VUL24_END_MSB */
7083	#define VUL24_END_ADDR_MSB_SFT 0
7084	#define VUL24_END_ADDR_MSB_MASK 0x1ff
7085	#define VUL24_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
7086
7087	/* AFE_VUL24_END */
7088	#define VUL24_END_ADDR_SFT 4
7089	#define VUL24_END_ADDR_MASK 0xfffffff
7090	#define VUL24_END_ADDR_MASK_SFT (0xfffffff << 4)
7091
7092	/* AFE_VUL24_CON0 */
7093	#define OUT_ON_USE_VUL24_SFT 29
7094	#define OUT_ON_USE_VUL24_MASK 0x1
7095	#define OUT_ON_USE_VUL24_MASK_SFT (0x1 << 29)
7096	#define VUL24_ON_SFT 28
7097	#define VUL24_ON_MASK 0x1
7098	#define VUL24_ON_MASK_SFT (0x1 << 28)
7099	#define VUL24_MINLEN_SFT 20
7100	#define VUL24_MINLEN_MASK 0x3
7101	#define VUL24_MINLEN_MASK_SFT (0x3 << 20)
7102	#define VUL24_MAXLEN_SFT 16
7103	#define VUL24_MAXLEN_MASK 0x3
7104	#define VUL24_MAXLEN_MASK_SFT (0x3 << 16)
7105	#define VUL24_SEL_DOMAIN_SFT 13
7106	#define VUL24_SEL_DOMAIN_MASK 0x7
7107	#define VUL24_SEL_DOMAIN_MASK_SFT (0x7 << 13)
7108	#define VUL24_SEL_FS_SFT 8
7109	#define VUL24_SEL_FS_MASK 0x1f
7110	#define VUL24_SEL_FS_MASK_SFT (0x1f << 8)
7111	#define VUL24_SW_CLEAR_BUF_FULL_SFT 7
7112	#define VUL24_SW_CLEAR_BUF_FULL_MASK 0x1
7113	#define VUL24_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
7114	#define VUL24_WR_SIGN_SFT 6
7115	#define VUL24_WR_SIGN_MASK 0x1
7116	#define VUL24_WR_SIGN_MASK_SFT (0x1 << 6)
7117	#define VUL24_R_MONO_SFT 5
7118	#define VUL24_R_MONO_MASK 0x1
7119	#define VUL24_R_MONO_MASK_SFT (0x1 << 5)
7120	#define VUL24_MONO_SFT 4
7121	#define VUL24_MONO_MASK 0x1
7122	#define VUL24_MONO_MASK_SFT (0x1 << 4)
7123	#define VUL24_NORMAL_MODE_SFT 3
7124	#define VUL24_NORMAL_MODE_MASK 0x1
7125	#define VUL24_NORMAL_MODE_MASK_SFT (0x1 << 3)
7126	#define VUL24_HALIGN_SFT 2
7127	#define VUL24_HALIGN_MASK 0x1
7128	#define VUL24_HALIGN_MASK_SFT (0x1 << 2)
7129	#define VUL24_HD_MODE_SFT 0
7130	#define VUL24_HD_MODE_MASK 0x3
7131	#define VUL24_HD_MODE_MASK_SFT (0x3 << 0)
7132
7133	/* AFE_VUL24_MON0 */
7134	#define MEM_HW_WEN_SFT 20
7135	#define MEM_HW_WEN_MASK 0xf
7136	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
7137	#define MEM_REQ_PENDING_SFT 19
7138	#define MEM_REQ_PENDING_MASK 0x1
7139	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
7140	#define BUF_FULL_SFT 18
7141	#define BUF_FULL_MASK 0x1
7142	#define BUF_FULL_MASK_SFT (0x1 << 18)
7143	#define ENABLE_SYNC_MEM_SFT 17
7144	#define ENABLE_SYNC_MEM_MASK 0x1
7145	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
7146	#define ENABLE_SYNC_AGENT_SFT 16
7147	#define ENABLE_SYNC_AGENT_MASK 0x1
7148	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
7149	#define RESERVED_02_SFT 6
7150	#define RESERVED_02_MASK 0x3ff
7151	#define RESERVED_02_MASK_SFT (0x3ff << 6)
7152	#define MEM_ADDR_DIFF_SFT 0
7153	#define MEM_ADDR_DIFF_MASK 0x3f
7154	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
7155
7156	/* AFE_VUL25_BASE_MSB */
7157	#define VUL25_BASE_ADDR_MSB_SFT 0
7158	#define VUL25_BASE_ADDR_MSB_MASK 0x1ff
7159	#define VUL25_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
7160
7161	/* AFE_VUL25_BASE */
7162	#define VUL25_BASE_ADDR_SFT 4
7163	#define VUL25_BASE_ADDR_MASK 0xfffffff
7164	#define VUL25_BASE_ADDR_MASK_SFT (0xfffffff << 4)
7165
7166	/* AFE_VUL25_CUR_MSB */
7167	#define VUL25_CUR_PTR_MSB_SFT 0
7168	#define VUL25_CUR_PTR_MSB_MASK 0x1ff
7169	#define VUL25_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
7170
7171	/* AFE_VUL25_CUR */
7172	#define VUL25_CUR_PTR_SFT 0
7173	#define VUL25_CUR_PTR_MASK 0xffffffff
7174	#define VUL25_CUR_PTR_MASK_SFT (0xffffffff << 0)
7175
7176	/* AFE_VUL25_END_MSB */
7177	#define VUL25_END_ADDR_MSB_SFT 0
7178	#define VUL25_END_ADDR_MSB_MASK 0x1ff
7179	#define VUL25_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
7180
7181	/* AFE_VUL25_END */
7182	#define VUL25_END_ADDR_SFT 4
7183	#define VUL25_END_ADDR_MASK 0xfffffff
7184	#define VUL25_END_ADDR_MASK_SFT (0xfffffff << 4)
7185
7186	/* AFE_VUL25_CON0 */
7187	#define OUT_ON_USE_VUL25_SFT 29
7188	#define OUT_ON_USE_VUL25_MASK 0x1
7189	#define OUT_ON_USE_VUL25_MASK_SFT (0x1 << 29)
7190	#define VUL25_ON_SFT 28
7191	#define VUL25_ON_MASK 0x1
7192	#define VUL25_ON_MASK_SFT (0x1 << 28)
7193	#define VUL25_MINLEN_SFT 20
7194	#define VUL25_MINLEN_MASK 0x3
7195	#define VUL25_MINLEN_MASK_SFT (0x3 << 20)
7196	#define VUL25_MAXLEN_SFT 16
7197	#define VUL25_MAXLEN_MASK 0x3
7198	#define VUL25_MAXLEN_MASK_SFT (0x3 << 16)
7199	#define VUL25_SEL_DOMAIN_SFT 13
7200	#define VUL25_SEL_DOMAIN_MASK 0x7
7201	#define VUL25_SEL_DOMAIN_MASK_SFT (0x7 << 13)
7202	#define VUL25_SEL_FS_SFT 8
7203	#define VUL25_SEL_FS_MASK 0x1f
7204	#define VUL25_SEL_FS_MASK_SFT (0x1f << 8)
7205	#define VUL25_SW_CLEAR_BUF_FULL_SFT 7
7206	#define VUL25_SW_CLEAR_BUF_FULL_MASK 0x1
7207	#define VUL25_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
7208	#define VUL25_WR_SIGN_SFT 6
7209	#define VUL25_WR_SIGN_MASK 0x1
7210	#define VUL25_WR_SIGN_MASK_SFT (0x1 << 6)
7211	#define VUL25_R_MONO_SFT 5
7212	#define VUL25_R_MONO_MASK 0x1
7213	#define VUL25_R_MONO_MASK_SFT (0x1 << 5)
7214	#define VUL25_MONO_SFT 4
7215	#define VUL25_MONO_MASK 0x1
7216	#define VUL25_MONO_MASK_SFT (0x1 << 4)
7217	#define VUL25_NORMAL_MODE_SFT 3
7218	#define VUL25_NORMAL_MODE_MASK 0x1
7219	#define VUL25_NORMAL_MODE_MASK_SFT (0x1 << 3)
7220	#define VUL25_HALIGN_SFT 2
7221	#define VUL25_HALIGN_MASK 0x1
7222	#define VUL25_HALIGN_MASK_SFT (0x1 << 2)
7223	#define VUL25_HD_MODE_SFT 0
7224	#define VUL25_HD_MODE_MASK 0x3
7225	#define VUL25_HD_MODE_MASK_SFT (0x3 << 0)
7226
7227	/* AFE_VUL25_MON0 */
7228	#define MEM_HW_WEN_SFT 20
7229	#define MEM_HW_WEN_MASK 0xf
7230	#define MEM_HW_WEN_MASK_SFT (0xf << 20)
7231	#define MEM_REQ_PENDING_SFT 19
7232	#define MEM_REQ_PENDING_MASK 0x1
7233	#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
7234	#define BUF_FULL_SFT 18
7235	#define BUF_FULL_MASK 0x1
7236	#define BUF_FULL_MASK_SFT (0x1 << 18)
7237	#define ENABLE_SYNC_MEM_SFT 17
7238	#define ENABLE_SYNC_MEM_MASK 0x1
7239	#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
7240	#define ENABLE_SYNC_AGENT_SFT 16
7241	#define ENABLE_SYNC_AGENT_MASK 0x1
7242	#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
7243	#define RESERVED_02_SFT 6
7244	#define RESERVED_02_MASK 0x3ff
7245	#define RESERVED_02_MASK_SFT (0x3ff << 6)
7246	#define MEM_ADDR_DIFF_SFT 0
7247	#define MEM_ADDR_DIFF_MASK 0x3f
7248	#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
7249
7250	/* AFE_VUL_CM0_BASE_MSB */
7251	#define VUL_CM0_BASE_ADDR_MSB_SFT 0
7252	#define VUL_CM0_BASE_ADDR_MSB_MASK 0x1ff
7253	#define VUL_CM0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
7254
7255	/* AFE_VUL_CM0_BASE */
7256	#define VUL_CM0_BASE_ADDR_SFT 4
7257	#define VUL_CM0_BASE_ADDR_MASK 0xfffffff
7258	#define VUL_CM0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
7259
7260	/* AFE_VUL_CM0_CUR_MSB */
7261	#define VUL_CM0_CUR_PTR_MSB_SFT 0
7262	#define VUL_CM0_CUR_PTR_MSB_MASK 0x1ff
7263	#define VUL_CM0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
7264
7265	/* AFE_VUL_CM0_CUR */
7266	#define VUL_CM0_CUR_PTR_SFT 0
7267	#define VUL_CM0_CUR_PTR_MASK 0xffffffff
7268	#define VUL_CM0_CUR_PTR_MASK_SFT (0xffffffff << 0)
7269
7270	/* AFE_VUL_CM0_END_MSB */
7271	#define VUL_CM0_END_ADDR_MSB_SFT 0
7272	#define VUL_CM0_END_ADDR_MSB_MASK 0x1ff
7273	#define VUL_CM0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
7274
7275	/* AFE_VUL_CM0_END */
7276	#define VUL_CM0_END_ADDR_SFT 4
7277	#define VUL_CM0_END_ADDR_MASK 0xfffffff
7278	#define VUL_CM0_END_ADDR_MASK_SFT (0xfffffff << 4)
7279
7280	/* AFE_VUL_CM0_CON0 */
7281	#define VUL_CM0_ON_SFT 28
7282	#define VUL_CM0_ON_MASK 0x1
7283	#define VUL_CM0_ON_MASK_SFT (0x1 << 28)
7284	#define VUL_CM0_REG_CH_SHIFT_MODE_SFT 26
7285	#define VUL_CM0_REG_CH_SHIFT_MODE_MASK 0x1
7286	#define VUL_CM0_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
7287	#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_SFT 25
7288	#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
7289	#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
7290	#define VUL_CM0_SW_CLEAR_BUF_FULL_SFT 24
7291	#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK 0x1
7292	#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
7293	#define VUL_CM0_ULTRA_TH_SFT 20
7294	#define VUL_CM0_ULTRA_TH_MASK 0xf
7295	#define VUL_CM0_ULTRA_TH_MASK_SFT (0xf << 20)
7296	#define VUL_CM0_NORMAL_MODE_SFT 17
7297	#define VUL_CM0_NORMAL_MODE_MASK 0x1
7298	#define VUL_CM0_NORMAL_MODE_MASK_SFT (0x1 << 17)
7299	#define VUL_CM0_ODD_USE_EVEN_SFT 16
7300	#define VUL_CM0_ODD_USE_EVEN_MASK 0x1
7301	#define VUL_CM0_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
7302	#define VUL_CM0_AXI_REQ_MAXLEN_SFT 12
7303	#define VUL_CM0_AXI_REQ_MAXLEN_MASK 0x3
7304	#define VUL_CM0_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
7305	#define VUL_CM0_AXI_REQ_MINLEN_SFT 8
7306	#define VUL_CM0_AXI_REQ_MINLEN_MASK 0x3
7307	#define VUL_CM0_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
7308	#define VUL_CM0_HALIGN_SFT 7
7309	#define VUL_CM0_HALIGN_MASK 0x1
7310	#define VUL_CM0_HALIGN_MASK_SFT (0x1 << 7)
7311	#define VUL_CM0_SIGN_EXT_SFT 6
7312	#define VUL_CM0_SIGN_EXT_MASK 0x1
7313	#define VUL_CM0_SIGN_EXT_MASK_SFT (0x1 << 6)
7314	#define VUL_CM0_HD_MODE_SFT 4
7315	#define VUL_CM0_HD_MODE_MASK 0x3
7316	#define VUL_CM0_HD_MODE_MASK_SFT (0x3 << 4)
7317	#define VUL_CM0_MAKE_EXTRA_UPDATE_SFT 3
7318	#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK 0x1
7319	#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
7320	#define VUL_CM0_AGENT_FREE_RUN_SFT 2
7321	#define VUL_CM0_AGENT_FREE_RUN_MASK 0x1
7322	#define VUL_CM0_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
7323	#define VUL_CM0_USE_INT_ODD_SFT 1
7324	#define VUL_CM0_USE_INT_ODD_MASK 0x1
7325	#define VUL_CM0_USE_INT_ODD_MASK_SFT (0x1 << 1)
7326	#define VUL_CM0_INT_ODD_FLAG_SFT 0
7327	#define VUL_CM0_INT_ODD_FLAG_MASK 0x1
7328	#define VUL_CM0_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
7329
7330	/* AFE_VUL_CM1_BASE_MSB */
7331	#define VUL_CM1_BASE_ADDR_MSB_SFT 0
7332	#define VUL_CM1_BASE_ADDR_MSB_MASK 0x1ff
7333	#define VUL_CM1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
7334
7335	/* AFE_VUL_CM1_BASE */
7336	#define VUL_CM1_BASE_ADDR_SFT 4
7337	#define VUL_CM1_BASE_ADDR_MASK 0xfffffff
7338	#define VUL_CM1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
7339
7340	/* AFE_VUL_CM1_CUR_MSB */
7341	#define VUL_CM1_CUR_PTR_MSB_SFT 0
7342	#define VUL_CM1_CUR_PTR_MSB_MASK 0x1ff
7343	#define VUL_CM1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
7344
7345	/* AFE_VUL_CM1_CUR */
7346	#define VUL_CM1_CUR_PTR_SFT 0
7347	#define VUL_CM1_CUR_PTR_MASK 0xffffffff
7348	#define VUL_CM1_CUR_PTR_MASK_SFT (0xffffffff << 0)
7349
7350	/* AFE_VUL_CM1_END_MSB */
7351	#define VUL_CM1_END_ADDR_MSB_SFT 0
7352	#define VUL_CM1_END_ADDR_MSB_MASK 0x1ff
7353	#define VUL_CM1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
7354
7355	/* AFE_VUL_CM1_END */
7356	#define VUL_CM1_END_ADDR_SFT 4
7357	#define VUL_CM1_END_ADDR_MASK 0xfffffff
7358	#define VUL_CM1_END_ADDR_MASK_SFT (0xfffffff << 4)
7359
7360	/* AFE_VUL_CM1_CON0 */
7361	#define VUL_CM1_ON_SFT 28
7362	#define VUL_CM1_ON_MASK 0x1
7363	#define VUL_CM1_ON_MASK_SFT (0x1 << 28)
7364	#define VUL_CM1_REG_CH_SHIFT_MODE_SFT 26
7365	#define VUL_CM1_REG_CH_SHIFT_MODE_MASK 0x1
7366	#define VUL_CM1_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
7367	#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_SFT 25
7368	#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
7369	#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
7370	#define VUL_CM1_SW_CLEAR_BUF_FULL_SFT 24
7371	#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK 0x1
7372	#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
7373	#define VUL_CM1_ULTRA_TH_SFT 20
7374	#define VUL_CM1_ULTRA_TH_MASK 0xf
7375	#define VUL_CM1_ULTRA_TH_MASK_SFT (0xf << 20)
7376	#define VUL_CM1_NORMAL_MODE_SFT 17
7377	#define VUL_CM1_NORMAL_MODE_MASK 0x1
7378	#define VUL_CM1_NORMAL_MODE_MASK_SFT (0x1 << 17)
7379	#define VUL_CM1_ODD_USE_EVEN_SFT 16
7380	#define VUL_CM1_ODD_USE_EVEN_MASK 0x1
7381	#define VUL_CM1_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
7382	#define VUL_CM1_AXI_REQ_MAXLEN_SFT 12
7383	#define VUL_CM1_AXI_REQ_MAXLEN_MASK 0x3
7384	#define VUL_CM1_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
7385	#define VUL_CM1_AXI_REQ_MINLEN_SFT 8
7386	#define VUL_CM1_AXI_REQ_MINLEN_MASK 0x3
7387	#define VUL_CM1_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
7388	#define VUL_CM1_HALIGN_SFT 7
7389	#define VUL_CM1_HALIGN_MASK 0x1
7390	#define VUL_CM1_HALIGN_MASK_SFT (0x1 << 7)
7391	#define VUL_CM1_SIGN_EXT_SFT 6
7392	#define VUL_CM1_SIGN_EXT_MASK 0x1
7393	#define VUL_CM1_SIGN_EXT_MASK_SFT (0x1 << 6)
7394	#define VUL_CM1_HD_MODE_SFT 4
7395	#define VUL_CM1_HD_MODE_MASK 0x3
7396	#define VUL_CM1_HD_MODE_MASK_SFT (0x3 << 4)
7397	#define VUL_CM1_MAKE_EXTRA_UPDATE_SFT 3
7398	#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK 0x1
7399	#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
7400	#define VUL_CM1_AGENT_FREE_RUN_SFT 2
7401	#define VUL_CM1_AGENT_FREE_RUN_MASK 0x1
7402	#define VUL_CM1_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
7403	#define VUL_CM1_USE_INT_ODD_SFT 1
7404	#define VUL_CM1_USE_INT_ODD_MASK 0x1
7405	#define VUL_CM1_USE_INT_ODD_MASK_SFT (0x1 << 1)
7406	#define VUL_CM1_INT_ODD_FLAG_SFT 0
7407	#define VUL_CM1_INT_ODD_FLAG_MASK 0x1
7408	#define VUL_CM1_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
7409
7410	/* AFE_ETDM_IN0_BASE_MSB */
7411	#define ETDM_IN0_BASE_ADDR_MSB_SFT 0
7412	#define ETDM_IN0_BASE_ADDR_MSB_MASK 0x1ff
7413	#define ETDM_IN0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
7414
7415	/* AFE_ETDM_IN0_BASE */
7416	#define ETDM_IN0_BASE_ADDR_SFT 4
7417	#define ETDM_IN0_BASE_ADDR_MASK 0xfffffff
7418	#define ETDM_IN0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
7419
7420	/* AFE_ETDM_IN0_CUR_MSB */
7421	#define ETDM_IN0_CUR_PTR_MSB_SFT 0
7422	#define ETDM_IN0_CUR_PTR_MSB_MASK 0x1ff
7423	#define ETDM_IN0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
7424
7425	/* AFE_ETDM_IN0_CUR */
7426	#define ETDM_IN0_CUR_PTR_SFT 0
7427	#define ETDM_IN0_CUR_PTR_MASK 0xffffffff
7428	#define ETDM_IN0_CUR_PTR_MASK_SFT (0xffffffff << 0)
7429
7430	/* AFE_ETDM_IN0_END_MSB */
7431	#define ETDM_IN0_END_ADDR_MSB_SFT 0
7432	#define ETDM_IN0_END_ADDR_MSB_MASK 0x1ff
7433	#define ETDM_IN0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
7434
7435	/* AFE_ETDM_IN0_END */
7436	#define ETDM_IN0_END_ADDR_SFT 4
7437	#define ETDM_IN0_END_ADDR_MASK 0xfffffff
7438	#define ETDM_IN0_END_ADDR_MASK_SFT (0xfffffff << 4)
7439
7440	/* AFE_ETDM_IN0_CON0 */
7441	#define ETDM_IN0_CH_NUM_SFT 28
7442	#define ETDM_IN0_CH_NUM_MASK 0xf
7443	#define ETDM_IN0_CH_NUM_MASK_SFT (0xf << 28)
7444	#define ETDM_IN0_ON_SFT 27
7445	#define ETDM_IN0_ON_MASK 0x1
7446	#define ETDM_IN0_ON_MASK_SFT (0x1 << 27)
7447	#define ETDM_IN0_REG_CH_SHIFT_MODE_SFT 26
7448	#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK 0x1
7449	#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
7450	#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_SFT 25
7451	#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
7452	#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
7453	#define ETDM_IN0_SW_CLEAR_BUF_FULL_SFT 24
7454	#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK 0x1
7455	#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
7456	#define ETDM_IN0_ULTRA_TH_SFT 20
7457	#define ETDM_IN0_ULTRA_TH_MASK 0xf
7458	#define ETDM_IN0_ULTRA_TH_MASK_SFT (0xf << 20)
7459	#define ETDM_IN0_NORMAL_MODE_SFT 17
7460	#define ETDM_IN0_NORMAL_MODE_MASK 0x1
7461	#define ETDM_IN0_NORMAL_MODE_MASK_SFT (0x1 << 17)
7462	#define ETDM_IN0_ODD_USE_EVEN_SFT 16
7463	#define ETDM_IN0_ODD_USE_EVEN_MASK 0x1
7464	#define ETDM_IN0_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
7465	#define ETDM_IN0_AXI_REQ_MAXLEN_SFT 12
7466	#define ETDM_IN0_AXI_REQ_MAXLEN_MASK 0x3
7467	#define ETDM_IN0_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
7468	#define ETDM_IN0_AXI_REQ_MINLEN_SFT 8
7469	#define ETDM_IN0_AXI_REQ_MINLEN_MASK 0x3
7470	#define ETDM_IN0_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
7471	#define ETDM_IN0_HALIGN_SFT 7
7472	#define ETDM_IN0_HALIGN_MASK 0x1
7473	#define ETDM_IN0_HALIGN_MASK_SFT (0x1 << 7)
7474	#define ETDM_IN0_SIGN_EXT_SFT 6
7475	#define ETDM_IN0_SIGN_EXT_MASK 0x1
7476	#define ETDM_IN0_SIGN_EXT_MASK_SFT (0x1 << 6)
7477	#define ETDM_IN0_HD_MODE_SFT 4
7478	#define ETDM_IN0_HD_MODE_MASK 0x3
7479	#define ETDM_IN0_HD_MODE_MASK_SFT (0x3 << 4)
7480	#define ETDM_IN0_MAKE_EXTRA_UPDATE_SFT 3
7481	#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK 0x1
7482	#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
7483	#define ETDM_IN0_AGENT_FREE_RUN_SFT 2
7484	#define ETDM_IN0_AGENT_FREE_RUN_MASK 0x1
7485	#define ETDM_IN0_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
7486	#define ETDM_IN0_USE_INT_ODD_SFT 1
7487	#define ETDM_IN0_USE_INT_ODD_MASK 0x1
7488	#define ETDM_IN0_USE_INT_ODD_MASK_SFT (0x1 << 1)
7489	#define ETDM_IN0_INT_ODD_FLAG_SFT 0
7490	#define ETDM_IN0_INT_ODD_FLAG_MASK 0x1
7491	#define ETDM_IN0_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
7492
7493	/* AFE_ETDM_IN1_BASE_MSB */
7494	#define ETDM_IN1_BASE_ADDR_MSB_SFT 0
7495	#define ETDM_IN1_BASE_ADDR_MSB_MASK 0x1ff
7496	#define ETDM_IN1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
7497
7498	/* AFE_ETDM_IN1_BASE */
7499	#define ETDM_IN1_BASE_ADDR_SFT 4
7500	#define ETDM_IN1_BASE_ADDR_MASK 0xfffffff
7501	#define ETDM_IN1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
7502
7503	/* AFE_ETDM_IN1_CUR_MSB */
7504	#define ETDM_IN1_CUR_PTR_MSB_SFT 0
7505	#define ETDM_IN1_CUR_PTR_MSB_MASK 0x1ff
7506	#define ETDM_IN1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
7507
7508	/* AFE_ETDM_IN1_CUR */
7509	#define ETDM_IN1_CUR_PTR_SFT 0
7510	#define ETDM_IN1_CUR_PTR_MASK 0xffffffff
7511	#define ETDM_IN1_CUR_PTR_MASK_SFT (0xffffffff << 0)
7512
7513	/* AFE_ETDM_IN1_END_MSB */
7514	#define ETDM_IN1_END_ADDR_MSB_SFT 0
7515	#define ETDM_IN1_END_ADDR_MSB_MASK 0x1ff
7516	#define ETDM_IN1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
7517
7518	/* AFE_ETDM_IN1_END */
7519	#define ETDM_IN1_END_ADDR_SFT 4
7520	#define ETDM_IN1_END_ADDR_MASK 0xfffffff
7521	#define ETDM_IN1_END_ADDR_MASK_SFT (0xfffffff << 4)
7522
7523	/* AFE_ETDM_IN1_CON0 */
7524	#define ETDM_IN1_CH_NUM_SFT 28
7525	#define ETDM_IN1_CH_NUM_MASK 0xf
7526	#define ETDM_IN1_CH_NUM_MASK_SFT (0xf << 28)
7527	#define ETDM_IN1_ON_SFT 27
7528	#define ETDM_IN1_ON_MASK 0x1
7529	#define ETDM_IN1_ON_MASK_SFT (0x1 << 27)
7530	#define ETDM_IN1_REG_CH_SHIFT_MODE_SFT 26
7531	#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK 0x1
7532	#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
7533	#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_SFT 25
7534	#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
7535	#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
7536	#define ETDM_IN1_SW_CLEAR_BUF_FULL_SFT 24
7537	#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK 0x1
7538	#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
7539	#define ETDM_IN1_ULTRA_TH_SFT 20
7540	#define ETDM_IN1_ULTRA_TH_MASK 0xf
7541	#define ETDM_IN1_ULTRA_TH_MASK_SFT (0xf << 20)
7542	#define ETDM_IN1_NORMAL_MODE_SFT 17
7543	#define ETDM_IN1_NORMAL_MODE_MASK 0x1
7544	#define ETDM_IN1_NORMAL_MODE_MASK_SFT (0x1 << 17)
7545	#define ETDM_IN1_ODD_USE_EVEN_SFT 16
7546	#define ETDM_IN1_ODD_USE_EVEN_MASK 0x1
7547	#define ETDM_IN1_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
7548	#define ETDM_IN1_AXI_REQ_MAXLEN_SFT 12
7549	#define ETDM_IN1_AXI_REQ_MAXLEN_MASK 0x3
7550	#define ETDM_IN1_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
7551	#define ETDM_IN1_AXI_REQ_MINLEN_SFT 8
7552	#define ETDM_IN1_AXI_REQ_MINLEN_MASK 0x3
7553	#define ETDM_IN1_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
7554	#define ETDM_IN1_HALIGN_SFT 7
7555	#define ETDM_IN1_HALIGN_MASK 0x1
7556	#define ETDM_IN1_HALIGN_MASK_SFT (0x1 << 7)
7557	#define ETDM_IN1_SIGN_EXT_SFT 6
7558	#define ETDM_IN1_SIGN_EXT_MASK 0x1
7559	#define ETDM_IN1_SIGN_EXT_MASK_SFT (0x1 << 6)
7560	#define ETDM_IN1_HD_MODE_SFT 4
7561	#define ETDM_IN1_HD_MODE_MASK 0x3
7562	#define ETDM_IN1_HD_MODE_MASK_SFT (0x3 << 4)
7563	#define ETDM_IN1_MAKE_EXTRA_UPDATE_SFT 3
7564	#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK 0x1
7565	#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
7566	#define ETDM_IN1_AGENT_FREE_RUN_SFT 2
7567	#define ETDM_IN1_AGENT_FREE_RUN_MASK 0x1
7568	#define ETDM_IN1_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
7569	#define ETDM_IN1_USE_INT_ODD_SFT 1
7570	#define ETDM_IN1_USE_INT_ODD_MASK 0x1
7571	#define ETDM_IN1_USE_INT_ODD_MASK_SFT (0x1 << 1)
7572	#define ETDM_IN1_INT_ODD_FLAG_SFT 0
7573	#define ETDM_IN1_INT_ODD_FLAG_MASK 0x1
7574	#define ETDM_IN1_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
7575
7576	/* AFE_VUL24_RCH_MON */
7577	#define VUL24_RCH_DATA_SFT 0
7578	#define VUL24_RCH_DATA_MASK 0xffffffff
7579	#define VUL24_RCH_DATA_MASK_SFT (0xffffffff << 0)
7580
7581	/* AFE_VUL24_LCH_MON */
7582	#define VUL24_LCH_DATA_SFT 0
7583	#define VUL24_LCH_DATA_MASK 0xffffffff
7584	#define VUL24_LCH_DATA_MASK_SFT (0xffffffff << 0)
7585
7586	/* AFE_VUL25_RCH_MON */
7587	#define VUL25_RCH_DATA_SFT 0
7588	#define VUL25_RCH_DATA_MASK 0xffffffff
7589	#define VUL25_RCH_DATA_MASK_SFT (0xffffffff << 0)
7590
7591	/* AFE_VUL25_LCH_MON */
7592	#define VUL25_LCH_DATA_SFT 0
7593	#define VUL25_LCH_DATA_MASK 0xffffffff
7594	#define VUL25_LCH_DATA_MASK_SFT (0xffffffff << 0)
7595
7596	/* AFE_VUL_CM0_RCH_MON */
7597	#define VUL_CM0_RCH_DATA_SFT 0
7598	#define VUL_CM0_RCH_DATA_MASK 0xffffffff
7599	#define VUL_CM0_RCH_DATA_MASK_SFT (0xffffffff << 0)
7600
7601	/* AFE_VUL_CM0_LCH_MON */
7602	#define VUL_CM0_LCH_DATA_SFT 0
7603	#define VUL_CM0_LCH_DATA_MASK 0xffffffff
7604	#define VUL_CM0_LCH_DATA_MASK_SFT (0xffffffff << 0)
7605
7606	/* AFE_VUL_CM1_RCH_MON */
7607	#define VUL_CM1_RCH_DATA_SFT 0
7608	#define VUL_CM1_RCH_DATA_MASK 0xffffffff
7609	#define VUL_CM1_RCH_DATA_MASK_SFT (0xffffffff << 0)
7610
7611	/* AFE_VUL_CM1_LCH_MON */
7612	#define VUL_CM1_LCH_DATA_SFT 0
7613	#define VUL_CM1_LCH_DATA_MASK 0xffffffff
7614	#define VUL_CM1_LCH_DATA_MASK_SFT (0xffffffff << 0)
7615
7616	/* AFE_DL_24CH_CH0_MON */
7617	#define DL_24CH_CH0_DATA_SFT 0
7618	#define DL_24CH_CH0_DATA_MASK 0xffffffff
7619	#define DL_24CH_CH0_DATA_MASK_SFT (0xffffffff << 0)
7620
7621	/* AFE_DL_24CH_CH1_MON */
7622	#define DL_24CH_CH1_DATA_SFT 0
7623	#define DL_24CH_CH1_DATA_MASK 0xffffffff
7624	#define DL_24CH_CH1_DATA_MASK_SFT (0xffffffff << 0)
7625
7626	/* AFE_DL_24CH_CH2_MON */
7627	#define DL_24CH_CH2_DATA_SFT 0
7628	#define DL_24CH_CH2_DATA_MASK 0xffffffff
7629	#define DL_24CH_CH2_DATA_MASK_SFT (0xffffffff << 0)
7630
7631	/* AFE_DL_24CH_CH3_MON */
7632	#define DL_24CH_CH3_DATA_SFT 0
7633	#define DL_24CH_CH3_DATA_MASK 0xffffffff
7634	#define DL_24CH_CH3_DATA_MASK_SFT (0xffffffff << 0)
7635
7636	/* AFE_DL_24CH_CH4_MON */
7637	#define DL_24CH_CH4_DATA_SFT 0
7638	#define DL_24CH_CH4_DATA_MASK 0xffffffff
7639	#define DL_24CH_CH4_DATA_MASK_SFT (0xffffffff << 0)
7640
7641	/* AFE_DL_24CH_CH5_MON */
7642	#define DL_24CH_CH5_DATA_SFT 0
7643	#define DL_24CH_CH5_DATA_MASK 0xffffffff
7644	#define DL_24CH_CH5_DATA_MASK_SFT (0xffffffff << 0)
7645
7646	/* AFE_DL_24CH_CH6_MON */
7647	#define DL_24CH_CH6_DATA_SFT 0
7648	#define DL_24CH_CH6_DATA_MASK 0xffffffff
7649	#define DL_24CH_CH6_DATA_MASK_SFT (0xffffffff << 0)
7650
7651	/* AFE_DL_24CH_CH7_MON */
7652	#define DL_24CH_CH7_DATA_SFT 0
7653	#define DL_24CH_CH7_DATA_MASK 0xffffffff
7654	#define DL_24CH_CH7_DATA_MASK_SFT (0xffffffff << 0)
7655
7656	/* AFE_SRAM_BOUND */
7657	#define SECURE_BIT_SFT 19
7658	#define SECURE_BIT_MASK 0x1
7659	#define SECURE_BIT_MASK_SFT (0x1 << 19)
7660	#define SECURE_SRAM_BOUND_SFT 0
7661	#define SECURE_SRAM_BOUND_MASK 0x7ffff
7662	#define SECURE_SRAM_BOUND_MASK_SFT (0x7ffff << 0)
7663
7664	/* AFE_SECURE_CON0 */
7665	#define READ_EN15_NS_SFT 31
7666	#define READ_EN15_NS_MASK 0x1
7667	#define READ_EN15_NS_MASK_SFT (0x1 << 31)
7668	#define WRITE_EN15_NS_SFT 30
7669	#define WRITE_EN15_NS_MASK 0x1
7670	#define WRITE_EN15_NS_MASK_SFT (0x1 << 30)
7671	#define READ_EN14_NS_SFT 29
7672	#define READ_EN14_NS_MASK 0x1
7673	#define READ_EN14_NS_MASK_SFT (0x1 << 29)
7674	#define WRITE_EN14_NS_SFT 28
7675	#define WRITE_EN14_NS_MASK 0x1
7676	#define WRITE_EN14_NS_MASK_SFT (0x1 << 28)
7677	#define READ_EN13_NS_SFT 27
7678	#define READ_EN13_NS_MASK 0x1
7679	#define READ_EN13_NS_MASK_SFT (0x1 << 27)
7680	#define WRITE_EN13_NS_SFT 26
7681	#define WRITE_EN13_NS_MASK 0x1
7682	#define WRITE_EN13_NS_MASK_SFT (0x1 << 26)
7683	#define READ_EN12_NS_SFT 25
7684	#define READ_EN12_NS_MASK 0x1
7685	#define READ_EN12_NS_MASK_SFT (0x1 << 25)
7686	#define WRITE_EN12_NS_SFT 24
7687	#define WRITE_EN12_NS_MASK 0x1
7688	#define WRITE_EN12_NS_MASK_SFT (0x1 << 24)
7689	#define READ_EN11_NS_SFT 23
7690	#define READ_EN11_NS_MASK 0x1
7691	#define READ_EN11_NS_MASK_SFT (0x1 << 23)
7692	#define WRITE_EN11_NS_SFT 22
7693	#define WRITE_EN11_NS_MASK 0x1
7694	#define WRITE_EN11_NS_MASK_SFT (0x1 << 22)
7695	#define READ_EN10_NS_SFT 21
7696	#define READ_EN10_NS_MASK 0x1
7697	#define READ_EN10_NS_MASK_SFT (0x1 << 21)
7698	#define WRITE_EN10_NS_SFT 20
7699	#define WRITE_EN10_NS_MASK 0x1
7700	#define WRITE_EN10_NS_MASK_SFT (0x1 << 20)
7701	#define READ_EN9_NS_SFT 19
7702	#define READ_EN9_NS_MASK 0x1
7703	#define READ_EN9_NS_MASK_SFT (0x1 << 19)
7704	#define WRITE_EN9_NS_SFT 18
7705	#define WRITE_EN9_NS_MASK 0x1
7706	#define WRITE_EN9_NS_MASK_SFT (0x1 << 18)
7707	#define READ_EN8_NS_SFT 17
7708	#define READ_EN8_NS_MASK 0x1
7709	#define READ_EN8_NS_MASK_SFT (0x1 << 17)
7710	#define WRITE_EN8_NS_SFT 16
7711	#define WRITE_EN8_NS_MASK 0x1
7712	#define WRITE_EN8_NS_MASK_SFT (0x1 << 16)
7713	#define READ_EN7_NS_SFT 15
7714	#define READ_EN7_NS_MASK 0x1
7715	#define READ_EN7_NS_MASK_SFT (0x1 << 15)
7716	#define WRITE_EN7_NS_SFT 14
7717	#define WRITE_EN7_NS_MASK 0x1
7718	#define WRITE_EN7_NS_MASK_SFT (0x1 << 14)
7719	#define READ_EN6_NS_SFT 13
7720	#define READ_EN6_NS_MASK 0x1
7721	#define READ_EN6_NS_MASK_SFT (0x1 << 13)
7722	#define WRITE_EN6_NS_SFT 12
7723	#define WRITE_EN6_NS_MASK 0x1
7724	#define WRITE_EN6_NS_MASK_SFT (0x1 << 12)
7725	#define READ_EN5_NS_SFT 11
7726	#define READ_EN5_NS_MASK 0x1
7727	#define READ_EN5_NS_MASK_SFT (0x1 << 11)
7728	#define WRITE_EN5_NS_SFT 10
7729	#define WRITE_EN5_NS_MASK 0x1
7730	#define WRITE_EN5_NS_MASK_SFT (0x1 << 10)
7731	#define READ_EN4_NS_SFT 9
7732	#define READ_EN4_NS_MASK 0x1
7733	#define READ_EN4_NS_MASK_SFT (0x1 << 9)
7734	#define WRITE_EN4_NS_SFT 8
7735	#define WRITE_EN4_NS_MASK 0x1
7736	#define WRITE_EN4_NS_MASK_SFT (0x1 << 8)
7737	#define READ_EN3_NS_SFT 7
7738	#define READ_EN3_NS_MASK 0x1
7739	#define READ_EN3_NS_MASK_SFT (0x1 << 7)
7740	#define WRITE_EN3_NS_SFT 6
7741	#define WRITE_EN3_NS_MASK 0x1
7742	#define WRITE_EN3_NS_MASK_SFT (0x1 << 6)
7743	#define READ_EN2_NS_SFT 5
7744	#define READ_EN2_NS_MASK 0x1
7745	#define READ_EN2_NS_MASK_SFT (0x1 << 5)
7746	#define WRITE_EN2_NS_SFT 4
7747	#define WRITE_EN2_NS_MASK 0x1
7748	#define WRITE_EN2_NS_MASK_SFT (0x1 << 4)
7749	#define READ_EN1_NS_SFT 3
7750	#define READ_EN1_NS_MASK 0x1
7751	#define READ_EN1_NS_MASK_SFT (0x1 << 3)
7752	#define WRITE_EN1_NS_SFT 2
7753	#define WRITE_EN1_NS_MASK 0x1
7754	#define WRITE_EN1_NS_MASK_SFT (0x1 << 2)
7755	#define READ_EN0_NS_SFT 1
7756	#define READ_EN0_NS_MASK 0x1
7757	#define READ_EN0_NS_MASK_SFT (0x1 << 1)
7758	#define WRITE_EN0_NS_SFT 0
7759	#define WRITE_EN0_NS_MASK 0x1
7760	#define WRITE_EN0_NS_MASK_SFT (0x1 << 0)
7761
7762	/* AFE_SECURE_CON1 */
7763	#define READ_EN15_S_SFT 31
7764	#define READ_EN15_S_MASK 0x1
7765	#define READ_EN15_S_MASK_SFT (0x1 << 31)
7766	#define WRITE_EN15_S_SFT 30
7767	#define WRITE_EN15_S_MASK 0x1
7768	#define WRITE_EN15_S_MASK_SFT (0x1 << 30)
7769	#define READ_EN14_S_SFT 29
7770	#define READ_EN14_S_MASK 0x1
7771	#define READ_EN14_S_MASK_SFT (0x1 << 29)
7772	#define WRITE_EN14_S_SFT 28
7773	#define WRITE_EN14_S_MASK 0x1
7774	#define WRITE_EN14_S_MASK_SFT (0x1 << 28)
7775	#define READ_EN13_S_SFT 27
7776	#define READ_EN13_S_MASK 0x1
7777	#define READ_EN13_S_MASK_SFT (0x1 << 27)
7778	#define WRITE_EN13_S_SFT 26
7779	#define WRITE_EN13_S_MASK 0x1
7780	#define WRITE_EN13_S_MASK_SFT (0x1 << 26)
7781	#define READ_EN12_S_SFT 25
7782	#define READ_EN12_S_MASK 0x1
7783	#define READ_EN12_S_MASK_SFT (0x1 << 25)
7784	#define WRITE_EN12_S_SFT 24
7785	#define WRITE_EN12_S_MASK 0x1
7786	#define WRITE_EN12_S_MASK_SFT (0x1 << 24)
7787	#define READ_EN11_S_SFT 23
7788	#define READ_EN11_S_MASK 0x1
7789	#define READ_EN11_S_MASK_SFT (0x1 << 23)
7790	#define WRITE_EN11_S_SFT 22
7791	#define WRITE_EN11_S_MASK 0x1
7792	#define WRITE_EN11_S_MASK_SFT (0x1 << 22)
7793	#define READ_EN10_S_SFT 21
7794	#define READ_EN10_S_MASK 0x1
7795	#define READ_EN10_S_MASK_SFT (0x1 << 21)
7796	#define WRITE_EN10_S_SFT 20
7797	#define WRITE_EN10_S_MASK 0x1
7798	#define WRITE_EN10_S_MASK_SFT (0x1 << 20)
7799	#define READ_EN9_S_SFT 19
7800	#define READ_EN9_S_MASK 0x1
7801	#define READ_EN9_S_MASK_SFT (0x1 << 19)
7802	#define WRITE_EN9_S_SFT 18
7803	#define WRITE_EN9_S_MASK 0x1
7804	#define WRITE_EN9_S_MASK_SFT (0x1 << 18)
7805	#define READ_EN8_S_SFT 17
7806	#define READ_EN8_S_MASK 0x1
7807	#define READ_EN8_S_MASK_SFT (0x1 << 17)
7808	#define WRITE_EN8_S_SFT 16
7809	#define WRITE_EN8_S_MASK 0x1
7810	#define WRITE_EN8_S_MASK_SFT (0x1 << 16)
7811	#define READ_EN7_S_SFT 15
7812	#define READ_EN7_S_MASK 0x1
7813	#define READ_EN7_S_MASK_SFT (0x1 << 15)
7814	#define WRITE_EN7_S_SFT 14
7815	#define WRITE_EN7_S_MASK 0x1
7816	#define WRITE_EN7_S_MASK_SFT (0x1 << 14)
7817	#define READ_EN6_S_SFT 13
7818	#define READ_EN6_S_MASK 0x1
7819	#define READ_EN6_S_MASK_SFT (0x1 << 13)
7820	#define WRITE_EN6_S_SFT 12
7821	#define WRITE_EN6_S_MASK 0x1
7822	#define WRITE_EN6_S_MASK_SFT (0x1 << 12)
7823	#define READ_EN5_S_SFT 11
7824	#define READ_EN5_S_MASK 0x1
7825	#define READ_EN5_S_MASK_SFT (0x1 << 11)
7826	#define WRITE_EN5_S_SFT 10
7827	#define WRITE_EN5_S_MASK 0x1
7828	#define WRITE_EN5_S_MASK_SFT (0x1 << 10)
7829	#define READ_EN4_S_SFT 9
7830	#define READ_EN4_S_MASK 0x1
7831	#define READ_EN4_S_MASK_SFT (0x1 << 9)
7832	#define WRITE_EN4_S_SFT 8
7833	#define WRITE_EN4_S_MASK 0x1
7834	#define WRITE_EN4_S_MASK_SFT (0x1 << 8)
7835	#define READ_EN3_S_SFT 7
7836	#define READ_EN3_S_MASK 0x1
7837	#define READ_EN3_S_MASK_SFT (0x1 << 7)
7838	#define WRITE_EN3_S_SFT 6
7839	#define WRITE_EN3_S_MASK 0x1
7840	#define WRITE_EN3_S_MASK_SFT (0x1 << 6)
7841	#define READ_EN2_S_SFT 5
7842	#define READ_EN2_S_MASK 0x1
7843	#define READ_EN2_S_MASK_SFT (0x1 << 5)
7844	#define WRITE_EN2_S_SFT 4
7845	#define WRITE_EN2_S_MASK 0x1
7846	#define WRITE_EN2_S_MASK_SFT (0x1 << 4)
7847	#define READ_EN1_S_SFT 3
7848	#define READ_EN1_S_MASK 0x1
7849	#define READ_EN1_S_MASK_SFT (0x1 << 3)
7850	#define WRITE_EN1_S_SFT 2
7851	#define WRITE_EN1_S_MASK 0x1
7852	#define WRITE_EN1_S_MASK_SFT (0x1 << 2)
7853	#define READ_EN0_S_SFT 1
7854	#define READ_EN0_S_MASK 0x1
7855	#define READ_EN0_S_MASK_SFT (0x1 << 1)
7856	#define WRITE_EN0_S_SFT 0
7857	#define WRITE_EN0_S_MASK 0x1
7858	#define WRITE_EN0_S_MASK_SFT (0x1 << 0)
7859
7860	/* AFE_SE_SECURE_CON0 */
7861	#define AFE_HDMI_SE_SECURE_BIT_SFT 11
7862	#define AFE_HDMI_SE_SECURE_BIT_MASK 0x1
7863	#define AFE_HDMI_SE_SECURE_BIT_MASK_SFT (0x1 << 11)
7864	#define AFE_SPDIF2_OUT_SE_SECURE_BIT_SFT 10
7865	#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK 0x1
7866	#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
7867	#define AFE_SPDIF_OUT_SE_SECURE_BIT_SFT 9
7868	#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK 0x1
7869	#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
7870	#define AFE_DL8_SE_SECURE_BIT_SFT 8
7871	#define AFE_DL8_SE_SECURE_BIT_MASK 0x1
7872	#define AFE_DL8_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
7873	#define AFE_DL7_SE_SECURE_BIT_SFT 7
7874	#define AFE_DL7_SE_SECURE_BIT_MASK 0x1
7875	#define AFE_DL7_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
7876	#define AFE_DL6_SE_SECURE_BIT_SFT 6
7877	#define AFE_DL6_SE_SECURE_BIT_MASK 0x1
7878	#define AFE_DL6_SE_SECURE_BIT_MASK_SFT (0x1 << 6)
7879	#define AFE_DL5_SE_SECURE_BIT_SFT 5
7880	#define AFE_DL5_SE_SECURE_BIT_MASK 0x1
7881	#define AFE_DL5_SE_SECURE_BIT_MASK_SFT (0x1 << 5)
7882	#define AFE_DL4_SE_SECURE_BIT_SFT 4
7883	#define AFE_DL4_SE_SECURE_BIT_MASK 0x1
7884	#define AFE_DL4_SE_SECURE_BIT_MASK_SFT (0x1 << 4)
7885	#define AFE_DL3_SE_SECURE_BIT_SFT 3
7886	#define AFE_DL3_SE_SECURE_BIT_MASK 0x1
7887	#define AFE_DL3_SE_SECURE_BIT_MASK_SFT (0x1 << 3)
7888	#define AFE_DL2_SE_SECURE_BIT_SFT 2
7889	#define AFE_DL2_SE_SECURE_BIT_MASK 0x1
7890	#define AFE_DL2_SE_SECURE_BIT_MASK_SFT (0x1 << 2)
7891	#define AFE_DL1_SE_SECURE_BIT_SFT 1
7892	#define AFE_DL1_SE_SECURE_BIT_MASK 0x1
7893	#define AFE_DL1_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
7894	#define AFE_DL0_SE_SECURE_BIT_SFT 0
7895	#define AFE_DL0_SE_SECURE_BIT_MASK 0x1
7896	#define AFE_DL0_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
7897
7898	/* AFE_SE_SECURE_CON1 */
7899	#define AFE_DL46_SE_SECURE_BIT_SFT 26
7900	#define AFE_DL46_SE_SECURE_BIT_MASK 0x1
7901	#define AFE_DL46_SE_SECURE_BIT_MASK_SFT (0x1 << 26)
7902	#define AFE_DL45_SE_SECURE_BIT_SFT 25
7903	#define AFE_DL45_SE_SECURE_BIT_MASK 0x1
7904	#define AFE_DL45_SE_SECURE_BIT_MASK_SFT (0x1 << 25)
7905	#define AFE_DL44_SE_SECURE_BIT_SFT 24
7906	#define AFE_DL44_SE_SECURE_BIT_MASK 0x1
7907	#define AFE_DL44_SE_SECURE_BIT_MASK_SFT (0x1 << 24)
7908	#define AFE_DL43_SE_SECURE_BIT_SFT 23
7909	#define AFE_DL43_SE_SECURE_BIT_MASK 0x1
7910	#define AFE_DL43_SE_SECURE_BIT_MASK_SFT (0x1 << 23)
7911	#define AFE_DL42_SE_SECURE_BIT_SFT 22
7912	#define AFE_DL42_SE_SECURE_BIT_MASK 0x1
7913	#define AFE_DL42_SE_SECURE_BIT_MASK_SFT (0x1 << 22)
7914	#define AFE_DL41_SE_SECURE_BIT_SFT 21
7915	#define AFE_DL41_SE_SECURE_BIT_MASK 0x1
7916	#define AFE_DL41_SE_SECURE_BIT_MASK_SFT (0x1 << 21)
7917	#define AFE_DL40_SE_SECURE_BIT_SFT 20
7918	#define AFE_DL40_SE_SECURE_BIT_MASK 0x1
7919	#define AFE_DL40_SE_SECURE_BIT_MASK_SFT (0x1 << 20)
7920	#define AFE_DL39_SE_SECURE_BIT_SFT 19
7921	#define AFE_DL39_SE_SECURE_BIT_MASK 0x1
7922	#define AFE_DL39_SE_SECURE_BIT_MASK_SFT (0x1 << 19)
7923	#define AFE_DL38_SE_SECURE_BIT_SFT 18
7924	#define AFE_DL38_SE_SECURE_BIT_MASK 0x1
7925	#define AFE_DL38_SE_SECURE_BIT_MASK_SFT (0x1 << 18)
7926	#define AFE_DL37_SE_SECURE_BIT_SFT 17
7927	#define AFE_DL37_SE_SECURE_BIT_MASK 0x1
7928	#define AFE_DL37_SE_SECURE_BIT_MASK_SFT (0x1 << 17)
7929	#define AFE_DL36_SE_SECURE_BIT_SFT 16
7930	#define AFE_DL36_SE_SECURE_BIT_MASK 0x1
7931	#define AFE_DL36_SE_SECURE_BIT_MASK_SFT (0x1 << 16)
7932	#define AFE_DL35_SE_SECURE_BIT_SFT 15
7933	#define AFE_DL35_SE_SECURE_BIT_MASK 0x1
7934	#define AFE_DL35_SE_SECURE_BIT_MASK_SFT (0x1 << 15)
7935	#define AFE_DL34_SE_SECURE_BIT_SFT 14
7936	#define AFE_DL34_SE_SECURE_BIT_MASK 0x1
7937	#define AFE_DL34_SE_SECURE_BIT_MASK_SFT (0x1 << 14)
7938	#define AFE_DL33_SE_SECURE_BIT_SFT 13
7939	#define AFE_DL33_SE_SECURE_BIT_MASK 0x1
7940	#define AFE_DL33_SE_SECURE_BIT_MASK_SFT (0x1 << 13)
7941	#define AFE_DL32_SE_SECURE_BIT_SFT 12
7942	#define AFE_DL32_SE_SECURE_BIT_MASK 0x1
7943	#define AFE_DL32_SE_SECURE_BIT_MASK_SFT (0x1 << 12)
7944	#define AFE_DL31_SE_SECURE_BIT_SFT 11
7945	#define AFE_DL31_SE_SECURE_BIT_MASK 0x1
7946	#define AFE_DL31_SE_SECURE_BIT_MASK_SFT (0x1 << 11)
7947	#define AFE_DL30_SE_SECURE_BIT_SFT 10
7948	#define AFE_DL30_SE_SECURE_BIT_MASK 0x1
7949	#define AFE_DL30_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
7950	#define AFE_DL29_SE_SECURE_BIT_SFT 9
7951	#define AFE_DL29_SE_SECURE_BIT_MASK 0x1
7952	#define AFE_DL29_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
7953	#define AFE_DL28_SE_SECURE_BIT_SFT 8
7954	#define AFE_DL28_SE_SECURE_BIT_MASK 0x1
7955	#define AFE_DL28_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
7956	#define AFE_DL27_SE_SECURE_BIT_SFT 7
7957	#define AFE_DL27_SE_SECURE_BIT_MASK 0x1
7958	#define AFE_DL27_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
7959	#define AFE_DL26_SE_SECURE_BIT_SFT 6
7960	#define AFE_DL26_SE_SECURE_BIT_MASK 0x1
7961	#define AFE_DL26_SE_SECURE_BIT_MASK_SFT (0x1 << 6)
7962	#define AFE_DL25_SE_SECURE_BIT_SFT 5
7963	#define AFE_DL25_SE_SECURE_BIT_MASK 0x1
7964	#define AFE_DL25_SE_SECURE_BIT_MASK_SFT (0x1 << 5)
7965	#define AFE_DL24_SE_SECURE_BIT_SFT 4
7966	#define AFE_DL24_SE_SECURE_BIT_MASK 0x1
7967	#define AFE_DL24_SE_SECURE_BIT_MASK_SFT (0x1 << 4)
7968	#define AFE_DL23_SE_SECURE_BIT_SFT 3
7969	#define AFE_DL23_SE_SECURE_BIT_MASK 0x1
7970	#define AFE_DL23_SE_SECURE_BIT_MASK_SFT (0x1 << 3)
7971	#define AFE_DL_48CH_SE_SECURE_BIT_SFT 2
7972	#define AFE_DL_48CH_SE_SECURE_BIT_MASK 0x1
7973	#define AFE_DL_48CH_SE_SECURE_BIT_MASK_SFT (0x1 << 2)
7974	#define AFE_DL_24CH_SE_SECURE_BIT_SFT 1
7975	#define AFE_DL_24CH_SE_SECURE_BIT_MASK 0x1
7976	#define AFE_DL_24CH_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
7977	#define AFE_DL_4CH_SE_SECURE_BIT_SFT 0
7978	#define AFE_DL_4CH_SE_SECURE_BIT_MASK 0x1
7979	#define AFE_DL_4CH_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
7980
7981	/* AFE_SE_SECURE_CON2 */
7982	#define AFE_VUL38_SE_SECURE_BIT_SFT 28
7983	#define AFE_VUL38_SE_SECURE_BIT_MASK 0x1
7984	#define AFE_VUL38_SE_SECURE_BIT_MASK_SFT (0x1 << 28)
7985	#define AFE_VUL37_SE_SECURE_BIT_SFT 27
7986	#define AFE_VUL37_SE_SECURE_BIT_MASK 0x1
7987	#define AFE_VUL37_SE_SECURE_BIT_MASK_SFT (0x1 << 27)
7988	#define AFE_VUL36_SE_SECURE_BIT_SFT 26
7989	#define AFE_VUL36_SE_SECURE_BIT_MASK 0x1
7990	#define AFE_VUL36_SE_SECURE_BIT_MASK_SFT (0x1 << 26)
7991	#define AFE_VUL35_SE_SECURE_BIT_SFT 25
7992	#define AFE_VUL35_SE_SECURE_BIT_MASK 0x1
7993	#define AFE_VUL35_SE_SECURE_BIT_MASK_SFT (0x1 << 25)
7994	#define AFE_VUL34_SE_SECURE_BIT_SFT 24
7995	#define AFE_VUL34_SE_SECURE_BIT_MASK 0x1
7996	#define AFE_VUL34_SE_SECURE_BIT_MASK_SFT (0x1 << 24)
7997	#define AFE_VUL33_SE_SECURE_BIT_SFT 23
7998	#define AFE_VUL33_SE_SECURE_BIT_MASK 0x1
7999	#define AFE_VUL33_SE_SECURE_BIT_MASK_SFT (0x1 << 23)
8000	#define AFE_VUL32_SE_SECURE_BIT_SFT 22
8001	#define AFE_VUL32_SE_SECURE_BIT_MASK 0x1
8002	#define AFE_VUL32_SE_SECURE_BIT_MASK_SFT (0x1 << 22)
8003	#define AFE_VUL31_SE_SECURE_BIT_SFT 21
8004	#define AFE_VUL31_SE_SECURE_BIT_MASK 0x1
8005	#define AFE_VUL31_SE_SECURE_BIT_MASK_SFT (0x1 << 21)
8006	#define AFE_VUL30_SE_SECURE_BIT_SFT 20
8007	#define AFE_VUL30_SE_SECURE_BIT_MASK 0x1
8008	#define AFE_VUL30_SE_SECURE_BIT_MASK_SFT (0x1 << 20)
8009	#define AFE_VUL29_SE_SECURE_BIT_SFT 19
8010	#define AFE_VUL29_SE_SECURE_BIT_MASK 0x1
8011	#define AFE_VUL29_SE_SECURE_BIT_MASK_SFT (0x1 << 19)
8012	#define AFE_VUL28_SE_SECURE_BIT_SFT 18
8013	#define AFE_VUL28_SE_SECURE_BIT_MASK 0x1
8014	#define AFE_VUL28_SE_SECURE_BIT_MASK_SFT (0x1 << 18)
8015	#define AFE_VUL27_SE_SECURE_BIT_SFT 17
8016	#define AFE_VUL27_SE_SECURE_BIT_MASK 0x1
8017	#define AFE_VUL27_SE_SECURE_BIT_MASK_SFT (0x1 << 17)
8018	#define AFE_VUL26_SE_SECURE_BIT_SFT 16
8019	#define AFE_VUL26_SE_SECURE_BIT_MASK 0x1
8020	#define AFE_VUL26_SE_SECURE_BIT_MASK_SFT (0x1 << 16)
8021	#define AFE_VUL25_SE_SECURE_BIT_SFT 15
8022	#define AFE_VUL25_SE_SECURE_BIT_MASK 0x1
8023	#define AFE_VUL25_SE_SECURE_BIT_MASK_SFT (0x1 << 15)
8024	#define AFE_VUL24_SE_SECURE_BIT_SFT 14
8025	#define AFE_VUL24_SE_SECURE_BIT_MASK 0x1
8026	#define AFE_VUL24_SE_SECURE_BIT_MASK_SFT (0x1 << 14)
8027	#define AFE_VUL_CM2_SE_SECURE_BIT_SFT 13
8028	#define AFE_VUL_CM2_SE_SECURE_BIT_MASK 0x1
8029	#define AFE_VUL_CM2_SE_SECURE_BIT_MASK_SFT (0x1 << 13)
8030	#define AFE_VUL_CM1_SE_SECURE_BIT_SFT 12
8031	#define AFE_VUL_CM1_SE_SECURE_BIT_MASK 0x1
8032	#define AFE_VUL_CM1_SE_SECURE_BIT_MASK_SFT (0x1 << 12)
8033	#define AFE_VUL_CM0_SE_SECURE_BIT_SFT 11
8034	#define AFE_VUL_CM0_SE_SECURE_BIT_MASK 0x1
8035	#define AFE_VUL_CM0_SE_SECURE_BIT_MASK_SFT (0x1 << 11)
8036	#define AFE_VUL10_SE_SECURE_BIT_SFT 10
8037	#define AFE_VUL10_SE_SECURE_BIT_MASK 0x1
8038	#define AFE_VUL10_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
8039	#define AFE_VUL9_SE_SECURE_BIT_SFT 9
8040	#define AFE_VUL9_SE_SECURE_BIT_MASK 0x1
8041	#define AFE_VUL9_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
8042	#define AFE_VUL8_SE_SECURE_BIT_SFT 8
8043	#define AFE_VUL8_SE_SECURE_BIT_MASK 0x1
8044	#define AFE_VUL8_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
8045	#define AFE_VUL7_SE_SECURE_BIT_SFT 7
8046	#define AFE_VUL7_SE_SECURE_BIT_MASK 0x1
8047	#define AFE_VUL7_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
8048	#define AFE_VUL6_SE_SECURE_BIT_SFT 6
8049	#define AFE_VUL6_SE_SECURE_BIT_MASK 0x1
8050	#define AFE_VUL6_SE_SECURE_BIT_MASK_SFT (0x1 << 6)
8051	#define AFE_VUL5_SE_SECURE_BIT_SFT 5
8052	#define AFE_VUL5_SE_SECURE_BIT_MASK 0x1
8053	#define AFE_VUL5_SE_SECURE_BIT_MASK_SFT (0x1 << 5)
8054	#define AFE_VUL4_SE_SECURE_BIT_SFT 4
8055	#define AFE_VUL4_SE_SECURE_BIT_MASK 0x1
8056	#define AFE_VUL4_SE_SECURE_BIT_MASK_SFT (0x1 << 4)
8057	#define AFE_VUL3_SE_SECURE_BIT_SFT 3
8058	#define AFE_VUL3_SE_SECURE_BIT_MASK 0x1
8059	#define AFE_VUL3_SE_SECURE_BIT_MASK_SFT (0x1 << 3)
8060	#define AFE_VUL2_SE_SECURE_BIT_SFT 2
8061	#define AFE_VUL2_SE_SECURE_BIT_MASK 0x1
8062	#define AFE_VUL2_SE_SECURE_BIT_MASK_SFT (0x1 << 2)
8063	#define AFE_VUL1_SE_SECURE_BIT_SFT 1
8064	#define AFE_VUL1_SE_SECURE_BIT_MASK 0x1
8065	#define AFE_VUL1_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
8066	#define AFE_VUL0_SE_SECURE_BIT_SFT 0
8067	#define AFE_VUL0_SE_SECURE_BIT_MASK 0x1
8068	#define AFE_VUL0_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
8069
8070	/* AFE_SE_SECURE_CON3 */
8071	#define AFE_SPDIFIN_SE_SECURE_BIT_SFT 10
8072	#define AFE_SPDIFIN_SE_SECURE_BIT_MASK 0x1
8073	#define AFE_SPDIFIN_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
8074	#define AFE_TDM_IN_SE_SECURE_BIT_SFT 9
8075	#define AFE_TDM_IN_SE_SECURE_BIT_MASK 0x1
8076	#define AFE_TDM_IN_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
8077	#define AFE_MPHONE_EARC_SE_SECURE_BIT_SFT 8
8078	#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK 0x1
8079	#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
8080	#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_SFT 7
8081	#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK 0x1
8082	#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
8083	#define AFE_ETDM_IN1_SE_SECURE_BIT_SFT 1
8084	#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK 0x1
8085	#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
8086	#define AFE_ETDM_IN0_SE_SECURE_BIT_SFT 0
8087	#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK 0x1
8088	#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
8089
8090	/* AFE_SE_PROT_SIDEBAND0 */
8091	#define HDMI_HPROT_SFT 11
8092	#define HDMI_HPROT_MASK 0x1
8093	#define HDMI_HPROT_MASK_SFT (0x1 << 11)
8094	#define SPDIF2_OUT_HPROT_SFT 10
8095	#define SPDIF2_OUT_HPROT_MASK 0x1
8096	#define SPDIF2_OUT_HPROT_MASK_SFT (0x1 << 10)
8097	#define SPDIF_OUT_HPROT_SFT 9
8098	#define SPDIF_OUT_HPROT_MASK 0x1
8099	#define SPDIF_OUT_HPROT_MASK_SFT (0x1 << 9)
8100	#define DL8_HPROT_SFT 8
8101	#define DL8_HPROT_MASK 0x1
8102	#define DL8_HPROT_MASK_SFT (0x1 << 8)
8103	#define DL7_HPROT_SFT 7
8104	#define DL7_HPROT_MASK 0x1
8105	#define DL7_HPROT_MASK_SFT (0x1 << 7)
8106	#define DL6_HPROT_SFT 6
8107	#define DL6_HPROT_MASK 0x1
8108	#define DL6_HPROT_MASK_SFT (0x1 << 6)
8109	#define DL5_HPROT_SFT 5
8110	#define DL5_HPROT_MASK 0x1
8111	#define DL5_HPROT_MASK_SFT (0x1 << 5)
8112	#define DL4_HPROT_SFT 4
8113	#define DL4_HPROT_MASK 0x1
8114	#define DL4_HPROT_MASK_SFT (0x1 << 4)
8115	#define DL3_HPROT_SFT 3
8116	#define DL3_HPROT_MASK 0x1
8117	#define DL3_HPROT_MASK_SFT (0x1 << 3)
8118	#define DL2_HPROT_SFT 2
8119	#define DL2_HPROT_MASK 0x1
8120	#define DL2_HPROT_MASK_SFT (0x1 << 2)
8121	#define DL1_HPROT_SFT 1
8122	#define DL1_HPROT_MASK 0x1
8123	#define DL1_HPROT_MASK_SFT (0x1 << 1)
8124	#define DL0_HPROT_SFT 0
8125	#define DL0_HPROT_MASK 0x1
8126	#define DL0_HPROT_MASK_SFT (0x1 << 0)
8127
8128	/* AFE_SE_PROT_SIDEBAND1 */
8129	#define DL46_HPROT_SFT 26
8130	#define DL46_HPROT_MASK 0x1
8131	#define DL46_HPROT_MASK_SFT (0x1 << 26)
8132	#define DL45_HPROT_SFT 25
8133	#define DL45_HPROT_MASK 0x1
8134	#define DL45_HPROT_MASK_SFT (0x1 << 25)
8135	#define DL44_HPROT_SFT 24
8136	#define DL44_HPROT_MASK 0x1
8137	#define DL44_HPROT_MASK_SFT (0x1 << 24)
8138	#define DL43_HPROT_SFT 23
8139	#define DL43_HPROT_MASK 0x1
8140	#define DL43_HPROT_MASK_SFT (0x1 << 23)
8141	#define DL42_HPROT_SFT 22
8142	#define DL42_HPROT_MASK 0x1
8143	#define DL42_HPROT_MASK_SFT (0x1 << 22)
8144	#define DL41_HPROT_SFT 21
8145	#define DL41_HPROT_MASK 0x1
8146	#define DL41_HPROT_MASK_SFT (0x1 << 21)
8147	#define DL40_HPROT_SFT 20
8148	#define DL40_HPROT_MASK 0x1
8149	#define DL40_HPROT_MASK_SFT (0x1 << 20)
8150	#define DL39_HPROT_SFT 19
8151	#define DL39_HPROT_MASK 0x1
8152	#define DL39_HPROT_MASK_SFT (0x1 << 19)
8153	#define DL38_HPROT_SFT 18
8154	#define DL38_HPROT_MASK 0x1
8155	#define DL38_HPROT_MASK_SFT (0x1 << 18)
8156	#define DL37_HPROT_SFT 17
8157	#define DL37_HPROT_MASK 0x1
8158	#define DL37_HPROT_MASK_SFT (0x1 << 17)
8159	#define DL36_HPROT_SFT 16
8160	#define DL36_HPROT_MASK 0x1
8161	#define DL36_HPROT_MASK_SFT (0x1 << 16)
8162	#define DL35_HPROT_SFT 15
8163	#define DL35_HPROT_MASK 0x1
8164	#define DL35_HPROT_MASK_SFT (0x1 << 15)
8165	#define DL34_HPROT_SFT 14
8166	#define DL34_HPROT_MASK 0x1
8167	#define DL34_HPROT_MASK_SFT (0x1 << 14)
8168	#define DL33_HPROT_SFT 13
8169	#define DL33_HPROT_MASK 0x1
8170	#define DL33_HPROT_MASK_SFT (0x1 << 13)
8171	#define DL32_HPROT_SFT 12
8172	#define DL32_HPROT_MASK 0x1
8173	#define DL32_HPROT_MASK_SFT (0x1 << 12)
8174	#define DL31_HPROT_SFT 11
8175	#define DL31_HPROT_MASK 0x1
8176	#define DL31_HPROT_MASK_SFT (0x1 << 11)
8177	#define DL30_HPROT_SFT 10
8178	#define DL30_HPROT_MASK 0x1
8179	#define DL30_HPROT_MASK_SFT (0x1 << 10)
8180	#define DL29_HPROT_SFT 9
8181	#define DL29_HPROT_MASK 0x1
8182	#define DL29_HPROT_MASK_SFT (0x1 << 9)
8183	#define DL28_HPROT_SFT 8
8184	#define DL28_HPROT_MASK 0x1
8185	#define DL28_HPROT_MASK_SFT (0x1 << 8)
8186	#define DL27_HPROT_SFT 7
8187	#define DL27_HPROT_MASK 0x1
8188	#define DL27_HPROT_MASK_SFT (0x1 << 7)
8189	#define DL26_HPROT_SFT 6
8190	#define DL26_HPROT_MASK 0x1
8191	#define DL26_HPROT_MASK_SFT (0x1 << 6)
8192	#define DL25_HPROT_SFT 5
8193	#define DL25_HPROT_MASK 0x1
8194	#define DL25_HPROT_MASK_SFT (0x1 << 5)
8195	#define DL24_HPROT_SFT 4
8196	#define DL24_HPROT_MASK 0x1
8197	#define DL24_HPROT_MASK_SFT (0x1 << 4)
8198	#define DL23_HPROT_SFT 3
8199	#define DL23_HPROT_MASK 0x1
8200	#define DL23_HPROT_MASK_SFT (0x1 << 3)
8201	#define DL_48CH_PROT_SFT 2
8202	#define DL_48CH_PROT_MASK 0x1
8203	#define DL_48CH_PROT_MASK_SFT (0x1 << 2)
8204	#define DL_24CH_PROT_SFT 1
8205	#define DL_24CH_PROT_MASK 0x1
8206	#define DL_24CH_PROT_MASK_SFT (0x1 << 1)
8207	#define DL_4CH_PROT_SFT 0
8208	#define DL_4CH_PROT_MASK 0x1
8209	#define DL_4CH_PROT_MASK_SFT (0x1 << 0)
8210
8211	/* AFE_SE_PROT_SIDEBAND2 */
8212	#define VUL38_HPROT_SFT 28
8213	#define VUL38_HPROT_MASK 0x1
8214	#define VUL38_HPROT_MASK_SFT (0x1 << 28)
8215	#define VUL37_HPROT_SFT 27
8216	#define VUL37_HPROT_MASK 0x1
8217	#define VUL37_HPROT_MASK_SFT (0x1 << 27)
8218	#define VUL36_HPROT_SFT 26
8219	#define VUL36_HPROT_MASK 0x1
8220	#define VUL36_HPROT_MASK_SFT (0x1 << 26)
8221	#define VUL35_HPROT_SFT 25
8222	#define VUL35_HPROT_MASK 0x1
8223	#define VUL35_HPROT_MASK_SFT (0x1 << 25)
8224	#define VUL34_HPROT_SFT 24
8225	#define VUL34_HPROT_MASK 0x1
8226	#define VUL34_HPROT_MASK_SFT (0x1 << 24)
8227	#define VUL33_HPROT_SFT 23
8228	#define VUL33_HPROT_MASK 0x1
8229	#define VUL33_HPROT_MASK_SFT (0x1 << 23)
8230	#define VUL32_HPROT_SFT 22
8231	#define VUL32_HPROT_MASK 0x1
8232	#define VUL32_HPROT_MASK_SFT (0x1 << 22)
8233	#define VUL31_HPROT_SFT 21
8234	#define VUL31_HPROT_MASK 0x1
8235	#define VUL31_HPROT_MASK_SFT (0x1 << 21)
8236	#define VUL30_HPROT_SFT 20
8237	#define VUL30_HPROT_MASK 0x1
8238	#define VUL30_HPROT_MASK_SFT (0x1 << 20)
8239	#define VUL29_HPROT_SFT 19
8240	#define VUL29_HPROT_MASK 0x1
8241	#define VUL29_HPROT_MASK_SFT (0x1 << 19)
8242	#define VUL28_HPROT_SFT 18
8243	#define VUL28_HPROT_MASK 0x1
8244	#define VUL28_HPROT_MASK_SFT (0x1 << 18)
8245	#define VUL27_HPROT_SFT 17
8246	#define VUL27_HPROT_MASK 0x1
8247	#define VUL27_HPROT_MASK_SFT (0x1 << 17)
8248	#define VUL26_HPROT_SFT 16
8249	#define VUL26_HPROT_MASK 0x1
8250	#define VUL26_HPROT_MASK_SFT (0x1 << 16)
8251	#define VUL25_HPROT_SFT 15
8252	#define VUL25_HPROT_MASK 0x1
8253	#define VUL25_HPROT_MASK_SFT (0x1 << 15)
8254	#define VUL24_HPROT_SFT 14
8255	#define VUL24_HPROT_MASK 0x1
8256	#define VUL24_HPROT_MASK_SFT (0x1 << 14)
8257	#define VUL_CM2_HPROT_SFT 13
8258	#define VUL_CM2_HPROT_MASK 0x1
8259	#define VUL_CM2_HPROT_MASK_SFT (0x1 << 13)
8260	#define VUL_CM1_HPROT_SFT 12
8261	#define VUL_CM1_HPROT_MASK 0x1
8262	#define VUL_CM1_HPROT_MASK_SFT (0x1 << 12)
8263	#define VUL_CM0_HPROT_SFT 11
8264	#define VUL_CM0_HPROT_MASK 0x1
8265	#define VUL_CM0_HPROT_MASK_SFT (0x1 << 11)
8266	#define VUL10_HPROT_SFT 10
8267	#define VUL10_HPROT_MASK 0x1
8268	#define VUL10_HPROT_MASK_SFT (0x1 << 10)
8269	#define VUL9_HPROT_SFT 9
8270	#define VUL9_HPROT_MASK 0x1
8271	#define VUL9_HPROT_MASK_SFT (0x1 << 9)
8272	#define VUL8_HPROT_SFT 8
8273	#define VUL8_HPROT_MASK 0x1
8274	#define VUL8_HPROT_MASK_SFT (0x1 << 8)
8275	#define VUL7_HPROT_SFT 7
8276	#define VUL7_HPROT_MASK 0x1
8277	#define VUL7_HPROT_MASK_SFT (0x1 << 7)
8278	#define VUL6_HPROT_SFT 6
8279	#define VUL6_HPROT_MASK 0x1
8280	#define VUL6_HPROT_MASK_SFT (0x1 << 6)
8281	#define VUL5_HPROT_SFT 5
8282	#define VUL5_HPROT_MASK 0x1
8283	#define VUL5_HPROT_MASK_SFT (0x1 << 5)
8284	#define VUL4_HPROT_SFT 4
8285	#define VUL4_HPROT_MASK 0x1
8286	#define VUL4_HPROT_MASK_SFT (0x1 << 4)
8287	#define VUL3_HPROT_SFT 3
8288	#define VUL3_HPROT_MASK 0x1
8289	#define VUL3_HPROT_MASK_SFT (0x1 << 3)
8290	#define VUL2_HPROT_SFT 2
8291	#define VUL2_HPROT_MASK 0x1
8292	#define VUL2_HPROT_MASK_SFT (0x1 << 2)
8293	#define VUL1_HPROT_SFT 1
8294	#define VUL1_HPROT_MASK 0x1
8295	#define VUL1_HPROT_MASK_SFT (0x1 << 1)
8296	#define VUL0_HPROT_SFT 0
8297	#define VUL0_HPROT_MASK 0x1
8298	#define VUL0_HPROT_MASK_SFT (0x1 << 0)
8299
8300	/* AFE_SE_PROT_SIDEBAND3 */
8301	#define MPHONE_EARC_HPROT_SFT 10
8302	#define MPHONE_EARC_HPROT_MASK 0x1
8303	#define MPHONE_EARC_HPROT_MASK_SFT (0x1 << 10)
8304	#define MPHONE_SPDIF_HPROT_SFT 9
8305	#define MPHONE_SPDIF_HPROT_MASK 0x1
8306	#define MPHONE_SPDIF_HPROT_MASK_SFT (0x1 << 9)
8307	#define SPDIFIN_HPROT_SFT 8
8308	#define SPDIFIN_HPROT_MASK 0x1
8309	#define SPDIFIN_HPROT_MASK_SFT (0x1 << 8)
8310	#define TDMIN_HPROT_SFT 7
8311	#define TDMIN_HPROT_MASK 0x1
8312	#define TDMIN_HPROT_MASK_SFT (0x1 << 7)
8313	#define ETDM_IN1_HPROT_SFT 1
8314	#define ETDM_IN1_HPROT_MASK 0x1
8315	#define ETDM_IN1_HPROT_MASK_SFT (0x1 << 1)
8316	#define ETDM_IN0_HPROT_SFT 0
8317	#define ETDM_IN0_HPROT_MASK 0x1
8318	#define ETDM_IN0_HPROT_MASK_SFT (0x1 << 0)
8319
8320	/* AFE_SE_DOMAIN_SIDEBAND0 */
8321	#define DL7_HDOMAIN_SFT 28
8322	#define DL7_HDOMAIN_MASK 0xf
8323	#define DL7_HDOMAIN_MASK_SFT (0xf << 28)
8324	#define DL6_HDOMAIN_SFT 24
8325	#define DL6_HDOMAIN_MASK 0xf
8326	#define DL6_HDOMAIN_MASK_SFT (0xf << 24)
8327	#define DL5_HDOMAIN_SFT 20
8328	#define DL5_HDOMAIN_MASK 0xf
8329	#define DL5_HDOMAIN_MASK_SFT (0xf << 20)
8330	#define DL4_HDOMAIN_SFT 16
8331	#define DL4_HDOMAIN_MASK 0xf
8332	#define DL4_HDOMAIN_MASK_SFT (0xf << 16)
8333	#define DL3_HDOMAIN_SFT 12
8334	#define DL3_HDOMAIN_MASK 0xf
8335	#define DL3_HDOMAIN_MASK_SFT (0xf << 12)
8336	#define DL2_HDOMAIN_SFT 8
8337	#define DL2_HDOMAIN_MASK 0xf
8338	#define DL2_HDOMAIN_MASK_SFT (0xf << 8)
8339	#define DL1_HDOMAIN_SFT 4
8340	#define DL1_HDOMAIN_MASK 0xf
8341	#define DL1_HDOMAIN_MASK_SFT (0xf << 4)
8342	#define DL0_HDOMAIN_SFT 0
8343	#define DL0_HDOMAIN_MASK 0xf
8344	#define DL0_HDOMAIN_MASK_SFT (0xf << 0)
8345
8346	/* AFE_SE_DOMAIN_SIDEBAND1 */
8347	#define DL_48CH_HDOMAIN_SFT 24
8348	#define DL_48CH_HDOMAIN_MASK 0xf
8349	#define DL_48CH_HDOMAIN_MASK_SFT (0xf << 24)
8350	#define DL_24CH_HDOMAIN_SFT 20
8351	#define DL_24CH_HDOMAIN_MASK 0xf
8352	#define DL_24CH_HDOMAIN_MASK_SFT (0xf << 20)
8353	#define DL_4CH_HDOMAIN_SFT 16
8354	#define DL_4CH_HDOMAIN_MASK 0xf
8355	#define DL_4CH_HDOMAIN_MASK_SFT (0xf << 16)
8356	#define HDMI_HDOMAIN_SFT 12
8357	#define HDMI_HDOMAIN_MASK 0xf
8358	#define HDMI_HDOMAIN_MASK_SFT (0xf << 12)
8359	#define SPDIF2_OUT_HDOMAIN_SFT 8
8360	#define SPDIF2_OUT_HDOMAIN_MASK 0xf
8361	#define SPDIF2_OUT_HDOMAIN_MASK_SFT (0xf << 8)
8362	#define SPDIF_OUT_HDOMAIN_SFT 4
8363	#define SPDIF_OUT_HDOMAIN_MASK 0xf
8364	#define SPDIF_OUT_HDOMAIN_MASK_SFT (0xf << 4)
8365	#define DL8_HDOMAIN_SFT 0
8366	#define DL8_HDOMAIN_MASK 0xf
8367	#define DL8_HDOMAIN_MASK_SFT (0xf << 0)
8368
8369	/* AFE_SE_DOMAIN_SIDEBAND2 */
8370	#define DL30_HDOMAIN_SFT 28
8371	#define DL30_HDOMAIN_MASK 0xf
8372	#define DL30_HDOMAIN_MASK_SFT (0xf << 28)
8373	#define DL29_HDOMAIN_SFT 24
8374	#define DL29_HDOMAIN_MASK 0xf
8375	#define DL29_HDOMAIN_MASK_SFT (0xf << 24)
8376	#define DL28_HDOMAIN_SFT 20
8377	#define DL28_HDOMAIN_MASK 0xf
8378	#define DL28_HDOMAIN_MASK_SFT (0xf << 20)
8379	#define DL27_HDOMAIN_SFT 16
8380	#define DL27_HDOMAIN_MASK 0xf
8381	#define DL27_HDOMAIN_MASK_SFT (0xf << 16)
8382	#define DL26_HDOMAIN_SFT 12
8383	#define DL26_HDOMAIN_MASK 0xf
8384	#define DL26_HDOMAIN_MASK_SFT (0xf << 12)
8385	#define DL25_HDOMAIN_SFT 8
8386	#define DL25_HDOMAIN_MASK 0xf
8387	#define DL25_HDOMAIN_MASK_SFT (0xf << 8)
8388	#define DL24_HDOMAIN_SFT 4
8389	#define DL24_HDOMAIN_MASK 0xf
8390	#define DL24_HDOMAIN_MASK_SFT (0xf << 4)
8391	#define DL23_HDOMAIN_SFT 0
8392	#define DL23_HDOMAIN_MASK 0xf
8393	#define DL23_HDOMAIN_MASK_SFT (0xf << 0)
8394
8395	/* AFE_SE_DOMAIN_SIDEBAND3 */
8396	#define DL38_HDOMAIN_SFT 28
8397	#define DL38_HDOMAIN_MASK 0xf
8398	#define DL38_HDOMAIN_MASK_SFT (0xf << 28)
8399	#define DL37_HDOMAIN_SFT 24
8400	#define DL37_HDOMAIN_MASK 0xf
8401	#define DL37_HDOMAIN_MASK_SFT (0xf << 24)
8402	#define DL36_HDOMAIN_SFT 20
8403	#define DL36_HDOMAIN_MASK 0xf
8404	#define DL36_HDOMAIN_MASK_SFT (0xf << 20)
8405	#define DL35_HDOMAIN_SFT 16
8406	#define DL35_HDOMAIN_MASK 0xf
8407	#define DL35_HDOMAIN_MASK_SFT (0xf << 16)
8408	#define DL34_HDOMAIN_SFT 12
8409	#define DL34_HDOMAIN_MASK 0xf
8410	#define DL34_HDOMAIN_MASK_SFT (0xf << 12)
8411	#define DL33_HDOMAIN_SFT 8
8412	#define DL33_HDOMAIN_MASK 0xf
8413	#define DL33_HDOMAIN_MASK_SFT (0xf << 8)
8414	#define DL32_HDOMAIN_SFT 4
8415	#define DL32_HDOMAIN_MASK 0xf
8416	#define DL32_HDOMAIN_MASK_SFT (0xf << 4)
8417	#define DL31_HDOMAIN_SFT 0
8418	#define DL31_HDOMAIN_MASK 0xf
8419	#define DL31_HDOMAIN_MASK_SFT (0xf << 0)
8420
8421	/* AFE_SE_DOMAIN_SIDEBAND4 */
8422	#define DL46_HDOMAIN_SFT 28
8423	#define DL46_HDOMAIN_MASK 0xf
8424	#define DL46_HDOMAIN_MASK_SFT (0xf << 28)
8425	#define DL45_HDOMAIN_SFT 24
8426	#define DL45_HDOMAIN_MASK 0xf
8427	#define DL45_HDOMAIN_MASK_SFT (0xf << 24)
8428	#define DL44_HDOMAIN_SFT 20
8429	#define DL44_HDOMAIN_MASK 0xf
8430	#define DL44_HDOMAIN_MASK_SFT (0xf << 20)
8431	#define DL43_HDOMAIN_SFT 16
8432	#define DL43_HDOMAIN_MASK 0xf
8433	#define DL43_HDOMAIN_MASK_SFT (0xf << 16)
8434	#define DL42_HDOMAIN_SFT 12
8435	#define DL42_HDOMAIN_MASK 0xf
8436	#define DL42_HDOMAIN_MASK_SFT (0xf << 12)
8437	#define DL41_HDOMAIN_SFT 8
8438	#define DL41_HDOMAIN_MASK 0xf
8439	#define DL41_HDOMAIN_MASK_SFT (0xf << 8)
8440	#define DL40_HDOMAIN_SFT 4
8441	#define DL40_HDOMAIN_MASK 0xf
8442	#define DL40_HDOMAIN_MASK_SFT (0xf << 4)
8443	#define DL39_HDOMAIN_SFT 0
8444	#define DL39_HDOMAIN_MASK 0xf
8445	#define DL39_HDOMAIN_MASK_SFT (0xf << 0)
8446
8447	/* AFE_SE_DOMAIN_SIDEBAND5 */
8448	#define VUL7_HDOMAIN_SFT 28
8449	#define VUL7_HDOMAIN_MASK 0xf
8450	#define VUL7_HDOMAIN_MASK_SFT (0xf << 28)
8451	#define VUL6_HDOMAIN_SFT 24
8452	#define VUL6_HDOMAIN_MASK 0xf
8453	#define VUL6_HDOMAIN_MASK_SFT (0xf << 24)
8454	#define VUL5_HDOMAIN_SFT 20
8455	#define VUL5_HDOMAIN_MASK 0xf
8456	#define VUL5_HDOMAIN_MASK_SFT (0xf << 20)
8457	#define VUL4_HDOMAIN_SFT 16
8458	#define VUL4_HDOMAIN_MASK 0xf
8459	#define VUL4_HDOMAIN_MASK_SFT (0xf << 16)
8460	#define VUL3_HDOMAIN_SFT 12
8461	#define VUL3_HDOMAIN_MASK 0xf
8462	#define VUL3_HDOMAIN_MASK_SFT (0xf << 12)
8463	#define VUL2_HDOMAIN_SFT 8
8464	#define VUL2_HDOMAIN_MASK 0xf
8465	#define VUL2_HDOMAIN_MASK_SFT (0xf << 8)
8466	#define VUL1_HDOMAIN_SFT 4
8467	#define VUL1_HDOMAIN_MASK 0xf
8468	#define VUL1_HDOMAIN_MASK_SFT (0xf << 4)
8469	#define VUL0_HDOMAIN_SFT 0
8470	#define VUL0_HDOMAIN_MASK 0xf
8471	#define VUL0_HDOMAIN_MASK_SFT (0xf << 0)
8472
8473	/* AFE_SE_DOMAIN_SIDEBAND6 */
8474	#define VU25_HDOMAIN_SFT 28
8475	#define VU25_HDOMAIN_MASK 0xf
8476	#define VU25_HDOMAIN_MASK_SFT (0xf << 28)
8477	#define VUL24_HDOMAIN_SFT 24
8478	#define VUL24_HDOMAIN_MASK 0xf
8479	#define VUL24_HDOMAIN_MASK_SFT (0xf << 24)
8480	#define VUL_CM2_HDOMAIN_SFT 20
8481	#define VUL_CM2_HDOMAIN_MASK 0xf
8482	#define VUL_CM2_HDOMAIN_MASK_SFT (0xf << 20)
8483	#define VUL_CM1_HDOMAIN_SFT 16
8484	#define VUL_CM1_HDOMAIN_MASK 0xf
8485	#define VUL_CM1_HDOMAIN_MASK_SFT (0xf << 16)
8486	#define VUL_CM0_HDOMAIN_SFT 12
8487	#define VUL_CM0_HDOMAIN_MASK 0xf
8488	#define VUL_CM0_HDOMAIN_MASK_SFT (0xf << 12)
8489	#define VUL10_HDOMAIN_SFT 8
8490	#define VUL10_HDOMAIN_MASK 0xf
8491	#define VUL10_HDOMAIN_MASK_SFT (0xf << 8)
8492	#define VUL9_HDOMAIN_SFT 4
8493	#define VUL9_HDOMAIN_MASK 0xf
8494	#define VUL9_HDOMAIN_MASK_SFT (0xf << 4)
8495	#define VUL8_HDOMAIN_SFT 0
8496	#define VUL8_HDOMAIN_MASK 0xf
8497	#define VUL8_HDOMAIN_MASK_SFT (0xf << 0)
8498
8499	/* AFE_SE_DOMAIN_SIDEBAND7 */
8500	#define VUL33_HDOMAIN_SFT 28
8501	#define VUL33_HDOMAIN_MASK 0xf
8502	#define VUL33_HDOMAIN_MASK_SFT (0xf << 28)
8503	#define VUL32_HDOMAIN_SFT 24
8504	#define VUL32_HDOMAIN_MASK 0xf
8505	#define VUL32_HDOMAIN_MASK_SFT (0xf << 24)
8506	#define VUL31_HDOMAIN_SFT 20
8507	#define VUL31_HDOMAIN_MASK 0xf
8508	#define VUL31_HDOMAIN_MASK_SFT (0xf << 20)
8509	#define VUL30_HDOMAIN_SFT 16
8510	#define VUL30_HDOMAIN_MASK 0xf
8511	#define VUL30_HDOMAIN_MASK_SFT (0xf << 16)
8512	#define VUL29_HDOMAIN_SFT 12
8513	#define VUL29_HDOMAIN_MASK 0xf
8514	#define VUL29_HDOMAIN_MASK_SFT (0xf << 12)
8515	#define VUL28_HDOMAIN_SFT 8
8516	#define VUL28_HDOMAIN_MASK 0xf
8517	#define VUL28_HDOMAIN_MASK_SFT (0xf << 8)
8518	#define VUL27_HDOMAIN_SFT 4
8519	#define VUL27_HDOMAIN_MASK 0xf
8520	#define VUL27_HDOMAIN_MASK_SFT (0xf << 4)
8521	#define VUL26_HDOMAIN_SFT 0
8522	#define VUL26_HDOMAIN_MASK 0xf
8523	#define VUL26_HDOMAIN_MASK_SFT (0xf << 0)
8524
8525	/* AFE_SE_DOMAIN_SIDEBAND8 */
8526	#define ETDM_IN1_HDOMAIN_SFT 24
8527	#define ETDM_IN1_HDOMAIN_MASK 0xf
8528	#define ETDM_IN1_HDOMAIN_MASK_SFT (0xf << 24)
8529	#define ETDM_IN0_HDOMAIN_SFT 20
8530	#define ETDM_IN0_HDOMAIN_MASK 0xf
8531	#define ETDM_IN0_HDOMAIN_MASK_SFT (0xf << 20)
8532	#define VUL38_HDOMAIN_SFT 16
8533	#define VUL38_HDOMAIN_MASK 0xf
8534	#define VUL38_HDOMAIN_MASK_SFT (0xf << 16)
8535	#define VUL37_HDOMAIN_SFT 12
8536	#define VUL37_HDOMAIN_MASK 0xf
8537	#define VUL37_HDOMAIN_MASK_SFT (0xf << 12)
8538	#define VUL36_HDOMAIN_SFT 8
8539	#define VUL36_HDOMAIN_MASK 0xf
8540	#define VUL36_HDOMAIN_MASK_SFT (0xf << 8)
8541	#define VUL35_HDOMAIN_SFT 4
8542	#define VUL35_HDOMAIN_MASK 0xf
8543	#define VUL35_HDOMAIN_MASK_SFT (0xf << 4)
8544	#define VUL34_HDOMAIN_SFT 0
8545	#define VUL34_HDOMAIN_MASK 0xf
8546	#define VUL34_HDOMAIN_MASK_SFT (0xf << 0)
8547
8548	/* AFE_SE_DOMAIN_SIDEBAND9 */
8549	#define MPHONE_EARC_HDOMAIN_SFT 28
8550	#define MPHONE_EARC_HDOMAIN_MASK 0xf
8551	#define MPHONE_EARC_HDOMAIN_MASK_SFT (0xf << 28)
8552	#define MPHONE_SPDIF_HDOMAIN_SFT 24
8553	#define MPHONE_SPDIF_HDOMAIN_MASK 0xf
8554	#define MPHONE_SPDIF_HDOMAIN_MASK_SFT (0xf << 24)
8555	#define SPDIFIN_HDOMAIN_SFT 20
8556	#define SPDIFIN_HDOMAIN_MASK 0xf
8557	#define SPDIFIN_HDOMAIN_MASK_SFT (0xf << 20)
8558	#define TDMIN_HDOMAIN_SFT 16
8559	#define TDMIN_HDOMAIN_MASK 0xf
8560	#define TDMIN_HDOMAIN_MASK_SFT (0xf << 16)
8561
8562	/* AFE_PROT_SIDEBAND0_MON */
8563	#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0
8564	#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff
8565	#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0)
8566
8567	/* AFE_PROT_SIDEBAND1_MON */
8568	#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0
8569	#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff
8570	#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0)
8571
8572	/* AFE_PROT_SIDEBAND2_MON */
8573	#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
8574	#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
8575	#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
8576
8577	/* AFE_PROT_SIDEBAND3_MON */
8578	#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
8579	#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
8580	#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
8581
8582	/* AFE_DOMAIN_SIDEBAND0_MON */
8583	#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0
8584	#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff
8585	#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0)
8586
8587	/* AFE_DOMAIN_SIDEBAND1_MON */
8588	#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0
8589	#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff
8590	#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0)
8591
8592	/* AFE_DOMAIN_SIDEBAND2_MON */
8593	#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
8594	#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
8595	#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
8596
8597	/* AFE_DOMAIN_SIDEBAND3_MON */
8598	#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
8599	#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
8600	#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
8601
8602	/* AFE_DOMAIN_SIDEBAND4_MON */
8603	#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0
8604	#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff
8605	#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0)
8606
8607	/* AFE_DOMAIN_SIDEBAND5_MON */
8608	#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0
8609	#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff
8610	#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0)
8611
8612	/* AFE_DOMAIN_SIDEBAND6_MON */
8613	#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
8614	#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
8615	#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
8616
8617	/* AFE_DOMAIN_SIDEBAND7_MON */
8618	#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
8619	#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
8620	#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
8621
8622	/* AFE_DOMAIN_SIDEBAND8_MON */
8623	#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
8624	#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
8625	#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
8626
8627	/* AFE_DOMAIN_SIDEBAND9_MON */
8628	#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
8629	#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
8630	#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
8631
8632	/* AFE_SECURE_CONN0 */
8633	#define AFE_SPDIFIN_LPBK_CON_MASK_S_SFT 26
8634	#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK 0x3
8635	#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK_SFT (0x3 << 26)
8636	#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_SFT 25
8637	#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK 0x1
8638	#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK_SFT (0x1 << 25)
8639	#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_SFT 24
8640	#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK 0x1
8641	#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK_SFT (0x1 << 24)
8642	#define AFE_ADDA_UL3_SRC_CON0_MASK_S_SFT 23
8643	#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK 0x1
8644	#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK_SFT (0x1 << 23)
8645	#define AFE_ADDA_UL2_SRC_CON0_MASK_S_SFT 22
8646	#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK 0x1
8647	#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK_SFT (0x1 << 22)
8648	#define AFE_ADDA_UL1_SRC_CON0_MASK_S_SFT 21
8649	#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK 0x1
8650	#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK_SFT (0x1 << 21)
8651	#define AFE_ADDA_UL0_SRC_CON0_MASK_S_SFT 20
8652	#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK 0x1
8653	#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK_SFT (0x1 << 20)
8654	#define AFE_MRKAIF1_CFG0_MASK_S_SFT 19
8655	#define AFE_MRKAIF1_CFG0_MASK_S_MASK 0x1
8656	#define AFE_MRKAIF1_CFG0_MASK_S_MASK_SFT (0x1 << 19)
8657	#define AFE_MRKAIF0_CFG0_MASK_S_SFT 18
8658	#define AFE_MRKAIF0_CFG0_MASK_S_MASK 0x1
8659	#define AFE_MRKAIF0_CFG0_MASK_S_MASK_SFT (0x1 << 18)
8660	#define AFE_TDMIN_CON1_MASK_S_SFT 17
8661	#define AFE_TDMIN_CON1_MASK_S_MASK 0x1
8662	#define AFE_TDMIN_CON1_MASK_S_MASK_SFT (0x1 << 17)
8663	#define AFE_TDM_CON2_MASK_S_SFT 16
8664	#define AFE_TDM_CON2_MASK_S_MASK 0x1
8665	#define AFE_TDM_CON2_MASK_S_MASK_SFT (0x1 << 16)
8666	#define AFE_DAIBT_CON_MASK_S_SFT 14
8667	#define AFE_DAIBT_CON_MASK_S_MASK 0x3
8668	#define AFE_DAIBT_CON_MASK_S_MASK_SFT (0x3 << 14)
8669	#define AFE_MRGIF_CON_MASK_S_SFT 12
8670	#define AFE_MRGIF_CON_MASK_S_MASK 0x3
8671	#define AFE_MRGIF_CON_MASK_S_MASK_SFT (0x3 << 12)
8672	#define AFE_CONNSYS_I2S_CON_MASK_S_SFT 11
8673	#define AFE_CONNSYS_I2S_CON_MASK_S_MASK 0x1
8674	#define AFE_CONNSYS_I2S_CON_MASK_S_MASK_SFT (0x1 << 11)
8675	#define AFE_PCM1_INFT_CON0_MASK_S_SFT 6
8676	#define AFE_PCM1_INFT_CON0_MASK_S_MASK 0x1f
8677	#define AFE_PCM1_INFT_CON0_MASK_S_MASK_SFT (0x1f << 6)
8678	#define AFE_PCM0_INTF_CON1_MASK_S_SFT 0
8679	#define AFE_PCM0_INTF_CON1_MASK_S_MASK 0x3f
8680	#define AFE_PCM0_INTF_CON1_MASK_S_MASK_SFT (0x3f << 0)
8681
8682	/* AFE_SECURE_CONN_ETDM1 */
8683	#define ETDM1_4_7_COWORK_CON1_MASK_S_0_SFT 24
8684	#define ETDM1_4_7_COWORK_CON1_MASK_S_0_MASK 0xff
8685	#define ETDM1_4_7_COWORK_CON1_MASK_S_0_MASK_SFT (0xff << 24)
8686	#define ETDM1_4_7_COWORK_CON0_MASK_S_0_SFT 20
8687	#define ETDM1_4_7_COWORK_CON0_MASK_S_0_MASK 0xf
8688	#define ETDM1_4_7_COWORK_CON0_MASK_S_0_MASK_SFT (0xf << 20)
8689	#define ETDM1_4_7_COWORK_CON0_MASK_S_1_SFT 16
8690	#define ETDM1_4_7_COWORK_CON0_MASK_S_1_MASK 0xf
8691	#define ETDM1_4_7_COWORK_CON0_MASK_S_1_MASK_SFT (0xf << 16)
8692	#define ETDM1_0_3_COWORK_CON3_MASK_S_0_SFT 8
8693	#define ETDM1_0_3_COWORK_CON3_MASK_S_0_MASK 0xff
8694	#define ETDM1_0_3_COWORK_CON3_MASK_S_0_MASK_SFT (0xff << 8)
8695	#define ETDM1_0_3_COWORK_CON3_MASK_S_1_SFT 0
8696	#define ETDM1_0_3_COWORK_CON3_MASK_S_1_MASK 0xff
8697	#define ETDM1_0_3_COWORK_CON3_MASK_S_1_MASK_SFT (0xff << 0)
8698
8699	/* AFE_SECURE_CONN_ETDM2 */
8700	#define ETDM2_4_7_COWORK_CON3_MASK_S_0_SFT 24
8701	#define ETDM2_4_7_COWORK_CON3_MASK_S_0_MASK 0xff
8702	#define ETDM2_4_7_COWORK_CON3_MASK_S_0_MASK_SFT (0xff << 24)
8703	#define ETDM2_4_7_COWORK_CON3_MASK_S_1_SFT 16
8704	#define ETDM2_4_7_COWORK_CON3_MASK_S_1_MASK 0xff
8705	#define ETDM2_4_7_COWORK_CON3_MASK_S_1_MASK_SFT (0xff << 16)
8706	#define ETDM2_4_7_COWORK_CON2_MASK_S_0_SFT 12
8707	#define ETDM2_4_7_COWORK_CON2_MASK_S_0_MASK 0xf
8708	#define ETDM2_4_7_COWORK_CON2_MASK_S_0_MASK_SFT (0xf << 12)
8709	#define ETDM2_4_7_COWORK_CON2_MASK_S_1_SFT 8
8710	#define ETDM2_4_7_COWORK_CON2_MASK_S_1_MASK 0xf
8711	#define ETDM2_4_7_COWORK_CON2_MASK_S_1_MASK_SFT (0xf << 8)
8712	#define ETDM2_4_7_COWORK_CON1_MASK_S_0_SFT 0
8713	#define ETDM2_4_7_COWORK_CON1_MASK_S_0_MASK 0xff
8714	#define ETDM2_4_7_COWORK_CON1_MASK_S_0_MASK_SFT (0xff << 0)
8715
8716	/* AFE_SECURE_SRAM_CON0 */
8717	#define SRAM_READ_EN15_NS_SFT 31
8718	#define SRAM_READ_EN15_NS_MASK 0x1
8719	#define SRAM_READ_EN15_NS_MASK_SFT (0x1 << 31)
8720	#define SRAM_WRITE_EN15_NS_SFT 30
8721	#define SRAM_WRITE_EN15_NS_MASK 0x1
8722	#define SRAM_WRITE_EN15_NS_MASK_SFT (0x1 << 30)
8723	#define SRAM_READ_EN14_NS_SFT 29
8724	#define SRAM_READ_EN14_NS_MASK 0x1
8725	#define SRAM_READ_EN14_NS_MASK_SFT (0x1 << 29)
8726	#define SRAM_WRITE_EN14_NS_SFT 28
8727	#define SRAM_WRITE_EN14_NS_MASK 0x1
8728	#define SRAM_WRITE_EN14_NS_MASK_SFT (0x1 << 28)
8729	#define SRAM_READ_EN13_NS_SFT 27
8730	#define SRAM_READ_EN13_NS_MASK 0x1
8731	#define SRAM_READ_EN13_NS_MASK_SFT (0x1 << 27)
8732	#define SRAM_WRITE_EN13_NS_SFT 26
8733	#define SRAM_WRITE_EN13_NS_MASK 0x1
8734	#define SRAM_WRITE_EN13_NS_MASK_SFT (0x1 << 26)
8735	#define SRAM_READ_EN12_NS_SFT 25
8736	#define SRAM_READ_EN12_NS_MASK 0x1
8737	#define SRAM_READ_EN12_NS_MASK_SFT (0x1 << 25)
8738	#define SRAM_WRITE_EN12_NS_SFT 24
8739	#define SRAM_WRITE_EN12_NS_MASK 0x1
8740	#define SRAM_WRITE_EN12_NS_MASK_SFT (0x1 << 24)
8741	#define SRAM_READ_EN11_NS_SFT 23
8742	#define SRAM_READ_EN11_NS_MASK 0x1
8743	#define SRAM_READ_EN11_NS_MASK_SFT (0x1 << 23)
8744	#define SRAM_WRITE_EN11_NS_SFT 22
8745	#define SRAM_WRITE_EN11_NS_MASK 0x1
8746	#define SRAM_WRITE_EN11_NS_MASK_SFT (0x1 << 22)
8747	#define SRAM_READ_EN10_NS_SFT 21
8748	#define SRAM_READ_EN10_NS_MASK 0x1
8749	#define SRAM_READ_EN10_NS_MASK_SFT (0x1 << 21)
8750	#define SRAM_WRITE_EN10_NS_SFT 20
8751	#define SRAM_WRITE_EN10_NS_MASK 0x1
8752	#define SRAM_WRITE_EN10_NS_MASK_SFT (0x1 << 20)
8753	#define SRAM_READ_EN9_NS_SFT 19
8754	#define SRAM_READ_EN9_NS_MASK 0x1
8755	#define SRAM_READ_EN9_NS_MASK_SFT (0x1 << 19)
8756	#define SRAM_WRITE_EN9_NS_SFT 18
8757	#define SRAM_WRITE_EN9_NS_MASK 0x1
8758	#define SRAM_WRITE_EN9_NS_MASK_SFT (0x1 << 18)
8759	#define SRAM_READ_EN8_NS_SFT 17
8760	#define SRAM_READ_EN8_NS_MASK 0x1
8761	#define SRAM_READ_EN8_NS_MASK_SFT (0x1 << 17)
8762	#define SRAM_WRITE_EN8_NS_SFT 16
8763	#define SRAM_WRITE_EN8_NS_MASK 0x1
8764	#define SRAM_WRITE_EN8_NS_MASK_SFT (0x1 << 16)
8765	#define SRAM_READ_EN7_NS_SFT 15
8766	#define SRAM_READ_EN7_NS_MASK 0x1
8767	#define SRAM_READ_EN7_NS_MASK_SFT (0x1 << 15)
8768	#define SRAM_WRITE_EN7_NS_SFT 14
8769	#define SRAM_WRITE_EN7_NS_MASK 0x1
8770	#define SRAM_WRITE_EN7_NS_MASK_SFT (0x1 << 14)
8771	#define SRAM_READ_EN6_NS_SFT 13
8772	#define SRAM_READ_EN6_NS_MASK 0x1
8773	#define SRAM_READ_EN6_NS_MASK_SFT (0x1 << 13)
8774	#define SRAM_WRITE_EN6_NS_SFT 12
8775	#define SRAM_WRITE_EN6_NS_MASK 0x1
8776	#define SRAM_WRITE_EN6_NS_MASK_SFT (0x1 << 12)
8777	#define SRAM_READ_EN5_NS_SFT 11
8778	#define SRAM_READ_EN5_NS_MASK 0x1
8779	#define SRAM_READ_EN5_NS_MASK_SFT (0x1 << 11)
8780	#define SRAM_WRITE_EN5_NS_SFT 10
8781	#define SRAM_WRITE_EN5_NS_MASK 0x1
8782	#define SRAM_WRITE_EN5_NS_MASK_SFT (0x1 << 10)
8783	#define SRAM_READ_EN4_NS_SFT 9
8784	#define SRAM_READ_EN4_NS_MASK 0x1
8785	#define SRAM_READ_EN4_NS_MASK_SFT (0x1 << 9)
8786	#define SRAM_WRITE_EN4_NS_SFT 8
8787	#define SRAM_WRITE_EN4_NS_MASK 0x1
8788	#define SRAM_WRITE_EN4_NS_MASK_SFT (0x1 << 8)
8789	#define SRAM_READ_EN3_NS_SFT 7
8790	#define SRAM_READ_EN3_NS_MASK 0x1
8791	#define SRAM_READ_EN3_NS_MASK_SFT (0x1 << 7)
8792	#define SRAM_WRITE_EN3_NS_SFT 6
8793	#define SRAM_WRITE_EN3_NS_MASK 0x1
8794	#define SRAM_WRITE_EN3_NS_MASK_SFT (0x1 << 6)
8795	#define SRAM_READ_EN2_NS_SFT 5
8796	#define SRAM_READ_EN2_NS_MASK 0x1
8797	#define SRAM_READ_EN2_NS_MASK_SFT (0x1 << 5)
8798	#define SRAM_WRITE_EN2_NS_SFT 4
8799	#define SRAM_WRITE_EN2_NS_MASK 0x1
8800	#define SRAM_WRITE_EN2_NS_MASK_SFT (0x1 << 4)
8801	#define SRAM_READ_EN1_NS_SFT 3
8802	#define SRAM_READ_EN1_NS_MASK 0x1
8803	#define SRAM_READ_EN1_NS_MASK_SFT (0x1 << 3)
8804	#define SRAM_WRITE_EN1_NS_SFT 2
8805	#define SRAM_WRITE_EN1_NS_MASK 0x1
8806	#define SRAM_WRITE_EN1_NS_MASK_SFT (0x1 << 2)
8807	#define SRAM_READ_EN0_NS_SFT 1
8808	#define SRAM_READ_EN0_NS_MASK 0x1
8809	#define SRAM_READ_EN0_NS_MASK_SFT (0x1 << 1)
8810	#define SRAM_WRITE_EN0_NS_SFT 0
8811	#define SRAM_WRITE_EN0_NS_MASK 0x1
8812	#define SRAM_WRITE_EN0_NS_MASK_SFT (0x1 << 0)
8813
8814	/* AFE_SECURE_SRAM_CON1 */
8815	#define SRAM_READ_EN15_S_SFT 31
8816	#define SRAM_READ_EN15_S_MASK 0x1
8817	#define SRAM_READ_EN15_S_MASK_SFT (0x1 << 31)
8818	#define SRAM_WRITE_EN15_S_SFT 30
8819	#define SRAM_WRITE_EN15_S_MASK 0x1
8820	#define SRAM_WRITE_EN15_S_MASK_SFT (0x1 << 30)
8821	#define SRAM_READ_EN14_S_SFT 29
8822	#define SRAM_READ_EN14_S_MASK 0x1
8823	#define SRAM_READ_EN14_S_MASK_SFT (0x1 << 29)
8824	#define SRAM_WRITE_EN14_S_SFT 28
8825	#define SRAM_WRITE_EN14_S_MASK 0x1
8826	#define SRAM_WRITE_EN14_S_MASK_SFT (0x1 << 28)
8827	#define SRAM_READ_EN13_S_SFT 27
8828	#define SRAM_READ_EN13_S_MASK 0x1
8829	#define SRAM_READ_EN13_S_MASK_SFT (0x1 << 27)
8830	#define SRAM_WRITE_EN13_S_SFT 26
8831	#define SRAM_WRITE_EN13_S_MASK 0x1
8832	#define SRAM_WRITE_EN13_S_MASK_SFT (0x1 << 26)
8833	#define SRAM_READ_EN12_S_SFT 25
8834	#define SRAM_READ_EN12_S_MASK 0x1
8835	#define SRAM_READ_EN12_S_MASK_SFT (0x1 << 25)
8836	#define SRAM_WRITE_EN12_S_SFT 24
8837	#define SRAM_WRITE_EN12_S_MASK 0x1
8838	#define SRAM_WRITE_EN12_S_MASK_SFT (0x1 << 24)
8839	#define SRAM_READ_EN11_S_SFT 23
8840	#define SRAM_READ_EN11_S_MASK 0x1
8841	#define SRAM_READ_EN11_S_MASK_SFT (0x1 << 23)
8842	#define SRAM_WRITE_EN11_S_SFT 22
8843	#define SRAM_WRITE_EN11_S_MASK 0x1
8844	#define SRAM_WRITE_EN11_S_MASK_SFT (0x1 << 22)
8845	#define SRAM_READ_EN10_S_SFT 21
8846	#define SRAM_READ_EN10_S_MASK 0x1
8847	#define SRAM_READ_EN10_S_MASK_SFT (0x1 << 21)
8848	#define SRAM_WRITE_EN10_S_SFT 20
8849	#define SRAM_WRITE_EN10_S_MASK 0x1
8850	#define SRAM_WRITE_EN10_S_MASK_SFT (0x1 << 20)
8851	#define SRAM_READ_EN9_S_SFT 19
8852	#define SRAM_READ_EN9_S_MASK 0x1
8853	#define SRAM_READ_EN9_S_MASK_SFT (0x1 << 19)
8854	#define SRAM_WRITE_EN9_S_SFT 18
8855	#define SRAM_WRITE_EN9_S_MASK 0x1
8856	#define SRAM_WRITE_EN9_S_MASK_SFT (0x1 << 18)
8857	#define SRAM_READ_EN8_S_SFT 17
8858	#define SRAM_READ_EN8_S_MASK 0x1
8859	#define SRAM_READ_EN8_S_MASK_SFT (0x1 << 17)
8860	#define SRAM_WRITE_EN8_S_SFT 16
8861	#define SRAM_WRITE_EN8_S_MASK 0x1
8862	#define SRAM_WRITE_EN8_S_MASK_SFT (0x1 << 16)
8863	#define SRAM_READ_EN7_S_SFT 15
8864	#define SRAM_READ_EN7_S_MASK 0x1
8865	#define SRAM_READ_EN7_S_MASK_SFT (0x1 << 15)
8866	#define SRAM_WRITE_EN7_S_SFT 14
8867	#define SRAM_WRITE_EN7_S_MASK 0x1
8868	#define SRAM_WRITE_EN7_S_MASK_SFT (0x1 << 14)
8869	#define SRAM_READ_EN6_S_SFT 13
8870	#define SRAM_READ_EN6_S_MASK 0x1
8871	#define SRAM_READ_EN6_S_MASK_SFT (0x1 << 13)
8872	#define SRAM_WRITE_EN6_S_SFT 12
8873	#define SRAM_WRITE_EN6_S_MASK 0x1
8874	#define SRAM_WRITE_EN6_S_MASK_SFT (0x1 << 12)
8875	#define SRAM_READ_EN5_S_SFT 11
8876	#define SRAM_READ_EN5_S_MASK 0x1
8877	#define SRAM_READ_EN5_S_MASK_SFT (0x1 << 11)
8878	#define SRAM_WRITE_EN5_S_SFT 10
8879	#define SRAM_WRITE_EN5_S_MASK 0x1
8880	#define SRAM_WRITE_EN5_S_MASK_SFT (0x1 << 10)
8881	#define SRAM_READ_EN4_S_SFT 9
8882	#define SRAM_READ_EN4_S_MASK 0x1
8883	#define SRAM_READ_EN4_S_MASK_SFT (0x1 << 9)
8884	#define SRAM_WRITE_EN4_S_SFT 8
8885	#define SRAM_WRITE_EN4_S_MASK 0x1
8886	#define SRAM_WRITE_EN4_S_MASK_SFT (0x1 << 8)
8887	#define SRAM_READ_EN3_S_SFT 7
8888	#define SRAM_READ_EN3_S_MASK 0x1
8889	#define SRAM_READ_EN3_S_MASK_SFT (0x1 << 7)
8890	#define SRAM_WRITE_EN3_S_SFT 6
8891	#define SRAM_WRITE_EN3_S_MASK 0x1
8892	#define SRAM_WRITE_EN3_S_MASK_SFT (0x1 << 6)
8893	#define SRAM_READ_EN2_S_SFT 5
8894	#define SRAM_READ_EN2_S_MASK 0x1
8895	#define SRAM_READ_EN2_S_MASK_SFT (0x1 << 5)
8896	#define SRAM_WRITE_EN2_S_SFT 4
8897	#define SRAM_WRITE_EN2_S_MASK 0x1
8898	#define SRAM_WRITE_EN2_S_MASK_SFT (0x1 << 4)
8899	#define SRAM_READ_EN1_S_SFT 3
8900	#define SRAM_READ_EN1_S_MASK 0x1
8901	#define SRAM_READ_EN1_S_MASK_SFT (0x1 << 3)
8902	#define SRAM_WRITE_EN1_S_SFT 2
8903	#define SRAM_WRITE_EN1_S_MASK 0x1
8904	#define SRAM_WRITE_EN1_S_MASK_SFT (0x1 << 2)
8905	#define SRAM_READ_EN0_S_SFT 1
8906	#define SRAM_READ_EN0_S_MASK 0x1
8907	#define SRAM_READ_EN0_S_MASK_SFT (0x1 << 1)
8908	#define SRAM_WRITE_EN0_S_SFT 0
8909	#define SRAM_WRITE_EN0_S_MASK 0x1
8910	#define SRAM_WRITE_EN0_S_MASK_SFT (0x1 << 0)
8911
8912	/* AFE_SE_CONN_INPUT_MASK0 */
8913	#define SECURE_INTRCONN_I0_I31_S_SFT 0
8914	#define SECURE_INTRCONN_I0_I31_S_MASK 0xffffffff
8915	#define SECURE_INTRCONN_I0_I31_S_MASK_SFT (0xffffffff << 0)
8916
8917	/* AFE_SE_CONN_INPUT_MASK1 */
8918	#define SECURE_INTRCONN_I32_I63_S_SFT 0
8919	#define SECURE_INTRCONN_I32_I63_S_MASK 0xffffffff
8920	#define SECURE_INTRCONN_I32_I63_S_MASK_SFT (0xffffffff << 0)
8921
8922	/* AFE_SE_CONN_INPUT_MASK2 */
8923	#define SECURE_INTRCONN_I64_I95_S_SFT 0
8924	#define SECURE_INTRCONN_I64_I95_S_MASK 0xffffffff
8925	#define SECURE_INTRCONN_I64_I95_S_MASK_SFT (0xffffffff << 0)
8926
8927	/* AFE_SE_CONN_INPUT_MASK3 */
8928	#define SECURE_INTRCONN_I96_I127_S_SFT 0
8929	#define SECURE_INTRCONN_I96_I127_S_MASK 0xffffffff
8930	#define SECURE_INTRCONN_I96_I127_S_MASK_SFT (0xffffffff << 0)
8931
8932	/* AFE_SE_CONN_INPUT_MASK4 */
8933	#define SECURE_INTRCONN_I128_I159_S_SFT 0
8934	#define SECURE_INTRCONN_I128_I159_S_MASK 0xffffffff
8935	#define SECURE_INTRCONN_I128_I159_S_MASK_SFT (0xffffffff << 0)
8936
8937	/* AFE_SE_CONN_INPUT_MASK5 */
8938	#define SECURE_INTRCONN_I160_I191_S_SFT 0
8939	#define SECURE_INTRCONN_I160_I191_S_MASK 0xffffffff
8940	#define SECURE_INTRCONN_I160_I191_S_MASK_SFT (0xffffffff << 0)
8941
8942	/* AFE_SE_CONN_INPUT_MASK6 */
8943	#define SECURE_INTRCONN_I192_I223_S_SFT 0
8944	#define SECURE_INTRCONN_I192_I223_S_MASK 0xffffffff
8945	#define SECURE_INTRCONN_I192_I223_S_MASK_SFT (0xffffffff << 0)
8946
8947	/* AFE_SE_CONN_INPUT_MASK7 */
8948	#define SECURE_INTRCONN_I224_I256_S_SFT 0
8949	#define SECURE_INTRCONN_I224_I256_S_MASK 0xffffffff
8950	#define SECURE_INTRCONN_I224_I256_S_MASK_SFT (0xffffffff << 0)
8951
8952	/* AFE_NON_SE_CONN_INPUT_MASK0 */
8953	#define NORMAL_INTRCONN_I0_I31_S_SFT 0
8954	#define NORMAL_INTRCONN_I0_I31_S_MASK 0xffffffff
8955	#define NORMAL_INTRCONN_I0_I31_S_MASK_SFT (0xffffffff << 0)
8956
8957	/* AFE_NON_SE_CONN_INPUT_MASK1 */
8958	#define NORMAL_INTRCONN_I32_I63_S_SFT 0
8959	#define NORMAL_INTRCONN_I32_I63_S_MASK 0xffffffff
8960	#define NORMAL_INTRCONN_I32_I63_S_MASK_SFT (0xffffffff << 0)
8961
8962	/* AFE_NON_SE_CONN_INPUT_MASK2 */
8963	#define NORMAL_INTRCONN_I64_I95_S_SFT 0
8964	#define NORMAL_INTRCONN_I64_I95_S_MASK 0xffffffff
8965	#define NORMAL_INTRCONN_I64_I95_S_MASK_SFT (0xffffffff << 0)
8966
8967	/* AFE_NON_SE_CONN_INPUT_MASK3 */
8968	#define NORMAL_INTRCONN_I96_I127_S_SFT 0
8969	#define NORMAL_INTRCONN_I96_I127_S_MASK 0xffffffff
8970	#define NORMAL_INTRCONN_I96_I127_S_MASK_SFT (0xffffffff << 0)
8971
8972	/* AFE_NON_SE_CONN_INPUT_MASK4 */
8973	#define NORMAL_INTRCONN_I128_I159_S_SFT 0
8974	#define NORMAL_INTRCONN_I128_I159_S_MASK 0xffffffff
8975	#define NORMAL_INTRCONN_I128_I159_S_MASK_SFT (0xffffffff << 0)
8976
8977	/* AFE_NON_SE_CONN_INPUT_MASK5 */
8978	#define NORMAL_INTRCONN_I160_I191_S_SFT 0
8979	#define NORMAL_INTRCONN_I160_I191_S_MASK 0xffffffff
8980	#define NORMAL_INTRCONN_I160_I191_S_MASK_SFT (0xffffffff << 0)
8981
8982	/* AFE_NON_SE_CONN_INPUT_MASK6 */
8983	#define NORMAL_INTRCONN_I192_I223_S_SFT 0
8984	#define NORMAL_INTRCONN_I192_I223_S_MASK 0xffffffff
8985	#define NORMAL_INTRCONN_I192_I223_S_MASK_SFT (0xffffffff << 0)
8986
8987	/* AFE_NON_SE_CONN_INPUT_MASK7 */
8988	#define NORMAL_INTRCONN_I224_I256_S_SFT 0
8989	#define NORMAL_INTRCONN_I224_I256_S_MASK 0xffffffff
8990	#define NORMAL_INTRCONN_I224_I256_S_MASK_SFT (0xffffffff << 0)
8991
8992	/* AFE_SE_CONN_OUTPUT_SEL0 */
8993	#define SECURE_INTRCONN_O0_O31_S_SFT 0
8994	#define SECURE_INTRCONN_O0_O31_S_MASK 0xffffffff
8995	#define SECURE_INTRCONN_O0_O31_S_MASK_SFT (0xffffffff << 0)
8996
8997	/* AFE_SE_CONN_OUTPUT_SEL1 */
8998	#define SECURE_INTRCONN_O32_O63_S_SFT 0
8999	#define SECURE_INTRCONN_O32_O63_S_MASK 0xffffffff
9000	#define SECURE_INTRCONN_O32_O63_S_MASK_SFT (0xffffffff << 0)
9001
9002	/* AFE_SE_CONN_OUTPUT_SEL2 */
9003	#define SECURE_INTRCONN_O64_O95_S_SFT 0
9004	#define SECURE_INTRCONN_O64_O95_S_MASK 0xffffffff
9005	#define SECURE_INTRCONN_O64_O95_S_MASK_SFT (0xffffffff << 0)
9006
9007	/* AFE_SE_CONN_OUTPUT_SEL3 */
9008	#define SECURE_INTRCONN_O96_O127_S_SFT 0
9009	#define SECURE_INTRCONN_O96_O127_S_MASK 0xffffffff
9010	#define SECURE_INTRCONN_O96_O127_S_MASK_SFT (0xffffffff << 0)
9011
9012	/* AFE_SE_CONN_OUTPUT_SEL4 */
9013	#define SECURE_INTRCONN_O128_O159_S_SFT 0
9014	#define SECURE_INTRCONN_O128_O159_S_MASK 0xffffffff
9015	#define SECURE_INTRCONN_O128_O159_S_MASK_SFT (0xffffffff << 0)
9016
9017	/* AFE_SE_CONN_OUTPUT_SEL5 */
9018	#define SECURE_INTRCONN_O160_O191_S_SFT 0
9019	#define SECURE_INTRCONN_O160_O191_S_MASK 0xffffffff
9020	#define SECURE_INTRCONN_O160_O191_S_MASK_SFT (0xffffffff << 0)
9021
9022	/* AFE_SE_CONN_OUTPUT_SEL6 */
9023	#define SECURE_INTRCONN_O192_O223_S_SFT 0
9024	#define SECURE_INTRCONN_O192_O223_S_MASK 0xffffffff
9025	#define SECURE_INTRCONN_O192_O223_S_MASK_SFT (0xffffffff << 0)
9026
9027	/* AFE_SE_CONN_OUTPUT_SEL7 */
9028	#define SECURE_INTRCONN_O224_O256_S_SFT 0
9029	#define SECURE_INTRCONN_O224_O256_S_MASK 0xffffffff
9030	#define SECURE_INTRCONN_O224_O256_S_MASK_SFT (0xffffffff << 0)
9031
9032	/* AFE_PCM0_INTF_CON1_MASK_MON */
9033	#define AFE_PCM0_INTF_CON1_MASK_MON_SFT 0
9034	#define AFE_PCM0_INTF_CON1_MASK_MON_MASK 0xffffffff
9035	#define AFE_PCM0_INTF_CON1_MASK_MON_MASK_SFT (0xffffffff << 0)
9036
9037	/* AFE_PCM0_INTF_CON0_MASK_MON */
9038	#define AFE_PCM0_INTF_CON0_MASK_MON_SFT 0
9039	#define AFE_PCM0_INTF_CON0_MASK_MON_MASK 0xffffffff
9040	#define AFE_PCM0_INTF_CON0_MASK_MON_MASK_SFT (0xffffffff << 0)
9041
9042	/* AFE_CONNSYS_I2S_CON_MASK_MON */
9043	#define AFE_CONNSYS_I2S_CON_MASK_MON_SFT 0
9044	#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK 0xffffffff
9045	#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK_SFT (0xffffffff << 0)
9046
9047	/* AFE_MTKAIF0_CFG0_MASK_MON */
9048	#define AFE_MTKAIF0_CFG0_MASK_MON_SFT 0
9049	#define AFE_MTKAIF0_CFG0_MASK_MON_MASK 0xffffffff
9050	#define AFE_MTKAIF0_CFG0_MASK_MON_MASK_SFT (0xffffffff << 0)
9051
9052	/* AFE_MTKAIF1_CFG0_MASK_MON */
9053	#define AFE_MTKAIF1_CFG0_MASK_MON_SFT 0
9054	#define AFE_MTKAIF1_CFG0_MASK_MON_MASK 0xffffffff
9055	#define AFE_MTKAIF1_CFG0_MASK_MON_MASK_SFT (0xffffffff << 0)
9056
9057	/* AFE_ADDA_UL0_SRC_CON0_MASK_MON */
9058	#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_SFT 0
9059	#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK 0xffffffff
9060	#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0)
9061
9062	/* AFE_ADDA_UL1_SRC_CON0_MASK_MON */
9063	#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_SFT 0
9064	#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK 0xffffffff
9065	#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0)
9066
9067	/* AFE_GASRC0_NEW_CON0 */
9068	#define ONE_HEART_SFT 31
9069	#define ONE_HEART_MASK 0x1
9070	#define ONE_HEART_MASK_SFT (0x1 << 31)
9071	#define CHSET0_OFS_ONE_HEART_DISABLE_SFT 30
9072	#define CHSET0_OFS_ONE_HEART_DISABLE_MASK 0x1
9073	#define CHSET0_OFS_ONE_HEART_DISABLE_MASK_SFT (0x1 << 30)
9074	#define USE_SHORT_DELAY_COEFF_SFT 29
9075	#define USE_SHORT_DELAY_COEFF_MASK 0x1
9076	#define USE_SHORT_DELAY_COEFF_MASK_SFT (0x1 << 29)
9077	#define CHSET0_O16BIT_SFT 19
9078	#define CHSET0_O16BIT_MASK 0x1
9079	#define CHSET0_O16BIT_MASK_SFT (0x1 << 19)
9080	#define CHSET0_CLR_IIR_HISTORY_SFT 17
9081	#define CHSET0_CLR_IIR_HISTORY_MASK 0x1
9082	#define CHSET0_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)
9083	#define CHSET0_IS_MONO_SFT 16
9084	#define CHSET0_IS_MONO_MASK 0x1
9085	#define CHSET0_IS_MONO_MASK_SFT (0x1 << 16)
9086	#define CHSET0_OFS_SEL_SFT 14
9087	#define CHSET0_OFS_SEL_MASK 0x3
9088	#define CHSET0_OFS_SEL_MASK_SFT (0x3 << 14)
9089	#define CHSET0_IFS_SEL_SFT 12
9090	#define CHSET0_IFS_SEL_MASK 0x3
9091	#define CHSET0_IFS_SEL_MASK_SFT (0x3 << 12)
9092	#define CHSET0_IIR_EN_SFT 11
9093	#define CHSET0_IIR_EN_MASK 0x1
9094	#define CHSET0_IIR_EN_MASK_SFT (0x1 << 11)
9095	#define CHSET0_IIR_STAGE_SFT 8
9096	#define CHSET0_IIR_STAGE_MASK 0x7
9097	#define CHSET0_IIR_STAGE_MASK_SFT (0x7 << 8)
9098	#define ASM_ON_MOD_SFT 7
9099	#define ASM_ON_MOD_MASK 0x1
9100	#define ASM_ON_MOD_MASK_SFT (0x1 << 7)
9101	#define CHSET_STR_CLR_SFT 4
9102	#define CHSET_STR_CLR_MASK 0x1
9103	#define CHSET_STR_CLR_MASK_SFT (0x1 << 4)
9104	#define CHSET_ON_SFT 2
9105	#define CHSET_ON_MASK 0x1
9106	#define CHSET_ON_MASK_SFT (0x1 << 2)
9107	#define COEFF_SRAM_CTRL_SFT 1
9108	#define COEFF_SRAM_CTRL_MASK 0x1
9109	#define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
9110	#define ASM_ON_SFT 0
9111	#define ASM_ON_MASK 0x1
9112	#define ASM_ON_MASK_SFT (0x1 << 0)
9113
9114	/* AFE_GASRC0_NEW_CON1 */
9115	#define ASM_FREQ_0_SFT 0
9116	#define ASM_FREQ_0_MASK 0xffffff
9117	#define ASM_FREQ_0_MASK_SFT (0xffffff << 0)
9118
9119	/* AFE_GASRC0_NEW_CON2 */
9120	#define ASM_FREQ_1_SFT 0
9121	#define ASM_FREQ_1_MASK 0xffffff
9122	#define ASM_FREQ_1_MASK_SFT (0xffffff << 0)
9123
9124	/* AFE_GASRC0_NEW_CON3 */
9125	#define ASM_FREQ_2_SFT 0
9126	#define ASM_FREQ_2_MASK 0xffffff
9127	#define ASM_FREQ_2_MASK_SFT (0xffffff << 0)
9128
9129	/* AFE_GASRC0_NEW_CON4 */
9130	#define ASM_FREQ_3_SFT 0
9131	#define ASM_FREQ_3_MASK 0xffffff
9132	#define ASM_FREQ_3_MASK_SFT (0xffffff << 0)
9133
9134	/* AFE_GASRC0_NEW_CON5 */
9135	#define OUT_EN_SEL_DOMAIN_SFT 29
9136	#define OUT_EN_SEL_DOMAIN_MASK 0x7
9137	#define OUT_EN_SEL_DOMAIN_MASK_SFT (0x7 << 29)
9138	#define OUT_EN_SEL_FS_SFT 24
9139	#define OUT_EN_SEL_FS_MASK 0x1f
9140	#define OUT_EN_SEL_FS_MASK_SFT (0x1f << 24)
9141	#define IN_EN_SEL_DOMAIN_SFT 21
9142	#define IN_EN_SEL_DOMAIN_MASK 0x7
9143	#define IN_EN_SEL_DOMAIN_MASK_SFT (0x7 << 21)
9144	#define IN_EN_SEL_FS_SFT 16
9145	#define IN_EN_SEL_FS_MASK 0x1f
9146	#define IN_EN_SEL_FS_MASK_SFT (0x1f << 16)
9147	#define RESULT_SEL_SFT 8
9148	#define RESULT_SEL_MASK 0x7
9149	#define RESULT_SEL_MASK_SFT (0x7 << 8)
9150	#define CALI_CK_SEL_SFT 4
9151	#define CALI_CK_SEL_MASK 0x7
9152	#define CALI_CK_SEL_MASK_SFT (0x7 << 4)
9153	#define CALI_LRCK_SEL_SFT 1
9154	#define CALI_LRCK_SEL_MASK 0x7
9155	#define CALI_LRCK_SEL_MASK_SFT (0x7 << 1)
9156	#define SOFT_RESET_SFT 0
9157	#define SOFT_RESET_MASK 0x1
9158	#define SOFT_RESET_MASK_SFT (0x1 << 0)
9159
9160	/* AFE_GASRC0_NEW_CON6 */
9161	#define FREQ_CALI_CYCLE_SFT 16
9162	#define FREQ_CALI_CYCLE_MASK 0xffff
9163	#define FREQ_CALI_CYCLE_MASK_SFT (0xffff << 16)
9164	#define FREQ_CALI_AUTORST_EN_SFT 15
9165	#define FREQ_CALI_AUTORST_EN_MASK 0x1
9166	#define FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 15)
9167	#define CALI_AUTORST_DETECT_SFT 14
9168	#define CALI_AUTORST_DETECT_MASK 0x1
9169	#define CALI_AUTORST_DETECT_MASK_SFT (0x1 << 14)
9170	#define FREQ_CALC_RUNNING_SFT 13
9171	#define FREQ_CALC_RUNNING_MASK 0x1
9172	#define FREQ_CALC_RUNNING_MASK_SFT (0x1 << 13)
9173	#define AUTO_TUNE_FREQ3_SFT 12
9174	#define AUTO_TUNE_FREQ3_MASK 0x1
9175	#define AUTO_TUNE_FREQ3_MASK_SFT (0x1 << 12)
9176	#define COMP_FREQ_RES_EN_SFT 11
9177	#define COMP_FREQ_RES_EN_MASK 0x1
9178	#define COMP_FREQ_RES_EN_MASK_SFT (0x1 << 11)
9179	#define FREQ_CALI_SEL_SFT 8
9180	#define FREQ_CALI_SEL_MASK 0x3
9181	#define FREQ_CALI_SEL_MASK_SFT (0x3 << 8)
9182	#define FREQ_CALI_BP_DGL_SFT 7
9183	#define FREQ_CALI_BP_DGL_MASK 0x1
9184	#define FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7)
9185	#define FREQ_CALI_MAX_GWIDTH_SFT 4
9186	#define FREQ_CALI_MAX_GWIDTH_MASK 0x7
9187	#define FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4)
9188	#define AUTO_TUNE_FREQ2_SFT 3
9189	#define AUTO_TUNE_FREQ2_MASK 0x1
9190	#define AUTO_TUNE_FREQ2_MASK_SFT (0x1 << 3)
9191	#define FREQ_CALI_AUTO_RESTART_SFT 2
9192	#define FREQ_CALI_AUTO_RESTART_MASK 0x1
9193	#define FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2)
9194	#define CALI_USE_FREQ_OUT_SFT 1
9195	#define CALI_USE_FREQ_OUT_MASK 0x1
9196	#define CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1)
9197	#define CALI_EN_SFT 0
9198	#define CALI_EN_MASK 0x1
9199	#define CALI_EN_MASK_SFT (0x1 << 0)
9200
9201	/* AFE_GASRC0_NEW_CON7 */
9202	#define FREQ_CALC_DENOMINATOR_SFT 0
9203	#define FREQ_CALC_DENOMINATOR_MASK 0xffffff
9204	#define FREQ_CALC_DENOMINATOR_MASK_SFT (0xffffff << 0)
9205
9206	/* AFE_GASRC0_NEW_CON8 */
9207	#define PRD_CALI_RESULT_RECORD_SFT 0
9208	#define PRD_CALI_RESULT_RECORD_MASK 0xffffff
9209	#define PRD_CALI_RESULT_RECORD_MASK_SFT (0xffffff << 0)
9210
9211	/* AFE_GASRC0_NEW_CON9 */
9212	#define FREQ_CALI_RESULT_SFT 0
9213	#define FREQ_CALI_RESULT_MASK 0xffffff
9214	#define FREQ_CALI_RESULT_MASK_SFT (0xffffff << 0)
9215
9216	/* AFE_GASRC0_NEW_CON10 */
9217	#define COEFF_SRAM_DATA_SFT 0
9218	#define COEFF_SRAM_DATA_MASK 0xffffffff
9219	#define COEFF_SRAM_DATA_MASK_SFT (0xffffffff << 0)
9220
9221	/* AFE_GASRC0_NEW_CON11 */
9222	#define COEFF_SRAM_ADR_SFT 0
9223	#define COEFF_SRAM_ADR_MASK 0x3f
9224	#define COEFF_SRAM_ADR_MASK_SFT (0x3f << 0)
9225
9226	/* AFE_GASRC0_NEW_CON12 */
9227	#define RING_DBG_RD_SFT 0
9228	#define RING_DBG_RD_MASK 0x3ffffff
9229	#define RING_DBG_RD_MASK_SFT (0x3ffffff << 0)
9230
9231	/* AFE_GASRC0_NEW_CON13 */
9232	#define FREQ_CALI_AUTORST_TH_HIGH_SFT 0
9233	#define FREQ_CALI_AUTORST_TH_HIGH_MASK 0xffffff
9234	#define FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xffffff << 0)
9235
9236	/* AFE_GASRC0_NEW_CON14 */
9237	#define FREQ_CALI_AUTORST_TH_LOW_SFT 0
9238	#define FREQ_CALI_AUTORST_TH_LOW_MASK 0xffffff
9239	#define FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xffffff << 0)
9240
9241	/* AFE_GASRC0_NEW_IP_VERSION */
9242	#define IP_VERSION_SFT 0
9243	#define IP_VERSION_MASK 0xffffffff
9244	#define IP_VERSION_MASK_SFT (0xffffffff << 0)
9245
9246	#define AUDIO_TOP_CON0 0x0
9247	#define AUDIO_TOP_CON1 0x4
9248	#define AUDIO_TOP_CON2 0x8
9249	#define AUDIO_TOP_CON3 0xc
9250	#define AUDIO_TOP_CON4 0x10
9251	#define AUDIO_ENGEN_CON0 0x14
9252	#define AUDIO_ENGEN_CON0_USER1 0x18
9253	#define AUDIO_ENGEN_CON0_USER2 0x1c
9254	#define AFE_SINEGEN_CON0 0x20
9255	#define AFE_SINEGEN_CON1 0x24
9256	#define AFE_SINEGEN_CON2 0x28
9257	#define AFE_SINEGEN_CON3 0x2c
9258	#define AFE_APLL1_TUNER_CFG 0x30
9259	#define AFE_APLL1_TUNER_MON0 0x34
9260	#define AFE_APLL2_TUNER_CFG 0x38
9261	#define AFE_APLL2_TUNER_MON0 0x3c
9262	#define AUDIO_TOP_RG0 0x4c
9263	#define AUDIO_TOP_RG1 0x50
9264	#define AUDIO_TOP_RG2 0x54
9265	#define AUDIO_TOP_RG3 0x58
9266	#define AUDIO_TOP_RG4 0x5c
9267	#define AFE_SPM_CONTROL_REQ 0x60
9268	#define AFE_SPM_CONTROL_ACK 0x64
9269	#define AUD_TOP_CFG_VCORE_RG 0x68
9270	#define AUDIO_TOP_IP_VERSION 0x6c
9271	#define AUDIO_ENGEN_CON0_MON 0x7c
9272	#define AUDIO_PROJECT_MON 0x80
9273	#define AUD_TOP_CFG_VLP_RG 0x98
9274	#define AUD_TOP_MON_RG 0x9c
9275	#define AUDIO_USE_DEFAULT_DELSEL0 0xa0
9276	#define AUDIO_USE_DEFAULT_DELSEL1 0xa4
9277	#define AUDIO_USE_DEFAULT_DELSEL2 0xa8
9278	#define AFE_CONNSYS_I2S_IPM_VER_MON 0xb0
9279	#define AFE_CONNSYS_I2S_MON_SEL 0xb4
9280	#define AFE_CONNSYS_I2S_MON 0xb8
9281	#define AFE_CONNSYS_I2S_CON 0xbc
9282	#define AFE_PCM0_INTF_CON0 0xc0
9283	#define AFE_PCM0_INTF_CON1 0xc4
9284	#define AFE_PCM_INTF_MON 0xc8
9285	#define AFE_PCM_TOP_IP_VERSION 0xe8
9286	#define AFE_GAIN0_CON0 0x400
9287	#define AFE_GAIN0_CON1_R 0x404
9288	#define AFE_GAIN0_CON1_L 0x408
9289	#define AFE_GAIN0_CON2 0x40c
9290	#define AFE_GAIN0_CON3 0x410
9291	#define AFE_GAIN0_CUR_R 0x414
9292	#define AFE_GAIN0_CUR_L 0x418
9293	#define AFE_GAIN1_CON0 0x41c
9294	#define AFE_GAIN1_CON1_R 0x420
9295	#define AFE_GAIN1_CON1_L 0x424
9296	#define AFE_GAIN1_CON2 0x428
9297	#define AFE_GAIN1_CON3 0x42c
9298	#define AFE_GAIN1_CUR_R 0x430
9299	#define AFE_GAIN1_CUR_L 0x434
9300	#define AFE_GAIN2_CON0 0x438
9301	#define AFE_GAIN2_CON1_R 0x43c
9302	#define AFE_GAIN2_CON1_L 0x440
9303	#define AFE_GAIN2_CON2 0x444
9304	#define AFE_GAIN2_CON3 0x448
9305	#define AFE_GAIN2_CUR_R 0x44c
9306	#define AFE_GAIN2_CUR_L 0x450
9307	#define AFE_GAIN3_CON0 0x454
9308	#define AFE_GAIN3_CON1_R 0x458
9309	#define AFE_GAIN3_CON1_L 0x45c
9310	#define AFE_GAIN3_CON2 0x460
9311	#define AFE_GAIN3_CON3 0x464
9312	#define AFE_GAIN3_CUR_R 0x468
9313	#define AFE_GAIN3_CUR_L 0x46c
9314	#define AFE_GAIN_0_1_IP_VERSION 0x474
9315	#define AFE_GAIN_2_3_IP_VERSION 0x478
9316	#define AFE_ADDA_DL_IPM_VER_MON 0x4c0
9317	#define AFE_ADDA_DL_SRC_CON0 0x4d0
9318	#define AFE_ADDA_DL_SRC_CON1 0x4d4
9319	#define AFE_ADDA_DL_SRC_DEBUG_MON0 0x4d8
9320	#define AFE_ADDA_DL_PREDIS_CON0 0x4dc
9321	#define AFE_ADDA_DL_PREDIS_CON1 0x4e0
9322	#define AFE_ADDA_DL_PREDIS_CON2 0x4e4
9323	#define AFE_ADDA_DL_PREDIS_CON3 0x4e8
9324	#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x4ec
9325	#define AFE_ADDA_DL_SDM_TEST 0x4f0
9326	#define AFE_ADDA_DL_DC_COMP_CFG0 0x4f4
9327	#define AFE_ADDA_DL_DC_COMP_CFG1 0x4f8
9328	#define AFE_ADDA_DL_SDM_OUT_MON 0x4fc
9329	#define AFE_ADDA_DL_SRC_LCH_MON 0x500
9330	#define AFE_ADDA_DL_SRC_RCH_MON 0x504
9331	#define AFE_ADDA_DL_SRC_DEBUG 0x508
9332	#define AFE_ADDA_DL_SDM_DITHER_CON 0x50c
9333	#define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x510
9334	#define AFE_ADDA_DL_HBF1_SCF1_CONFIG 0x514
9335	#define AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG 0x518
9336	#define AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG 0x51c
9337	#define AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG 0x520
9338	#define AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG 0x524
9339	#define AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG 0x528
9340	#define AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG 0x52c
9341	#define AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG 0x530
9342	#define AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG 0x534
9343	#define AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG 0x538
9344	#define AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG 0x53c
9345	#define AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG 0x540
9346	#define AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG 0x544
9347	#define AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG 0x548
9348	#define AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG 0x54c
9349	#define AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG 0x550
9350	#define AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG 0x554
9351	#define AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG 0x558
9352	#define AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG 0x55c
9353	#define AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG 0x560
9354	#define AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG 0x564
9355	#define AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG 0x568
9356	#define AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG 0x56c
9357	#define AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG 0x570
9358	#define AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG 0x574
9359	#define AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG 0x578
9360	#define AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG 0x57c
9361	#define AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG 0x580
9362	#define AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG 0x584
9363	#define AFE_DEM_IDWA_CON0 0xa1c
9364	#define DEM_RECONSTRUCT_MON 0xa20
9365	#define AFE_CM0_CON0 0xba0
9366	#define AFE_CM0_MON 0xba4
9367	#define AFE_CM0_IP_VERSION 0xba8
9368	#define AFE_CM1_CON0 0xbb0
9369	#define AFE_CM1_MON 0xbb4
9370	#define AFE_CM1_IP_VERSION 0xbb8
9371	#define AFE_ADDA_UL0_SRC_CON0 0xbd0
9372	#define AFE_ADDA_UL0_SRC_CON1 0xbd4
9373	#define AFE_ADDA_UL0_SRC_CON2 0xbd8
9374	#define AFE_ADDA_UL0_SRC_DEBUG 0xbdc
9375	#define AFE_ADDA_UL0_SRC_DEBUG_MON0 0xbe0
9376	#define AFE_ADDA_UL0_SRC_MON0 0xbe4
9377	#define AFE_ADDA_UL0_SRC_MON1 0xbe8
9378	#define AFE_ADDA_UL0_IIR_COEF_02_01 0xbec
9379	#define AFE_ADDA_UL0_IIR_COEF_04_03 0xbf0
9380	#define AFE_ADDA_UL0_IIR_COEF_06_05 0xbf4
9381	#define AFE_ADDA_UL0_IIR_COEF_08_07 0xbf8
9382	#define AFE_ADDA_UL0_IIR_COEF_10_09 0xbfc
9383	#define AFE_ADDA_UL0_ULCF_CFG_02_01 0xc00
9384	#define AFE_ADDA_UL0_ULCF_CFG_04_03 0xc04
9385	#define AFE_ADDA_UL0_ULCF_CFG_06_05 0xc08
9386	#define AFE_ADDA_UL0_ULCF_CFG_08_07 0xc0c
9387	#define AFE_ADDA_UL0_ULCF_CFG_10_09 0xc10
9388	#define AFE_ADDA_UL0_ULCF_CFG_12_11 0xc14
9389	#define AFE_ADDA_UL0_ULCF_CFG_14_13 0xc18
9390	#define AFE_ADDA_UL0_ULCF_CFG_16_15 0xc1c
9391	#define AFE_ADDA_UL0_ULCF_CFG_18_17 0xc20
9392	#define AFE_ADDA_UL0_ULCF_CFG_20_19 0xc24
9393	#define AFE_ADDA_UL0_ULCF_CFG_22_21 0xc28
9394	#define AFE_ADDA_UL0_ULCF_CFG_24_23 0xc2c
9395	#define AFE_ADDA_UL0_ULCF_CFG_26_25 0xc30
9396	#define AFE_ADDA_UL0_ULCF_CFG_28_27 0xc34
9397	#define AFE_ADDA_UL0_ULCF_CFG_30_29 0xc38
9398	#define AFE_ADDA_UL0_ULCF_CFG_32_31 0xc3c
9399	#define AFE_ADDA_UL0_IP_VERSION 0xc4c
9400	#define AFE_ADDA_DMIC0_SRC_CON0 0xdd0
9401	#define AFE_ADDA_DMIC0_SRC_CON1 0xdd4
9402	#define AFE_ADDA_DMIC0_SRC_CON2 0xdd8
9403	#define AFE_ADDA_DMIC0_SRC_DEBUG 0xddc
9404	#define AFE_ADDA_DMIC0_SRC_DEBUG_MON0 0xde0
9405	#define AFE_ADDA_DMIC0_SRC_MON0 0xde4
9406	#define AFE_ADDA_DMIC0_SRC_MON1 0xde8
9407	#define AFE_ADDA_DMIC0_IIR_COEF_02_01 0xdec
9408	#define AFE_ADDA_DMIC0_IIR_COEF_04_03 0xdf0
9409	#define AFE_ADDA_DMIC0_IIR_COEF_06_05 0xdf4
9410	#define AFE_ADDA_DMIC0_IIR_COEF_08_07 0xdf8
9411	#define AFE_ADDA_DMIC0_IIR_COEF_10_09 0xdfc
9412	#define AFE_ADDA_DMIC0_ULCF_CFG_02_01 0xe00
9413	#define AFE_ADDA_DMIC0_ULCF_CFG_04_03 0xe04
9414	#define AFE_ADDA_DMIC0_ULCF_CFG_06_05 0xe08
9415	#define AFE_ADDA_DMIC0_ULCF_CFG_08_07 0xe0c
9416	#define AFE_ADDA_DMIC0_ULCF_CFG_10_09 0xe10
9417	#define AFE_ADDA_DMIC0_ULCF_CFG_12_11 0xe14
9418	#define AFE_ADDA_DMIC0_ULCF_CFG_14_13 0xe18
9419	#define AFE_ADDA_DMIC0_ULCF_CFG_16_15 0xe1c
9420	#define AFE_ADDA_DMIC0_ULCF_CFG_18_17 0xe20
9421	#define AFE_ADDA_DMIC0_ULCF_CFG_20_19 0xe24
9422	#define AFE_ADDA_DMIC0_ULCF_CFG_22_21 0xe28
9423	#define AFE_ADDA_DMIC0_ULCF_CFG_24_23 0xe2c
9424	#define AFE_ADDA_DMIC0_ULCF_CFG_26_25 0xe30
9425	#define AFE_ADDA_DMIC0_ULCF_CFG_28_27 0xe34
9426	#define AFE_ADDA_DMIC0_ULCF_CFG_30_29 0xe38
9427	#define AFE_ADDA_DMIC0_ULCF_CFG_32_31 0xe3c
9428	#define AFE_ADDA_DMIC0_IP_VERSION 0xe4c
9429	#define AFE_ADDA_DMIC1_SRC_CON0 0xe50
9430	#define AFE_ADDA_DMIC1_SRC_CON1 0xe54
9431	#define AFE_ADDA_DMIC1_SRC_CON2 0xe58
9432	#define AFE_ADDA_DMIC1_SRC_DEBUG 0xe5c
9433	#define AFE_ADDA_DMIC1_SRC_DEBUG_MON0 0xe60
9434	#define AFE_ADDA_DMIC1_SRC_MON0 0xe64
9435	#define AFE_ADDA_DMIC1_SRC_MON1 0xe68
9436	#define AFE_ADDA_DMIC1_IIR_COEF_02_01 0xe6c
9437	#define AFE_ADDA_DMIC1_IIR_COEF_04_03 0xe70
9438	#define AFE_ADDA_DMIC1_IIR_COEF_06_05 0xe74
9439	#define AFE_ADDA_DMIC1_IIR_COEF_08_07 0xe78
9440	#define AFE_ADDA_DMIC1_IIR_COEF_10_09 0xe7c
9441	#define AFE_ADDA_DMIC1_ULCF_CFG_02_01 0xe80
9442	#define AFE_ADDA_DMIC1_ULCF_CFG_04_03 0xe84
9443	#define AFE_ADDA_DMIC1_ULCF_CFG_06_05 0xe88
9444	#define AFE_ADDA_DMIC1_ULCF_CFG_08_07 0xe8c
9445	#define AFE_ADDA_DMIC1_ULCF_CFG_10_09 0xe90
9446	#define AFE_ADDA_DMIC1_ULCF_CFG_12_11 0xe94
9447	#define AFE_ADDA_DMIC1_ULCF_CFG_14_13 0xe98
9448	#define AFE_ADDA_DMIC1_ULCF_CFG_16_15 0xe9c
9449	#define AFE_ADDA_DMIC1_ULCF_CFG_18_17 0xea0
9450	#define AFE_ADDA_DMIC1_ULCF_CFG_20_19 0xea4
9451	#define AFE_ADDA_DMIC1_ULCF_CFG_22_21 0xea8
9452	#define AFE_ADDA_DMIC1_ULCF_CFG_24_23 0xeac
9453	#define AFE_ADDA_DMIC1_ULCF_CFG_26_25 0xeb0
9454	#define AFE_ADDA_DMIC1_ULCF_CFG_28_27 0xeb4
9455	#define AFE_ADDA_DMIC1_ULCF_CFG_30_29 0xeb8
9456	#define AFE_ADDA_DMIC1_ULCF_CFG_32_31 0xebc
9457	#define AFE_ADDA_DMIC1_IP_VERSION 0xecc
9458	#define AFE_ADDA_ULSRC_PHASE_CLK_CON0 0xf00
9459	#define AFE_ADDA_ULSRC_PHASE_CLK_CON1 0xf04
9460	#define AFE_ADDA_ULSRC_PHASE_CLK_CON2 0xf08
9461	#define AFE_ADDA_ULSRC_PHASE_CLK_CON3 0xf0c
9462	#define AFE_ADDA_ULSRC_PHASE_CLK_CON4 0xf10
9463	#define AFE_ADDA_ULSRC_PHASE_ENGEN_CON0 0xf14
9464	#define AFE_ADDA_ULSRC_PHASE_ENGEN_CON1 0xf18
9465	#define AFE_ADDA_ULSRC_PHASE_RST_CON0 0xf1c
9466	#define AFE_MTKAIF_IPM_VER_MON 0x1180
9467	#define AFE_MTKAIF_MON_SEL 0x1184
9468	#define AFE_MTKAIF_MON 0x1188
9469	#define AFE_MTKAIF0_CFG0 0x1190
9470	#define AFE_MTKAIF0_TX_CFG0 0x1194
9471	#define AFE_MTKAIF0_RX_CFG0 0x1198
9472	#define AFE_MTKAIF0_RX_CFG1 0x119c
9473	#define AFE_MTKAIF0_RX_CFG2 0x11a0
9474	#define AFE_MTKAIF1_CFG0 0x11f0
9475	#define AFE_MTKAIF1_TX_CFG0 0x11f4
9476	#define AFE_MTKAIF1_RX_CFG0 0x11f8
9477	#define AFE_MTKAIF1_RX_CFG1 0x11fc
9478	#define AFE_MTKAIF1_RX_CFG2 0x1200
9479	#define AFE_AUD_PAD_TOP_CFG0 0x1204
9480	#define AFE_AUD_PAD_TOP_MON 0x1208
9481	#define AFE_ADDA_MTKAIFV4_TX_CFG0 0x1280
9482	#define AFE_ADDA6_MTKAIFV4_TX_CFG0 0x1284
9483	#define AFE_ADDA_MTKAIFV4_RX_CFG0 0x1288
9484	#define AFE_ADDA_MTKAIFV4_RX_CFG1 0x128c
9485	#define AFE_ADDA6_MTKAIFV4_RX_CFG0 0x1290
9486	#define AFE_ADDA6_MTKAIFV4_RX_CFG1 0x1294
9487	#define AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG 0x1298
9488	#define AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG 0x129c
9489	#define AFE_ADDA_MTKAIFV4_MON0 0x12a0
9490	#define AFE_ADDA_MTKAIFV4_MON1 0x12a4
9491	#define AFE_ADDA6_MTKAIFV4_MON0 0x12a8
9492	#define ETDM_IN0_CON0 0x1300
9493	#define ETDM_IN0_CON1 0x1304
9494	#define ETDM_IN0_CON2 0x1308
9495	#define ETDM_IN0_CON3 0x130c
9496	#define ETDM_IN0_CON4 0x1310
9497	#define ETDM_IN0_CON5 0x1314
9498	#define ETDM_IN0_CON6 0x1318
9499	#define ETDM_IN0_CON7 0x131c
9500	#define ETDM_IN0_CON8 0x1320
9501	#define ETDM_IN0_CON9 0x1324
9502	#define ETDM_IN0_MON 0x1328
9503	#define ETDM_IN1_CON0 0x1330
9504	#define ETDM_IN1_CON1 0x1334
9505	#define ETDM_IN1_CON2 0x1338
9506	#define ETDM_IN1_CON3 0x133c
9507	#define ETDM_IN1_CON4 0x1340
9508	#define ETDM_IN1_CON5 0x1344
9509	#define ETDM_IN1_CON6 0x1348
9510	#define ETDM_IN1_CON7 0x134c
9511	#define ETDM_IN1_CON8 0x1350
9512	#define ETDM_IN1_CON9 0x1354
9513	#define ETDM_IN1_MON 0x1358
9514	#define ETDM_OUT0_CON0 0x1480
9515	#define ETDM_OUT0_CON1 0x1484
9516	#define ETDM_OUT0_CON2 0x1488
9517	#define ETDM_OUT0_CON3 0x148c
9518	#define ETDM_OUT0_CON4 0x1490
9519	#define ETDM_OUT0_CON5 0x1494
9520	#define ETDM_OUT0_CON6 0x1498
9521	#define ETDM_OUT0_CON7 0x149c
9522	#define ETDM_OUT0_CON8 0x14a0
9523	#define ETDM_OUT0_CON9 0x14a4
9524	#define ETDM_OUT0_MON 0x14a8
9525	#define ETDM_OUT1_CON0 0x14c0
9526	#define ETDM_OUT1_CON1 0x14c4
9527	#define ETDM_OUT1_CON2 0x14c8
9528	#define ETDM_OUT1_CON3 0x14cc
9529	#define ETDM_OUT1_CON4 0x14d0
9530	#define ETDM_OUT1_CON5 0x14d4
9531	#define ETDM_OUT1_CON6 0x14d8
9532	#define ETDM_OUT1_CON7 0x14dc
9533	#define ETDM_OUT1_CON8 0x14e0
9534	#define ETDM_OUT1_CON9 0x14e4
9535	#define ETDM_OUT1_MON 0x14e8
9536	#define ETDM_OUT4_CON0 0x1580
9537	#define ETDM_OUT4_CON1 0x1584
9538	#define ETDM_OUT4_CON2 0x1588
9539	#define ETDM_OUT4_CON3 0x158c
9540	#define ETDM_OUT4_CON4 0x1590
9541	#define ETDM_OUT4_CON5 0x1594
9542	#define ETDM_OUT4_CON6 0x1598
9543	#define ETDM_OUT4_CON7 0x159c
9544	#define ETDM_OUT4_CON8 0x15a0
9545	#define ETDM_OUT4_CON9 0x15a4
9546	#define ETDM_OUT4_MON 0x15a8
9547	#define ETDM_0_3_COWORK_CON0 0x1680
9548	#define ETDM_0_3_COWORK_CON1 0x1684
9549	#define ETDM_0_3_COWORK_CON2 0x1688
9550	#define ETDM_0_3_COWORK_CON3 0x168c
9551	#define ETDM_4_7_COWORK_CON0 0x1690
9552	#define ETDM_4_7_COWORK_CON1 0x1694
9553	#define ETDM_4_7_COWORK_CON2 0x1698
9554	#define ETDM_4_7_COWORK_CON3 0x169c
9555	#define ETDM_IP_VERSION 0x1c4c
9556	#define AFE_DPTX_CON 0x2040
9557	#define AFE_DPTX_MON 0x2044
9558	#define AFE_TDM_CON1 0x2048
9559	#define AFE_TDM_CON2 0x204c
9560	#define AFE_TDM_CON3 0x2050
9561	#define AFE_TDM_OUT_MON 0x2054
9562	#define AFE_HDMI_CONN0 0x2078
9563	#define AFE_TDM_TOP_IP_VERSION 0x207c
9564	#define AFE_CONN004_0 0x2100
9565	#define AFE_CONN004_1 0x2104
9566	#define AFE_CONN004_2 0x2108
9567	#define AFE_CONN004_4 0x2110
9568	#define AFE_CONN004_6 0x2118
9569	#define AFE_CONN005_0 0x2120
9570	#define AFE_CONN005_1 0x2124
9571	#define AFE_CONN005_2 0x2128
9572	#define AFE_CONN005_4 0x2130
9573	#define AFE_CONN005_6 0x2138
9574	#define AFE_CONN006_0 0x2140
9575	#define AFE_CONN006_1 0x2144
9576	#define AFE_CONN006_2 0x2148
9577	#define AFE_CONN006_4 0x2150
9578	#define AFE_CONN006_6 0x2158
9579	#define AFE_CONN007_0 0x2160
9580	#define AFE_CONN007_1 0x2164
9581	#define AFE_CONN007_2 0x2168
9582	#define AFE_CONN007_4 0x2170
9583	#define AFE_CONN007_6 0x2178
9584	#define AFE_CONN008_0 0x2180
9585	#define AFE_CONN008_1 0x2184
9586	#define AFE_CONN008_2 0x2188
9587	#define AFE_CONN008_4 0x2190
9588	#define AFE_CONN008_6 0x2198
9589	#define AFE_CONN009_0 0x21a0
9590	#define AFE_CONN009_1 0x21a4
9591	#define AFE_CONN009_2 0x21a8
9592	#define AFE_CONN009_4 0x21b0
9593	#define AFE_CONN009_6 0x21b8
9594	#define AFE_CONN010_0 0x21c0
9595	#define AFE_CONN010_1 0x21c4
9596	#define AFE_CONN010_2 0x21c8
9597	#define AFE_CONN010_4 0x21d0
9598	#define AFE_CONN010_6 0x21d8
9599	#define AFE_CONN011_0 0x21e0
9600	#define AFE_CONN011_1 0x21e4
9601	#define AFE_CONN011_2 0x21e8
9602	#define AFE_CONN011_4 0x21f0
9603	#define AFE_CONN011_6 0x21f8
9604	#define AFE_CONN014_0 0x2240
9605	#define AFE_CONN014_1 0x2244
9606	#define AFE_CONN014_2 0x2248
9607	#define AFE_CONN014_4 0x2250
9608	#define AFE_CONN014_6 0x2258
9609	#define AFE_CONN015_0 0x2260
9610	#define AFE_CONN015_1 0x2264
9611	#define AFE_CONN015_2 0x2268
9612	#define AFE_CONN015_4 0x2270
9613	#define AFE_CONN015_6 0x2278
9614	#define AFE_CONN016_0 0x2280
9615	#define AFE_CONN016_1 0x2284
9616	#define AFE_CONN016_2 0x2288
9617	#define AFE_CONN016_4 0x2290
9618	#define AFE_CONN016_6 0x2298
9619	#define AFE_CONN017_0 0x22a0
9620	#define AFE_CONN017_1 0x22a4
9621	#define AFE_CONN017_2 0x22a8
9622	#define AFE_CONN017_4 0x22b0
9623	#define AFE_CONN017_6 0x22b8
9624	#define AFE_CONN018_0 0x22c0
9625	#define AFE_CONN018_1 0x22c4
9626	#define AFE_CONN018_2 0x22c8
9627	#define AFE_CONN018_4 0x22d0
9628	#define AFE_CONN018_6 0x22d8
9629	#define AFE_CONN019_0 0x22e0
9630	#define AFE_CONN019_1 0x22e4
9631	#define AFE_CONN019_2 0x22e8
9632	#define AFE_CONN019_4 0x22f0
9633	#define AFE_CONN019_6 0x22f8
9634	#define AFE_CONN020_0 0x2300
9635	#define AFE_CONN020_1 0x2304
9636	#define AFE_CONN020_2 0x2308
9637	#define AFE_CONN020_4 0x2310
9638	#define AFE_CONN020_6 0x2318
9639	#define AFE_CONN021_0 0x2320
9640	#define AFE_CONN021_1 0x2324
9641	#define AFE_CONN021_2 0x2328
9642	#define AFE_CONN021_4 0x2330
9643	#define AFE_CONN021_6 0x2338
9644	#define AFE_CONN022_0 0x2340
9645	#define AFE_CONN022_1 0x2344
9646	#define AFE_CONN022_2 0x2348
9647	#define AFE_CONN022_4 0x2350
9648	#define AFE_CONN022_6 0x2358
9649	#define AFE_CONN023_0 0x2360
9650	#define AFE_CONN023_1 0x2364
9651	#define AFE_CONN023_2 0x2368
9652	#define AFE_CONN023_4 0x2370
9653	#define AFE_CONN023_6 0x2378
9654	#define AFE_CONN024_0 0x2380
9655	#define AFE_CONN024_1 0x2384
9656	#define AFE_CONN024_2 0x2388
9657	#define AFE_CONN024_4 0x2390
9658	#define AFE_CONN024_6 0x2398
9659	#define AFE_CONN025_0 0x23a0
9660	#define AFE_CONN025_1 0x23a4
9661	#define AFE_CONN025_2 0x23a8
9662	#define AFE_CONN025_4 0x23b0
9663	#define AFE_CONN025_6 0x23b8
9664	#define AFE_CONN026_0 0x23c0
9665	#define AFE_CONN026_1 0x23c4
9666	#define AFE_CONN026_2 0x23c8
9667	#define AFE_CONN026_4 0x23d0
9668	#define AFE_CONN026_6 0x23d8
9669	#define AFE_CONN027_0 0x23e0
9670	#define AFE_CONN027_1 0x23e4
9671	#define AFE_CONN027_2 0x23e8
9672	#define AFE_CONN027_4 0x23f0
9673	#define AFE_CONN027_6 0x23f8
9674	#define AFE_CONN028_0 0x2400
9675	#define AFE_CONN028_1 0x2404
9676	#define AFE_CONN028_2 0x2408
9677	#define AFE_CONN028_4 0x2410
9678	#define AFE_CONN028_6 0x2418
9679	#define AFE_CONN029_0 0x2420
9680	#define AFE_CONN029_1 0x2424
9681	#define AFE_CONN029_2 0x2428
9682	#define AFE_CONN029_4 0x2430
9683	#define AFE_CONN029_6 0x2438
9684	#define AFE_CONN030_0 0x2440
9685	#define AFE_CONN030_1 0x2444
9686	#define AFE_CONN030_2 0x2448
9687	#define AFE_CONN030_4 0x2450
9688	#define AFE_CONN030_6 0x2458
9689	#define AFE_CONN031_0 0x2460
9690	#define AFE_CONN031_1 0x2464
9691	#define AFE_CONN031_2 0x2468
9692	#define AFE_CONN031_4 0x2470
9693	#define AFE_CONN031_6 0x2478
9694	#define AFE_CONN032_0 0x2480
9695	#define AFE_CONN032_1 0x2484
9696	#define AFE_CONN032_2 0x2488
9697	#define AFE_CONN032_4 0x2490
9698	#define AFE_CONN032_6 0x2498
9699	#define AFE_CONN033_0 0x24a0
9700	#define AFE_CONN033_1 0x24a4
9701	#define AFE_CONN033_2 0x24a8
9702	#define AFE_CONN033_4 0x24b0
9703	#define AFE_CONN033_6 0x24b8
9704	#define AFE_CONN034_0 0x24c0
9705	#define AFE_CONN034_1 0x24c4
9706	#define AFE_CONN034_2 0x24c8
9707	#define AFE_CONN034_4 0x24d0
9708	#define AFE_CONN034_6 0x24d8
9709	#define AFE_CONN035_0 0x24e0
9710	#define AFE_CONN035_1 0x24e4
9711	#define AFE_CONN035_2 0x24e8
9712	#define AFE_CONN035_4 0x24f0
9713	#define AFE_CONN035_6 0x24f8
9714	#define AFE_CONN036_0 0x2500
9715	#define AFE_CONN036_1 0x2504
9716	#define AFE_CONN036_2 0x2508
9717	#define AFE_CONN036_4 0x2510
9718	#define AFE_CONN036_6 0x2518
9719	#define AFE_CONN037_0 0x2520
9720	#define AFE_CONN037_1 0x2524
9721	#define AFE_CONN037_2 0x2528
9722	#define AFE_CONN037_4 0x2530
9723	#define AFE_CONN037_6 0x2538
9724	#define AFE_CONN038_0 0x2540
9725	#define AFE_CONN038_1 0x2544
9726	#define AFE_CONN038_2 0x2548
9727	#define AFE_CONN038_4 0x2550
9728	#define AFE_CONN038_6 0x2558
9729	#define AFE_CONN039_0 0x2560
9730	#define AFE_CONN039_1 0x2564
9731	#define AFE_CONN039_2 0x2568
9732	#define AFE_CONN039_4 0x2570
9733	#define AFE_CONN039_6 0x2578
9734	#define AFE_CONN040_0 0x2580
9735	#define AFE_CONN040_1 0x2584
9736	#define AFE_CONN040_2 0x2588
9737	#define AFE_CONN040_4 0x2590
9738	#define AFE_CONN040_6 0x2598
9739	#define AFE_CONN041_0 0x25a0
9740	#define AFE_CONN041_1 0x25a4
9741	#define AFE_CONN041_2 0x25a8
9742	#define AFE_CONN041_4 0x25b0
9743	#define AFE_CONN041_6 0x25b8
9744	#define AFE_CONN042_0 0x25c0
9745	#define AFE_CONN042_1 0x25c4
9746	#define AFE_CONN042_2 0x25c8
9747	#define AFE_CONN042_4 0x25d0
9748	#define AFE_CONN042_6 0x25d8
9749	#define AFE_CONN043_0 0x25e0
9750	#define AFE_CONN043_1 0x25e4
9751	#define AFE_CONN043_2 0x25e8
9752	#define AFE_CONN043_4 0x25f0
9753	#define AFE_CONN043_6 0x25f8
9754	#define AFE_CONN044_0 0x2600
9755	#define AFE_CONN044_1 0x2604
9756	#define AFE_CONN044_2 0x2608
9757	#define AFE_CONN044_4 0x2610
9758	#define AFE_CONN044_6 0x2618
9759	#define AFE_CONN045_0 0x2620
9760	#define AFE_CONN045_1 0x2624
9761	#define AFE_CONN045_2 0x2628
9762	#define AFE_CONN045_4 0x2630
9763	#define AFE_CONN045_6 0x2638
9764	#define AFE_CONN046_0 0x2640
9765	#define AFE_CONN046_1 0x2644
9766	#define AFE_CONN046_2 0x2648
9767	#define AFE_CONN046_4 0x2650
9768	#define AFE_CONN046_6 0x2658
9769	#define AFE_CONN047_0 0x2660
9770	#define AFE_CONN047_1 0x2664
9771	#define AFE_CONN047_2 0x2668
9772	#define AFE_CONN047_4 0x2670
9773	#define AFE_CONN047_6 0x2678
9774	#define AFE_CONN048_0 0x2680
9775	#define AFE_CONN048_1 0x2684
9776	#define AFE_CONN048_2 0x2688
9777	#define AFE_CONN048_4 0x2690
9778	#define AFE_CONN048_6 0x2698
9779	#define AFE_CONN049_0 0x26a0
9780	#define AFE_CONN049_1 0x26a4
9781	#define AFE_CONN049_2 0x26a8
9782	#define AFE_CONN049_4 0x26b0
9783	#define AFE_CONN049_6 0x26b8
9784	#define AFE_CONN050_0 0x26c0
9785	#define AFE_CONN050_1 0x26c4
9786	#define AFE_CONN050_2 0x26c8
9787	#define AFE_CONN050_4 0x26d0
9788	#define AFE_CONN050_6 0x26d8
9789	#define AFE_CONN051_0 0x26e0
9790	#define AFE_CONN051_1 0x26e4
9791	#define AFE_CONN051_2 0x26e8
9792	#define AFE_CONN051_4 0x26f0
9793	#define AFE_CONN051_6 0x26f8
9794	#define AFE_CONN052_0 0x2700
9795	#define AFE_CONN052_1 0x2704
9796	#define AFE_CONN052_2 0x2708
9797	#define AFE_CONN052_4 0x2710
9798	#define AFE_CONN052_6 0x2718
9799	#define AFE_CONN053_0 0x2720
9800	#define AFE_CONN053_1 0x2724
9801	#define AFE_CONN053_2 0x2728
9802	#define AFE_CONN053_4 0x2730
9803	#define AFE_CONN053_6 0x2738
9804	#define AFE_CONN054_0 0x2740
9805	#define AFE_CONN054_1 0x2744
9806	#define AFE_CONN054_2 0x2748
9807	#define AFE_CONN054_4 0x2750
9808	#define AFE_CONN054_6 0x2758
9809	#define AFE_CONN055_0 0x2760
9810	#define AFE_CONN055_1 0x2764
9811	#define AFE_CONN055_2 0x2768
9812	#define AFE_CONN055_4 0x2770
9813	#define AFE_CONN055_6 0x2778
9814	#define AFE_CONN056_0 0x2780
9815	#define AFE_CONN056_1 0x2784
9816	#define AFE_CONN056_2 0x2788
9817	#define AFE_CONN056_4 0x2790
9818	#define AFE_CONN056_6 0x2798
9819	#define AFE_CONN057_0 0x27a0
9820	#define AFE_CONN057_1 0x27a4
9821	#define AFE_CONN057_2 0x27a8
9822	#define AFE_CONN057_4 0x27b0
9823	#define AFE_CONN057_6 0x27b8
9824	#define AFE_CONN058_0 0x27c0
9825	#define AFE_CONN058_1 0x27c4
9826	#define AFE_CONN058_2 0x27c8
9827	#define AFE_CONN058_4 0x27d0
9828	#define AFE_CONN058_6 0x27d8
9829	#define AFE_CONN059_0 0x27e0
9830	#define AFE_CONN059_1 0x27e4
9831	#define AFE_CONN059_2 0x27e8
9832	#define AFE_CONN059_4 0x27f0
9833	#define AFE_CONN059_6 0x27f8
9834	#define AFE_CONN060_0 0x2800
9835	#define AFE_CONN060_1 0x2804
9836	#define AFE_CONN060_2 0x2808
9837	#define AFE_CONN060_4 0x2810
9838	#define AFE_CONN060_6 0x2818
9839	#define AFE_CONN061_0 0x2820
9840	#define AFE_CONN061_1 0x2824
9841	#define AFE_CONN061_2 0x2828
9842	#define AFE_CONN061_4 0x2830
9843	#define AFE_CONN061_6 0x2838
9844	#define AFE_CONN062_0 0x2840
9845	#define AFE_CONN062_1 0x2844
9846	#define AFE_CONN062_2 0x2848
9847	#define AFE_CONN062_4 0x2850
9848	#define AFE_CONN062_6 0x2858
9849	#define AFE_CONN063_0 0x2860
9850	#define AFE_CONN063_1 0x2864
9851	#define AFE_CONN063_2 0x2868
9852	#define AFE_CONN063_4 0x2870
9853	#define AFE_CONN063_6 0x2878
9854	#define AFE_CONN066_0 0x28c0
9855	#define AFE_CONN066_1 0x28c4
9856	#define AFE_CONN066_2 0x28c8
9857	#define AFE_CONN066_4 0x28d0
9858	#define AFE_CONN066_6 0x28d8
9859	#define AFE_CONN067_0 0x28e0
9860	#define AFE_CONN067_1 0x28e4
9861	#define AFE_CONN067_2 0x28e8
9862	#define AFE_CONN067_4 0x28f0
9863	#define AFE_CONN067_6 0x28f8
9864	#define AFE_CONN068_0 0x2900
9865	#define AFE_CONN068_1 0x2904
9866	#define AFE_CONN068_2 0x2908
9867	#define AFE_CONN068_4 0x2910
9868	#define AFE_CONN068_6 0x2918
9869	#define AFE_CONN069_0 0x2920
9870	#define AFE_CONN069_1 0x2924
9871	#define AFE_CONN069_2 0x2928
9872	#define AFE_CONN069_4 0x2930
9873	#define AFE_CONN069_6 0x2938
9874	#define AFE_CONN096_0 0x2c80
9875	#define AFE_CONN096_1 0x2c84
9876	#define AFE_CONN096_2 0x2c88
9877	#define AFE_CONN096_4 0x2c90
9878	#define AFE_CONN096_6 0x2c98
9879	#define AFE_CONN097_0 0x2ca0
9880	#define AFE_CONN097_1 0x2ca4
9881	#define AFE_CONN097_2 0x2ca8
9882	#define AFE_CONN097_4 0x2cb0
9883	#define AFE_CONN097_6 0x2cb8
9884	#define AFE_CONN098_0 0x2cc0
9885	#define AFE_CONN098_1 0x2cc4
9886	#define AFE_CONN098_2 0x2cc8
9887	#define AFE_CONN098_4 0x2cd0
9888	#define AFE_CONN098_6 0x2cd8
9889	#define AFE_CONN099_0 0x2ce0
9890	#define AFE_CONN099_1 0x2ce4
9891	#define AFE_CONN099_2 0x2ce8
9892	#define AFE_CONN099_4 0x2cf0
9893	#define AFE_CONN099_6 0x2cf8
9894	#define AFE_CONN100_0 0x2d00
9895	#define AFE_CONN100_1 0x2d04
9896	#define AFE_CONN100_2 0x2d08
9897	#define AFE_CONN100_4 0x2d10
9898	#define AFE_CONN100_6 0x2d18
9899	#define AFE_CONN108_0 0x2e00
9900	#define AFE_CONN108_1 0x2e04
9901	#define AFE_CONN108_2 0x2e08
9902	#define AFE_CONN108_4 0x2e10
9903	#define AFE_CONN108_6 0x2e18
9904	#define AFE_CONN109_0 0x2e20
9905	#define AFE_CONN109_1 0x2e24
9906	#define AFE_CONN109_2 0x2e28
9907	#define AFE_CONN109_4 0x2e30
9908	#define AFE_CONN109_6 0x2e38
9909	#define AFE_CONN110_0 0x2e40
9910	#define AFE_CONN110_1 0x2e44
9911	#define AFE_CONN110_2 0x2e48
9912	#define AFE_CONN110_4 0x2e50
9913	#define AFE_CONN110_6 0x2e58
9914	#define AFE_CONN111_0 0x2e60
9915	#define AFE_CONN111_1 0x2e64
9916	#define AFE_CONN111_2 0x2e68
9917	#define AFE_CONN111_4 0x2e70
9918	#define AFE_CONN111_6 0x2e78
9919	#define AFE_CONN116_0 0x2f00
9920	#define AFE_CONN116_1 0x2f04
9921	#define AFE_CONN116_2 0x2f08
9922	#define AFE_CONN116_4 0x2f10
9923	#define AFE_CONN116_6 0x2f18
9924	#define AFE_CONN117_0 0x2f20
9925	#define AFE_CONN117_1 0x2f24
9926	#define AFE_CONN117_2 0x2f28
9927	#define AFE_CONN117_4 0x2f30
9928	#define AFE_CONN117_6 0x2f38
9929	#define AFE_CONN118_0 0x2f40
9930	#define AFE_CONN118_1 0x2f44
9931	#define AFE_CONN118_2 0x2f48
9932	#define AFE_CONN118_4 0x2f50
9933	#define AFE_CONN118_6 0x2f58
9934	#define AFE_CONN119_0 0x2f60
9935	#define AFE_CONN119_1 0x2f64
9936	#define AFE_CONN119_2 0x2f68
9937	#define AFE_CONN119_4 0x2f70
9938	#define AFE_CONN119_6 0x2f78
9939	#define AFE_CONN120_0 0x2f80
9940	#define AFE_CONN120_1 0x2f84
9941	#define AFE_CONN120_2 0x2f88
9942	#define AFE_CONN120_4 0x2f90
9943	#define AFE_CONN120_6 0x2f98
9944	#define AFE_CONN121_0 0x2fa0
9945	#define AFE_CONN121_1 0x2fa4
9946	#define AFE_CONN121_2 0x2fa8
9947	#define AFE_CONN121_4 0x2fb0
9948	#define AFE_CONN121_6 0x2fb8
9949	#define AFE_CONN122_0 0x2fc0
9950	#define AFE_CONN122_1 0x2fc4
9951	#define AFE_CONN122_2 0x2fc8
9952	#define AFE_CONN122_4 0x2fd0
9953	#define AFE_CONN122_6 0x2fd8
9954	#define AFE_CONN123_0 0x2fe0
9955	#define AFE_CONN123_1 0x2fe4
9956	#define AFE_CONN123_2 0x2fe8
9957	#define AFE_CONN123_4 0x2ff0
9958	#define AFE_CONN123_6 0x2ff8
9959	#define AFE_CONN180_0 0x3700
9960	#define AFE_CONN180_1 0x3704
9961	#define AFE_CONN180_2 0x3708
9962	#define AFE_CONN180_4 0x3710
9963	#define AFE_CONN180_6 0x3718
9964	#define AFE_CONN181_0 0x3720
9965	#define AFE_CONN181_1 0x3724
9966	#define AFE_CONN181_2 0x3728
9967	#define AFE_CONN181_4 0x3730
9968	#define AFE_CONN181_6 0x3738
9969	#define AFE_CONN182_0 0x3740
9970	#define AFE_CONN182_1 0x3744
9971	#define AFE_CONN182_2 0x3748
9972	#define AFE_CONN182_4 0x3750
9973	#define AFE_CONN182_6 0x3758
9974	#define AFE_CONN183_0 0x3760
9975	#define AFE_CONN183_1 0x3764
9976	#define AFE_CONN183_2 0x3768
9977	#define AFE_CONN183_4 0x3770
9978	#define AFE_CONN183_6 0x3778
9979	#define AFE_CONN184_0 0x3780
9980	#define AFE_CONN184_1 0x3784
9981	#define AFE_CONN184_2 0x3788
9982	#define AFE_CONN184_4 0x3790
9983	#define AFE_CONN184_6 0x3798
9984	#define AFE_CONN185_0 0x37a0
9985	#define AFE_CONN185_1 0x37a4
9986	#define AFE_CONN185_2 0x37a8
9987	#define AFE_CONN185_4 0x37b0
9988	#define AFE_CONN185_6 0x37b8
9989	#define AFE_CONN186_0 0x37c0
9990	#define AFE_CONN186_1 0x37c4
9991	#define AFE_CONN186_2 0x37c8
9992	#define AFE_CONN186_4 0x37d0
9993	#define AFE_CONN186_6 0x37d8
9994	#define AFE_CONN187_0 0x37e0
9995	#define AFE_CONN187_1 0x37e4
9996	#define AFE_CONN187_2 0x37e8
9997	#define AFE_CONN187_4 0x37f0
9998	#define AFE_CONN187_6 0x37f8
9999	#define AFE_CONN188_0 0x3800
10000	#define AFE_CONN188_1 0x3804
10001	#define AFE_CONN188_2 0x3808
10002	#define AFE_CONN188_4 0x3810
10003	#define AFE_CONN188_6 0x3818
10004	#define AFE_CONN189_0 0x3820
10005	#define AFE_CONN189_1 0x3824
10006	#define AFE_CONN189_2 0x3828
10007	#define AFE_CONN189_4 0x3830
10008	#define AFE_CONN189_6 0x3838
10009	#define AFE_CONN_MON_CFG 0x4080
10010	#define AFE_CONN_MON0 0x4084
10011	#define AFE_CONN_MON1 0x4088
10012	#define AFE_CONN_MON2 0x408c
10013	#define AFE_CONN_MON3 0x4090
10014	#define AFE_CONN_MON4 0x4094
10015	#define AFE_CONN_MON5 0x4098
10016	#define AFE_CONN_RS_0 0x40a0
10017	#define AFE_CONN_RS_1 0x40a4
10018	#define AFE_CONN_RS_2 0x40a8
10019	#define AFE_CONN_RS_3 0x40ac
10020	#define AFE_CONN_RS_5 0x40b4
10021	#define AFE_CONN_DI_0 0x40c0
10022	#define AFE_CONN_DI_1 0x40c4
10023	#define AFE_CONN_DI_2 0x40c8
10024	#define AFE_CONN_DI_3 0x40cc
10025	#define AFE_CONN_DI_5 0x40d4
10026	#define AFE_CONN_16BIT_0 0x40e0
10027	#define AFE_CONN_16BIT_1 0x40e4
10028	#define AFE_CONN_16BIT_2 0x40e8
10029	#define AFE_CONN_16BIT_3 0x40ec
10030	#define AFE_CONN_16BIT_5 0x40f4
10031	#define AFE_CONN_24BIT_0 0x4100
10032	#define AFE_CONN_24BIT_1 0x4104
10033	#define AFE_CONN_24BIT_2 0x4108
10034	#define AFE_CONN_24BIT_3 0x410c
10035	#define AFE_CONN_24BIT_5 0x4114
10036	#define AFE_CONN_TOP_IP_VERSION 0x4120
10037	#define AFE_CBIP_CFG0 0x4380
10038	#define AFE_CBIP_SLV_DECODER_MON0 0x4384
10039	#define AFE_CBIP_SLV_DECODER_MON1 0x4388
10040	#define AFE_CBIP_SLV_MUX_MON_CFG 0x438c
10041	#define AFE_CBIP_SLV_MUX_MON0 0x4390
10042	#define AFE_CBIP_SLV_MUX_MON1 0x4394
10043	#define AFE_MEMIF_IP_VERSION 0x4398
10044	#define AFE_MEMIF_CON0 0x4400
10045	#define AFE_MEMIF_RD_MON 0x4408
10046	#define AFE_MEMIF_WR_MON 0x440c
10047	#define AFE_MEMIF_CFG_MON0 0x4410
10048	#define AFE_BUS_CFG0 0x4414
10049	#define AFE_BUS_MON1 0x4418
10050	#define AFE_BUS_MON2 0x441c
10051	#define AFE_MEMIF_ONE_HEART 0x4420
10052	#define AFE_DL0_BASE_MSB 0x4440
10053	#define AFE_DL0_BASE 0x4444
10054	#define AFE_DL0_CUR_MSB 0x4448
10055	#define AFE_DL0_CUR 0x444c
10056	#define AFE_DL0_END_MSB 0x4450
10057	#define AFE_DL0_END 0x4454
10058	#define AFE_DL0_RCH_MON 0x4458
10059	#define AFE_DL0_LCH_MON 0x445c
10060	#define AFE_DL0_CON0 0x4460
10061	#define AFE_DL0_MON0 0x4464
10062	#define AFE_DL0_MEM_UP_MSB 0x4468
10063	#define AFE_DL0_MEM_UP 0x446c
10064	#define AFE_DL1_BASE_MSB 0x4470
10065	#define AFE_DL1_BASE 0x4474
10066	#define AFE_DL1_CUR_MSB 0x4478
10067	#define AFE_DL1_CUR 0x447c
10068	#define AFE_DL1_END_MSB 0x4480
10069	#define AFE_DL1_END 0x4484
10070	#define AFE_DL1_RCH_MON 0x4488
10071	#define AFE_DL1_LCH_MON 0x448c
10072	#define AFE_DL1_CON0 0x4490
10073	#define AFE_DL1_MON0 0x4494
10074	#define AFE_DL1_MEM_UP_MSB 0x4498
10075	#define AFE_DL1_MEM_UP 0x449c
10076	#define AFE_DL2_BASE_MSB 0x44a0
10077	#define AFE_DL2_BASE 0x44a4
10078	#define AFE_DL2_CUR_MSB 0x44a8
10079	#define AFE_DL2_CUR 0x44ac
10080	#define AFE_DL2_END_MSB 0x44b0
10081	#define AFE_DL2_END 0x44b4
10082	#define AFE_DL2_RCH_MON 0x44b8
10083	#define AFE_DL2_LCH_MON 0x44bc
10084	#define AFE_DL2_CON0 0x44c0
10085	#define AFE_DL2_MON0 0x44c4
10086	#define AFE_DL2_MEM_UP_MSB 0x44c8
10087	#define AFE_DL2_MEM_UP 0x44cc
10088	#define AFE_DL3_BASE_MSB 0x44d0
10089	#define AFE_DL3_BASE 0x44d4
10090	#define AFE_DL3_CUR_MSB 0x44d8
10091	#define AFE_DL3_CUR 0x44dc
10092	#define AFE_DL3_END_MSB 0x44e0
10093	#define AFE_DL3_END 0x44e4
10094	#define AFE_DL3_RCH_MON 0x44e8
10095	#define AFE_DL3_LCH_MON 0x44ec
10096	#define AFE_DL3_CON0 0x44f0
10097	#define AFE_DL3_MON0 0x44f4
10098	#define AFE_DL3_MEM_UP_MSB 0x44f8
10099	#define AFE_DL3_MEM_UP 0x44fc
10100	#define AFE_DL4_BASE_MSB 0x4500
10101	#define AFE_DL4_BASE 0x4504
10102	#define AFE_DL4_CUR_MSB 0x4508
10103	#define AFE_DL4_CUR 0x450c
10104	#define AFE_DL4_END_MSB 0x4510
10105	#define AFE_DL4_END 0x4514
10106	#define AFE_DL4_RCH_MON 0x4518
10107	#define AFE_DL4_LCH_MON 0x451c
10108	#define AFE_DL4_CON0 0x4520
10109	#define AFE_DL4_MON0 0x4524
10110	#define AFE_DL4_MEM_UP_MSB 0x4528
10111	#define AFE_DL4_MEM_UP 0x452c
10112	#define AFE_DL5_BASE_MSB 0x4530
10113	#define AFE_DL5_BASE 0x4534
10114	#define AFE_DL5_CUR_MSB 0x4538
10115	#define AFE_DL5_CUR 0x453c
10116	#define AFE_DL5_END_MSB 0x4540
10117	#define AFE_DL5_END 0x4544
10118	#define AFE_DL5_RCH_MON 0x4548
10119	#define AFE_DL5_LCH_MON 0x454c
10120	#define AFE_DL5_CON0 0x4550
10121	#define AFE_DL5_MON0 0x4554
10122	#define AFE_DL5_MEM_UP_MSB 0x4558
10123	#define AFE_DL5_MEM_UP 0x455c
10124	#define AFE_DL6_BASE_MSB 0x4560
10125	#define AFE_DL6_BASE 0x4564
10126	#define AFE_DL6_CUR_MSB 0x4568
10127	#define AFE_DL6_CUR 0x456c
10128	#define AFE_DL6_END_MSB 0x4570
10129	#define AFE_DL6_END 0x4574
10130	#define AFE_DL6_RCH_MON 0x4578
10131	#define AFE_DL6_LCH_MON 0x457c
10132	#define AFE_DL6_CON0 0x4580
10133	#define AFE_DL6_MON0 0x4584
10134	#define AFE_DL6_MEM_UP_MSB 0x4588
10135	#define AFE_DL6_MEM_UP 0x458c
10136	#define AFE_DL7_BASE_MSB 0x4590
10137	#define AFE_DL7_BASE 0x4594
10138	#define AFE_DL7_CUR_MSB 0x4598
10139	#define AFE_DL7_CUR 0x459c
10140	#define AFE_DL7_END_MSB 0x45a0
10141	#define AFE_DL7_END 0x45a4
10142	#define AFE_DL7_RCH_MON 0x45a8
10143	#define AFE_DL7_LCH_MON 0x45ac
10144	#define AFE_DL7_CON0 0x45b0
10145	#define AFE_DL7_MON0 0x45b4
10146	#define AFE_DL7_MEM_UP_MSB 0x45b8
10147	#define AFE_DL7_MEM_UP 0x45bc
10148	#define AFE_DL8_BASE_MSB 0x45c0
10149	#define AFE_DL8_BASE 0x45c4
10150	#define AFE_DL8_CUR_MSB 0x45c8
10151	#define AFE_DL8_CUR 0x45cc
10152	#define AFE_DL8_END_MSB 0x45d0
10153	#define AFE_DL8_END 0x45d4
10154	#define AFE_DL8_RCH_MON 0x45d8
10155	#define AFE_DL8_LCH_MON 0x45dc
10156	#define AFE_DL8_CON0 0x45e0
10157	#define AFE_DL8_MON0 0x45e4
10158	#define AFE_DL8_MEM_UP_MSB 0x45e8
10159	#define AFE_DL8_MEM_UP 0x45ec
10160	#define AFE_DL_24CH_BASE_MSB 0x4620
10161	#define AFE_DL_24CH_BASE 0x4624
10162	#define AFE_DL_24CH_CUR_MSB 0x4628
10163	#define AFE_DL_24CH_CUR 0x462c
10164	#define AFE_DL_24CH_END_MSB 0x4630
10165	#define AFE_DL_24CH_END 0x4634
10166	#define AFE_DL_24CH_CON0 0x4640
10167	#define AFE_DL_24CH_MON0 0x4644
10168	#define AFE_DL_24CH_MEM_UP_MSB 0x4648
10169	#define AFE_DL_24CH_MEM_UP 0x464c
10170	#define AFE_DL23_BASE_MSB 0x4680
10171	#define AFE_DL23_BASE 0x4684
10172	#define AFE_DL23_CUR_MSB 0x4688
10173	#define AFE_DL23_CUR 0x468c
10174	#define AFE_DL23_END_MSB 0x4690
10175	#define AFE_DL23_END 0x4694
10176	#define AFE_DL23_RCH_MON 0x4698
10177	#define AFE_DL23_LCH_MON 0x469c
10178	#define AFE_DL23_CON0 0x46a0
10179	#define AFE_DL23_MON0 0x46a4
10180	#define AFE_DL23_MEM_UP_MSB 0x46a8
10181	#define AFE_DL23_MEM_UP 0x46ac
10182	#define AFE_DL24_BASE_MSB 0x46b0
10183	#define AFE_DL24_BASE 0x46b4
10184	#define AFE_DL24_CUR_MSB 0x46b8
10185	#define AFE_DL24_CUR 0x46bc
10186	#define AFE_DL24_END_MSB 0x46c0
10187	#define AFE_DL24_END 0x46c4
10188	#define AFE_DL24_RCH_MON 0x46c8
10189	#define AFE_DL24_LCH_MON 0x46cc
10190	#define AFE_DL24_CON0 0x46d0
10191	#define AFE_DL24_MON0 0x46d4
10192	#define AFE_DL24_MEM_UP_MSB 0x46d8
10193	#define AFE_DL24_MEM_UP 0x46dc
10194	#define AFE_DL25_BASE_MSB 0x46e0
10195	#define AFE_DL25_BASE 0x46e4
10196	#define AFE_DL25_CUR_MSB 0x46e8
10197	#define AFE_DL25_CUR 0x46ec
10198	#define AFE_DL25_END_MSB 0x46f0
10199	#define AFE_DL25_END 0x46f4
10200	#define AFE_DL25_RCH_MON 0x46f8
10201	#define AFE_DL25_LCH_MON 0x46fc
10202	#define AFE_DL25_CON0 0x4700
10203	#define AFE_DL25_MON0 0x4704
10204	#define AFE_DL25_MEM_UP_MSB 0x4708
10205	#define AFE_DL25_MEM_UP 0x470c
10206	#define AFE_VUL0_BASE_MSB 0x4d60
10207	#define AFE_VUL0_BASE 0x4d64
10208	#define AFE_VUL0_CUR_MSB 0x4d68
10209	#define AFE_VUL0_CUR 0x4d6c
10210	#define AFE_VUL0_END_MSB 0x4d70
10211	#define AFE_VUL0_END 0x4d74
10212	#define AFE_VUL0_RCH_MON 0x4d78
10213	#define AFE_VUL0_LCH_MON 0x4d7c
10214	#define AFE_VUL0_CON0 0x4d80
10215	#define AFE_VUL0_MON0 0x4d84
10216	#define AFE_VUL1_BASE_MSB 0x4d90
10217	#define AFE_VUL1_BASE 0x4d94
10218	#define AFE_VUL1_CUR_MSB 0x4d98
10219	#define AFE_VUL1_CUR 0x4d9c
10220	#define AFE_VUL1_END_MSB 0x4da0
10221	#define AFE_VUL1_END 0x4da4
10222	#define AFE_VUL1_RCH_MON 0x4da8
10223	#define AFE_VUL1_LCH_MON 0x4dac
10224	#define AFE_VUL1_CON0 0x4db0
10225	#define AFE_VUL1_MON0 0x4db4
10226	#define AFE_VUL2_BASE_MSB 0x4dc0
10227	#define AFE_VUL2_BASE 0x4dc4
10228	#define AFE_VUL2_CUR_MSB 0x4dc8
10229	#define AFE_VUL2_CUR 0x4dcc
10230	#define AFE_VUL2_END_MSB 0x4dd0
10231	#define AFE_VUL2_END 0x4dd4
10232	#define AFE_VUL2_RCH_MON 0x4dd8
10233	#define AFE_VUL2_LCH_MON 0x4ddc
10234	#define AFE_VUL2_CON0 0x4de0
10235	#define AFE_VUL2_MON0 0x4de4
10236	#define AFE_VUL3_BASE_MSB 0x4df0
10237	#define AFE_VUL3_BASE 0x4df4
10238	#define AFE_VUL3_CUR_MSB 0x4df8
10239	#define AFE_VUL3_CUR 0x4dfc
10240	#define AFE_VUL3_END_MSB 0x4e00
10241	#define AFE_VUL3_END 0x4e04
10242	#define AFE_VUL3_RCH_MON 0x4e08
10243	#define AFE_VUL3_LCH_MON 0x4e0c
10244	#define AFE_VUL3_CON0 0x4e10
10245	#define AFE_VUL3_MON0 0x4e14
10246	#define AFE_VUL4_BASE_MSB 0x4e20
10247	#define AFE_VUL4_BASE 0x4e24
10248	#define AFE_VUL4_CUR_MSB 0x4e28
10249	#define AFE_VUL4_CUR 0x4e2c
10250	#define AFE_VUL4_END_MSB 0x4e30
10251	#define AFE_VUL4_END 0x4e34
10252	#define AFE_VUL4_RCH_MON 0x4e38
10253	#define AFE_VUL4_LCH_MON 0x4e3c
10254	#define AFE_VUL4_CON0 0x4e40
10255	#define AFE_VUL4_MON0 0x4e44
10256	#define AFE_VUL5_BASE_MSB 0x4e50
10257	#define AFE_VUL5_BASE 0x4e54
10258	#define AFE_VUL5_CUR_MSB 0x4e58
10259	#define AFE_VUL5_CUR 0x4e5c
10260	#define AFE_VUL5_END_MSB 0x4e60
10261	#define AFE_VUL5_END 0x4e64
10262	#define AFE_VUL5_RCH_MON 0x4e68
10263	#define AFE_VUL5_LCH_MON 0x4e6c
10264	#define AFE_VUL5_CON0 0x4e70
10265	#define AFE_VUL5_MON0 0x4e74
10266	#define AFE_VUL6_BASE_MSB 0x4e80
10267	#define AFE_VUL6_BASE 0x4e84
10268	#define AFE_VUL6_CUR_MSB 0x4e88
10269	#define AFE_VUL6_CUR 0x4e8c
10270	#define AFE_VUL6_END_MSB 0x4e90
10271	#define AFE_VUL6_END 0x4e94
10272	#define AFE_VUL6_RCH_MON 0x4e98
10273	#define AFE_VUL6_LCH_MON 0x4e9c
10274	#define AFE_VUL6_CON0 0x4ea0
10275	#define AFE_VUL6_MON0 0x4ea4
10276	#define AFE_VUL7_BASE_MSB 0x4eb0
10277	#define AFE_VUL7_BASE 0x4eb4
10278	#define AFE_VUL7_CUR_MSB 0x4eb8
10279	#define AFE_VUL7_CUR 0x4ebc
10280	#define AFE_VUL7_END_MSB 0x4ec0
10281	#define AFE_VUL7_END 0x4ec4
10282	#define AFE_VUL7_RCH_MON 0x4ec8
10283	#define AFE_VUL7_LCH_MON 0x4ecc
10284	#define AFE_VUL7_CON0 0x4ed0
10285	#define AFE_VUL7_MON0 0x4ed4
10286	#define AFE_VUL8_BASE_MSB 0x4ee0
10287	#define AFE_VUL8_BASE 0x4ee4
10288	#define AFE_VUL8_CUR_MSB 0x4ee8
10289	#define AFE_VUL8_CUR 0x4eec
10290	#define AFE_VUL8_END_MSB 0x4ef0
10291	#define AFE_VUL8_END 0x4ef4
10292	#define AFE_VUL8_RCH_MON 0x4ef8
10293	#define AFE_VUL8_LCH_MON 0x4efc
10294	#define AFE_VUL8_CON0 0x4f00
10295	#define AFE_VUL8_MON0 0x4f04
10296	#define AFE_VUL9_BASE_MSB 0x4f10
10297	#define AFE_VUL9_BASE 0x4f14
10298	#define AFE_VUL9_CUR_MSB 0x4f18
10299	#define AFE_VUL9_CUR 0x4f1c
10300	#define AFE_VUL9_END_MSB 0x4f20
10301	#define AFE_VUL9_END 0x4f24
10302	#define AFE_VUL9_RCH_MON 0x4f28
10303	#define AFE_VUL9_LCH_MON 0x4f2c
10304	#define AFE_VUL9_CON0 0x4f30
10305	#define AFE_VUL9_MON0 0x4f34
10306	#define AFE_VUL10_BASE_MSB 0x4f40
10307	#define AFE_VUL10_BASE 0x4f44
10308	#define AFE_VUL10_CUR_MSB 0x4f48
10309	#define AFE_VUL10_CUR 0x4f4c
10310	#define AFE_VUL10_END_MSB 0x4f50
10311	#define AFE_VUL10_END 0x4f54
10312	#define AFE_VUL10_RCH_MON 0x4f58
10313	#define AFE_VUL10_LCH_MON 0x4f5c
10314	#define AFE_VUL10_CON0 0x4f60
10315	#define AFE_VUL10_MON0 0x4f64
10316	#define AFE_VUL24_BASE_MSB 0x4fa0
10317	#define AFE_VUL24_BASE 0x4fa4
10318	#define AFE_VUL24_CUR_MSB 0x4fa8
10319	#define AFE_VUL24_CUR 0x4fac
10320	#define AFE_VUL24_END_MSB 0x4fb0
10321	#define AFE_VUL24_END 0x4fb4
10322	#define AFE_VUL24_CON0 0x4fb8
10323	#define AFE_VUL24_MON0 0x4fbc
10324	#define AFE_VUL25_BASE_MSB 0x4fc0
10325	#define AFE_VUL25_BASE 0x4fc4
10326	#define AFE_VUL25_CUR_MSB 0x4fc8
10327	#define AFE_VUL25_CUR 0x4fcc
10328	#define AFE_VUL25_END_MSB 0x4fd0
10329	#define AFE_VUL25_END 0x4fd4
10330	#define AFE_VUL25_CON0 0x4fd8
10331	#define AFE_VUL25_MON0 0x4fdc
10332	#define AFE_VUL_CM0_BASE_MSB 0x51c0
10333	#define AFE_VUL_CM0_BASE 0x51c4
10334	#define AFE_VUL_CM0_CUR_MSB 0x51c8
10335	#define AFE_VUL_CM0_CUR 0x51cc
10336	#define AFE_VUL_CM0_END_MSB 0x51d0
10337	#define AFE_VUL_CM0_END 0x51d4
10338	#define AFE_VUL_CM0_CON0 0x51d8
10339	#define AFE_VUL_CM0_MON0 0x51dc
10340	#define AFE_VUL_CM1_BASE_MSB 0x51e0
10341	#define AFE_VUL_CM1_BASE 0x51e4
10342	#define AFE_VUL_CM1_CUR_MSB 0x51e8
10343	#define AFE_VUL_CM1_CUR 0x51ec
10344	#define AFE_VUL_CM1_END_MSB 0x51f0
10345	#define AFE_VUL_CM1_END 0x51f4
10346	#define AFE_VUL_CM1_CON0 0x51f8
10347	#define AFE_VUL_CM1_MON0 0x51fc
10348	#define AFE_ETDM_IN0_BASE_MSB 0x5220
10349	#define AFE_ETDM_IN0_BASE 0x5224
10350	#define AFE_ETDM_IN0_CUR_MSB 0x5228
10351	#define AFE_ETDM_IN0_CUR 0x522c
10352	#define AFE_ETDM_IN0_END_MSB 0x5230
10353	#define AFE_ETDM_IN0_END 0x5234
10354	#define AFE_ETDM_IN0_CON0 0x5238
10355	#define AFE_ETDM_IN1_BASE_MSB 0x5240
10356	#define AFE_ETDM_IN1_BASE 0x5244
10357	#define AFE_ETDM_IN1_CUR_MSB 0x5248
10358	#define AFE_ETDM_IN1_CUR 0x524c
10359	#define AFE_ETDM_IN1_END_MSB 0x5250
10360	#define AFE_ETDM_IN1_END 0x5254
10361	#define AFE_ETDM_IN1_CON0 0x5258
10362	#define AFE_HDMI_OUT_BASE_MSB 0x5360
10363	#define AFE_HDMI_OUT_BASE 0x5364
10364	#define AFE_HDMI_OUT_CUR_MSB 0x5368
10365	#define AFE_HDMI_OUT_CUR 0x536c
10366	#define AFE_HDMI_OUT_END_MSB 0x5370
10367	#define AFE_HDMI_OUT_END 0x5374
10368	#define AFE_HDMI_OUT_CON0 0x5378
10369	#define AFE_HDMI_OUT_MON0 0x537c
10370	#define AFE_VUL24_RCH_MON 0x53e0
10371	#define AFE_VUL24_LCH_MON 0x53e4
10372	#define AFE_VUL25_RCH_MON 0x53e8
10373	#define AFE_VUL25_LCH_MON 0x53ec
10374	#define AFE_VUL_CM0_RCH_MON 0x5458
10375	#define AFE_VUL_CM0_LCH_MON 0x545c
10376	#define AFE_VUL_CM1_RCH_MON 0x5460
10377	#define AFE_VUL_CM1_LCH_MON 0x5464
10378	#define AFE_DL_24CH_CH0_MON 0x5504
10379	#define AFE_DL_24CH_CH1_MON 0x5508
10380	#define AFE_DL_24CH_CH2_MON 0x550c
10381	#define AFE_DL_24CH_CH3_MON 0x5510
10382	#define AFE_DL_24CH_CH4_MON 0x5514
10383	#define AFE_DL_24CH_CH5_MON 0x5518
10384	#define AFE_DL_24CH_CH6_MON 0x551c
10385	#define AFE_DL_24CH_CH7_MON 0x5520
10386	#define AFE_HDMI_OUT_MEM_UP_MSB 0x55b0
10387	#define AFE_HDMI_OUT_MEM_UP 0x55b4
10388	#define AFE_SRAM_BOUND 0x5620
10389	#define AFE_SECURE_CON0 0x5624
10390	#define AFE_SECURE_CON1 0x5628
10391	#define AFE_SE_SECURE_CON0 0x5630
10392	#define AFE_SE_SECURE_CON1 0x5634
10393	#define AFE_SE_SECURE_CON2 0x5638
10394	#define AFE_SE_SECURE_CON3 0x563c
10395	#define AFE_SE_PROT_SIDEBAND0 0x5640
10396	#define AFE_SE_PROT_SIDEBAND1 0x5644
10397	#define AFE_SE_PROT_SIDEBAND2 0x5648
10398	#define AFE_SE_PROT_SIDEBAND3 0x564c
10399	#define AFE_SE_DOMAIN_SIDEBAND0 0x5650
10400	#define AFE_SE_DOMAIN_SIDEBAND1 0x5654
10401	#define AFE_SE_DOMAIN_SIDEBAND2 0x5658
10402	#define AFE_SE_DOMAIN_SIDEBAND3 0x565c
10403	#define AFE_SE_DOMAIN_SIDEBAND4 0x5660
10404	#define AFE_SE_DOMAIN_SIDEBAND5 0x5664
10405	#define AFE_SE_DOMAIN_SIDEBAND6 0x5668
10406	#define AFE_SE_DOMAIN_SIDEBAND7 0x566c
10407	#define AFE_SE_DOMAIN_SIDEBAND8 0x5670
10408	#define AFE_SE_DOMAIN_SIDEBAND9 0x5674
10409	#define AFE_PROT_SIDEBAND0_MON 0x5678
10410	#define AFE_PROT_SIDEBAND1_MON 0x567c
10411	#define AFE_PROT_SIDEBAND2_MON 0x5680
10412	#define AFE_PROT_SIDEBAND3_MON 0x5684
10413	#define AFE_DOMAIN_SIDEBAND0_MON 0x5688
10414	#define AFE_DOMAIN_SIDEBAND1_MON 0x568c
10415	#define AFE_DOMAIN_SIDEBAND2_MON 0x5690
10416	#define AFE_DOMAIN_SIDEBAND3_MON 0x5694
10417	#define AFE_DOMAIN_SIDEBAND4_MON 0x5698
10418	#define AFE_DOMAIN_SIDEBAND5_MON 0x569c
10419	#define AFE_DOMAIN_SIDEBAND6_MON 0x56a0
10420	#define AFE_DOMAIN_SIDEBAND7_MON 0x56a4
10421	#define AFE_DOMAIN_SIDEBAND8_MON 0x56a8
10422	#define AFE_DOMAIN_SIDEBAND9_MON 0x56ac
10423	#define AFE_SECURE_CONN0 0x56b0
10424	#define AFE_SECURE_CONN_ETDM0 0x56b4
10425	#define AFE_SECURE_CONN_ETDM1 0x56b8
10426	#define AFE_SECURE_CONN_ETDM2 0x56bc
10427	#define AFE_SECURE_SRAM_CON0 0x56c0
10428	#define AFE_SECURE_SRAM_CON1 0x56c4
10429	#define AFE_SE_CONN_INPUT_MASK0 0x56d0
10430	#define AFE_SE_CONN_INPUT_MASK1 0x56d4
10431	#define AFE_SE_CONN_INPUT_MASK2 0x56d8
10432	#define AFE_SE_CONN_INPUT_MASK3 0x56dc
10433	#define AFE_SE_CONN_INPUT_MASK4 0x56e0
10434	#define AFE_SE_CONN_INPUT_MASK5 0x56e4
10435	#define AFE_SE_CONN_INPUT_MASK6 0x56e8
10436	#define AFE_SE_CONN_INPUT_MASK7 0x56ec
10437	#define AFE_NON_SE_CONN_INPUT_MASK0 0x56f0
10438	#define AFE_NON_SE_CONN_INPUT_MASK1 0x56f4
10439	#define AFE_NON_SE_CONN_INPUT_MASK2 0x56f8
10440	#define AFE_NON_SE_CONN_INPUT_MASK3 0x56fc
10441	#define AFE_NON_SE_CONN_INPUT_MASK4 0x5700
10442	#define AFE_NON_SE_CONN_INPUT_MASK5 0x5704
10443	#define AFE_NON_SE_CONN_INPUT_MASK6 0x5708
10444	#define AFE_NON_SE_CONN_INPUT_MASK7 0x570c
10445	#define AFE_SE_CONN_OUTPUT_SEL0 0x5710
10446	#define AFE_SE_CONN_OUTPUT_SEL1 0x5714
10447	#define AFE_SE_CONN_OUTPUT_SEL2 0x5718
10448	#define AFE_SE_CONN_OUTPUT_SEL3 0x571c
10449	#define AFE_SE_CONN_OUTPUT_SEL4 0x5720
10450	#define AFE_SE_CONN_OUTPUT_SEL5 0x5724
10451	#define AFE_SE_CONN_OUTPUT_SEL6 0x5728
10452	#define AFE_SE_CONN_OUTPUT_SEL7 0x572c
10453	#define AFE_PCM0_INTF_CON1_MASK_MON 0x5730
10454	#define AFE_CONNSYS_I2S_CON_MASK_MON 0x5738
10455	#define AFE_TDM_CON2_MASK_MON 0x5744
10456	#define AFE_MTKAIF0_CFG0_MASK_MON 0x574c
10457	#define AFE_MTKAIF1_CFG0_MASK_MON 0x5750
10458	#define AFE_ADDA_UL0_SRC_CON0_MASK_MON 0x5754
10459	#define AFE_ADDA_DMIC0_SRC_CON0_MASK_MON 0x5764
10460	#define AFE_ADDA_DMIC1_SRC_CON0_MASK_MON 0x5768
10461	#define AFE_MON_SECURE_CON0 0x5840
10462	#define AFE_SECURE_CONN_ETDM3 0x5850
10463	#define AFE_ASRC_NEW_CON0 0x7800
10464	#define AFE_ASRC_NEW_CON1 0x7804
10465	#define AFE_ASRC_NEW_CON2 0x7808
10466	#define AFE_ASRC_NEW_CON3 0x780c
10467	#define AFE_ASRC_NEW_CON4 0x7810
10468	#define AFE_ASRC_NEW_CON5 0x7814
10469	#define AFE_ASRC_NEW_CON6 0x7818
10470	#define AFE_ASRC_NEW_CON7 0x781c
10471	#define AFE_ASRC_NEW_CON8 0x7820
10472	#define AFE_ASRC_NEW_CON9 0x7824
10473	#define AFE_ASRC_NEW_CON10 0x7828
10474	#define AFE_ASRC_NEW_CON11 0x782c
10475	#define AFE_ASRC_NEW_CON12 0x7830
10476	#define AFE_ASRC_NEW_CON13 0x7834
10477	#define AFE_ASRC_NEW_CON14 0x7838
10478	#define AFE_ASRC_NEW_IP_VERSION 0x783c
10479	#define AFE_GASRC0_NEW_CON0 0x7840
10480	#define AFE_GASRC0_NEW_CON1 0x7844
10481	#define AFE_GASRC0_NEW_CON2 0x7848
10482	#define AFE_GASRC0_NEW_CON3 0x784c
10483	#define AFE_GASRC0_NEW_CON4 0x7850
10484	#define AFE_GASRC0_NEW_CON5 0x7854
10485	#define AFE_GASRC0_NEW_CON6 0x7858
10486	#define AFE_GASRC0_NEW_CON7 0x785c
10487	#define AFE_GASRC0_NEW_CON8 0x7860
10488	#define AFE_GASRC0_NEW_CON9 0x7864
10489	#define AFE_GASRC0_NEW_CON10 0x7868
10490	#define AFE_GASRC0_NEW_CON11 0x786c
10491	#define AFE_GASRC0_NEW_CON12 0x7870
10492	#define AFE_GASRC0_NEW_CON13 0x7874
10493	#define AFE_GASRC0_NEW_CON14 0x7878
10494	#define AFE_GASRC0_NEW_IP_VERSION 0x787c
10495	#define AFE_GASRC1_NEW_CON0 0x7880
10496	#define AFE_GASRC1_NEW_CON1 0x7884
10497	#define AFE_GASRC1_NEW_CON2 0x7888
10498	#define AFE_GASRC1_NEW_CON3 0x788c
10499	#define AFE_GASRC1_NEW_CON4 0x7890
10500	#define AFE_GASRC1_NEW_CON5 0x7894
10501	#define AFE_GASRC1_NEW_CON6 0x7898
10502	#define AFE_GASRC1_NEW_CON7 0x789c
10503	#define AFE_GASRC1_NEW_CON8 0x78a0
10504	#define AFE_GASRC1_NEW_CON9 0x78a4
10505	#define AFE_GASRC1_NEW_CON10 0x78a8
10506	#define AFE_GASRC1_NEW_CON11 0x78ac
10507	#define AFE_GASRC1_NEW_CON12 0x78b0
10508	#define AFE_GASRC1_NEW_CON13 0x78b4
10509	#define AFE_GASRC1_NEW_CON14 0x78b8
10510	#define AFE_GASRC1_NEW_IP_VERSION 0x78bc
10511	#define AFE_GASRC2_NEW_CON0 0x78c0
10512	#define AFE_GASRC2_NEW_CON1 0x78c4
10513	#define AFE_GASRC2_NEW_CON2 0x78c8
10514	#define AFE_GASRC2_NEW_CON3 0x78cc
10515	#define AFE_GASRC2_NEW_CON4 0x78d0
10516	#define AFE_GASRC2_NEW_CON5 0x78d4
10517	#define AFE_GASRC2_NEW_CON6 0x78d8
10518	#define AFE_GASRC2_NEW_CON7 0x78dc
10519	#define AFE_GASRC2_NEW_CON8 0x78e0
10520	#define AFE_GASRC2_NEW_CON9 0x78e4
10521	#define AFE_GASRC2_NEW_CON10 0x78e8
10522	#define AFE_GASRC2_NEW_CON11 0x78ec
10523	#define AFE_GASRC2_NEW_CON12 0x78f0
10524	#define AFE_GASRC2_NEW_CON13 0x78f4
10525	#define AFE_GASRC2_NEW_CON14 0x78f8
10526	#define AFE_GASRC2_NEW_IP_VERSION 0x78fc
10527	#define AFE_GASRC3_NEW_CON0 0x7900
10528	#define AFE_GASRC3_NEW_CON1 0x7904
10529	#define AFE_GASRC3_NEW_CON2 0x7908
10530	#define AFE_GASRC3_NEW_CON3 0x790c
10531	#define AFE_GASRC3_NEW_CON4 0x7910
10532	#define AFE_GASRC3_NEW_CON5 0x7914
10533	#define AFE_GASRC3_NEW_CON6 0x7918
10534	#define AFE_GASRC3_NEW_CON7 0x791c
10535	#define AFE_GASRC3_NEW_CON8 0x7920
10536	#define AFE_GASRC3_NEW_CON9 0x7924
10537	#define AFE_GASRC3_NEW_CON10 0x7928
10538	#define AFE_GASRC3_NEW_CON11 0x792c
10539	#define AFE_GASRC3_NEW_CON12 0x7930
10540	#define AFE_GASRC3_NEW_CON13 0x7934
10541	#define AFE_GASRC3_NEW_CON14 0x7938
10542	#define AFE_GASRC3_NEW_IP_VERSION 0x793c
10543	#define AFE_GASRC4_NEW_CON0 0x7940
10544	#define AFE_GASRC4_NEW_CON1 0x7944
10545	#define AFE_GASRC4_NEW_CON2 0x7948
10546	#define AFE_GASRC4_NEW_CON3 0x794c
10547	#define AFE_GASRC4_NEW_CON4 0x7950
10548	#define AFE_GASRC4_NEW_CON5 0x7954
10549	#define AFE_GASRC4_NEW_CON6 0x7958
10550	#define AFE_GASRC4_NEW_CON7 0x795c
10551	#define AFE_GASRC4_NEW_CON8 0x7960
10552	#define AFE_GASRC4_NEW_CON9 0x7964
10553	#define AFE_GASRC4_NEW_CON10 0x7968
10554	#define AFE_GASRC4_NEW_CON11 0x796c
10555	#define AFE_GASRC4_NEW_CON12 0x7970
10556	#define AFE_GASRC4_NEW_CON13 0x7974
10557	#define AFE_GASRC4_NEW_CON14 0x7978
10558	#define AFE_GASRC4_NEW_IP_VERSION 0x797c
10559	#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON0 0x9400
10560	#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON1 0x9404
10561	#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON2 0x9408
10562	#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON3 0x940c
10563	#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON4 0x9410
10564	#define AFE_SOUNDWIRE_ULSRC_PHASE_ENGEN_CON0 0x9414
10565	#define AFE_SOUNDWIRE_ULSRC_PHASE_ENGEN_CON1 0x9418
10566	#define AFE_SOUNDWIRE_ULSRC_PHASE_RST_CON0 0x941c
10567	#define AFE_IRQ_MCU_EN 0x9d00
10568	#define AFE_IRQ_MCU_DSP_EN 0x9d04
10569	#define AFE_IRQ_MCU_DSP2_EN 0x9d08
10570	#define AFE_IRQ_MCU_SCP_EN 0x9d0c
10571	#define AFE_CUSTOM_IRQ_MCU_EN 0x9d10
10572	#define AFE_CUSTOM_IRQ_MCU_DSP_EN 0x9d14
10573	#define AFE_CUSTOM_IRQ_MCU_DSP2_EN 0x9d18
10574	#define AFE_CUSTOM_IRQ_MCU_SCP_EN 0x9d1c
10575	#define AFE_IRQ_MCU_STATUS 0x9d20
10576	#define AFE_CUSTOM_IRQ_MCU_STATUS 0x9d24
10577	#define AFE_IRQ0_MCU_CFG0 0x9d40
10578	#define AFE_IRQ0_MCU_CFG1 0x9d44
10579	#define AFE_IRQ1_MCU_CFG0 0x9d48
10580	#define AFE_IRQ1_MCU_CFG1 0x9d4c
10581	#define AFE_IRQ2_MCU_CFG0 0x9d50
10582	#define AFE_IRQ2_MCU_CFG1 0x9d54
10583	#define AFE_IRQ3_MCU_CFG0 0x9d58
10584	#define AFE_IRQ3_MCU_CFG1 0x9d5c
10585	#define AFE_IRQ4_MCU_CFG0 0x9d60
10586	#define AFE_IRQ4_MCU_CFG1 0x9d64
10587	#define AFE_IRQ5_MCU_CFG0 0x9d68
10588	#define AFE_IRQ5_MCU_CFG1 0x9d6c
10589	#define AFE_IRQ6_MCU_CFG0 0x9d70
10590	#define AFE_IRQ6_MCU_CFG1 0x9d74
10591	#define AFE_IRQ7_MCU_CFG0 0x9d78
10592	#define AFE_IRQ7_MCU_CFG1 0x9d7c
10593	#define AFE_IRQ8_MCU_CFG0 0x9d80
10594	#define AFE_IRQ8_MCU_CFG1 0x9d84
10595	#define AFE_IRQ9_MCU_CFG0 0x9d88
10596	#define AFE_IRQ9_MCU_CFG1 0x9d8c
10597	#define AFE_IRQ10_MCU_CFG0 0x9d90
10598	#define AFE_IRQ10_MCU_CFG1 0x9d94
10599	#define AFE_IRQ11_MCU_CFG0 0x9d98
10600	#define AFE_IRQ11_MCU_CFG1 0x9d9c
10601	#define AFE_IRQ12_MCU_CFG0 0x9da0
10602	#define AFE_IRQ12_MCU_CFG1 0x9da4
10603	#define AFE_IRQ13_MCU_CFG0 0x9da8
10604	#define AFE_IRQ13_MCU_CFG1 0x9dac
10605	#define AFE_IRQ14_MCU_CFG0 0x9db0
10606	#define AFE_IRQ14_MCU_CFG1 0x9db4
10607	#define AFE_IRQ15_MCU_CFG0 0x9db8
10608	#define AFE_IRQ15_MCU_CFG1 0x9dbc
10609	#define AFE_IRQ16_MCU_CFG0 0x9dc0
10610	#define AFE_IRQ16_MCU_CFG1 0x9dc4
10611	#define AFE_IRQ17_MCU_CFG0 0x9dc8
10612	#define AFE_IRQ17_MCU_CFG1 0x9dcc
10613	#define AFE_IRQ18_MCU_CFG0 0x9dd0
10614	#define AFE_IRQ18_MCU_CFG1 0x9dd4
10615	#define AFE_IRQ19_MCU_CFG0 0x9dd8
10616	#define AFE_IRQ19_MCU_CFG1 0x9ddc
10617	#define AFE_IRQ20_MCU_CFG0 0x9de0
10618	#define AFE_IRQ20_MCU_CFG1 0x9de4
10619	#define AFE_IRQ21_MCU_CFG0 0x9de8
10620	#define AFE_IRQ21_MCU_CFG1 0x9dec
10621	#define AFE_IRQ22_MCU_CFG0 0x9df0
10622	#define AFE_IRQ22_MCU_CFG1 0x9df4
10623	#define AFE_IRQ23_MCU_CFG0 0x9df8
10624	#define AFE_IRQ23_MCU_CFG1 0x9dfc
10625	#define AFE_IRQ24_MCU_CFG0 0x9e00
10626	#define AFE_IRQ24_MCU_CFG1 0x9e04
10627	#define AFE_IRQ25_MCU_CFG0 0x9e08
10628	#define AFE_IRQ25_MCU_CFG1 0x9e0c
10629	#define AFE_IRQ26_MCU_CFG0 0x9e10
10630	#define AFE_IRQ26_MCU_CFG1 0x9e14
10631	#define AFE_CUSTOM_IRQ0_MCU_CFG0 0x9e68
10632	#define AFE_CUSTOM_IRQ22_MCU_CFG0 0x9ec8
10633	#define AFE_CUSTOM_IRQ22_MCU_CFG1 0x9ecc
10634	#define AFE_CUSTOM_IRQ23_MCU_CFG0 0x9ed0
10635	#define AFE_CUSTOM_IRQ23_MCU_CFG1 0x9ed4
10636	#define AFE_IRQ0_CNT_MON 0x9f10
10637	#define AFE_IRQ1_CNT_MON 0x9f14
10638	#define AFE_IRQ2_CNT_MON 0x9f18
10639	#define AFE_IRQ3_CNT_MON 0x9f1c
10640	#define AFE_IRQ4_CNT_MON 0x9f20
10641	#define AFE_IRQ5_CNT_MON 0x9f24
10642	#define AFE_IRQ6_CNT_MON 0x9f28
10643	#define AFE_IRQ7_CNT_MON 0x9f2c
10644	#define AFE_IRQ8_CNT_MON 0x9f30
10645	#define AFE_IRQ9_CNT_MON 0x9f34
10646	#define AFE_IRQ10_CNT_MON 0x9f38
10647	#define AFE_IRQ11_CNT_MON 0x9f3c
10648	#define AFE_IRQ12_CNT_MON 0x9f40
10649	#define AFE_IRQ13_CNT_MON 0x9f44
10650	#define AFE_IRQ14_CNT_MON 0x9f48
10651	#define AFE_IRQ15_CNT_MON 0x9f4c
10652	#define AFE_IRQ16_CNT_MON 0x9f50
10653	#define AFE_IRQ17_CNT_MON 0x9f54
10654	#define AFE_IRQ18_CNT_MON 0x9f58
10655	#define AFE_IRQ19_CNT_MON 0x9f5c
10656	#define AFE_IRQ20_CNT_MON 0x9f60
10657	#define AFE_IRQ21_CNT_MON 0x9f64
10658	#define AFE_IRQ22_CNT_MON 0x9f68
10659	#define AFE_IRQ23_CNT_MON 0x9f6c
10660	#define AFE_IRQ24_CNT_MON 0x9f70
10661	#define AFE_IRQ25_CNT_MON 0x9f74
10662	#define AFE_IRQ26_CNT_MON 0x9f78
10663	#define AFE_CUSTOM_IRQ0_CNT_MON 0x9f90
10664	#define AFE_CUSTOM_IRQ0_MCU_CFG1 0x9fdc
10665	#define AFE_IRQ_MCU_DSP3_EN 0xa000
10666	#define AFE_CUSTOM_IRQ_MCU_DSP3_EN 0xa004
10667	#define AFE_CUSTOM2_IRQ_MCU_EN 0xa008
10668	#define AFE_CUSTOM2_IRQ_MCU_DSP_EN 0xa00c
10669	#define AFE_CUSTOM2_IRQ_MCU_DSP2_EN 0xa010
10670	#define AFE_CUSTOM2_IRQ_MCU_DSP3_EN 0xa014
10671	#define AFE_CUSTOM2_IRQ_MCU_SCP_EN 0xa018
10672	#define AFE_IRQ_MCU_MON3 0xa01c
10673	#define AFE_IRQ_MCU_MON0 0xa024
10674	#define AFE_IRQ_MCU_MON1 0xa028
10675	#define AFE_IRQ_MCU_MON2 0xa02c
10676	#define AFE_CUSTOM2_IRQ_MISS_FLAG_MCU_MON 0xa034
10677	#define AFE_CUSTOM2_IRQ_DELAY_EN 0xa038
10678	#define AFE_CUSTOM2_IRQ_MCU_STATUS 0xa03c
10679	#define AFE_CUSTOM2_IRQ0_MCU_CFG0 0xa040
10680	#define AFE_CUSTOM2_IRQ0_MCU_CFG1 0xa044
10681	#define AFE_CUSTOM2_IRQ0_CNT_MON 0xa048
10682	#define AFE_CUSTOM2_IRQ0_MCU_DELAY_CNT_CFG0 0xa04c
10683	#define AFE_CUSTOM2_IRQ1_MCU_CFG0 0xa050
10684	#define AFE_CUSTOM2_IRQ1_MCU_CFG1 0xa054
10685	#define AFE_CUSTOM2_IRQ1_CNT_MON 0xa058
10686	#define AFE_CUSTOM2_IRQ1_MCU_DELAY_CNT_CFG0 0xa05c
10687	#define AFE_CUSTOM2_IRQ2_MCU_CFG0 0xa060
10688	#define AFE_CUSTOM2_IRQ2_MCU_CFG1 0xa064
10689	#define AFE_CUSTOM2_IRQ2_CNT_MON 0xa068
10690	#define AFE_CUSTOM2_IRQ2_MCU_DELAY_CNT_CFG0 0xa06c
10691	#define AFE_CUSTOM2_IRQ3_MCU_CFG0 0xa070
10692	#define AFE_CUSTOM2_IRQ3_MCU_CFG1 0xa074
10693	#define AFE_CUSTOM2_IRQ3_CNT_MON 0xa078
10694	#define AFE_CUSTOM2_IRQ3_MCU_DELAY_CNT_CFG0 0xa07c
10695	#define AFE_CUSTOM2_IRQ4_MCU_CFG0 0xa080
10696	#define AFE_CUSTOM2_IRQ4_MCU_CFG1 0xa084
10697	#define AFE_CUSTOM2_IRQ4_CNT_MON 0xa088
10698	#define AFE_CUSTOM2_IRQ4_MCU_DELAY_CNT_CFG0 0xa08c
10699	#define AFE_CUSTOM2_IRQ5_MCU_CFG0 0xa090
10700	#define AFE_CUSTOM2_IRQ5_MCU_CFG1 0xa094
10701	#define AFE_CUSTOM2_IRQ5_CNT_MON 0xa098
10702	#define AFE_CUSTOM2_IRQ5_MCU_DELAY_CNT_CFG0 0xa09c
10703	#define AFE_CUSTOM2_IRQ6_MCU_CFG0 0xa0a0
10704	#define AFE_CUSTOM2_IRQ6_MCU_CFG1 0xa0a4
10705	#define AFE_CUSTOM2_IRQ6_CNT_MON 0xa0a8
10706	#define AFE_CUSTOM2_IRQ6_MCU_DELAY_CNT_CFG0 0xa0ac
10707	#define AFE_CUSTOM2_IRQ7_MCU_CFG0 0xa0b0
10708	#define AFE_CUSTOM2_IRQ7_MCU_CFG1 0xa0b4
10709	#define AFE_CUSTOM2_IRQ7_CNT_MON 0xa0b8
10710	#define AFE_CUSTOM2_IRQ7_MCU_DELAY_CNT_CFG0 0xa0bc
10711	#define AFE_CUSTOM2_IRQ8_MCU_CFG0 0xa0c0
10712	#define AFE_CUSTOM2_IRQ8_MCU_CFG1 0xa0c4
10713	#define AFE_CUSTOM2_IRQ8_CNT_MON 0xa0c8
10714	#define AFE_CUSTOM2_IRQ8_MCU_DELAY_CNT_CFG0 0xa0cc
10715	#define AFE_CUSTOM2_IRQ9_MCU_CFG0 0xa0d0
10716	#define AFE_CUSTOM2_IRQ9_MCU_CFG1 0xa0d4
10717	#define AFE_CUSTOM2_IRQ9_CNT_MON 0xa0d8
10718	#define AFE_CUSTOM2_IRQ9_MCU_DELAY_CNT_CFG0 0xa0dc
10719	#define AFE_CUSTOM2_IRQ10_MCU_CFG0 0xa0e0
10720	#define AFE_CUSTOM2_IRQ10_MCU_CFG1 0xa0e4
10721	#define AFE_CUSTOM2_IRQ10_CNT_MON 0xa0e8
10722	#define AFE_CUSTOM2_IRQ10_MCU_DELAY_CNT_CFG0 0xa0ec
10723	#define AFE_CUSTOM2_IRQ11_MCU_CFG0 0xa0f0
10724	#define AFE_CUSTOM2_IRQ11_MCU_CFG1 0xa0f4
10725	#define AFE_CUSTOM2_IRQ11_CNT_MON 0xa0f8
10726	#define AFE_CUSTOM2_IRQ11_MCU_DELAY_CNT_CFG0 0xa0fc
10727	#define AFE_CUSTOM2_IRQ12_MCU_CFG0 0xa100
10728	#define AFE_CUSTOM2_IRQ12_MCU_CFG1 0xa104
10729	#define AFE_CUSTOM2_IRQ12_CNT_MON 0xa108
10730	#define AFE_CUSTOM2_IRQ12_MCU_DELAY_CNT_CFG0 0xa10c
10731	#define AFE_CUSTOM2_IRQ30_MCU_CFG0 0xa220
10732	#define AFE_CUSTOM2_IRQ30_MCU_CFG1 0xa224
10733	#define AFE_CUSTOM2_IRQ30_CNT_MON 0xa228
10734	#define AFE_CUSTOM2_IRQ30_MCU_DELAY_CNT_CFG0 0xa22c
10735	#define AFE_CUSTOM2_IRQ31_MCU_CFG0 0xa230
10736	#define AFE_CUSTOM2_IRQ31_MCU_CFG1 0xa234
10737	#define AFE_CUSTOM2_IRQ31_CNT_MON 0xa238
10738	#define AFE_CUSTOM2_IRQ31_MCU_DELAY_CNT_CFG0 0xa23c
10739	#define AFE_CUSTOM3_IRQ8_MCU_CFG0 0xa2c0
10740	#define AFE_CUSTOM3_IRQ8_MCU_CFG1 0xa2c4
10741	#define AFE_CUSTOM3_IRQ8_CNT_MON 0xa2c8
10742	#define AFE_CUSTOM3_IRQ8_MCU_DELAY_CNT_CFG0 0xa2cc
10743	#define AFE_CUSTOM3_IRQ9_MCU_CFG0 0xa2d0
10744	#define AFE_CUSTOM3_IRQ9_MCU_CFG1 0xa2d4
10745	#define AFE_CUSTOM3_IRQ9_CNT_MON 0xa2d8
10746	#define AFE_CUSTOM3_IRQ9_MCU_DELAY_CNT_CFG0 0xa2dc
10747	#define AFE_CUSTOM3_IRQ_MISS_FLAG_MCU_MON 0xa440
10748	#define AFE_CUSTOM3_IRQ_DELAY_EN 0xa444
10749	#define AFE_CUSTOM3_IRQ_MCU_STATUS 0xa448
10750	#define AFE_CUSTOM3_IRQ_MCU_EN 0xa44c
10751	#define AFE_CUSTOM3_IRQ_MCU_DSP_EN 0xa450
10752	#define AFE_CUSTOM3_IRQ_MCU_DSP2_EN 0xa454
10753	#define AFE_CUSTOM3_IRQ_MCU_DSP3_EN 0xa458
10754	#define AFE_CUSTOM3_IRQ_MCU_DSP_WLA_EN 0xa45c
10755	#define AFE_CUSTOM3_IRQ_MCU_SCP_EN 0xa460
10756	#define AFE_CUSTOM2_IRQ_MCU_DSP_WLA_EN 0xa464
10757	#define AFE_IRQ_MCU_DSP_WLA_EN 0xa468
10758	#define AFE_COMMON2_IRQ_MCU_STATUS 0xa46c
10759	#define AFE_COMMON2_IRQ_MCU_EN 0xa470
10760	#define AFE_COMMON2_IRQ_MCU_DSP_EN 0xa474
10761	#define AFE_COMMON2_IRQ_MCU_DSP2_EN 0xa478
10762	#define AFE_COMMON2_IRQ_MCU_DSP3_EN 0xa47c
10763	#define AFE_COMMON2_IRQ_MCU_DSP_WLA_EN 0xa480
10764	#define AFE_COMMON2_IRQ_MCU_SCP_EN 0xa484
10765	#define AFE_CUSTOM_IRQ_MCU_DSP_WLA_EN 0xa508
10766
10767	#define AFE_MAX_REGISTER AFE_CUSTOM_IRQ_MCU_DSP_WLA_EN
10768
10769	#define AFE_IRQ_STATUS_BITS 0x7FFFFFF
10770	#define AFE_IRQ_CNT_SHIFT 0
10771	#define AFE_IRQ_CNT_MASK 0xffffff
10772
10773	#endif
10774