1// SPDX-License-Identifier: GPL-2.0
2//
3// MediaTek ALSA SoC Audio DAI ADDA Control
4//
5// Copyright (c) 2020 MediaTek Inc.
6// Author: Shane Chien <shane.chien@mediatek.com>
7//
8
9#include <linux/delay.h>
10#include <linux/regmap.h>
11
12#include "mt8192-afe-clk.h"
13#include "mt8192-afe-common.h"
14#include "mt8192-afe-gpio.h"
15#include "mt8192-interconnection.h"
16#include "../common/mtk-dai-adda-common.h"
17
18enum {
19 UL_IIR_SW = 0,
20 UL_IIR_5HZ,
21 UL_IIR_10HZ,
22 UL_IIR_25HZ,
23 UL_IIR_50HZ,
24 UL_IIR_75HZ,
25};
26
27enum {
28 AUDIO_SDM_LEVEL_MUTE = 0,
29 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
30 /* if you change level normal */
31 /* you need to change formula of hp impedance and dc trim too */
32};
33
34enum {
35 AUDIO_SDM_2ND = 0,
36 AUDIO_SDM_3RD,
37};
38
39#define SDM_AUTO_RESET_THRESHOLD 0x190000
40
41/* dai component */
42static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
43 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
44 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0),
45 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
46 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
47 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0),
48 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0),
49 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0),
50 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0),
51 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3,
52 I_ADDA_UL_CH3, 1, 0),
53 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
54 I_ADDA_UL_CH2, 1, 0),
55 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
56 I_ADDA_UL_CH1, 1, 0),
57 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3,
58 I_GAIN1_OUT_CH1, 1, 0),
59 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
60 I_PCM_1_CAP_CH1, 1, 0),
61 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
62 I_PCM_2_CAP_CH1, 1, 0),
63 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1,
64 I_SRC_1_OUT_CH1, 1, 0),
65 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1,
66 I_SRC_2_OUT_CH1, 1, 0),
67};
68
69static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
70 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
71 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
72 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0),
73 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
74 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
75 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
76 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
77 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0),
78 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0),
79 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0),
80 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0),
81 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4,
82 I_ADDA_UL_CH3, 1, 0),
83 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
84 I_ADDA_UL_CH2, 1, 0),
85 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
86 I_ADDA_UL_CH1, 1, 0),
87 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4,
88 I_GAIN1_OUT_CH2, 1, 0),
89 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
90 I_PCM_1_CAP_CH1, 1, 0),
91 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
92 I_PCM_2_CAP_CH1, 1, 0),
93 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
94 I_PCM_1_CAP_CH2, 1, 0),
95 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
96 I_PCM_2_CAP_CH2, 1, 0),
97 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1,
98 I_SRC_1_OUT_CH2, 1, 0),
99 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1,
100 I_SRC_2_OUT_CH2, 1, 0),
101};
102
103static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
104 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0),
105 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0),
106 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0),
107 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0),
108 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0),
109 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0),
110 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0),
111 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52,
112 I_ADDA_UL_CH3, 1, 0),
113 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52,
114 I_ADDA_UL_CH2, 1, 0),
115 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52,
116 I_ADDA_UL_CH1, 1, 0),
117 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52,
118 I_GAIN1_OUT_CH1, 1, 0),
119 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52,
120 I_PCM_1_CAP_CH1, 1, 0),
121 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52,
122 I_PCM_2_CAP_CH1, 1, 0),
123};
124
125static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
126 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0),
127 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0),
128 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0),
129 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0),
130 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0),
131 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0),
132 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0),
133 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0),
134 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0),
135 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0),
136 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53,
137 I_ADDA_UL_CH3, 1, 0),
138 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53,
139 I_ADDA_UL_CH2, 1, 0),
140 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53,
141 I_ADDA_UL_CH1, 1, 0),
142 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53,
143 I_GAIN1_OUT_CH2, 1, 0),
144 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53,
145 I_PCM_1_CAP_CH1, 1, 0),
146 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53,
147 I_PCM_2_CAP_CH1, 1, 0),
148 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53,
149 I_PCM_1_CAP_CH2, 1, 0),
150 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53,
151 I_PCM_2_CAP_CH2, 1, 0),
152};
153
154static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = {
155 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19,
156 I_ADDA_UL_CH1, 1, 0),
157};
158
159static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = {
160 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20,
161 I_ADDA_UL_CH2, 1, 0),
162};
163
164enum {
165 SUPPLY_SEQ_ADDA_AFE_ON,
166 SUPPLY_SEQ_ADDA_DL_ON,
167 SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
168 SUPPLY_SEQ_ADDA_MTKAIF_CFG,
169 SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
170 SUPPLY_SEQ_ADDA_FIFO,
171 SUPPLY_SEQ_ADDA_AP_DMIC,
172 SUPPLY_SEQ_ADDA_UL_ON,
173};
174
175static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
176{
177 unsigned int reg;
178
179 switch (id) {
180 case MT8192_DAI_ADDA:
181 case MT8192_DAI_AP_DMIC:
182 reg = AFE_ADDA_UL_SRC_CON0;
183 break;
184 case MT8192_DAI_ADDA_CH34:
185 case MT8192_DAI_AP_DMIC_CH34:
186 reg = AFE_ADDA6_UL_SRC_CON0;
187 break;
188 default:
189 return -EINVAL;
190 }
191
192 /* dmic mode, 3.25M*/
193 regmap_update_bits(map: afe->regmap, reg,
194 DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
195 val: 0x0);
196 regmap_update_bits(map: afe->regmap, reg,
197 DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
198 val: 0x0);
199
200 /* turn on dmic, ch1, ch2 */
201 regmap_update_bits(map: afe->regmap, reg,
202 UL_SDM_3_LEVEL_CTL_MASK_SFT,
203 val: 0x1 << UL_SDM_3_LEVEL_CTL_SFT);
204 regmap_update_bits(map: afe->regmap, reg,
205 UL_MODE_3P25M_CH1_CTL_MASK_SFT,
206 val: 0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
207 regmap_update_bits(map: afe->regmap, reg,
208 UL_MODE_3P25M_CH2_CTL_MASK_SFT,
209 val: 0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
210 return 0;
211}
212
213static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
214 struct snd_kcontrol *kcontrol,
215 int event)
216{
217 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
218 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
219 struct mt8192_afe_private *afe_priv = afe->platform_priv;
220 int mtkaif_dmic = afe_priv->mtkaif_dmic;
221
222 switch (event) {
223 case SND_SOC_DAPM_PRE_PMU:
224 mt8192_afe_gpio_request(dev: afe->dev, enable: true, dai: MT8192_DAI_ADDA, uplink: 1);
225
226 /* update setting to dmic */
227 if (mtkaif_dmic) {
228 /* mtkaif_rxif_data_mode = 1, dmic */
229 regmap_update_bits(map: afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
230 mask: 0x1, val: 0x1);
231
232 /* dmic mode, 3.25M*/
233 regmap_update_bits(map: afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
234 MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
235 val: 0x0);
236 mtk_adda_ul_src_dmic(afe, id: MT8192_DAI_ADDA);
237 }
238 break;
239 case SND_SOC_DAPM_POST_PMD:
240 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
241 usleep_range(min: 125, max: 135);
242 mt8192_afe_gpio_request(dev: afe->dev, enable: false, dai: MT8192_DAI_ADDA, uplink: 1);
243 break;
244 default:
245 break;
246 }
247
248 return 0;
249}
250
251static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w,
252 struct snd_kcontrol *kcontrol,
253 int event)
254{
255 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
256 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
257 struct mt8192_afe_private *afe_priv = afe->platform_priv;
258 int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34;
259 int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only;
260
261 switch (event) {
262 case SND_SOC_DAPM_PRE_PMU:
263 mt8192_afe_gpio_request(dev: afe->dev, enable: true, dai: MT8192_DAI_ADDA_CH34,
264 uplink: 1);
265
266 /* update setting to dmic */
267 if (mtkaif_dmic) {
268 /* mtkaif_rxif_data_mode = 1, dmic */
269 regmap_update_bits(map: afe->regmap,
270 AFE_ADDA6_MTKAIF_RX_CFG0,
271 mask: 0x1, val: 0x1);
272
273 /* dmic mode, 3.25M*/
274 regmap_update_bits(map: afe->regmap,
275 AFE_ADDA6_MTKAIF_RX_CFG0,
276 MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
277 val: 0x0);
278 mtk_adda_ul_src_dmic(afe, id: MT8192_DAI_ADDA_CH34);
279 }
280
281 /* when using adda6 without adda enabled,
282 * RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or
283 * data cannot be received.
284 */
285 if (mtkaif_adda6_only) {
286 regmap_update_bits(map: afe->regmap,
287 AFE_ADDA_MTKAIF_SYNCWORD_CFG,
288 mask: 0x1 << 23, val: 0x1 << 23);
289 }
290 break;
291 case SND_SOC_DAPM_POST_PMD:
292 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
293 usleep_range(min: 125, max: 135);
294 mt8192_afe_gpio_request(dev: afe->dev, enable: false, dai: MT8192_DAI_ADDA_CH34,
295 uplink: 1);
296
297 /* reset dmic */
298 afe_priv->mtkaif_dmic_ch34 = 0;
299
300 if (mtkaif_adda6_only) {
301 regmap_update_bits(map: afe->regmap,
302 AFE_ADDA_MTKAIF_SYNCWORD_CFG,
303 mask: 0x1 << 23, val: 0x0 << 23);
304 }
305 break;
306 default:
307 break;
308 }
309
310 return 0;
311}
312
313static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
314 struct snd_kcontrol *kcontrol,
315 int event)
316{
317 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
318 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
319 struct mt8192_afe_private *afe_priv = afe->platform_priv;
320
321 switch (event) {
322 case SND_SOC_DAPM_PRE_PMU:
323 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
324 regmap_write(map: afe->regmap, AFE_AUD_PAD_TOP, val: 0x38);
325 else
326 regmap_write(map: afe->regmap, AFE_AUD_PAD_TOP, val: 0x30);
327 break;
328 default:
329 break;
330 }
331
332 return 0;
333}
334
335static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
336 struct snd_kcontrol *kcontrol,
337 int event)
338{
339 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
340 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
341 struct mt8192_afe_private *afe_priv = afe->platform_priv;
342 int delay_data;
343 int delay_cycle;
344
345 switch (event) {
346 case SND_SOC_DAPM_PRE_PMU:
347 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
348 /* set protocol 2 */
349 regmap_write(map: afe->regmap, AFE_ADDA_MTKAIF_CFG0,
350 val: 0x00010000);
351 regmap_write(map: afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
352 val: 0x00010000);
353
354 if (snd_soc_dapm_widget_name_cmp(widget: w, s: "ADDA_MTKAIF_CFG") == 0 &&
355 (afe_priv->mtkaif_chosen_phase[0] < 0 ||
356 afe_priv->mtkaif_chosen_phase[1] < 0)) {
357 dev_warn(afe->dev,
358 "%s(), mtkaif_chosen_phase[0/1]:%d/%d\n",
359 __func__,
360 afe_priv->mtkaif_chosen_phase[0],
361 afe_priv->mtkaif_chosen_phase[1]);
362 break;
363 } else if (snd_soc_dapm_widget_name_cmp(widget: w, s: "ADDA6_MTKAIF_CFG") == 0 &&
364 afe_priv->mtkaif_chosen_phase[2] < 0) {
365 dev_warn(afe->dev,
366 "%s(), mtkaif_chosen_phase[2]:%d\n",
367 __func__,
368 afe_priv->mtkaif_chosen_phase[2]);
369 break;
370 }
371
372 /* mtkaif_rxif_clkinv_adc inverse for calibration */
373 regmap_update_bits(map: afe->regmap, AFE_ADDA_MTKAIF_CFG0,
374 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
375 val: 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
376 regmap_update_bits(map: afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
377 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
378 val: 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
379
380 /* set delay for ch12 */
381 if (afe_priv->mtkaif_phase_cycle[0] >=
382 afe_priv->mtkaif_phase_cycle[1]) {
383 delay_data = DELAY_DATA_MISO1;
384 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
385 afe_priv->mtkaif_phase_cycle[1];
386 } else {
387 delay_data = DELAY_DATA_MISO2;
388 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
389 afe_priv->mtkaif_phase_cycle[0];
390 }
391
392 regmap_update_bits(map: afe->regmap,
393 AFE_ADDA_MTKAIF_RX_CFG2,
394 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
395 val: delay_data <<
396 MTKAIF_RXIF_DELAY_DATA_SFT);
397
398 regmap_update_bits(map: afe->regmap,
399 AFE_ADDA_MTKAIF_RX_CFG2,
400 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
401 val: delay_cycle <<
402 MTKAIF_RXIF_DELAY_CYCLE_SFT);
403
404 /* set delay between ch3 and ch2 */
405 if (afe_priv->mtkaif_phase_cycle[2] >=
406 afe_priv->mtkaif_phase_cycle[1]) {
407 delay_data = DELAY_DATA_MISO1; /* ch3 */
408 delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
409 afe_priv->mtkaif_phase_cycle[1];
410 } else {
411 delay_data = DELAY_DATA_MISO2; /* ch2 */
412 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
413 afe_priv->mtkaif_phase_cycle[2];
414 }
415
416 regmap_update_bits(map: afe->regmap,
417 AFE_ADDA6_MTKAIF_RX_CFG2,
418 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
419 val: delay_data <<
420 MTKAIF_RXIF_DELAY_DATA_SFT);
421 regmap_update_bits(map: afe->regmap,
422 AFE_ADDA6_MTKAIF_RX_CFG2,
423 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
424 val: delay_cycle <<
425 MTKAIF_RXIF_DELAY_CYCLE_SFT);
426 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
427 regmap_write(map: afe->regmap, AFE_ADDA_MTKAIF_CFG0,
428 val: 0x00010000);
429 regmap_write(map: afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
430 val: 0x00010000);
431 } else {
432 regmap_write(map: afe->regmap, AFE_ADDA_MTKAIF_CFG0, val: 0x0);
433 regmap_write(map: afe->regmap, AFE_ADDA6_MTKAIF_CFG0, val: 0x0);
434 }
435 break;
436 default:
437 break;
438 }
439
440 return 0;
441}
442
443static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
444 struct snd_kcontrol *kcontrol,
445 int event)
446{
447 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
448 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
449
450 switch (event) {
451 case SND_SOC_DAPM_PRE_PMU:
452 mt8192_afe_gpio_request(dev: afe->dev, enable: true, dai: MT8192_DAI_ADDA, uplink: 0);
453 break;
454 case SND_SOC_DAPM_POST_PMD:
455 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
456 usleep_range(min: 125, max: 135);
457 mt8192_afe_gpio_request(dev: afe->dev, enable: false, dai: MT8192_DAI_ADDA, uplink: 0);
458 break;
459 default:
460 break;
461 }
462
463 return 0;
464}
465
466static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w,
467 struct snd_kcontrol *kcontrol,
468 int event)
469{
470 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
471 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
472
473 switch (event) {
474 case SND_SOC_DAPM_PRE_PMU:
475 mt8192_afe_gpio_request(dev: afe->dev, enable: true, dai: MT8192_DAI_ADDA_CH34,
476 uplink: 0);
477 break;
478 case SND_SOC_DAPM_POST_PMD:
479 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
480 usleep_range(min: 125, max: 135);
481 mt8192_afe_gpio_request(dev: afe->dev, enable: false, dai: MT8192_DAI_ADDA_CH34,
482 uplink: 0);
483 break;
484 default:
485 break;
486 }
487
488 return 0;
489}
490
491/* stf */
492static int stf_positive_gain_get(struct snd_kcontrol *kcontrol,
493 struct snd_ctl_elem_value *ucontrol)
494{
495 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
496 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
497 struct mt8192_afe_private *afe_priv = afe->platform_priv;
498
499 ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db;
500 return 0;
501}
502
503static int stf_positive_gain_set(struct snd_kcontrol *kcontrol,
504 struct snd_ctl_elem_value *ucontrol)
505{
506 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
507 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
508 struct mt8192_afe_private *afe_priv = afe->platform_priv;
509 int gain_db = ucontrol->value.integer.value[0];
510 bool change = false;
511
512 afe_priv->stf_positive_gain_db = gain_db;
513
514 if (gain_db >= 0 && gain_db <= 24) {
515 regmap_update_bits_check(map: afe->regmap,
516 AFE_SIDETONE_GAIN,
517 POSITIVE_GAIN_MASK_SFT,
518 val: (gain_db / 6) << POSITIVE_GAIN_SFT,
519 change: &change);
520 } else {
521 return -EINVAL;
522 }
523
524 return change;
525}
526
527static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol,
528 struct snd_ctl_elem_value *ucontrol)
529{
530 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
531 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
532 struct mt8192_afe_private *afe_priv = afe->platform_priv;
533
534 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
535 return 0;
536}
537
538static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol,
539 struct snd_ctl_elem_value *ucontrol)
540{
541 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
542 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
543 struct mt8192_afe_private *afe_priv = afe->platform_priv;
544 int dmic_on;
545 bool change;
546
547 dmic_on = ucontrol->value.integer.value[0];
548
549 change = (afe_priv->mtkaif_dmic != dmic_on) ||
550 (afe_priv->mtkaif_dmic_ch34 != dmic_on);
551
552 afe_priv->mtkaif_dmic = dmic_on;
553 afe_priv->mtkaif_dmic_ch34 = dmic_on;
554
555 return change;
556}
557
558static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol,
559 struct snd_ctl_elem_value *ucontrol)
560{
561 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
562 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
563 struct mt8192_afe_private *afe_priv = afe->platform_priv;
564
565 ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only;
566 return 0;
567}
568
569static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol,
570 struct snd_ctl_elem_value *ucontrol)
571{
572 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
573 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
574 struct mt8192_afe_private *afe_priv = afe->platform_priv;
575 int mtkaif_adda6_only;
576 bool change;
577
578 mtkaif_adda6_only = ucontrol->value.integer.value[0];
579
580 change = afe_priv->mtkaif_adda6_only != mtkaif_adda6_only;
581 afe_priv->mtkaif_adda6_only = mtkaif_adda6_only;
582
583 return change;
584}
585
586static const struct snd_kcontrol_new mtk_adda_controls[] = {
587 SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN,
588 SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0),
589 SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 24, 0,
590 stf_positive_gain_get, stf_positive_gain_set),
591 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
592 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
593 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
594 mt8192_adda_dmic_get, mt8192_adda_dmic_set),
595 SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0,
596 mt8192_adda6_only_get, mt8192_adda6_only_set),
597};
598
599static const struct snd_kcontrol_new stf_ctl =
600 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
601
602static const u16 stf_coeff_table_16k[] = {
603 0x049C, 0x09E8, 0x09E0, 0x089C,
604 0xFF54, 0xF488, 0xEAFC, 0xEBAC,
605 0xfA40, 0x17AC, 0x3D1C, 0x6028,
606 0x7538
607};
608
609static const u16 stf_coeff_table_32k[] = {
610 0xFE52, 0x0042, 0x00C5, 0x0194,
611 0x029A, 0x03B7, 0x04BF, 0x057D,
612 0x05BE, 0x0555, 0x0426, 0x0230,
613 0xFF92, 0xFC89, 0xF973, 0xF6C6,
614 0xF500, 0xF49D, 0xF603, 0xF970,
615 0xFEF3, 0x065F, 0x0F4F, 0x1928,
616 0x2329, 0x2C80, 0x345E, 0x3A0D,
617 0x3D08
618};
619
620static const u16 stf_coeff_table_48k[] = {
621 0x0401, 0xFFB0, 0xFF5A, 0xFECE,
622 0xFE10, 0xFD28, 0xFC21, 0xFB08,
623 0xF9EF, 0xF8E8, 0xF80A, 0xF76C,
624 0xF724, 0xF746, 0xF7E6, 0xF90F,
625 0xFACC, 0xFD1E, 0xFFFF, 0x0364,
626 0x0737, 0x0B62, 0x0FC1, 0x1431,
627 0x188A, 0x1CA4, 0x2056, 0x237D,
628 0x25F9, 0x27B0, 0x2890
629};
630
631static int mtk_stf_event(struct snd_soc_dapm_widget *w,
632 struct snd_kcontrol *kcontrol,
633 int event)
634{
635 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(dapm: w->dapm);
636 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(c: cmpnt);
637
638 size_t half_tap_num;
639 const u16 *stf_coeff_table;
640 unsigned int ul_rate, reg_value;
641 size_t coef_addr;
642
643 regmap_read(map: afe->regmap, AFE_ADDA_UL_SRC_CON0, val: &ul_rate);
644 ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT;
645 ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK;
646
647 if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) {
648 half_tap_num = ARRAY_SIZE(stf_coeff_table_48k);
649 stf_coeff_table = stf_coeff_table_48k;
650 } else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) {
651 half_tap_num = ARRAY_SIZE(stf_coeff_table_32k);
652 stf_coeff_table = stf_coeff_table_32k;
653 } else {
654 half_tap_num = ARRAY_SIZE(stf_coeff_table_16k);
655 stf_coeff_table = stf_coeff_table_16k;
656 }
657
658 regmap_read(map: afe->regmap, AFE_SIDETONE_CON1, val: &reg_value);
659
660 switch (event) {
661 case SND_SOC_DAPM_PRE_PMU:
662 /* set side tone gain = 0 */
663 regmap_update_bits(map: afe->regmap,
664 AFE_SIDETONE_GAIN,
665 SIDE_TONE_GAIN_MASK_SFT,
666 val: 0);
667 regmap_update_bits(map: afe->regmap,
668 AFE_SIDETONE_GAIN,
669 POSITIVE_GAIN_MASK_SFT,
670 val: 0);
671 /* don't bypass stf */
672 regmap_update_bits(map: afe->regmap,
673 AFE_SIDETONE_CON1,
674 mask: 0x1f << 27,
675 val: 0x0);
676 /* set stf half tap num */
677 regmap_update_bits(map: afe->regmap,
678 AFE_SIDETONE_CON1,
679 SIDE_TONE_HALF_TAP_NUM_MASK_SFT,
680 val: half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT);
681
682 /* set side tone coefficient */
683 regmap_read(map: afe->regmap, AFE_SIDETONE_CON0, val: &reg_value);
684 for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) {
685 bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
686 bool new_w_ready = 0;
687 int try_cnt = 0;
688
689 regmap_update_bits(map: afe->regmap,
690 AFE_SIDETONE_CON0,
691 mask: 0x39FFFFF,
692 val: (1 << R_W_EN_SFT) |
693 (1 << R_W_SEL_SFT) |
694 (0 << SEL_CH2_SFT) |
695 (coef_addr <<
696 SIDE_TONE_COEFFICIENT_ADDR_SFT) |
697 stf_coeff_table[coef_addr]);
698
699 /* wait until flag write_ready changed */
700 for (try_cnt = 0; try_cnt < 10; try_cnt++) {
701 regmap_read(map: afe->regmap,
702 AFE_SIDETONE_CON0, val: &reg_value);
703 new_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
704
705 /* flip => ok */
706 if (new_w_ready == old_w_ready) {
707 udelay(usec: 3);
708 if (try_cnt == 9) {
709 dev_warn(afe->dev,
710 "%s(), write coeff not ready",
711 __func__);
712 }
713 } else {
714 break;
715 }
716 }
717 /* need write -> read -> write to write next coeff */
718 regmap_update_bits(map: afe->regmap,
719 AFE_SIDETONE_CON0,
720 R_W_SEL_MASK_SFT,
721 val: 0x0);
722 }
723 break;
724 case SND_SOC_DAPM_POST_PMD:
725 /* bypass stf */
726 regmap_update_bits(map: afe->regmap,
727 AFE_SIDETONE_CON1,
728 mask: 0x1f << 27,
729 val: 0x1f << 27);
730
731 /* set side tone gain = 0 */
732 regmap_update_bits(map: afe->regmap,
733 AFE_SIDETONE_GAIN,
734 SIDE_TONE_GAIN_MASK_SFT,
735 val: 0);
736 regmap_update_bits(map: afe->regmap,
737 AFE_SIDETONE_GAIN,
738 POSITIVE_GAIN_MASK_SFT,
739 val: 0);
740 break;
741 default:
742 break;
743 }
744
745 return 0;
746}
747
748/* stf mux */
749enum {
750 STF_SRC_ADDA_ADDA6 = 0,
751 STF_SRC_O19O20,
752};
753
754static const char *const stf_o19o20_mux_map[] = {
755 "ADDA_ADDA6",
756 "O19O20",
757};
758
759static int stf_o19o20_mux_map_value[] = {
760 STF_SRC_ADDA_ADDA6,
761 STF_SRC_O19O20,
762};
763
764static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum,
765 AFE_SIDETONE_CON1,
766 STF_SOURCE_FROM_O19O20_SFT,
767 STF_SOURCE_FROM_O19O20_MASK,
768 stf_o19o20_mux_map,
769 stf_o19o20_mux_map_value);
770
771static const struct snd_kcontrol_new stf_o19O20_mux_control =
772 SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum);
773
774enum {
775 STF_SRC_ADDA = 0,
776 STF_SRC_ADDA6,
777};
778
779static const char *const stf_adda_mux_map[] = {
780 "ADDA",
781 "ADDA6",
782};
783
784static int stf_adda_mux_map_value[] = {
785 STF_SRC_ADDA,
786 STF_SRC_ADDA6,
787};
788
789static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum,
790 AFE_SIDETONE_CON1,
791 STF_O19O20_OUT_EN_SEL_SFT,
792 STF_O19O20_OUT_EN_SEL_MASK,
793 stf_adda_mux_map,
794 stf_adda_mux_map_value);
795
796static const struct snd_kcontrol_new stf_adda_mux_control =
797 SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum);
798
799/* ADDA UL MUX */
800enum {
801 ADDA_UL_MUX_MTKAIF = 0,
802 ADDA_UL_MUX_AP_DMIC,
803 ADDA_UL_MUX_MASK = 0x1,
804};
805
806static const char * const adda_ul_mux_map[] = {
807 "MTKAIF", "AP_DMIC"
808};
809
810static int adda_ul_map_value[] = {
811 ADDA_UL_MUX_MTKAIF,
812 ADDA_UL_MUX_AP_DMIC,
813};
814
815static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
816 SND_SOC_NOPM,
817 0,
818 ADDA_UL_MUX_MASK,
819 adda_ul_mux_map,
820 adda_ul_map_value);
821
822static const struct snd_kcontrol_new adda_ul_mux_control =
823 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
824
825static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
826 SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
827
828static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
829 /* inter-connections */
830 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
831 mtk_adda_dl_ch1_mix,
832 ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
833 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
834 mtk_adda_dl_ch2_mix,
835 ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
836
837 SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
838 mtk_adda_dl_ch3_mix,
839 ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
840 SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
841 mtk_adda_dl_ch4_mix,
842 ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
843
844 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
845 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
846 NULL, 0),
847
848 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
849 AFE_ADDA_DL_SRC2_CON0,
850 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
851 mtk_adda_dl_event,
852 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
853 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable",
854 SUPPLY_SEQ_ADDA_DL_ON,
855 AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
856 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
857 mtk_adda_ch34_dl_event,
858 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
859
860 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
861 AFE_ADDA_UL_SRC_CON0,
862 UL_SRC_ON_TMP_CTL_SFT, 0,
863 mtk_adda_ul_event,
864 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
865 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
866 AFE_ADDA6_UL_SRC_CON0,
867 UL_SRC_ON_TMP_CTL_SFT, 0,
868 mtk_adda_ch34_ul_event,
869 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
870
871 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
872 AFE_AUD_PAD_TOP,
873 RG_RX_FIFO_ON_SFT, 0,
874 mtk_adda_pad_top_event,
875 SND_SOC_DAPM_PRE_PMU),
876 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
877 SND_SOC_NOPM, 0, 0,
878 mtk_adda_mtkaif_cfg_event,
879 SND_SOC_DAPM_PRE_PMU),
880 SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
881 SND_SOC_NOPM, 0, 0,
882 mtk_adda_mtkaif_cfg_event,
883 SND_SOC_DAPM_PRE_PMU),
884
885 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
886 AFE_ADDA_UL_SRC_CON0,
887 UL_AP_DMIC_ON_SFT, 0,
888 NULL, 0),
889 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
890 AFE_ADDA6_UL_SRC_CON0,
891 UL_AP_DMIC_ON_SFT, 0,
892 NULL, 0),
893
894 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
895 AFE_ADDA_UL_DL_CON0,
896 AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
897 NULL, 0),
898 SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
899 AFE_ADDA_UL_DL_CON0,
900 AFE_ADDA6_FIFO_AUTO_RST_SFT, 1,
901 NULL, 0),
902
903 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
904 &adda_ul_mux_control),
905 SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
906 &adda_ch34_ul_mux_control),
907
908 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
909 SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"),
910
911 /* stf */
912 SND_SOC_DAPM_SWITCH_E("Sidetone Filter",
913 AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0,
914 &stf_ctl,
915 mtk_stf_event,
916 SND_SOC_DAPM_PRE_PMU |
917 SND_SOC_DAPM_POST_PMD),
918 SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0,
919 &stf_o19O20_mux_control),
920 SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0,
921 &stf_adda_mux_control),
922 SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0,
923 mtk_stf_ch1_mix,
924 ARRAY_SIZE(mtk_stf_ch1_mix)),
925 SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0,
926 mtk_stf_ch2_mix,
927 ARRAY_SIZE(mtk_stf_ch2_mix)),
928 SND_SOC_DAPM_OUTPUT("STF_OUTPUT"),
929
930 /* clock */
931 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
932
933 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
934 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
935 SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"),
936 SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"),
937
938 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
939 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"),
940};
941
942static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
943 /* playback */
944 {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
945 {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
946 {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
947
948 {"ADDA_DL_CH1", "DL12_CH1", "DL12"},
949 {"ADDA_DL_CH2", "DL12_CH2", "DL12"},
950
951 {"ADDA_DL_CH1", "DL6_CH1", "DL6"},
952 {"ADDA_DL_CH2", "DL6_CH2", "DL6"},
953
954 {"ADDA_DL_CH1", "DL8_CH1", "DL8"},
955 {"ADDA_DL_CH2", "DL8_CH2", "DL8"},
956
957 {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
958 {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
959 {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
960
961 {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
962 {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
963 {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
964
965 {"ADDA_DL_CH1", "DL4_CH1", "DL4"},
966 {"ADDA_DL_CH2", "DL4_CH2", "DL4"},
967
968 {"ADDA_DL_CH1", "DL5_CH1", "DL5"},
969 {"ADDA_DL_CH2", "DL5_CH2", "DL5"},
970
971 {"ADDA Playback", NULL, "ADDA_DL_CH1"},
972 {"ADDA Playback", NULL, "ADDA_DL_CH2"},
973
974 {"ADDA Playback", NULL, "ADDA Enable"},
975 {"ADDA Playback", NULL, "ADDA Playback Enable"},
976
977 {"ADDA_DL_CH3", "DL1_CH1", "DL1"},
978 {"ADDA_DL_CH4", "DL1_CH1", "DL1"},
979 {"ADDA_DL_CH4", "DL1_CH2", "DL1"},
980
981 {"ADDA_DL_CH3", "DL12_CH1", "DL12"},
982 {"ADDA_DL_CH4", "DL12_CH2", "DL12"},
983
984 {"ADDA_DL_CH3", "DL6_CH1", "DL6"},
985 {"ADDA_DL_CH4", "DL6_CH2", "DL6"},
986
987 {"ADDA_DL_CH3", "DL2_CH1", "DL2"},
988 {"ADDA_DL_CH4", "DL2_CH1", "DL2"},
989 {"ADDA_DL_CH4", "DL2_CH2", "DL2"},
990
991 {"ADDA_DL_CH3", "DL3_CH1", "DL3"},
992 {"ADDA_DL_CH4", "DL3_CH1", "DL3"},
993 {"ADDA_DL_CH4", "DL3_CH2", "DL3"},
994
995 {"ADDA_DL_CH3", "DL4_CH1", "DL4"},
996 {"ADDA_DL_CH4", "DL4_CH2", "DL4"},
997
998 {"ADDA_DL_CH3", "DL5_CH1", "DL5"},
999 {"ADDA_DL_CH4", "DL5_CH2", "DL5"},
1000
1001 {"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"},
1002 {"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"},
1003
1004 {"ADDA CH34 Playback", NULL, "ADDA Enable"},
1005 {"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"},
1006
1007 /* capture */
1008 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
1009 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
1010
1011 {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"},
1012 {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
1013
1014 {"ADDA Capture", NULL, "ADDA Enable"},
1015 {"ADDA Capture", NULL, "ADDA Capture Enable"},
1016 {"ADDA Capture", NULL, "AUD_PAD_TOP"},
1017 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
1018
1019 {"AP DMIC Capture", NULL, "ADDA Enable"},
1020 {"AP DMIC Capture", NULL, "ADDA Capture Enable"},
1021 {"AP DMIC Capture", NULL, "ADDA_FIFO"},
1022 {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
1023
1024 {"ADDA CH34 Capture", NULL, "ADDA Enable"},
1025 {"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1026 {"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"},
1027 {"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"},
1028
1029 {"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
1030 {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1031 {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"},
1032 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
1033
1034 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
1035 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"},
1036
1037 /* sidetone filter */
1038 {"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"},
1039 {"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"},
1040
1041 {"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"},
1042 {"STF_O19O20_MUX", "O19O20", "STF_CH1"},
1043 {"STF_O19O20_MUX", "O19O20", "STF_CH2"},
1044
1045 {"Sidetone Filter", "Switch", "STF_O19O20_MUX"},
1046 {"STF_OUTPUT", NULL, "Sidetone Filter"},
1047 {"ADDA Playback", NULL, "Sidetone Filter"},
1048 {"ADDA CH34 Playback", NULL, "Sidetone Filter"},
1049
1050 /* clk */
1051 {"ADDA Playback", NULL, "aud_dac_clk"},
1052 {"ADDA Playback", NULL, "aud_dac_predis_clk"},
1053
1054 {"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"},
1055 {"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"},
1056
1057 {"ADDA Capture Enable", NULL, "aud_adc_clk"},
1058 {"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"},
1059};
1060
1061/* dai ops */
1062static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
1063 struct snd_pcm_hw_params *params,
1064 struct snd_soc_dai *dai)
1065{
1066 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1067 unsigned int rate = params_rate(p: params);
1068 int id = dai->id;
1069
1070 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1071 unsigned int dl_src2_con0 = 0;
1072 unsigned int dl_src2_con1 = 0;
1073
1074 /* set sampling rate */
1075 dl_src2_con0 = mtk_adda_dl_rate_transform(afe, rate) <<
1076 DL_2_INPUT_MODE_CTL_SFT;
1077
1078 /* set output mode, UP_SAMPLING_RATE_X8 */
1079 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
1080
1081 /* turn off mute function */
1082 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
1083 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
1084
1085 /* set voice input data if input sample rate is 8k or 16k */
1086 if (rate == 8000 || rate == 16000)
1087 dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT;
1088
1089 /* SA suggest apply -0.3db to audio/speech path */
1090 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
1091 DL_2_GAIN_CTL_PRE_SFT;
1092
1093 /* turn on down-link gain */
1094 dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT);
1095
1096 if (id == MT8192_DAI_ADDA) {
1097 /* clean predistortion */
1098 regmap_write(map: afe->regmap, AFE_ADDA_PREDIS_CON0, val: 0);
1099 regmap_write(map: afe->regmap, AFE_ADDA_PREDIS_CON1, val: 0);
1100
1101 regmap_write(map: afe->regmap,
1102 AFE_ADDA_DL_SRC2_CON0, val: dl_src2_con0);
1103 regmap_write(map: afe->regmap,
1104 AFE_ADDA_DL_SRC2_CON1, val: dl_src2_con1);
1105
1106 /* set sdm gain */
1107 regmap_update_bits(map: afe->regmap,
1108 AFE_ADDA_DL_SDM_DCCOMP_CON,
1109 ATTGAIN_CTL_MASK_SFT,
1110 val: AUDIO_SDM_LEVEL_NORMAL <<
1111 ATTGAIN_CTL_SFT);
1112
1113 /* 2nd sdm */
1114 regmap_update_bits(map: afe->regmap,
1115 AFE_ADDA_DL_SDM_DCCOMP_CON,
1116 USE_3RD_SDM_MASK_SFT,
1117 val: AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1118
1119 /* sdm auto reset */
1120 regmap_write(map: afe->regmap,
1121 AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1122 SDM_AUTO_RESET_THRESHOLD);
1123 regmap_update_bits(map: afe->regmap,
1124 AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1125 ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1126 val: 0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT);
1127 } else {
1128 /* clean predistortion */
1129 regmap_write(map: afe->regmap,
1130 AFE_ADDA_3RD_DAC_PREDIS_CON0, val: 0);
1131 regmap_write(map: afe->regmap,
1132 AFE_ADDA_3RD_DAC_PREDIS_CON1, val: 0);
1133
1134 regmap_write(map: afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
1135 val: dl_src2_con0);
1136 regmap_write(map: afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1,
1137 val: dl_src2_con1);
1138
1139 /* set sdm gain */
1140 regmap_update_bits(map: afe->regmap,
1141 AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1142 ATTGAIN_CTL_MASK_SFT,
1143 val: AUDIO_SDM_LEVEL_NORMAL <<
1144 ATTGAIN_CTL_SFT);
1145
1146 /* 2nd sdm */
1147 regmap_update_bits(map: afe->regmap,
1148 AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1149 USE_3RD_SDM_MASK_SFT,
1150 val: AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1151
1152 /* sdm auto reset */
1153 regmap_write(map: afe->regmap,
1154 AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1155 SDM_AUTO_RESET_THRESHOLD);
1156 regmap_update_bits(map: afe->regmap,
1157 AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1158 ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1159 val: 0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT);
1160 }
1161 } else {
1162 unsigned int voice_mode = 0;
1163 unsigned int ul_src_con0 = 0; /* default value */
1164
1165 voice_mode = mtk_adda_ul_rate_transform(afe, rate);
1166
1167 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
1168
1169 /* enable iir */
1170 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
1171 UL_IIR_ON_TMP_CTL_MASK_SFT;
1172 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
1173 UL_IIRMODE_CTL_MASK_SFT;
1174
1175 switch (id) {
1176 case MT8192_DAI_ADDA:
1177 case MT8192_DAI_AP_DMIC:
1178 /* 35Hz @ 48k */
1179 regmap_write(map: afe->regmap,
1180 AFE_ADDA_IIR_COEF_02_01, val: 0x00000000);
1181 regmap_write(map: afe->regmap,
1182 AFE_ADDA_IIR_COEF_04_03, val: 0x00003FB8);
1183 regmap_write(map: afe->regmap,
1184 AFE_ADDA_IIR_COEF_06_05, val: 0x3FB80000);
1185 regmap_write(map: afe->regmap,
1186 AFE_ADDA_IIR_COEF_08_07, val: 0x3FB80000);
1187 regmap_write(map: afe->regmap,
1188 AFE_ADDA_IIR_COEF_10_09, val: 0x0000C048);
1189
1190 regmap_write(map: afe->regmap,
1191 AFE_ADDA_UL_SRC_CON0, val: ul_src_con0);
1192
1193 /* Using Internal ADC */
1194 regmap_update_bits(map: afe->regmap,
1195 AFE_ADDA_TOP_CON0,
1196 mask: 0x1 << 0,
1197 val: 0x0 << 0);
1198
1199 /* mtkaif_rxif_data_mode = 0, amic */
1200 regmap_update_bits(map: afe->regmap,
1201 AFE_ADDA_MTKAIF_RX_CFG0,
1202 mask: 0x1 << 0,
1203 val: 0x0 << 0);
1204 break;
1205 case MT8192_DAI_ADDA_CH34:
1206 case MT8192_DAI_AP_DMIC_CH34:
1207 /* 35Hz @ 48k */
1208 regmap_write(map: afe->regmap,
1209 AFE_ADDA6_IIR_COEF_02_01, val: 0x00000000);
1210 regmap_write(map: afe->regmap,
1211 AFE_ADDA6_IIR_COEF_04_03, val: 0x00003FB8);
1212 regmap_write(map: afe->regmap,
1213 AFE_ADDA6_IIR_COEF_06_05, val: 0x3FB80000);
1214 regmap_write(map: afe->regmap,
1215 AFE_ADDA6_IIR_COEF_08_07, val: 0x3FB80000);
1216 regmap_write(map: afe->regmap,
1217 AFE_ADDA6_IIR_COEF_10_09, val: 0x0000C048);
1218
1219 regmap_write(map: afe->regmap,
1220 AFE_ADDA6_UL_SRC_CON0, val: ul_src_con0);
1221
1222 /* Using Internal ADC */
1223 regmap_update_bits(map: afe->regmap,
1224 AFE_ADDA6_TOP_CON0,
1225 mask: 0x1 << 0,
1226 val: 0x0 << 0);
1227
1228 /* mtkaif_rxif_data_mode = 0, amic */
1229 regmap_update_bits(map: afe->regmap,
1230 AFE_ADDA6_MTKAIF_RX_CFG0,
1231 mask: 0x1 << 0,
1232 val: 0x0 << 0);
1233 break;
1234 default:
1235 break;
1236 }
1237
1238 /* ap dmic */
1239 switch (id) {
1240 case MT8192_DAI_AP_DMIC:
1241 case MT8192_DAI_AP_DMIC_CH34:
1242 mtk_adda_ul_src_dmic(afe, id);
1243 break;
1244 default:
1245 break;
1246 }
1247 }
1248
1249 return 0;
1250}
1251
1252static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
1253 .hw_params = mtk_dai_adda_hw_params,
1254};
1255
1256/* dai driver */
1257#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
1258 SNDRV_PCM_RATE_96000 |\
1259 SNDRV_PCM_RATE_192000)
1260
1261#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1262 SNDRV_PCM_RATE_16000 |\
1263 SNDRV_PCM_RATE_32000 |\
1264 SNDRV_PCM_RATE_48000 |\
1265 SNDRV_PCM_RATE_96000 |\
1266 SNDRV_PCM_RATE_192000)
1267
1268#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1269 SNDRV_PCM_FMTBIT_S24_LE |\
1270 SNDRV_PCM_FMTBIT_S32_LE)
1271
1272static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
1273 {
1274 .name = "ADDA",
1275 .id = MT8192_DAI_ADDA,
1276 .playback = {
1277 .stream_name = "ADDA Playback",
1278 .channels_min = 1,
1279 .channels_max = 2,
1280 .rates = MTK_ADDA_PLAYBACK_RATES,
1281 .formats = MTK_ADDA_FORMATS,
1282 },
1283 .capture = {
1284 .stream_name = "ADDA Capture",
1285 .channels_min = 1,
1286 .channels_max = 2,
1287 .rates = MTK_ADDA_CAPTURE_RATES,
1288 .formats = MTK_ADDA_FORMATS,
1289 },
1290 .ops = &mtk_dai_adda_ops,
1291 },
1292 {
1293 .name = "ADDA_CH34",
1294 .id = MT8192_DAI_ADDA_CH34,
1295 .playback = {
1296 .stream_name = "ADDA CH34 Playback",
1297 .channels_min = 1,
1298 .channels_max = 2,
1299 .rates = MTK_ADDA_PLAYBACK_RATES,
1300 .formats = MTK_ADDA_FORMATS,
1301 },
1302 .capture = {
1303 .stream_name = "ADDA CH34 Capture",
1304 .channels_min = 1,
1305 .channels_max = 2,
1306 .rates = MTK_ADDA_CAPTURE_RATES,
1307 .formats = MTK_ADDA_FORMATS,
1308 },
1309 .ops = &mtk_dai_adda_ops,
1310 },
1311 {
1312 .name = "AP_DMIC",
1313 .id = MT8192_DAI_AP_DMIC,
1314 .capture = {
1315 .stream_name = "AP DMIC Capture",
1316 .channels_min = 1,
1317 .channels_max = 2,
1318 .rates = MTK_ADDA_CAPTURE_RATES,
1319 .formats = MTK_ADDA_FORMATS,
1320 },
1321 .ops = &mtk_dai_adda_ops,
1322 },
1323 {
1324 .name = "AP_DMIC_CH34",
1325 .id = MT8192_DAI_AP_DMIC_CH34,
1326 .capture = {
1327 .stream_name = "AP DMIC CH34 Capture",
1328 .channels_min = 1,
1329 .channels_max = 2,
1330 .rates = MTK_ADDA_CAPTURE_RATES,
1331 .formats = MTK_ADDA_FORMATS,
1332 },
1333 .ops = &mtk_dai_adda_ops,
1334 },
1335};
1336
1337int mt8192_dai_adda_register(struct mtk_base_afe *afe)
1338{
1339 struct mtk_base_afe_dai *dai;
1340 struct mt8192_afe_private *afe_priv = afe->platform_priv;
1341
1342 dai = devm_kzalloc(dev: afe->dev, size: sizeof(*dai), GFP_KERNEL);
1343 if (!dai)
1344 return -ENOMEM;
1345
1346 list_add(new: &dai->list, head: &afe->sub_dais);
1347
1348 dai->dai_drivers = mtk_dai_adda_driver;
1349 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
1350
1351 dai->controls = mtk_adda_controls;
1352 dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
1353 dai->dapm_widgets = mtk_dai_adda_widgets;
1354 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
1355 dai->dapm_routes = mtk_dai_adda_routes;
1356 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
1357
1358 /* ap dmic priv share with adda */
1359 afe_priv->dai_priv[MT8192_DAI_AP_DMIC] =
1360 afe_priv->dai_priv[MT8192_DAI_ADDA];
1361 afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] =
1362 afe_priv->dai_priv[MT8192_DAI_ADDA_CH34];
1363
1364 return 0;
1365}
1366

source code of linux/sound/soc/mediatek/mt8192/mt8192-dai-adda.c