1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * Copyright (c) 2021 MediaTek Corporation. All rights reserved.
5 *
6 * Header file for the mt8195 DSP register definition
7 */
8
9#ifndef __MT8195_H
10#define __MT8195_H
11
12struct mtk_adsp_chip_info;
13struct snd_sof_dev;
14
15#define DSP_REG_BASE 0x10803000
16#define SCP_CFGREG_BASE 0x10724000
17#define DSP_SYSAO_BASE 0x1080C000
18
19/*****************************************************************************
20 * R E G I S T E R TABLE
21 *****************************************************************************/
22#define DSP_JTAGMUX 0x0000
23#define DSP_ALTRESETVEC 0x0004
24#define DSP_PDEBUGDATA 0x0008
25#define DSP_PDEBUGBUS0 0x000c
26#define PDEBUG_ENABLE BIT(0)
27#define DSP_PDEBUGBUS1 0x0010
28#define DSP_PDEBUGINST 0x0014
29#define DSP_PDEBUGLS0STAT 0x0018
30#define DSP_PDEBUGLS1STAT 0x001c
31#define DSP_PDEBUGPC 0x0020
32#define DSP_RESET_SW 0x0024 /*reset sw*/
33#define ADSP_BRESET_SW BIT(0)
34#define ADSP_DRESET_SW BIT(1)
35#define ADSP_RUNSTALL BIT(3)
36#define STATVECTOR_SEL BIT(4)
37#define ADSP_PWAIT BIT(16)
38#define DSP_PFAULTBUS 0x0028
39#define DSP_PFAULTINFO 0x002c
40#define DSP_GPR00 0x0030
41#define DSP_GPR01 0x0034
42#define DSP_GPR02 0x0038
43#define DSP_GPR03 0x003c
44#define DSP_GPR04 0x0040
45#define DSP_GPR05 0x0044
46#define DSP_GPR06 0x0048
47#define DSP_GPR07 0x004c
48#define DSP_GPR08 0x0050
49#define DSP_GPR09 0x0054
50#define DSP_GPR0A 0x0058
51#define DSP_GPR0B 0x005c
52#define DSP_GPR0C 0x0060
53#define DSP_GPR0D 0x0064
54#define DSP_GPR0E 0x0068
55#define DSP_GPR0F 0x006c
56#define DSP_GPR10 0x0070
57#define DSP_GPR11 0x0074
58#define DSP_GPR12 0x0078
59#define DSP_GPR13 0x007c
60#define DSP_GPR14 0x0080
61#define DSP_GPR15 0x0084
62#define DSP_GPR16 0x0088
63#define DSP_GPR17 0x008c
64#define DSP_GPR18 0x0090
65#define DSP_GPR19 0x0094
66#define DSP_GPR1A 0x0098
67#define DSP_GPR1B 0x009c
68#define DSP_GPR1C 0x00a0
69#define DSP_GPR1D 0x00a4
70#define DSP_GPR1E 0x00a8
71#define DSP_GPR1F 0x00ac
72#define DSP_TCM_OFFSET 0x00b0 /* not used */
73#define DSP_DDR_OFFSET 0x00b4 /* not used */
74#define DSP_INTFDSP 0x00d0
75#define DSP_INTFDSP_CLR 0x00d4
76#define DSP_SRAM_PD_SW1 0x00d8
77#define DSP_SRAM_PD_SW2 0x00dc
78#define DSP_OCD 0x00e0
79#define DSP_RG_DSP_IRQ_POL 0x00f0 /* not used */
80#define DSP_DSP_IRQ_EN 0x00f4 /* not used */
81#define DSP_DSP_IRQ_LEVEL 0x00f8 /* not used */
82#define DSP_DSP_IRQ_STATUS 0x00fc /* not used */
83#define DSP_RG_INT2CIRQ 0x0114
84#define DSP_RG_INT_POL_CTL0 0x0120
85#define DSP_RG_INT_EN_CTL0 0x0130
86#define DSP_RG_INT_LV_CTL0 0x0140
87#define DSP_RG_INT_STATUS0 0x0150
88#define DSP_PDEBUGSTATUS0 0x0200
89#define DSP_PDEBUGSTATUS1 0x0204
90#define DSP_PDEBUGSTATUS2 0x0208
91#define DSP_PDEBUGSTATUS3 0x020c
92#define DSP_PDEBUGSTATUS4 0x0210
93#define DSP_PDEBUGSTATUS5 0x0214
94#define DSP_PDEBUGSTATUS6 0x0218
95#define DSP_PDEBUGSTATUS7 0x021c
96#define DSP_DSP2PSRAM_PRIORITY 0x0220 /* not used */
97#define DSP_AUDIO_DSP2SPM_INT 0x0224
98#define DSP_AUDIO_DSP2SPM_INT_ACK 0x0228
99#define DSP_AUDIO_DSP_DEBUG_SEL 0x022C
100#define DSP_AUDIO_DSP_EMI_BASE_ADDR 0x02E0 /* not used */
101#define DSP_AUDIO_DSP_SHARED_IRAM 0x02E4
102#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON 0x02F0
103#define DSP_RG_SEMAPHORE00 0x0300
104#define DSP_RG_SEMAPHORE01 0x0304
105#define DSP_RG_SEMAPHORE02 0x0308
106#define DSP_RG_SEMAPHORE03 0x030C
107#define DSP_RG_SEMAPHORE04 0x0310
108#define DSP_RG_SEMAPHORE05 0x0314
109#define DSP_RG_SEMAPHORE06 0x0318
110#define DSP_RG_SEMAPHORE07 0x031C
111#define DSP_RESERVED_0 0x03F0
112#define DSP_RESERVED_1 0x03F4
113
114/* dsp wdt */
115#define DSP_WDT_MODE 0x0400
116
117/* dsp mbox */
118#define DSP_MBOX_IN_CMD 0x00
119#define DSP_MBOX_IN_CMD_CLR 0x04
120#define DSP_MBOX_OUT_CMD 0x1c
121#define DSP_MBOX_OUT_CMD_CLR 0x20
122#define DSP_MBOX_IN_MSG0 0x08
123#define DSP_MBOX_IN_MSG1 0x0C
124#define DSP_MBOX_OUT_MSG0 0x24
125#define DSP_MBOX_OUT_MSG1 0x28
126
127/*dsp sys ao*/
128#define ADSP_SRAM_POOL_CON (DSP_SYSAO_BASE + 0x30)
129#define DSP_SRAM_POOL_PD_MASK 0xf
130#define DSP_EMI_MAP_ADDR (DSP_SYSAO_BASE + 0x81c)
131
132/* DSP memories */
133#define MBOX_OFFSET 0x800000 /* DRAM */
134#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */
135#define DSP_DRAM_SIZE 0x1000000 /* 16M */
136
137#define DSP_REG_BAR 4
138#define DSP_MBOX0_BAR 5
139#define DSP_MBOX1_BAR 6
140#define DSP_MBOX2_BAR 7
141
142#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/
143#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/
144
145#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL \
146 (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)
147
148#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x40000000 /* MT8195 DSP view */
149#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8195 DSP view */
150
151/*remap dram between AP and DSP view, 4KB aligned*/
152#define DRAM_REMAP_SHIFT 12
153#define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1)
154
155/* suspend dsp idle check interval and timeout */
156#define SUSPEND_DSP_IDLE_TIMEOUT_US 1000000 /* timeout to wait dsp idle, 1 sec */
157#define SUSPEND_DSP_IDLE_POLL_INTERVAL_US 500 /* 0.5 msec */
158
159void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
160void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
161#endif
162

source code of linux/sound/soc/sof/mediatek/mt8195/mt8195.h