| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * arm_spe_decoder.h: Arm Statistical Profiling Extensions support |
| 4 | * Copyright (c) 2019-2020, Arm Ltd. |
| 5 | */ |
| 6 | |
| 7 | #ifndef INCLUDE__ARM_SPE_DECODER_H__ |
| 8 | #define INCLUDE__ARM_SPE_DECODER_H__ |
| 9 | |
| 10 | #include <stdbool.h> |
| 11 | #include <stddef.h> |
| 12 | #include <stdint.h> |
| 13 | |
| 14 | #include "arm-spe-pkt-decoder.h" |
| 15 | |
| 16 | #define ARM_SPE_L1D_ACCESS BIT(EV_L1D_ACCESS) |
| 17 | #define ARM_SPE_L1D_MISS BIT(EV_L1D_REFILL) |
| 18 | #define ARM_SPE_LLC_ACCESS BIT(EV_LLC_ACCESS) |
| 19 | #define ARM_SPE_LLC_MISS BIT(EV_LLC_MISS) |
| 20 | #define ARM_SPE_TLB_ACCESS BIT(EV_TLB_ACCESS) |
| 21 | #define ARM_SPE_TLB_MISS BIT(EV_TLB_WALK) |
| 22 | #define ARM_SPE_BRANCH_MISS BIT(EV_MISPRED) |
| 23 | #define ARM_SPE_BRANCH_NOT_TAKEN BIT(EV_NOT_TAKEN) |
| 24 | #define ARM_SPE_REMOTE_ACCESS BIT(EV_REMOTE_ACCESS) |
| 25 | #define ARM_SPE_SVE_PARTIAL_PRED BIT(EV_PARTIAL_PREDICATE) |
| 26 | #define ARM_SPE_SVE_EMPTY_PRED BIT(EV_EMPTY_PREDICATE) |
| 27 | #define ARM_SPE_IN_TXN BIT(EV_TRANSACTIONAL) |
| 28 | #define ARM_SPE_L2D_ACCESS BIT(EV_L2D_ACCESS) |
| 29 | #define ARM_SPE_L2D_MISS BIT(EV_L2D_MISS) |
| 30 | #define ARM_SPE_RECENTLY_FETCHED BIT(EV_RECENTLY_FETCHED) |
| 31 | #define ARM_SPE_DATA_SNOOPED BIT(EV_DATA_SNOOPED) |
| 32 | #define ARM_SPE_HITM BIT(EV_CACHE_DATA_MODIFIED) |
| 33 | |
| 34 | enum arm_spe_op_type { |
| 35 | /* First level operation type */ |
| 36 | ARM_SPE_OP_OTHER = 1 << 0, |
| 37 | ARM_SPE_OP_LDST = 1 << 1, |
| 38 | ARM_SPE_OP_BRANCH_ERET = 1 << 2, |
| 39 | }; |
| 40 | |
| 41 | enum arm_spe_2nd_op_ldst { |
| 42 | ARM_SPE_OP_GP_REG = 1 << 8, |
| 43 | ARM_SPE_OP_UNSPEC_REG = 1 << 9, |
| 44 | ARM_SPE_OP_NV_SYSREG = 1 << 10, |
| 45 | ARM_SPE_OP_SIMD_FP = 1 << 11, |
| 46 | ARM_SPE_OP_SVE = 1 << 12, |
| 47 | ARM_SPE_OP_MTE_TAG = 1 << 13, |
| 48 | ARM_SPE_OP_MEMCPY = 1 << 14, |
| 49 | ARM_SPE_OP_MEMSET = 1 << 15, |
| 50 | ARM_SPE_OP_GCS = 1 << 16, |
| 51 | ARM_SPE_OP_SME = 1 << 17, |
| 52 | ARM_SPE_OP_ASE = 1 << 18, |
| 53 | |
| 54 | /* Assisted information for memory / SIMD */ |
| 55 | ARM_SPE_OP_LD = 1 << 20, |
| 56 | ARM_SPE_OP_ST = 1 << 21, |
| 57 | ARM_SPE_OP_ATOMIC = 1 << 22, |
| 58 | ARM_SPE_OP_EXCL = 1 << 23, |
| 59 | ARM_SPE_OP_AR = 1 << 24, |
| 60 | ARM_SPE_OP_DP = 1 << 25, /* Data processing */ |
| 61 | ARM_SPE_OP_PRED = 1 << 26, /* Predicated */ |
| 62 | ARM_SPE_OP_SG = 1 << 27, /* Gather/Scatter */ |
| 63 | ARM_SPE_OP_COMM = 1 << 28, /* Common */ |
| 64 | ARM_SPE_OP_FP = 1 << 29, /* Floating-point */ |
| 65 | ARM_SPE_OP_COND = 1 << 30, /* Conditional */ |
| 66 | }; |
| 67 | |
| 68 | enum arm_spe_2nd_op_branch { |
| 69 | ARM_SPE_OP_BR_COND = 1 << 8, |
| 70 | ARM_SPE_OP_BR_INDIRECT = 1 << 9, |
| 71 | ARM_SPE_OP_BR_GCS = 1 << 10, |
| 72 | ARM_SPE_OP_BR_CR_BL = 1 << 11, |
| 73 | ARM_SPE_OP_BR_CR_RET = 1 << 12, |
| 74 | ARM_SPE_OP_BR_CR_NON_BL_RET = 1 << 13, |
| 75 | }; |
| 76 | |
| 77 | enum arm_spe_common_data_source { |
| 78 | ARM_SPE_COMMON_DS_L1D = 0x0, |
| 79 | ARM_SPE_COMMON_DS_L2 = 0x8, |
| 80 | ARM_SPE_COMMON_DS_PEER_CORE = 0x9, |
| 81 | ARM_SPE_COMMON_DS_LOCAL_CLUSTER = 0xa, |
| 82 | ARM_SPE_COMMON_DS_SYS_CACHE = 0xb, |
| 83 | ARM_SPE_COMMON_DS_PEER_CLUSTER = 0xc, |
| 84 | ARM_SPE_COMMON_DS_REMOTE = 0xd, |
| 85 | ARM_SPE_COMMON_DS_DRAM = 0xe, |
| 86 | }; |
| 87 | |
| 88 | enum arm_spe_ampereone_data_source { |
| 89 | ARM_SPE_AMPEREONE_LOCAL_CHIP_CACHE_OR_DEVICE = 0x0, |
| 90 | ARM_SPE_AMPEREONE_SLC = 0x3, |
| 91 | ARM_SPE_AMPEREONE_REMOTE_CHIP_CACHE = 0x5, |
| 92 | ARM_SPE_AMPEREONE_DDR = 0x7, |
| 93 | ARM_SPE_AMPEREONE_L1D = 0x8, |
| 94 | ARM_SPE_AMPEREONE_L2D = 0x9, |
| 95 | }; |
| 96 | |
| 97 | enum arm_spe_hisi_hip_data_source { |
| 98 | ARM_SPE_HISI_HIP_PEER_CPU = 0, |
| 99 | ARM_SPE_HISI_HIP_PEER_CPU_HITM = 1, |
| 100 | ARM_SPE_HISI_HIP_L3 = 2, |
| 101 | ARM_SPE_HISI_HIP_L3_HITM = 3, |
| 102 | ARM_SPE_HISI_HIP_PEER_CLUSTER = 4, |
| 103 | ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM = 5, |
| 104 | ARM_SPE_HISI_HIP_REMOTE_SOCKET = 6, |
| 105 | ARM_SPE_HISI_HIP_REMOTE_SOCKET_HITM = 7, |
| 106 | ARM_SPE_HISI_HIP_LOCAL_MEM = 8, |
| 107 | ARM_SPE_HISI_HIP_REMOTE_MEM = 9, |
| 108 | ARM_SPE_HISI_HIP_NC_DEV = 13, |
| 109 | ARM_SPE_HISI_HIP_L2 = 16, |
| 110 | ARM_SPE_HISI_HIP_L2_HITM = 17, |
| 111 | ARM_SPE_HISI_HIP_L1 = 18, |
| 112 | }; |
| 113 | |
| 114 | struct arm_spe_record { |
| 115 | u64 type; |
| 116 | int err; |
| 117 | u32 op; |
| 118 | u32 latency; |
| 119 | u64 from_ip; |
| 120 | u64 to_ip; |
| 121 | u64 prev_br_tgt; |
| 122 | u64 timestamp; |
| 123 | u64 virt_addr; |
| 124 | u64 phys_addr; |
| 125 | u64 context_id; |
| 126 | u16 source; |
| 127 | }; |
| 128 | |
| 129 | struct arm_spe_insn; |
| 130 | |
| 131 | struct arm_spe_buffer { |
| 132 | const unsigned char *buf; |
| 133 | size_t len; |
| 134 | u64 offset; |
| 135 | u64 trace_nr; |
| 136 | }; |
| 137 | |
| 138 | struct arm_spe_params { |
| 139 | int (*get_trace)(struct arm_spe_buffer *buffer, void *data); |
| 140 | void *data; |
| 141 | }; |
| 142 | |
| 143 | struct arm_spe_decoder { |
| 144 | int (*get_trace)(struct arm_spe_buffer *buffer, void *data); |
| 145 | void *data; |
| 146 | struct arm_spe_record record; |
| 147 | |
| 148 | const unsigned char *buf; |
| 149 | size_t len; |
| 150 | |
| 151 | struct arm_spe_pkt packet; |
| 152 | }; |
| 153 | |
| 154 | struct arm_spe_decoder *arm_spe_decoder_new(struct arm_spe_params *params); |
| 155 | void arm_spe_decoder_free(struct arm_spe_decoder *decoder); |
| 156 | |
| 157 | int arm_spe_decode(struct arm_spe_decoder *decoder); |
| 158 | |
| 159 | #endif |
| 160 | |