1	//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//
7	//===----------------------------------------------------------------------===//
8	//
9	// This file contains the declaration of the MachineInstr class, which is the
10	// basic representation for all target dependent machine instructions used by
11	// the back end.
12	//
13	//===----------------------------------------------------------------------===//
14
15	#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16	#define LLVM_CODEGEN_MACHINEINSTR_H
17
18	#include "llvm/ADT/ArrayRef.h"
19	#include "llvm/ADT/DenseMapInfo.h"
20	#include "llvm/ADT/PointerSumType.h"
21	#include "llvm/ADT/ilist.h"
22	#include "llvm/ADT/ilist_node.h"
23	#include "llvm/ADT/iterator_range.h"
24	#include "llvm/Analysis/MemoryLocation.h"
25	#include "llvm/CodeGen/MachineMemOperand.h"
26	#include "llvm/CodeGen/MachineOperand.h"
27	#include "llvm/CodeGen/TargetOpcodes.h"
28	#include "llvm/IR/DebugLoc.h"
29	#include "llvm/IR/InlineAsm.h"
30	#include "llvm/MC/MCInstrDesc.h"
31	#include "llvm/MC/MCSymbol.h"
32	#include "llvm/Support/ArrayRecycler.h"
33	#include "llvm/Support/Compiler.h"
34	#include "llvm/Support/MathExtras.h"
35	#include "llvm/Support/TrailingObjects.h"
36	#include <algorithm>
37	#include <cassert>
38	#include <cstdint>
39	#include <utility>
40
41	namespace llvm {
42
43	class DILabel;
44	class Instruction;
45	class MDNode;
46	class AAResults;
47	class BatchAAResults;
48	class DIExpression;
49	class DILocalVariable;
50	class LiveRegUnits;
51	class MachineBasicBlock;
52	class MachineFunction;
53	class MachineRegisterInfo;
54	class ModuleSlotTracker;
55	class raw_ostream;
56	template <typename T> class SmallVectorImpl;
57	class SmallBitVector;
58	class StringRef;
59	class TargetInstrInfo;
60	class TargetRegisterClass;
61	class TargetRegisterInfo;
62
63	//===----------------------------------------------------------------------===//
64	/// Representation of each machine instruction.
65	///
66	/// This class isn't a POD type, but it must have a trivial destructor. When a
67	/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
68	/// without having their destructor called.
69	///
70	class MachineInstr
71	: public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
72	ilist_sentinel_tracking<true>> {
73	public:
74	using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
75
76	/// Flags to specify different kinds of comments to output in
77	/// assembly code. These flags carry semantic information not
78	/// otherwise easily derivable from the IR text.
79	///
80	enum CommentFlag {
81	ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
82	NoSchedComment = 0x2,
83	TAsmComments = 0x4 // Target Asm comments should start from this value.
84	};
85
86	enum MIFlag {
87	NoFlags = 0,
88	FrameSetup = 1 << 0, // Instruction is used as a part of
89	// function frame setup code.
90	FrameDestroy = 1 << 1, // Instruction is used as a part of
91	// function frame destruction code.
92	BundledPred = 1 << 2, // Instruction has bundled predecessors.
93	BundledSucc = 1 << 3, // Instruction has bundled successors.
94	FmNoNans = 1 << 4, // Instruction does not support Fast
95	// math nan values.
96	FmNoInfs = 1 << 5, // Instruction does not support Fast
97	// math infinity values.
98	FmNsz = 1 << 6, // Instruction is not required to retain
99	// signed zero values.
100	FmArcp = 1 << 7, // Instruction supports Fast math
101	// reciprocal approximations.
102	FmContract = 1 << 8, // Instruction supports Fast math
103	// contraction operations like fma.
104	FmAfn = 1 << 9, // Instruction may map to Fast math
105	// intrinsic approximation.
106	FmReassoc = 1 << 10, // Instruction supports Fast math
107	// reassociation of operand order.
108	NoUWrap = 1 << 11, // Instruction supports binary operator
109	// no unsigned wrap.
110	NoSWrap = 1 << 12, // Instruction supports binary operator
111	// no signed wrap.
112	IsExact = 1 << 13, // Instruction supports division is
113	// known to be exact.
114	NoFPExcept = 1 << 14, // Instruction does not raise
115	// floatint-point exceptions.
116	NoMerge = 1 << 15, // Passes that drop source location info
117	// (e.g. branch folding) should skip
118	// this instruction.
119	Unpredictable = 1 << 16, // Instruction with unpredictable condition.
120	NoConvergent = 1 << 17, // Call does not require convergence guarantees.
121	NonNeg = 1 << 18, // The operand is non-negative.
122	Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
123	NoUSWrap = 1 << 20, // Instruction supports geps
124	// no unsigned signed wrap.
125	SameSign = 1 << 21 // Both operands have the same sign.
126	};
127
128	private:
129	const MCInstrDesc *MCID; // Instruction descriptor.
130	MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
131
132	// Operands are allocated by an ArrayRecycler.
133	MachineOperand *Operands = nullptr; // Pointer to the first operand.
134
135	#define LLVM_MI_NUMOPERANDS_BITS 24
136	#define LLVM_MI_FLAGS_BITS 24
137	#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
138
139	/// Number of operands on instruction.
140	uint32_t NumOperands : LLVM_MI_NUMOPERANDS_BITS;
141
142	// OperandCapacity has uint8_t size, so it should be next to NumOperands
143	// to properly pack.
144	using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
145	OperandCapacity CapOperands; // Capacity of the Operands array.
146
147	/// Various bits of additional information about the machine instruction.
148	uint32_t Flags : LLVM_MI_FLAGS_BITS;
149
150	/// Various bits of information used by the AsmPrinter to emit helpful
151	/// comments. This is *not* semantic information. Do not use this for
152	/// anything other than to convey comment information to AsmPrinter.
153	uint32_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
154
155	/// Internal implementation detail class that provides out-of-line storage for
156	/// extra info used by the machine instruction when this info cannot be stored
157	/// in-line within the instruction itself.
158	///
159	/// This has to be defined eagerly due to the implementation constraints of
160	/// `PointerSumType` where it is used.
161	class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
162	MCSymbol *, MDNode *, uint32_t> {
163	public:
164	static ExtraInfo *create(BumpPtrAllocator &Allocator,
165	ArrayRef<MachineMemOperand *> MMOs,
166	MCSymbol *PreInstrSymbol = nullptr,
167	MCSymbol *PostInstrSymbol = nullptr,
168	MDNode *HeapAllocMarker = nullptr,
169	MDNode *PCSections = nullptr, uint32_t CFIType = 0,
170	MDNode *MMRAs = nullptr) {
171	bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
172	bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
173	bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
174	bool HasMMRAs = MMRAs != nullptr;
175	bool HasCFIType = CFIType != 0;
176	bool HasPCSections = PCSections != nullptr;
177	auto *Result = new (Allocator.Allocate(
178	Size: totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
179	Counts: MMOs.size(), Counts: HasPreInstrSymbol + HasPostInstrSymbol,
180	Counts: HasHeapAllocMarker + HasPCSections + HasMMRAs, Counts: HasCFIType),
181	Alignment: alignof(ExtraInfo)))
182	ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
183	HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
184
185	// Copy the actual data into the trailing objects.
186	std::copy(first: MMOs.begin(), last: MMOs.end(),
187	result: Result->getTrailingObjects<MachineMemOperand *>());
188
189	unsigned MDNodeIdx = 0;
190
191	if (HasPreInstrSymbol)
192	Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
193	if (HasPostInstrSymbol)
194	Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
195	PostInstrSymbol;
196	if (HasHeapAllocMarker)
197	Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
198	if (HasPCSections)
199	Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
200	if (HasCFIType)
201	Result->getTrailingObjects<uint32_t>()[0] = CFIType;
202	if (HasMMRAs)
203	Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
204
205	return Result;
206	}
207
208	ArrayRef<MachineMemOperand *> getMMOs() const {
209	return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
210	}
211
212	MCSymbol *getPreInstrSymbol() const {
213	return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
214	}
215
216	MCSymbol *getPostInstrSymbol() const {
217	return HasPostInstrSymbol
218	? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
219	: nullptr;
220	}
221
222	MDNode *getHeapAllocMarker() const {
223	return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
224	}
225
226	MDNode *getPCSections() const {
227	return HasPCSections
228	? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
229	: nullptr;
230	}
231
232	uint32_t getCFIType() const {
233	return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
234	}
235
236	MDNode *getMMRAMetadata() const {
237	return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
238	HasPCSections]
239	: nullptr;
240	}
241
242	private:
243	friend TrailingObjects;
244
245	// Description of the extra info, used to interpret the actual optional
246	// data appended.
247	//
248	// Note that this is not terribly space optimized. This leaves a great deal
249	// of flexibility to fit more in here later.
250	const int NumMMOs;
251	const bool HasPreInstrSymbol;
252	const bool HasPostInstrSymbol;
253	const bool HasHeapAllocMarker;
254	const bool HasPCSections;
255	const bool HasCFIType;
256	const bool HasMMRAs;
257
258	// Implement the `TrailingObjects` internal API.
259	size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
260	return NumMMOs;
261	}
262	size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
263	return HasPreInstrSymbol + HasPostInstrSymbol;
264	}
265	size_t numTrailingObjects(OverloadToken<MDNode *>) const {
266	return HasHeapAllocMarker + HasPCSections;
267	}
268	size_t numTrailingObjects(OverloadToken<uint32_t>) const {
269	return HasCFIType;
270	}
271
272	// Just a boring constructor to allow us to initialize the sizes. Always use
273	// the `create` routine above.
274	ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
275	bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
276	bool HasMMRAs)
277	: NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
278	HasPostInstrSymbol(HasPostInstrSymbol),
279	HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
280	HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
281	};
282
283	/// Enumeration of the kinds of inline extra info available. It is important
284	/// that the `MachineMemOperand` inline kind has a tag value of zero to make
285	/// it accessible as an `ArrayRef`.
286	enum ExtraInfoInlineKinds {
287	EIIK_MMO = 0,
288	EIIK_PreInstrSymbol,
289	EIIK_PostInstrSymbol,
290	EIIK_OutOfLine
291	};
292
293	// We store extra information about the instruction here. The common case is
294	// expected to be nothing or a single pointer (typically a MMO or a symbol).
295	// We work to optimize this common case by storing it inline here rather than
296	// requiring a separate allocation, but we fall back to an allocation when
297	// multiple pointers are needed.
298	PointerSumType<ExtraInfoInlineKinds,
299	PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
300	PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
301	PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
302	PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
303	Info;
304
305	DebugLoc DbgLoc; // Source line information.
306
307	/// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
308	/// defined by this instruction.
309	unsigned DebugInstrNum;
310
311	/// Cached opcode from MCID.
312	uint16_t Opcode;
313
314	// Intrusive list support
315	friend struct ilist_traits<MachineInstr>;
316	friend struct ilist_callback_traits<MachineBasicBlock>;
317	void setParent(MachineBasicBlock *P) { Parent = P; }
318
319	/// This constructor creates a copy of the given
320	/// MachineInstr in the given MachineFunction.
321	MachineInstr(MachineFunction &, const MachineInstr &);
322
323	/// This constructor create a MachineInstr and add the implicit operands.
324	/// It reserves space for number of operands specified by
325	/// MCInstrDesc. An explicit DebugLoc is supplied.
326	MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL,
327	bool NoImp = false);
328
329	// MachineInstrs are pool-allocated and owned by MachineFunction.
330	friend class MachineFunction;
331
332	void
333	dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
334	SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
335
336	static bool opIsRegDef(const MachineOperand &Op) {
337	return Op.isReg() && Op.isDef();
338	}
339
340	static bool opIsRegUse(const MachineOperand &Op) {
341	return Op.isReg() && Op.isUse();
342	}
343
344	MutableArrayRef<MachineOperand> operands_impl() {
345	return {Operands, NumOperands};
346	}
347	ArrayRef<MachineOperand> operands_impl() const {
348	return {Operands, NumOperands};
349	}
350
351	public:
352	MachineInstr(const MachineInstr &) = delete;
353	MachineInstr &operator=(const MachineInstr &) = delete;
354	// Use MachineFunction::DeleteMachineInstr() instead.
355	~MachineInstr() = delete;
356
357	const MachineBasicBlock* getParent() const { return Parent; }
358	MachineBasicBlock* getParent() { return Parent; }
359
360	/// Move the instruction before \p MovePos.
361	LLVM_ABI void moveBefore(MachineInstr *MovePos);
362
363	/// Return the function that contains the basic block that this instruction
364	/// belongs to.
365	///
366	/// Note: this is undefined behaviour if the instruction does not have a
367	/// parent.
368	LLVM_ABI const MachineFunction *getMF() const;
369	MachineFunction *getMF() {
370	return const_cast<MachineFunction *>(
371	static_cast<const MachineInstr *>(this)->getMF());
372	}
373
374	/// Return the asm printer flags bitvector.
375	uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
376
377	/// Clear the AsmPrinter bitvector.
378	void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
379
380	/// Return whether an AsmPrinter flag is set.
381	bool getAsmPrinterFlag(CommentFlag Flag) const {
382	assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
383	"Flag is out of range for the AsmPrinterFlags field");
384	return AsmPrinterFlags & Flag;
385	}
386
387	/// Set a flag for the AsmPrinter.
388	void setAsmPrinterFlag(uint8_t Flag) {
389	assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
390	"Flag is out of range for the AsmPrinterFlags field");
391	AsmPrinterFlags |= Flag;
392	}
393
394	/// Clear specific AsmPrinter flags.
395	void clearAsmPrinterFlag(CommentFlag Flag) {
396	assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
397	"Flag is out of range for the AsmPrinterFlags field");
398	AsmPrinterFlags &= ~Flag;
399	}
400
401	/// Return the MI flags bitvector.
402	uint32_t getFlags() const {
403	return Flags;
404	}
405
406	/// Return whether an MI flag is set.
407	bool getFlag(MIFlag Flag) const {
408	assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
409	"Flag is out of range for the Flags field");
410	return Flags & Flag;
411	}
412
413	/// Set a MI flag.
414	void setFlag(MIFlag Flag) {
415	assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
416	"Flag is out of range for the Flags field");
417	Flags |= (uint32_t)Flag;
418	}
419
420	void setFlags(unsigned flags) {
421	assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
422	"flags to be set are out of range for the Flags field");
423	// Filter out the automatically maintained flags.
424	unsigned Mask = BundledPred | BundledSucc;
425	Flags = (Flags & Mask) | (flags & ~Mask);
426	}
427
428	/// clearFlag - Clear a MI flag.
429	void clearFlag(MIFlag Flag) {
430	assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
431	"Flag to clear is out of range for the Flags field");
432	Flags &= ~((uint32_t)Flag);
433	}
434
435	void clearFlags(unsigned flags) {
436	assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
437	"flags to be cleared are out of range for the Flags field");
438	Flags &= ~flags;
439	}
440
441	/// Return true if MI is in a bundle (but not the first MI in a bundle).
442	///
443	/// A bundle looks like this before it's finalized:
444	/// ----------------
445	/// | MI |
446	/// ----------------
447	/// |
448	/// ----------------
449	/// | MI * |
450	/// ----------------
451	/// |
452	/// ----------------
453	/// | MI * |
454	/// ----------------
455	/// In this case, the first MI starts a bundle but is not inside a bundle, the
456	/// next 2 MIs are considered "inside" the bundle.
457	///
458	/// After a bundle is finalized, it looks like this:
459	/// ----------------
460	/// | Bundle |
461	/// ----------------
462	/// |
463	/// ----------------
464	/// | MI * |
465	/// ----------------
466	/// |
467	/// ----------------
468	/// | MI * |
469	/// ----------------
470	/// |
471	/// ----------------
472	/// | MI * |
473	/// ----------------
474	/// The first instruction has the special opcode "BUNDLE". It's not "inside"
475	/// a bundle, but the next three MIs are.
476	bool isInsideBundle() const {
477	return getFlag(Flag: BundledPred);
478	}
479
480	/// Return true if this instruction part of a bundle. This is true
481	/// if either itself or its following instruction is marked "InsideBundle".
482	bool isBundled() const {
483	return isBundledWithPred() || isBundledWithSucc();
484	}
485
486	/// Return true if this instruction is part of a bundle, and it is not the
487	/// first instruction in the bundle.
488	bool isBundledWithPred() const { return getFlag(Flag: BundledPred); }
489
490	/// Return true if this instruction is part of a bundle, and it is not the
491	/// last instruction in the bundle.
492	bool isBundledWithSucc() const { return getFlag(Flag: BundledSucc); }
493
494	/// Bundle this instruction with its predecessor. This can be an unbundled
495	/// instruction, or it can be the first instruction in a bundle.
496	LLVM_ABI void bundleWithPred();
497
498	/// Bundle this instruction with its successor. This can be an unbundled
499	/// instruction, or it can be the last instruction in a bundle.
500	LLVM_ABI void bundleWithSucc();
501
502	/// Break bundle above this instruction.
503	LLVM_ABI void unbundleFromPred();
504
505	/// Break bundle below this instruction.
506	LLVM_ABI void unbundleFromSucc();
507
508	/// Returns the debug location id of this MachineInstr.
509	const DebugLoc &getDebugLoc() const { return DbgLoc; }
510
511	/// Return the operand containing the offset to be used if this DBG_VALUE
512	/// instruction is indirect; will be an invalid register if this value is
513	/// not indirect, and an immediate with value 0 otherwise.
514	const MachineOperand &getDebugOffset() const {
515	assert(isNonListDebugValue() && "not a DBG_VALUE");
516	return getOperand(i: 1);
517	}
518	MachineOperand &getDebugOffset() {
519	assert(isNonListDebugValue() && "not a DBG_VALUE");
520	return getOperand(i: 1);
521	}
522
523	/// Return the operand for the debug variable referenced by
524	/// this DBG_VALUE instruction.
525	LLVM_ABI const MachineOperand &getDebugVariableOp() const;
526	LLVM_ABI MachineOperand &getDebugVariableOp();
527
528	/// Return the debug variable referenced by
529	/// this DBG_VALUE instruction.
530	LLVM_ABI const DILocalVariable *getDebugVariable() const;
531
532	/// Return the operand for the complex address expression referenced by
533	/// this DBG_VALUE instruction.
534	LLVM_ABI const MachineOperand &getDebugExpressionOp() const;
535	LLVM_ABI MachineOperand &getDebugExpressionOp();
536
537	/// Return the complex address expression referenced by
538	/// this DBG_VALUE instruction.
539	LLVM_ABI const DIExpression *getDebugExpression() const;
540
541	/// Return the debug label referenced by
542	/// this DBG_LABEL instruction.
543	LLVM_ABI const DILabel *getDebugLabel() const;
544
545	/// Fetch the instruction number of this MachineInstr. If it does not have
546	/// one already, a new and unique number will be assigned.
547	LLVM_ABI unsigned getDebugInstrNum();
548
549	/// Fetch instruction number of this MachineInstr -- but before it's inserted
550	/// into \p MF. Needed for transformations that create an instruction but
551	/// don't immediately insert them.
552	LLVM_ABI unsigned getDebugInstrNum(MachineFunction &MF);
553
554	/// Examine the instruction number of this MachineInstr. May be zero if
555	/// it hasn't been assigned a number yet.
556	unsigned peekDebugInstrNum() const { return DebugInstrNum; }
557
558	/// Set instruction number of this MachineInstr. Avoid using unless you're
559	/// deserializing this information.
560	void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
561
562	/// Drop any variable location debugging information associated with this
563	/// instruction. Use when an instruction is modified in such a way that it no
564	/// longer defines the value it used to. Variable locations using that value
565	/// will be dropped.
566	void dropDebugNumber() { DebugInstrNum = 0; }
567
568	/// For inline asm, get the !srcloc metadata node if we have it, and decode
569	/// the loc cookie from it.
570	LLVM_ABI const MDNode *getLocCookieMD() const;
571
572	/// Emit an error referring to the source location of this instruction. This
573	/// should only be used for inline assembly that is somehow impossible to
574	/// compile. Other errors should have been handled much earlier.
575	LLVM_ABI void emitInlineAsmError(const Twine &ErrMsg) const;
576
577	// Emit an error in the LLVMContext referring to the source location of this
578	// instruction, if available.
579	LLVM_ABI void emitGenericError(const Twine &ErrMsg) const;
580
581	/// Returns the target instruction descriptor of this MachineInstr.
582	const MCInstrDesc &getDesc() const { return *MCID; }
583
584	/// Returns the opcode of this MachineInstr.
585	unsigned getOpcode() const { return Opcode; }
586
587	/// Retuns the total number of operands.
588	unsigned getNumOperands() const { return NumOperands; }
589
590	/// Returns the total number of operands which are debug locations.
591	unsigned getNumDebugOperands() const { return size(Range: debug_operands()); }
592
593	const MachineOperand &getOperand(unsigned i) const {
594	return operands_impl()[i];
595	}
596	MachineOperand &getOperand(unsigned i) { return operands_impl()[i]; }
597
598	MachineOperand &getDebugOperand(unsigned Index) {
599	assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
600	return *(debug_operands().begin() + Index);
601	}
602	const MachineOperand &getDebugOperand(unsigned Index) const {
603	assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
604	return *(debug_operands().begin() + Index);
605	}
606
607	/// Returns whether this debug value has at least one debug operand with the
608	/// register \p Reg.
609	bool hasDebugOperandForReg(Register Reg) const {
610	return any_of(Range: debug_operands(), P: [Reg](const MachineOperand &Op) {
611	return Op.isReg() && Op.getReg() == Reg;
612	});
613	}
614
615	/// Returns a range of all of the operands that correspond to a debug use of
616	/// \p Reg.
617	LLVM_ABI iterator_range<filter_iterator<
618	const MachineOperand *, std::function<bool(const MachineOperand &Op)>>>
619	getDebugOperandsForReg(Register Reg) const;
620	LLVM_ABI
621	iterator_range<filter_iterator<MachineOperand *,
622	std::function<bool(MachineOperand &Op)>>>
623	getDebugOperandsForReg(Register Reg);
624
625	bool isDebugOperand(const MachineOperand *Op) const {
626	return Op >= adl_begin(range: debug_operands()) && Op <= adl_end(range: debug_operands());
627	}
628
629	unsigned getDebugOperandIndex(const MachineOperand *Op) const {
630	assert(isDebugOperand(Op) && "Expected a debug operand.");
631	return std::distance(first: adl_begin(range: debug_operands()), last: Op);
632	}
633
634	/// Returns the total number of definitions.
635	unsigned getNumDefs() const {
636	return getNumExplicitDefs() + MCID->implicit_defs().size();
637	}
638
639	/// Returns true if the instruction has implicit definition.
640	bool hasImplicitDef() const {
641	for (const MachineOperand &MO : implicit_operands())
642	if (MO.isDef())
643	return true;
644	return false;
645	}
646
647	/// Returns the implicit operands number.
648	unsigned getNumImplicitOperands() const {
649	return getNumOperands() - getNumExplicitOperands();
650	}
651
652	/// Return true if operand \p OpIdx is a subregister index.
653	bool isOperandSubregIdx(unsigned OpIdx) const {
654	assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
655	if (isExtractSubreg() && OpIdx == 2)
656	return true;
657	if (isInsertSubreg() && OpIdx == 3)
658	return true;
659	if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
660	return true;
661	if (isSubregToReg() && OpIdx == 3)
662	return true;
663	return false;
664	}
665
666	/// Returns the number of non-implicit operands.
667	LLVM_ABI unsigned getNumExplicitOperands() const;
668
669	/// Returns the number of non-implicit definitions.
670	LLVM_ABI unsigned getNumExplicitDefs() const;
671
672	/// iterator/begin/end - Iterate over all operands of a machine instruction.
673
674	// The operands must always be in the following order:
675	// - explicit reg defs,
676	// - other explicit operands (reg uses, immediates, etc.),
677	// - implicit reg defs
678	// - implicit reg uses
679	using mop_iterator = MachineOperand *;
680	using const_mop_iterator = const MachineOperand *;
681
682	using mop_range = iterator_range<mop_iterator>;
683	using const_mop_range = iterator_range<const_mop_iterator>;
684
685	mop_iterator operands_begin() { return Operands; }
686	mop_iterator operands_end() { return Operands + NumOperands; }
687
688	const_mop_iterator operands_begin() const { return Operands; }
689	const_mop_iterator operands_end() const { return Operands + NumOperands; }
690
691	mop_range operands() { return operands_impl(); }
692	const_mop_range operands() const { return operands_impl(); }
693
694	mop_range explicit_operands() {
695	return operands_impl().take_front(N: getNumExplicitOperands());
696	}
697	const_mop_range explicit_operands() const {
698	return operands_impl().take_front(N: getNumExplicitOperands());
699	}
700	mop_range implicit_operands() {
701	return operands_impl().drop_front(N: getNumExplicitOperands());
702	}
703	const_mop_range implicit_operands() const {
704	return operands_impl().drop_front(N: getNumExplicitOperands());
705	}
706
707	/// Returns all operands that are used to determine the variable
708	/// location for this DBG_VALUE instruction.
709	mop_range debug_operands() {
710	assert(isDebugValueLike() && "Must be a debug value instruction.");
711	return isNonListDebugValue() ? operands_impl().take_front(N: 1)
712	: operands_impl().drop_front(N: 2);
713	}
714	/// \copydoc debug_operands()
715	const_mop_range debug_operands() const {
716	assert(isDebugValueLike() && "Must be a debug value instruction.");
717	return isNonListDebugValue() ? operands_impl().take_front(N: 1)
718	: operands_impl().drop_front(N: 2);
719	}
720	/// Returns all explicit operands that are register definitions.
721	/// Implicit definition are not included!
722	mop_range defs() { return operands_impl().take_front(N: getNumExplicitDefs()); }
723	/// \copydoc defs()
724	const_mop_range defs() const {
725	return operands_impl().take_front(N: getNumExplicitDefs());
726	}
727	/// Returns all operands which may be register uses.
728	/// This may include unrelated operands which are not register uses.
729	mop_range uses() { return operands_impl().drop_front(N: getNumExplicitDefs()); }
730	/// \copydoc uses()
731	const_mop_range uses() const {
732	return operands_impl().drop_front(N: getNumExplicitDefs());
733	}
734	mop_range explicit_uses() {
735	return operands_impl()
736	.take_front(N: getNumExplicitOperands())
737	.drop_front(N: getNumExplicitDefs());
738	}
739	const_mop_range explicit_uses() const {
740	return operands_impl()
741	.take_front(N: getNumExplicitOperands())
742	.drop_front(N: getNumExplicitDefs());
743	}
744
745	using filtered_mop_range = iterator_range<
746	filter_iterator<mop_iterator, bool (*)(const MachineOperand &)>>;
747	using filtered_const_mop_range = iterator_range<
748	filter_iterator<const_mop_iterator, bool (*)(const MachineOperand &)>>;
749
750	/// Returns an iterator range over all operands that are (explicit or
751	/// implicit) register defs.
752	filtered_mop_range all_defs() {
753	return make_filter_range(Range: operands(), Pred: opIsRegDef);
754	}
755	/// \copydoc all_defs()
756	filtered_const_mop_range all_defs() const {
757	return make_filter_range(Range: operands(), Pred: opIsRegDef);
758	}
759
760	/// Returns an iterator range over all operands that are (explicit or
761	/// implicit) register uses.
762	filtered_mop_range all_uses() {
763	return make_filter_range(Range: uses(), Pred: opIsRegUse);
764	}
765	/// \copydoc all_uses()
766	filtered_const_mop_range all_uses() const {
767	return make_filter_range(Range: uses(), Pred: opIsRegUse);
768	}
769
770	/// Returns the number of the operand iterator \p I points to.
771	unsigned getOperandNo(const_mop_iterator I) const {
772	return I - operands_begin();
773	}
774
775	/// Access to memory operands of the instruction. If there are none, that does
776	/// not imply anything about whether the function accesses memory. Instead,
777	/// the caller must behave conservatively.
778	ArrayRef<MachineMemOperand *> memoperands() const {
779	if (!Info)
780	return {};
781
782	if (Info.is<EIIK_MMO>())
783	return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
784
785	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
786	return EI->getMMOs();
787
788	return {};
789	}
790
791	/// Access to memory operands of the instruction.
792	///
793	/// If `memoperands_begin() == memoperands_end()`, that does not imply
794	/// anything about whether the function accesses memory. Instead, the caller
795	/// must behave conservatively.
796	mmo_iterator memoperands_begin() const { return memoperands().begin(); }
797
798	/// Access to memory operands of the instruction.
799	///
800	/// If `memoperands_begin() == memoperands_end()`, that does not imply
801	/// anything about whether the function accesses memory. Instead, the caller
802	/// must behave conservatively.
803	mmo_iterator memoperands_end() const { return memoperands().end(); }
804
805	/// Return true if we don't have any memory operands which described the
806	/// memory access done by this instruction. If this is true, calling code
807	/// must be conservative.
808	bool memoperands_empty() const { return memoperands().empty(); }
809
810	/// Return true if this instruction has exactly one MachineMemOperand.
811	bool hasOneMemOperand() const { return memoperands().size() == 1; }
812
813	/// Return the number of memory operands.
814	unsigned getNumMemOperands() const { return memoperands().size(); }
815
816	/// Helper to extract a pre-instruction symbol if one has been added.
817	MCSymbol *getPreInstrSymbol() const {
818	if (!Info)
819	return nullptr;
820	if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
821	return S;
822	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
823	return EI->getPreInstrSymbol();
824
825	return nullptr;
826	}
827
828	/// Helper to extract a post-instruction symbol if one has been added.
829	MCSymbol *getPostInstrSymbol() const {
830	if (!Info)
831	return nullptr;
832	if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
833	return S;
834	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
835	return EI->getPostInstrSymbol();
836
837	return nullptr;
838	}
839
840	/// Helper to extract a heap alloc marker if one has been added.
841	MDNode *getHeapAllocMarker() const {
842	if (!Info)
843	return nullptr;
844	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
845	return EI->getHeapAllocMarker();
846
847	return nullptr;
848	}
849
850	/// Helper to extract PCSections metadata target sections.
851	MDNode *getPCSections() const {
852	if (!Info)
853	return nullptr;
854	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
855	return EI->getPCSections();
856
857	return nullptr;
858	}
859
860	/// Helper to extract mmra.op metadata.
861	MDNode *getMMRAMetadata() const {
862	if (!Info)
863	return nullptr;
864	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
865	return EI->getMMRAMetadata();
866	return nullptr;
867	}
868
869	/// Helper to extract a CFI type hash if one has been added.
870	uint32_t getCFIType() const {
871	if (!Info)
872	return 0;
873	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
874	return EI->getCFIType();
875
876	return 0;
877	}
878
879	/// API for querying MachineInstr properties. They are the same as MCInstrDesc
880	/// queries but they are bundle aware.
881
882	enum QueryType {
883	IgnoreBundle, // Ignore bundles
884	AnyInBundle, // Return true if any instruction in bundle has property
885	AllInBundle // Return true if all instructions in bundle have property
886	};
887
888	/// Return true if the instruction (or in the case of a bundle,
889	/// the instructions inside the bundle) has the specified property.
890	/// The first argument is the property being queried.
891	/// The second argument indicates whether the query should look inside
892	/// instruction bundles.
893	bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
894	assert(MCFlag < 64 &&
895	"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
896	// Inline the fast path for unbundled or bundle-internal instructions.
897	if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
898	return getDesc().getFlags() & (1ULL << MCFlag);
899
900	// If this is the first instruction in a bundle, take the slow path.
901	return hasPropertyInBundle(Mask: 1ULL << MCFlag, Type);
902	}
903
904	/// Return true if this is an instruction that should go through the usual
905	/// legalization steps.
906	bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
907	return hasProperty(MCFlag: MCID::PreISelOpcode, Type);
908	}
909
910	/// Return true if this instruction can have a variable number of operands.
911	/// In this case, the variable operands will be after the normal
912	/// operands but before the implicit definitions and uses (if any are
913	/// present).
914	bool isVariadic(QueryType Type = IgnoreBundle) const {
915	return hasProperty(MCFlag: MCID::Variadic, Type);
916	}
917
918	/// Set if this instruction has an optional definition, e.g.
919	/// ARM instructions which can set condition code if 's' bit is set.
920	bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
921	return hasProperty(MCFlag: MCID::HasOptionalDef, Type);
922	}
923
924	/// Return true if this is a pseudo instruction that doesn't
925	/// correspond to a real machine instruction.
926	bool isPseudo(QueryType Type = IgnoreBundle) const {
927	return hasProperty(MCFlag: MCID::Pseudo, Type);
928	}
929
930	/// Return true if this instruction doesn't produce any output in the form of
931	/// executable instructions.
932	bool isMetaInstruction(QueryType Type = IgnoreBundle) const {
933	return hasProperty(MCFlag: MCID::Meta, Type);
934	}
935
936	bool isReturn(QueryType Type = AnyInBundle) const {
937	return hasProperty(MCFlag: MCID::Return, Type);
938	}
939
940	/// Return true if this is an instruction that marks the end of an EH scope,
941	/// i.e., a catchpad or a cleanuppad instruction.
942	bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
943	return hasProperty(MCFlag: MCID::EHScopeReturn, Type);
944	}
945
946	bool isCall(QueryType Type = AnyInBundle) const {
947	return hasProperty(MCFlag: MCID::Call, Type);
948	}
949
950	/// Return true if this is a call instruction that may have an additional
951	/// information associated with it.
952	LLVM_ABI bool
953	isCandidateForAdditionalCallInfo(QueryType Type = IgnoreBundle) const;
954
955	/// Return true if copying, moving, or erasing this instruction requires
956	/// updating additional call info (see \ref copyCallInfo, \ref moveCallInfo,
957	/// \ref eraseCallInfo).
958	LLVM_ABI bool shouldUpdateAdditionalCallInfo() const;
959
960	/// Returns true if the specified instruction stops control flow
961	/// from executing the instruction immediately following it. Examples include
962	/// unconditional branches and return instructions.
963	bool isBarrier(QueryType Type = AnyInBundle) const {
964	return hasProperty(MCFlag: MCID::Barrier, Type);
965	}
966
967	/// Returns true if this instruction part of the terminator for a basic block.
968	/// Typically this is things like return and branch instructions.
969	///
970	/// Various passes use this to insert code into the bottom of a basic block,
971	/// but before control flow occurs.
972	bool isTerminator(QueryType Type = AnyInBundle) const {
973	return hasProperty(MCFlag: MCID::Terminator, Type);
974	}
975
976	/// Returns true if this is a conditional, unconditional, or indirect branch.
977	/// Predicates below can be used to discriminate between
978	/// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
979	/// get more information.
980	bool isBranch(QueryType Type = AnyInBundle) const {
981	return hasProperty(MCFlag: MCID::Branch, Type);
982	}
983
984	/// Return true if this is an indirect branch, such as a
985	/// branch through a register.
986	bool isIndirectBranch(QueryType Type = AnyInBundle) const {
987	return hasProperty(MCFlag: MCID::IndirectBranch, Type);
988	}
989
990	/// Return true if this is a branch which may fall
991	/// through to the next instruction or may transfer control flow to some other
992	/// block. The TargetInstrInfo::analyzeBranch method can be used to get more
993	/// information about this branch.
994	bool isConditionalBranch(QueryType Type = AnyInBundle) const {
995	return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
996	}
997
998	/// Return true if this is a branch which always
999	/// transfers control flow to some other block. The
1000	/// TargetInstrInfo::analyzeBranch method can be used to get more information
1001	/// about this branch.
1002	bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
1003	return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
1004	}
1005
1006	/// Return true if this instruction has a predicate operand that
1007	/// controls execution. It may be set to 'always', or may be set to other
1008	/// values. There are various methods in TargetInstrInfo that can be used to
1009	/// control and modify the predicate in this instruction.
1010	bool isPredicable(QueryType Type = AllInBundle) const {
1011	// If it's a bundle than all bundled instructions must be predicable for this
1012	// to return true.
1013	return hasProperty(MCFlag: MCID::Predicable, Type);
1014	}
1015
1016	/// Return true if this instruction is a comparison.
1017	bool isCompare(QueryType Type = IgnoreBundle) const {
1018	return hasProperty(MCFlag: MCID::Compare, Type);
1019	}
1020
1021	/// Return true if this instruction is a move immediate
1022	/// (including conditional moves) instruction.
1023	bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
1024	return hasProperty(MCFlag: MCID::MoveImm, Type);
1025	}
1026
1027	/// Return true if this instruction is a register move.
1028	/// (including moving values from subreg to reg)
1029	bool isMoveReg(QueryType Type = IgnoreBundle) const {
1030	return hasProperty(MCFlag: MCID::MoveReg, Type);
1031	}
1032
1033	/// Return true if this instruction is a bitcast instruction.
1034	bool isBitcast(QueryType Type = IgnoreBundle) const {
1035	return hasProperty(MCFlag: MCID::Bitcast, Type);
1036	}
1037
1038	/// Return true if this instruction is a select instruction.
1039	bool isSelect(QueryType Type = IgnoreBundle) const {
1040	return hasProperty(MCFlag: MCID::Select, Type);
1041	}
1042
1043	/// Return true if this instruction cannot be safely duplicated.
1044	/// For example, if the instruction has a unique labels attached
1045	/// to it, duplicating it would cause multiple definition errors.
1046	bool isNotDuplicable(QueryType Type = AnyInBundle) const {
1047	if (getPreInstrSymbol() || getPostInstrSymbol())
1048	return true;
1049	return hasProperty(MCFlag: MCID::NotDuplicable, Type);
1050	}
1051
1052	/// Return true if this instruction is convergent.
1053	/// Convergent instructions can not be made control-dependent on any
1054	/// additional values.
1055	bool isConvergent(QueryType Type = AnyInBundle) const {
1056	if (isInlineAsm()) {
1057	unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1058	if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1059	return true;
1060	}
1061	if (getFlag(Flag: NoConvergent))
1062	return false;
1063	return hasProperty(MCFlag: MCID::Convergent, Type);
1064	}
1065
1066	/// Returns true if the specified instruction has a delay slot
1067	/// which must be filled by the code generator.
1068	bool hasDelaySlot(QueryType Type = AnyInBundle) const {
1069	return hasProperty(MCFlag: MCID::DelaySlot, Type);
1070	}
1071
1072	/// Return true for instructions that can be folded as
1073	/// memory operands in other instructions. The most common use for this
1074	/// is instructions that are simple loads from memory that don't modify
1075	/// the loaded value in any way, but it can also be used for instructions
1076	/// that can be expressed as constant-pool loads, such as V_SETALLONES
1077	/// on x86, to allow them to be folded when it is beneficial.
1078	/// This should only be set on instructions that return a value in their
1079	/// only virtual register definition.
1080	bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
1081	return hasProperty(MCFlag: MCID::FoldableAsLoad, Type);
1082	}
1083
1084	/// Return true if this instruction behaves
1085	/// the same way as the generic REG_SEQUENCE instructions.
1086	/// E.g., on ARM,
1087	/// dX VMOVDRR rY, rZ
1088	/// is equivalent to
1089	/// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1090	///
1091	/// Note that for the optimizers to be able to take advantage of
1092	/// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1093	/// override accordingly.
1094	bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
1095	return hasProperty(MCFlag: MCID::RegSequence, Type);
1096	}
1097
1098	/// Return true if this instruction behaves
1099	/// the same way as the generic EXTRACT_SUBREG instructions.
1100	/// E.g., on ARM,
1101	/// rX, rY VMOVRRD dZ
1102	/// is equivalent to two EXTRACT_SUBREG:
1103	/// rX = EXTRACT_SUBREG dZ, ssub_0
1104	/// rY = EXTRACT_SUBREG dZ, ssub_1
1105	///
1106	/// Note that for the optimizers to be able to take advantage of
1107	/// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1108	/// override accordingly.
1109	bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
1110	return hasProperty(MCFlag: MCID::ExtractSubreg, Type);
1111	}
1112
1113	/// Return true if this instruction behaves
1114	/// the same way as the generic INSERT_SUBREG instructions.
1115	/// E.g., on ARM,
1116	/// dX = VSETLNi32 dY, rZ, Imm
1117	/// is equivalent to a INSERT_SUBREG:
1118	/// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1119	///
1120	/// Note that for the optimizers to be able to take advantage of
1121	/// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1122	/// override accordingly.
1123	bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
1124	return hasProperty(MCFlag: MCID::InsertSubreg, Type);
1125	}
1126
1127	//===--------------------------------------------------------------------===//
1128	// Side Effect Analysis
1129	//===--------------------------------------------------------------------===//
1130
1131	/// Return true if this instruction could possibly read memory.
1132	/// Instructions with this flag set are not necessarily simple load
1133	/// instructions, they may load a value and modify it, for example.
1134	bool mayLoad(QueryType Type = AnyInBundle) const {
1135	if (isInlineAsm()) {
1136	unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1137	if (ExtraInfo & InlineAsm::Extra_MayLoad)
1138	return true;
1139	}
1140	return hasProperty(MCFlag: MCID::MayLoad, Type);
1141	}
1142
1143	/// Return true if this instruction could possibly modify memory.
1144	/// Instructions with this flag set are not necessarily simple store
1145	/// instructions, they may store a modified value based on their operands, or
1146	/// may not actually modify anything, for example.
1147	bool mayStore(QueryType Type = AnyInBundle) const {
1148	if (isInlineAsm()) {
1149	unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1150	if (ExtraInfo & InlineAsm::Extra_MayStore)
1151	return true;
1152	}
1153	return hasProperty(MCFlag: MCID::MayStore, Type);
1154	}
1155
1156	/// Return true if this instruction could possibly read or modify memory.
1157	bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
1158	return mayLoad(Type) || mayStore(Type);
1159	}
1160
1161	/// Return true if this instruction could possibly raise a floating-point
1162	/// exception. This is the case if the instruction is a floating-point
1163	/// instruction that can in principle raise an exception, as indicated
1164	/// by the MCID::MayRaiseFPException property, *and* at the same time,
1165	/// the instruction is used in a context where we expect floating-point
1166	/// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1167	bool mayRaiseFPException() const {
1168	return hasProperty(MCFlag: MCID::MayRaiseFPException) &&
1169	!getFlag(Flag: MachineInstr::MIFlag::NoFPExcept);
1170	}
1171
1172	//===--------------------------------------------------------------------===//
1173	// Flags that indicate whether an instruction can be modified by a method.
1174	//===--------------------------------------------------------------------===//
1175
1176	/// Return true if this may be a 2- or 3-address
1177	/// instruction (of the form "X = op Y, Z, ..."), which produces the same
1178	/// result if Y and Z are exchanged. If this flag is set, then the
1179	/// TargetInstrInfo::commuteInstruction method may be used to hack on the
1180	/// instruction.
1181	///
1182	/// Note that this flag may be set on instructions that are only commutable
1183	/// sometimes. In these cases, the call to commuteInstruction will fail.
1184	/// Also note that some instructions require non-trivial modification to
1185	/// commute them.
1186	bool isCommutable(QueryType Type = IgnoreBundle) const {
1187	return hasProperty(MCFlag: MCID::Commutable, Type);
1188	}
1189
1190	/// Return true if this is a 2-address instruction
1191	/// which can be changed into a 3-address instruction if needed. Doing this
1192	/// transformation can be profitable in the register allocator, because it
1193	/// means that the instruction can use a 2-address form if possible, but
1194	/// degrade into a less efficient form if the source and dest register cannot
1195	/// be assigned to the same register. For example, this allows the x86
1196	/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1197	/// is the same speed as the shift but has bigger code size.
1198	///
1199	/// If this returns true, then the target must implement the
1200	/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1201	/// is allowed to fail if the transformation isn't valid for this specific
1202	/// instruction (e.g. shl reg, 4 on x86).
1203	///
1204	bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
1205	return hasProperty(MCFlag: MCID::ConvertibleTo3Addr, Type);
1206	}
1207
1208	/// Return true if this instruction requires
1209	/// custom insertion support when the DAG scheduler is inserting it into a
1210	/// machine basic block. If this is true for the instruction, it basically
1211	/// means that it is a pseudo instruction used at SelectionDAG time that is
1212	/// expanded out into magic code by the target when MachineInstrs are formed.
1213	///
1214	/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1215	/// is used to insert this into the MachineBasicBlock.
1216	bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
1217	return hasProperty(MCFlag: MCID::UsesCustomInserter, Type);
1218	}
1219
1220	/// Return true if this instruction requires *adjustment*
1221	/// after instruction selection by calling a target hook. For example, this
1222	/// can be used to fill in ARM 's' optional operand depending on whether
1223	/// the conditional flag register is used.
1224	bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
1225	return hasProperty(MCFlag: MCID::HasPostISelHook, Type);
1226	}
1227
1228	/// Returns true if this instruction is a candidate for remat.
1229	/// This flag is deprecated, please don't use it anymore. If this
1230	/// flag is set, the isReallyTriviallyReMaterializable() method is called to
1231	/// verify the instruction is really rematerializable.
1232	bool isRematerializable(QueryType Type = AllInBundle) const {
1233	// It's only possible to re-mat a bundle if all bundled instructions are
1234	// re-materializable.
1235	return hasProperty(MCFlag: MCID::Rematerializable, Type);
1236	}
1237
1238	/// Returns true if this instruction has the same cost (or less) than a move
1239	/// instruction. This is useful during certain types of optimizations
1240	/// (e.g., remat during two-address conversion or machine licm)
1241	/// where we would like to remat or hoist the instruction, but not if it costs
1242	/// more than moving the instruction into the appropriate register. Note, we
1243	/// are not marking copies from and to the same register class with this flag.
1244	bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
1245	// Only returns true for a bundle if all bundled instructions are cheap.
1246	return hasProperty(MCFlag: MCID::CheapAsAMove, Type);
1247	}
1248
1249	/// Returns true if this instruction source operands
1250	/// have special register allocation requirements that are not captured by the
1251	/// operand register classes. e.g. ARM::STRD's two source registers must be an
1252	/// even / odd pair, ARM::STM registers have to be in ascending order.
1253	/// Post-register allocation passes should not attempt to change allocations
1254	/// for sources of instructions with this flag.
1255	bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
1256	return hasProperty(MCFlag: MCID::ExtraSrcRegAllocReq, Type);
1257	}
1258
1259	/// Returns true if this instruction def operands
1260	/// have special register allocation requirements that are not captured by the
1261	/// operand register classes. e.g. ARM::LDRD's two def registers must be an
1262	/// even / odd pair, ARM::LDM registers have to be in ascending order.
1263	/// Post-register allocation passes should not attempt to change allocations
1264	/// for definitions of instructions with this flag.
1265	bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
1266	return hasProperty(MCFlag: MCID::ExtraDefRegAllocReq, Type);
1267	}
1268
1269	enum MICheckType {
1270	CheckDefs, // Check all operands for equality
1271	CheckKillDead, // Check all operands including kill / dead markers
1272	IgnoreDefs, // Ignore all definitions
1273	IgnoreVRegDefs // Ignore virtual register definitions
1274	};
1275
1276	/// Return true if this instruction is identical to \p Other.
1277	/// Two instructions are identical if they have the same opcode and all their
1278	/// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1279	/// Note that this means liveness related flags (dead, undef, kill) do not
1280	/// affect the notion of identical.
1281	LLVM_ABI bool isIdenticalTo(const MachineInstr &Other,
1282	MICheckType Check = CheckDefs) const;
1283
1284	/// Returns true if this instruction is a debug instruction that represents an
1285	/// identical debug value to \p Other.
1286	/// This function considers these debug instructions equivalent if they have
1287	/// identical variables, debug locations, and debug operands, and if the
1288	/// DIExpressions combined with the directness flags are equivalent.
1289	LLVM_ABI bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1290
1291	/// Unlink 'this' from the containing basic block, and return it without
1292	/// deleting it.
1293	///
1294	/// This function can not be used on bundled instructions, use
1295	/// removeFromBundle() to remove individual instructions from a bundle.
1296	LLVM_ABI MachineInstr *removeFromParent();
1297
1298	/// Unlink this instruction from its basic block and return it without
1299	/// deleting it.
1300	///
1301	/// If the instruction is part of a bundle, the other instructions in the
1302	/// bundle remain bundled.
1303	LLVM_ABI MachineInstr *removeFromBundle();
1304
1305	/// Unlink 'this' from the containing basic block and delete it.
1306	///
1307	/// If this instruction is the header of a bundle, the whole bundle is erased.
1308	/// This function can not be used for instructions inside a bundle, use
1309	/// eraseFromBundle() to erase individual bundled instructions.
1310	LLVM_ABI void eraseFromParent();
1311
1312	/// Unlink 'this' from its basic block and delete it.
1313	///
1314	/// If the instruction is part of a bundle, the other instructions in the
1315	/// bundle remain bundled.
1316	LLVM_ABI void eraseFromBundle();
1317
1318	bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1319	bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1320	bool isAnnotationLabel() const {
1321	return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1322	}
1323
1324	bool isLifetimeMarker() const {
1325	return getOpcode() == TargetOpcode::LIFETIME_START ||
1326	getOpcode() == TargetOpcode::LIFETIME_END;
1327	}
1328
1329	/// Returns true if the MachineInstr represents a label.
1330	bool isLabel() const {
1331	return isEHLabel() || isGCLabel() || isAnnotationLabel();
1332	}
1333
1334	bool isCFIInstruction() const {
1335	return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1336	}
1337
1338	bool isPseudoProbe() const {
1339	return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1340	}
1341
1342	// True if the instruction represents a position in the function.
1343	bool isPosition() const { return isLabel() || isCFIInstruction(); }
1344
1345	bool isNonListDebugValue() const {
1346	return getOpcode() == TargetOpcode::DBG_VALUE;
1347	}
1348	bool isDebugValueList() const {
1349	return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1350	}
1351	bool isDebugValue() const {
1352	return isNonListDebugValue() || isDebugValueList();
1353	}
1354	bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1355	bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1356	bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1357	bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1358	bool isDebugInstr() const {
1359	return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1360	}
1361	bool isDebugOrPseudoInstr() const {
1362	return isDebugInstr() || isPseudoProbe();
1363	}
1364
1365	bool isDebugOffsetImm() const {
1366	return isNonListDebugValue() && getDebugOffset().isImm();
1367	}
1368
1369	/// A DBG_VALUE is indirect iff the location operand is a register and
1370	/// the offset operand is an immediate.
1371	bool isIndirectDebugValue() const {
1372	return isDebugOffsetImm() && getDebugOperand(Index: 0).isReg();
1373	}
1374
1375	/// A DBG_VALUE is an entry value iff its debug expression contains the
1376	/// DW_OP_LLVM_entry_value operation.
1377	LLVM_ABI bool isDebugEntryValue() const;
1378
1379	/// Return true if the instruction is a debug value which describes a part of
1380	/// a variable as unavailable.
1381	bool isUndefDebugValue() const {
1382	if (!isDebugValue())
1383	return false;
1384	// If any $noreg locations are given, this DV is undef.
1385	for (const MachineOperand &Op : debug_operands())
1386	if (Op.isReg() && !Op.getReg().isValid())
1387	return true;
1388	return false;
1389	}
1390
1391	bool isJumpTableDebugInfo() const {
1392	return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1393	}
1394
1395	bool isPHI() const {
1396	return getOpcode() == TargetOpcode::PHI ||
1397	getOpcode() == TargetOpcode::G_PHI;
1398	}
1399	bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1400	bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1401	bool isInlineAsm() const {
1402	return getOpcode() == TargetOpcode::INLINEASM ||
1403	getOpcode() == TargetOpcode::INLINEASM_BR;
1404	}
1405	/// Returns true if the register operand can be folded with a load or store
1406	/// into a frame index. Does so by checking the InlineAsm::Flag immediate
1407	/// operand at OpId - 1.
1408	LLVM_ABI bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1409
1410	LLVM_ABI bool isStackAligningInlineAsm() const;
1411	LLVM_ABI InlineAsm::AsmDialect getInlineAsmDialect() const;
1412
1413	bool isInsertSubreg() const {
1414	return getOpcode() == TargetOpcode::INSERT_SUBREG;
1415	}
1416
1417	bool isSubregToReg() const {
1418	return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1419	}
1420
1421	bool isRegSequence() const {
1422	return getOpcode() == TargetOpcode::REG_SEQUENCE;
1423	}
1424
1425	bool isBundle() const {
1426	return getOpcode() == TargetOpcode::BUNDLE;
1427	}
1428
1429	bool isCopy() const {
1430	return getOpcode() == TargetOpcode::COPY;
1431	}
1432
1433	bool isFullCopy() const {
1434	return isCopy() && !getOperand(i: 0).getSubReg() && !getOperand(i: 1).getSubReg();
1435	}
1436
1437	bool isExtractSubreg() const {
1438	return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1439	}
1440
1441	bool isFakeUse() const { return getOpcode() == TargetOpcode::FAKE_USE; }
1442
1443	/// Return true if the instruction behaves like a copy.
1444	/// This does not include native copy instructions.
1445	bool isCopyLike() const {
1446	return isCopy() || isSubregToReg();
1447	}
1448
1449	/// Return true is the instruction is an identity copy.
1450	bool isIdentityCopy() const {
1451	return isCopy() && getOperand(i: 0).getReg() == getOperand(i: 1).getReg() &&
1452	getOperand(i: 0).getSubReg() == getOperand(i: 1).getSubReg();
1453	}
1454
1455	/// Return true if this is a transient instruction that is either very likely
1456	/// to be eliminated during register allocation (such as copy-like
1457	/// instructions), or if this instruction doesn't have an execution-time cost.
1458	bool isTransient() const {
1459	switch (getOpcode()) {
1460	default:
1461	return isMetaInstruction();
1462	// Copy-like instructions are usually eliminated during register allocation.
1463	case TargetOpcode::PHI:
1464	case TargetOpcode::G_PHI:
1465	case TargetOpcode::COPY:
1466	case TargetOpcode::INSERT_SUBREG:
1467	case TargetOpcode::SUBREG_TO_REG:
1468	case TargetOpcode::REG_SEQUENCE:
1469	return true;
1470	}
1471	}
1472
1473	/// Return the number of instructions inside the MI bundle, excluding the
1474	/// bundle header.
1475	///
1476	/// This is the number of instructions that MachineBasicBlock::iterator
1477	/// skips, 0 for unbundled instructions.
1478	LLVM_ABI unsigned getBundleSize() const;
1479
1480	/// Return true if the MachineInstr reads the specified register.
1481	/// If TargetRegisterInfo is non-null, then it also checks if there
1482	/// is a read of a super-register.
1483	/// This does not count partial redefines of virtual registers as reads:
1484	/// %reg1024:6 = OP.
1485	bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1486	return findRegisterUseOperandIdx(Reg, TRI, isKill: false) != -1;
1487	}
1488
1489	/// Return true if the MachineInstr reads the specified virtual register.
1490	/// Take into account that a partial define is a
1491	/// read-modify-write operation.
1492	bool readsVirtualRegister(Register Reg) const {
1493	return readsWritesVirtualRegister(Reg).first;
1494	}
1495
1496	/// Return a pair of bools (reads, writes) indicating if this instruction
1497	/// reads or writes Reg. This also considers partial defines.
1498	/// If Ops is not null, all operand indices for Reg are added.
1499	LLVM_ABI std::pair<bool, bool>
1500	readsWritesVirtualRegister(Register Reg,
1501	SmallVectorImpl<unsigned> *Ops = nullptr) const;
1502
1503	/// Return true if the MachineInstr kills the specified register.
1504	/// If TargetRegisterInfo is non-null, then it also checks if there is
1505	/// a kill of a super-register.
1506	bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1507	return findRegisterUseOperandIdx(Reg, TRI, isKill: true) != -1;
1508	}
1509
1510	/// Return true if the MachineInstr fully defines the specified register.
1511	/// If TargetRegisterInfo is non-null, then it also checks
1512	/// if there is a def of a super-register.
1513	/// NOTE: It's ignoring subreg indices on virtual registers.
1514	bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1515	return findRegisterDefOperandIdx(Reg, TRI, isDead: false, Overlap: false) != -1;
1516	}
1517
1518	/// Return true if the MachineInstr modifies (fully define or partially
1519	/// define) the specified register.
1520	/// NOTE: It's ignoring subreg indices on virtual registers.
1521	bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1522	return findRegisterDefOperandIdx(Reg, TRI, isDead: false, Overlap: true) != -1;
1523	}
1524
1525	/// Returns true if the register is dead in this machine instruction.
1526	/// If TargetRegisterInfo is non-null, then it also checks
1527	/// if there is a dead def of a super-register.
1528	bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const {
1529	return findRegisterDefOperandIdx(Reg, TRI, isDead: true, Overlap: false) != -1;
1530	}
1531
1532	/// Returns true if the MachineInstr has an implicit-use operand of exactly
1533	/// the given register (not considering sub/super-registers).
1534	LLVM_ABI bool hasRegisterImplicitUseOperand(Register Reg) const;
1535
1536	/// Returns the operand index that is a use of the specific register or -1
1537	/// if it is not found. It further tightens the search criteria to a use
1538	/// that kills the register if isKill is true.
1539	LLVM_ABI int findRegisterUseOperandIdx(Register Reg,
1540	const TargetRegisterInfo *TRI,
1541	bool isKill = false) const;
1542
1543	/// Wrapper for findRegisterUseOperandIdx, it returns
1544	/// a pointer to the MachineOperand rather than an index.
1545	MachineOperand *findRegisterUseOperand(Register Reg,
1546	const TargetRegisterInfo *TRI,
1547	bool isKill = false) {
1548	int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill);
1549	return (Idx == -1) ? nullptr : &getOperand(i: Idx);
1550	}
1551
1552	const MachineOperand *findRegisterUseOperand(Register Reg,
1553	const TargetRegisterInfo *TRI,
1554	bool isKill = false) const {
1555	return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1556	isKill);
1557	}
1558
1559	/// Returns the operand index that is a def of the specified register or
1560	/// -1 if it is not found. If isDead is true, defs that are not dead are
1561	/// skipped. If Overlap is true, then it also looks for defs that merely
1562	/// overlap the specified register. If TargetRegisterInfo is non-null,
1563	/// then it also checks if there is a def of a super-register.
1564	/// This may also return a register mask operand when Overlap is true.
1565	LLVM_ABI int findRegisterDefOperandIdx(Register Reg,
1566	const TargetRegisterInfo *TRI,
1567	bool isDead = false,
1568	bool Overlap = false) const;
1569
1570	/// Wrapper for findRegisterDefOperandIdx, it returns
1571	/// a pointer to the MachineOperand rather than an index.
1572	MachineOperand *findRegisterDefOperand(Register Reg,
1573	const TargetRegisterInfo *TRI,
1574	bool isDead = false,
1575	bool Overlap = false) {
1576	int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
1577	return (Idx == -1) ? nullptr : &getOperand(i: Idx);
1578	}
1579
1580	const MachineOperand *findRegisterDefOperand(Register Reg,
1581	const TargetRegisterInfo *TRI,
1582	bool isDead = false,
1583	bool Overlap = false) const {
1584	return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1585	Reg, TRI, isDead, Overlap);
1586	}
1587
1588	/// Find the index of the first operand in the
1589	/// operand list that is used to represent the predicate. It returns -1 if
1590	/// none is found.
1591	LLVM_ABI int findFirstPredOperandIdx() const;
1592
1593	/// Find the index of the flag word operand that
1594	/// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1595	/// getOperand(OpIdx) does not belong to an inline asm operand group.
1596	///
1597	/// If GroupNo is not NULL, it will receive the number of the operand group
1598	/// containing OpIdx.
1599	LLVM_ABI int findInlineAsmFlagIdx(unsigned OpIdx,
1600	unsigned *GroupNo = nullptr) const;
1601
1602	/// Compute the static register class constraint for operand OpIdx.
1603	/// For normal instructions, this is derived from the MCInstrDesc.
1604	/// For inline assembly it is derived from the flag words.
1605	///
1606	/// Returns NULL if the static register class constraint cannot be
1607	/// determined.
1608	LLVM_ABI const TargetRegisterClass *
1609	getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII,
1610	const TargetRegisterInfo *TRI) const;
1611
1612	/// Applies the constraints (def/use) implied by this MI on \p Reg to
1613	/// the given \p CurRC.
1614	/// If \p ExploreBundle is set and MI is part of a bundle, all the
1615	/// instructions inside the bundle will be taken into account. In other words,
1616	/// this method accumulates all the constraints of the operand of this MI and
1617	/// the related bundle if MI is a bundle or inside a bundle.
1618	///
1619	/// Returns the register class that satisfies both \p CurRC and the
1620	/// constraints set by MI. Returns NULL if such a register class does not
1621	/// exist.
1622	///
1623	/// \pre CurRC must not be NULL.
1624	LLVM_ABI const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1625	Register Reg, const TargetRegisterClass *CurRC,
1626	const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1627	bool ExploreBundle = false) const;
1628
1629	/// Applies the constraints (def/use) implied by the \p OpIdx operand
1630	/// to the given \p CurRC.
1631	///
1632	/// Returns the register class that satisfies both \p CurRC and the
1633	/// constraints set by \p OpIdx MI. Returns NULL if such a register class
1634	/// does not exist.
1635	///
1636	/// \pre CurRC must not be NULL.
1637	/// \pre The operand at \p OpIdx must be a register.
1638	LLVM_ABI const TargetRegisterClass *
1639	getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1640	const TargetInstrInfo *TII,
1641	const TargetRegisterInfo *TRI) const;
1642
1643	/// Add a tie between the register operands at DefIdx and UseIdx.
1644	/// The tie will cause the register allocator to ensure that the two
1645	/// operands are assigned the same physical register.
1646	///
1647	/// Tied operands are managed automatically for explicit operands in the
1648	/// MCInstrDesc. This method is for exceptional cases like inline asm.
1649	LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx);
1650
1651	/// Given the index of a tied register operand, find the
1652	/// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1653	/// index of the tied operand which must exist.
1654	LLVM_ABI unsigned findTiedOperandIdx(unsigned OpIdx) const;
1655
1656	/// Given the index of a register def operand,
1657	/// check if the register def is tied to a source operand, due to either
1658	/// two-address elimination or inline assembly constraints. Returns the
1659	/// first tied use operand index by reference if UseOpIdx is not null.
1660	bool isRegTiedToUseOperand(unsigned DefOpIdx,
1661	unsigned *UseOpIdx = nullptr) const {
1662	const MachineOperand &MO = getOperand(i: DefOpIdx);
1663	if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1664	return false;
1665	if (UseOpIdx)
1666	*UseOpIdx = findTiedOperandIdx(OpIdx: DefOpIdx);
1667	return true;
1668	}
1669
1670	/// Return true if the use operand of the specified index is tied to a def
1671	/// operand. It also returns the def operand index by reference if DefOpIdx
1672	/// is not null.
1673	bool isRegTiedToDefOperand(unsigned UseOpIdx,
1674	unsigned *DefOpIdx = nullptr) const {
1675	const MachineOperand &MO = getOperand(i: UseOpIdx);
1676	if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1677	return false;
1678	if (DefOpIdx)
1679	*DefOpIdx = findTiedOperandIdx(OpIdx: UseOpIdx);
1680	return true;
1681	}
1682
1683	/// Clears kill flags on all operands.
1684	LLVM_ABI void clearKillInfo();
1685
1686	/// Replace all occurrences of FromReg with ToReg:SubIdx,
1687	/// properly composing subreg indices where necessary.
1688	LLVM_ABI void substituteRegister(Register FromReg, Register ToReg,
1689	unsigned SubIdx,
1690	const TargetRegisterInfo &RegInfo);
1691
1692	/// We have determined MI kills a register. Look for the
1693	/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1694	/// add a implicit operand if it's not found. Returns true if the operand
1695	/// exists / is added.
1696	LLVM_ABI bool addRegisterKilled(Register IncomingReg,
1697	const TargetRegisterInfo *RegInfo,
1698	bool AddIfNotFound = false);
1699
1700	/// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1701	/// all aliasing registers.
1702	LLVM_ABI void clearRegisterKills(Register Reg,
1703	const TargetRegisterInfo *RegInfo);
1704
1705	/// We have determined MI defined a register without a use.
1706	/// Look for the operand that defines it and mark it as IsDead. If
1707	/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1708	/// true if the operand exists / is added.
1709	LLVM_ABI bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1710	bool AddIfNotFound = false);
1711
1712	/// Clear all dead flags on operands defining register @p Reg.
1713	LLVM_ABI void clearRegisterDeads(Register Reg);
1714
1715	/// Mark all subregister defs of register @p Reg with the undef flag.
1716	/// This function is used when we determined to have a subregister def in an
1717	/// otherwise undefined super register.
1718	LLVM_ABI void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1719
1720	/// We have determined MI defines a register. Make sure there is an operand
1721	/// defining Reg.
1722	LLVM_ABI void addRegisterDefined(Register Reg,
1723	const TargetRegisterInfo *RegInfo = nullptr);
1724
1725	/// Mark every physreg used by this instruction as
1726	/// dead except those in the UsedRegs list.
1727	///
1728	/// On instructions with register mask operands, also add implicit-def
1729	/// operands for all registers in UsedRegs.
1730	LLVM_ABI void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1731	const TargetRegisterInfo &TRI);
1732
1733	/// Return true if it is safe to move this instruction. If
1734	/// SawStore is set to true, it means that there is a store (or call) between
1735	/// the instruction's location and its intended destination.
1736	LLVM_ABI bool isSafeToMove(bool &SawStore) const;
1737
1738	/// Return true if this instruction would be trivially dead if all of its
1739	/// defined registers were dead.
1740	LLVM_ABI bool wouldBeTriviallyDead() const;
1741
1742	/// Check whether an MI is dead. If \p LivePhysRegs is provided, it is assumed
1743	/// to be at the position of MI and will be used to check the Liveness of
1744	/// physical register defs. If \p LivePhysRegs is not provided, this will
1745	/// pessimistically assume any PhysReg def is live.
1746	/// For trivially dead instructions (i.e. those without hard to model effects
1747	/// / wouldBeTriviallyDead), this checks deadness by analyzing defs of the
1748	/// MachineInstr. If the instruction wouldBeTriviallyDead, and all the defs
1749	/// either have dead flags or have no uses, then the instruction is said to be
1750	/// dead.
1751	LLVM_ABI bool isDead(const MachineRegisterInfo &MRI,
1752	LiveRegUnits *LivePhysRegs = nullptr) const;
1753
1754	/// Returns true if this instruction's memory access aliases the memory
1755	/// access of Other.
1756	//
1757	/// Assumes any physical registers used to compute addresses
1758	/// have the same value for both instructions. Returns false if neither
1759	/// instruction writes to memory.
1760	///
1761	/// @param AA Optional alias analysis, used to compare memory operands.
1762	/// @param Other MachineInstr to check aliasing against.
1763	/// @param UseTBAA Whether to pass TBAA information to alias analysis.
1764	LLVM_ABI bool mayAlias(BatchAAResults *AA, const MachineInstr &Other,
1765	bool UseTBAA) const;
1766	LLVM_ABI bool mayAlias(AAResults *AA, const MachineInstr &Other,
1767	bool UseTBAA) const;
1768
1769	/// Return true if this instruction may have an ordered
1770	/// or volatile memory reference, or if the information describing the memory
1771	/// reference is not available. Return false if it is known to have no
1772	/// ordered or volatile memory references.
1773	LLVM_ABI bool hasOrderedMemoryRef() const;
1774
1775	/// Return true if this load instruction never traps and points to a memory
1776	/// location whose value doesn't change during the execution of this function.
1777	///
1778	/// Examples include loading a value from the constant pool or from the
1779	/// argument area of a function (if it does not change). If the instruction
1780	/// does multiple loads, this returns true only if all of the loads are
1781	/// dereferenceable and invariant.
1782	LLVM_ABI bool isDereferenceableInvariantLoad() const;
1783
1784	/// If the specified instruction is a PHI that always merges together the
1785	/// same virtual register, return the register, otherwise return Register().
1786	LLVM_ABI Register isConstantValuePHI() const;
1787
1788	/// Return true if this instruction has side effects that are not modeled
1789	/// by mayLoad / mayStore, etc.
1790	/// For all instructions, the property is encoded in MCInstrDesc::Flags
1791	/// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1792	/// INLINEASM instruction, in which case the side effect property is encoded
1793	/// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1794	///
1795	LLVM_ABI bool hasUnmodeledSideEffects() const;
1796
1797	/// Returns true if it is illegal to fold a load across this instruction.
1798	LLVM_ABI bool isLoadFoldBarrier() const;
1799
1800	/// Return true if all the defs of this instruction are dead.
1801	LLVM_ABI bool allDefsAreDead() const;
1802
1803	/// Return true if all the implicit defs of this instruction are dead.
1804	LLVM_ABI bool allImplicitDefsAreDead() const;
1805
1806	/// Return a valid size if the instruction is a spill instruction.
1807	LLVM_ABI std::optional<LocationSize>
1808	getSpillSize(const TargetInstrInfo *TII) const;
1809
1810	/// Return a valid size if the instruction is a folded spill instruction.
1811	LLVM_ABI std::optional<LocationSize>
1812	getFoldedSpillSize(const TargetInstrInfo *TII) const;
1813
1814	/// Return a valid size if the instruction is a restore instruction.
1815	LLVM_ABI std::optional<LocationSize>
1816	getRestoreSize(const TargetInstrInfo *TII) const;
1817
1818	/// Return a valid size if the instruction is a folded restore instruction.
1819	LLVM_ABI std::optional<LocationSize>
1820	getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1821
1822	/// Copy implicit register operands from specified
1823	/// instruction to this instruction.
1824	LLVM_ABI void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1825
1826	/// Debugging support
1827	/// @{
1828	/// Determine the generic type to be printed (if needed) on uses and defs.
1829	LLVM_ABI LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1830	const MachineRegisterInfo &MRI) const;
1831
1832	/// Return true when an instruction has tied register that can't be determined
1833	/// by the instruction's descriptor. This is useful for MIR printing, to
1834	/// determine whether we need to print the ties or not.
1835	LLVM_ABI bool hasComplexRegisterTies() const;
1836
1837	/// Print this MI to \p OS.
1838	/// Don't print information that can be inferred from other instructions if
1839	/// \p IsStandalone is false. It is usually true when only a fragment of the
1840	/// function is printed.
1841	/// Only print the defs and the opcode if \p SkipOpers is true.
1842	/// Otherwise, also print operands if \p SkipDebugLoc is true.
1843	/// Otherwise, also print the debug loc, with a terminating newline.
1844	/// \p TII is used to print the opcode name. If it's not present, but the
1845	/// MI is in a function, the opcode will be printed using the function's TII.
1846	LLVM_ABI void print(raw_ostream &OS, bool IsStandalone = true,
1847	bool SkipOpers = false, bool SkipDebugLoc = false,
1848	bool AddNewLine = true,
1849	const TargetInstrInfo *TII = nullptr) const;
1850	LLVM_ABI void print(raw_ostream &OS, ModuleSlotTracker &MST,
1851	bool IsStandalone = true, bool SkipOpers = false,
1852	bool SkipDebugLoc = false, bool AddNewLine = true,
1853	const TargetInstrInfo *TII = nullptr) const;
1854	LLVM_ABI void dump() const;
1855	/// Print on dbgs() the current instruction and the instructions defining its
1856	/// operands and so on until we reach \p MaxDepth.
1857	LLVM_ABI void dumpr(const MachineRegisterInfo &MRI,
1858	unsigned MaxDepth = UINT_MAX) const;
1859	/// @}
1860
1861	//===--------------------------------------------------------------------===//
1862	// Accessors used to build up machine instructions.
1863
1864	/// Add the specified operand to the instruction. If it is an implicit
1865	/// operand, it is added to the end of the operand list. If it is an
1866	/// explicit operand it is added at the end of the explicit operand list
1867	/// (before the first implicit operand).
1868	///
1869	/// MF must be the machine function that was used to allocate this
1870	/// instruction.
1871	///
1872	/// MachineInstrBuilder provides a more convenient interface for creating
1873	/// instructions and adding operands.
1874	LLVM_ABI void addOperand(MachineFunction &MF, const MachineOperand &Op);
1875
1876	/// Add an operand without providing an MF reference. This only works for
1877	/// instructions that are inserted in a basic block.
1878	///
1879	/// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1880	/// preferred.
1881	LLVM_ABI void addOperand(const MachineOperand &Op);
1882
1883	/// Inserts Ops BEFORE It. Can untie/retie tied operands.
1884	LLVM_ABI void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1885
1886	/// Replace the instruction descriptor (thus opcode) of
1887	/// the current instruction with a new one.
1888	LLVM_ABI void setDesc(const MCInstrDesc &TID);
1889
1890	/// Replace current source information with new such.
1891	/// Avoid using this, the constructor argument is preferable.
1892	void setDebugLoc(DebugLoc DL) {
1893	DbgLoc = std::move(DL);
1894	assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1895	}
1896
1897	/// Erase an operand from an instruction, leaving it with one
1898	/// fewer operand than it started with.
1899	LLVM_ABI void removeOperand(unsigned OpNo);
1900
1901	/// Clear this MachineInstr's memory reference descriptor list. This resets
1902	/// the memrefs to their most conservative state. This should be used only
1903	/// as a last resort since it greatly pessimizes our knowledge of the memory
1904	/// access performed by the instruction.
1905	LLVM_ABI void dropMemRefs(MachineFunction &MF);
1906
1907	/// Assign this MachineInstr's memory reference descriptor list.
1908	///
1909	/// Unlike other methods, this *will* allocate them into a new array
1910	/// associated with the provided `MachineFunction`.
1911	LLVM_ABI void setMemRefs(MachineFunction &MF,
1912	ArrayRef<MachineMemOperand *> MemRefs);
1913
1914	/// Add a MachineMemOperand to the machine instruction.
1915	/// This function should be used only occasionally. The setMemRefs function
1916	/// is the primary method for setting up a MachineInstr's MemRefs list.
1917	LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1918
1919	/// Clone another MachineInstr's memory reference descriptor list and replace
1920	/// ours with it.
1921	///
1922	/// Note that `*this` may be the incoming MI!
1923	///
1924	/// Prefer this API whenever possible as it can avoid allocations in common
1925	/// cases.
1926	LLVM_ABI void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1927
1928	/// Clone the merge of multiple MachineInstrs' memory reference descriptors
1929	/// list and replace ours with it.
1930	///
1931	/// Note that `*this` may be one of the incoming MIs!
1932	///
1933	/// Prefer this API whenever possible as it can avoid allocations in common
1934	/// cases.
1935	LLVM_ABI void cloneMergedMemRefs(MachineFunction &MF,
1936	ArrayRef<const MachineInstr *> MIs);
1937
1938	/// Set a symbol that will be emitted just prior to the instruction itself.
1939	///
1940	/// Setting this to a null pointer will remove any such symbol.
1941	///
1942	/// FIXME: This is not fully implemented yet.
1943	LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1944
1945	/// Set a symbol that will be emitted just after the instruction itself.
1946	///
1947	/// Setting this to a null pointer will remove any such symbol.
1948	///
1949	/// FIXME: This is not fully implemented yet.
1950	LLVM_ABI void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1951
1952	/// Clone another MachineInstr's pre- and post- instruction symbols and
1953	/// replace ours with it.
1954	LLVM_ABI void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1955
1956	/// Set a marker on instructions that denotes where we should create and emit
1957	/// heap alloc site labels. This waits until after instruction selection and
1958	/// optimizations to create the label, so it should still work if the
1959	/// instruction is removed or duplicated.
1960	LLVM_ABI void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1961
1962	// Set metadata on instructions that say which sections to emit instruction
1963	// addresses into.
1964	LLVM_ABI void setPCSections(MachineFunction &MF, MDNode *MD);
1965
1966	LLVM_ABI void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs);
1967
1968	/// Set the CFI type for the instruction.
1969	LLVM_ABI void setCFIType(MachineFunction &MF, uint32_t Type);
1970
1971	/// Return the MIFlags which represent both MachineInstrs. This
1972	/// should be used when merging two MachineInstrs into one. This routine does
1973	/// not modify the MIFlags of this MachineInstr.
1974	LLVM_ABI uint32_t mergeFlagsWith(const MachineInstr &Other) const;
1975
1976	LLVM_ABI static uint32_t copyFlagsFromInstruction(const Instruction &I);
1977
1978	/// Copy all flags to MachineInst MIFlags
1979	LLVM_ABI void copyIRFlags(const Instruction &I);
1980
1981	/// Break any tie involving OpIdx.
1982	void untieRegOperand(unsigned OpIdx) {
1983	MachineOperand &MO = getOperand(i: OpIdx);
1984	if (MO.isReg() && MO.isTied()) {
1985	getOperand(i: findTiedOperandIdx(OpIdx)).TiedTo = 0;
1986	MO.TiedTo = 0;
1987	}
1988	}
1989
1990	/// Add all implicit def and use operands to this instruction.
1991	LLVM_ABI void addImplicitDefUseOperands(MachineFunction &MF);
1992
1993	/// Scan instructions immediately following MI and collect any matching
1994	/// DBG_VALUEs.
1995	LLVM_ABI void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1996
1997	/// Find all DBG_VALUEs that point to the register def in this instruction
1998	/// and point them to \p Reg instead.
1999	LLVM_ABI void changeDebugValuesDefReg(Register Reg);
2000
2001	/// Sets all register debug operands in this debug value instruction to be
2002	/// undef.
2003	void setDebugValueUndef() {
2004	assert(isDebugValue() && "Must be a debug value instruction.");
2005	for (MachineOperand &MO : debug_operands()) {
2006	if (MO.isReg()) {
2007	MO.setReg(0);
2008	MO.setSubReg(0);
2009	}
2010	}
2011	}
2012
2013	std::tuple<Register, Register> getFirst2Regs() const {
2014	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg());
2015	}
2016
2017	std::tuple<Register, Register, Register> getFirst3Regs() const {
2018	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
2019	getOperand(i: 2).getReg());
2020	}
2021
2022	std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
2023	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
2024	getOperand(i: 2).getReg(), getOperand(i: 3).getReg());
2025	}
2026
2027	std::tuple<Register, Register, Register, Register, Register>
2028	getFirst5Regs() const {
2029	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
2030	getOperand(i: 2).getReg(), getOperand(i: 3).getReg(),
2031	getOperand(i: 4).getReg());
2032	}
2033
2034	LLVM_ABI std::tuple<LLT, LLT> getFirst2LLTs() const;
2035	LLVM_ABI std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
2036	LLVM_ABI std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
2037	LLVM_ABI std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
2038
2039	LLVM_ABI std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
2040	LLVM_ABI std::tuple<Register, LLT, Register, LLT, Register, LLT>
2041	getFirst3RegLLTs() const;
2042	LLVM_ABI
2043	std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2044	getFirst4RegLLTs() const;
2045	LLVM_ABI std::tuple<Register, LLT, Register, LLT, Register, LLT, Register,
2046	LLT, Register, LLT>
2047	getFirst5RegLLTs() const;
2048
2049	private:
2050	/// If this instruction is embedded into a MachineFunction, return the
2051	/// MachineRegisterInfo object for the current function, otherwise
2052	/// return null.
2053	MachineRegisterInfo *getRegInfo();
2054	const MachineRegisterInfo *getRegInfo() const;
2055
2056	/// Unlink all of the register operands in this instruction from their
2057	/// respective use lists. This requires that the operands already be on their
2058	/// use lists.
2059	void removeRegOperandsFromUseLists(MachineRegisterInfo&);
2060
2061	/// Add all of the register operands in this instruction from their
2062	/// respective use lists. This requires that the operands not be on their
2063	/// use lists yet.
2064	void addRegOperandsToUseLists(MachineRegisterInfo&);
2065
2066	/// Slow path for hasProperty when we're dealing with a bundle.
2067	LLVM_ABI bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2068
2069	/// Implements the logic of getRegClassConstraintEffectForVReg for the
2070	/// this MI and the given operand index \p OpIdx.
2071	/// If the related operand does not constrained Reg, this returns CurRC.
2072	const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2073	unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2074	const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2075
2076	/// Stores extra instruction information inline or allocates as ExtraInfo
2077	/// based on the number of pointers.
2078	void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2079	MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2080	MDNode *HeapAllocMarker, MDNode *PCSections,
2081	uint32_t CFIType, MDNode *MMRAs);
2082	};
2083
2084	/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2085	/// instruction rather than by pointer value.
2086	/// The hashing and equality testing functions ignore definitions so this is
2087	/// useful for CSE, etc.
2088	struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
2089	static inline MachineInstr *getEmptyKey() {
2090	return nullptr;
2091	}
2092
2093	static inline MachineInstr *getTombstoneKey() {
2094	return reinterpret_cast<MachineInstr*>(-1);
2095	}
2096
2097	LLVM_ABI static unsigned getHashValue(const MachineInstr *const &MI);
2098
2099	static bool isEqual(const MachineInstr* const &LHS,
2100	const MachineInstr* const &RHS) {
2101	if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2102	LHS == getEmptyKey() || LHS == getTombstoneKey())
2103	return LHS == RHS;
2104	return LHS->isIdenticalTo(Other: *RHS, Check: MachineInstr::IgnoreVRegDefs);
2105	}
2106	};
2107
2108	//===----------------------------------------------------------------------===//
2109	// Debugging Support
2110
2111	inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
2112	MI.print(OS);
2113	return OS;
2114	}
2115
2116	} // end namespace llvm
2117
2118	#endif // LLVM_CODEGEN_MACHINEINSTR_H
2119