1//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/IndexedMap.h"
19#include "llvm/ADT/PointerUnion.h"
20#include "llvm/ADT/SmallPtrSet.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/StringSet.h"
23#include "llvm/ADT/iterator_range.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBundle.h"
27#include "llvm/CodeGen/MachineOperand.h"
28#include "llvm/CodeGen/RegisterBank.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/CodeGen/TargetSubtargetInfo.h"
31#include "llvm/MC/LaneBitmask.h"
32#include <cassert>
33#include <cstddef>
34#include <cstdint>
35#include <iterator>
36#include <memory>
37#include <utility>
38#include <vector>
39
40namespace llvm {
41
42class PSetIterator;
43
44/// Convenient type to represent either a register class or a register bank.
45using RegClassOrRegBank =
46 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
47
48/// MachineRegisterInfo - Keep track of information for virtual and physical
49/// registers, including vreg register classes, use/def chains for registers,
50/// etc.
51class MachineRegisterInfo {
52public:
53 class Delegate {
54 virtual void anchor();
55
56 public:
57 virtual ~Delegate() = default;
58
59 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
60 virtual void MRI_NoteCloneVirtualRegister(Register NewReg,
61 Register SrcReg) {
62 MRI_NoteNewVirtualRegister(Reg: NewReg);
63 }
64 };
65
66private:
67 MachineFunction *MF;
68 SmallPtrSet<Delegate *, 1> TheDelegates;
69
70 /// True if subregister liveness is tracked.
71 const bool TracksSubRegLiveness;
72
73 /// VRegInfo - Information we keep for each virtual register.
74 ///
75 /// Each element in this list contains the register class of the vreg and the
76 /// start of the use/def list for the register.
77 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
78 VirtReg2IndexFunctor>
79 VRegInfo;
80
81 /// Map for recovering vreg name from vreg number.
82 /// This map is used by the MIR Printer.
83 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
84
85 /// StringSet that is used to unique vreg names.
86 StringSet<> VRegNames;
87
88 /// The flag is true upon \p UpdatedCSRs initialization
89 /// and false otherwise.
90 bool IsUpdatedCSRsInitialized = false;
91
92 /// Contains the updated callee saved register list.
93 /// As opposed to the static list defined in register info,
94 /// all registers that were disabled are removed from the list.
95 SmallVector<MCPhysReg, 16> UpdatedCSRs;
96
97 /// RegAllocHints - This vector records register allocation hints for
98 /// virtual registers. For each virtual register, it keeps a pair of hint
99 /// type and hints vector making up the allocation hints. Only the first
100 /// hint may be target specific, and in that case this is reflected by the
101 /// first member of the pair being non-zero. If the hinted register is
102 /// virtual, it means the allocator should prefer the physical register
103 /// allocated to it if any.
104 IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>,
105 VirtReg2IndexFunctor>
106 RegAllocHints;
107
108 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
109 /// physical registers.
110 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
111
112 /// getRegUseDefListHead - Return the head pointer for the register use/def
113 /// list for the specified virtual or physical register.
114 MachineOperand *&getRegUseDefListHead(Register RegNo) {
115 if (RegNo.isVirtual())
116 return VRegInfo[RegNo.id()].second;
117 return PhysRegUseDefLists[RegNo.id()];
118 }
119
120 MachineOperand *getRegUseDefListHead(Register RegNo) const {
121 if (RegNo.isVirtual())
122 return VRegInfo[RegNo.id()].second;
123 return PhysRegUseDefLists[RegNo.id()];
124 }
125
126 /// Get the next element in the use-def chain.
127 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
128 assert(MO && MO->isReg() && "This is not a register operand!");
129 return MO->Contents.Reg.Next;
130 }
131
132 /// UsedPhysRegMask - Additional used physregs including aliases.
133 /// This bit vector represents all the registers clobbered by function calls.
134 BitVector UsedPhysRegMask;
135
136 /// ReservedRegs - This is a bit vector of reserved registers. The target
137 /// may change its mind about which registers should be reserved. This
138 /// vector is the frozen set of reserved registers when register allocation
139 /// started.
140 BitVector ReservedRegs;
141
142 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
143 /// Map generic virtual registers to their low-level type.
144 VRegToTypeMap VRegToType;
145
146 /// Keep track of the physical registers that are live in to the function.
147 /// Live in values are typically arguments in registers. LiveIn values are
148 /// allowed to have virtual registers associated with them, stored in the
149 /// second element.
150 std::vector<std::pair<MCRegister, Register>> LiveIns;
151
152public:
153 explicit MachineRegisterInfo(MachineFunction *MF);
154 MachineRegisterInfo(const MachineRegisterInfo &) = delete;
155 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
156
157 const TargetRegisterInfo *getTargetRegisterInfo() const {
158 return MF->getSubtarget().getRegisterInfo();
159 }
160
161 void resetDelegate(Delegate *delegate) {
162 // Ensure another delegate does not take over unless the current
163 // delegate first unattaches itself.
164 assert(TheDelegates.count(delegate) &&
165 "Only an existing delegate can perform reset!");
166 TheDelegates.erase(Ptr: delegate);
167 }
168
169 void addDelegate(Delegate *delegate) {
170 assert(delegate && !TheDelegates.count(delegate) &&
171 "Attempted to add null delegate, or to change it without "
172 "first resetting it!");
173
174 TheDelegates.insert(Ptr: delegate);
175 }
176
177 void noteNewVirtualRegister(Register Reg) {
178 for (auto *TheDelegate : TheDelegates)
179 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
180 }
181
182 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) {
183 for (auto *TheDelegate : TheDelegates)
184 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
185 }
186
187 //===--------------------------------------------------------------------===//
188 // Function State
189 //===--------------------------------------------------------------------===//
190
191 // isSSA - Returns true when the machine function is in SSA form. Early
192 // passes require the machine function to be in SSA form where every virtual
193 // register has a single defining instruction.
194 //
195 // The TwoAddressInstructionPass and PHIElimination passes take the machine
196 // function out of SSA form when they introduce multiple defs per virtual
197 // register.
198 bool isSSA() const {
199 return MF->getProperties().hasProperty(
200 P: MachineFunctionProperties::Property::IsSSA);
201 }
202
203 // leaveSSA - Indicates that the machine function is no longer in SSA form.
204 void leaveSSA() {
205 MF->getProperties().reset(P: MachineFunctionProperties::Property::IsSSA);
206 }
207
208 /// tracksLiveness - Returns true when tracking register liveness accurately.
209 /// (see MachineFUnctionProperties::Property description for details)
210 bool tracksLiveness() const {
211 return MF->getProperties().hasProperty(
212 P: MachineFunctionProperties::Property::TracksLiveness);
213 }
214
215 /// invalidateLiveness - Indicates that register liveness is no longer being
216 /// tracked accurately.
217 ///
218 /// This should be called by late passes that invalidate the liveness
219 /// information.
220 void invalidateLiveness() {
221 MF->getProperties().reset(
222 P: MachineFunctionProperties::Property::TracksLiveness);
223 }
224
225 /// Returns true if liveness for register class @p RC should be tracked at
226 /// the subregister level.
227 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
228 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
229 }
230 bool shouldTrackSubRegLiveness(Register VReg) const {
231 assert(VReg.isVirtual() && "Must pass a VReg");
232 const TargetRegisterClass *RC = getRegClassOrNull(Reg: VReg);
233 return LLVM_LIKELY(RC) ? shouldTrackSubRegLiveness(RC: *RC) : false;
234 }
235 bool subRegLivenessEnabled() const {
236 return TracksSubRegLiveness;
237 }
238
239 //===--------------------------------------------------------------------===//
240 // Register Info
241 //===--------------------------------------------------------------------===//
242
243 /// Returns true if the updated CSR list was initialized and false otherwise.
244 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
245
246 /// Returns true if a register can be used as an argument to a function.
247 bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
248
249 /// Returns true if a register is a fixed register.
250 bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
251
252 /// Returns true if a register is a general purpose register.
253 bool isGeneralPurposeRegister(const MachineFunction &MF,
254 MCRegister Reg) const;
255
256 /// Disables the register from the list of CSRs.
257 /// I.e. the register will not appear as part of the CSR mask.
258 /// \see UpdatedCalleeSavedRegs.
259 void disableCalleeSavedRegister(MCRegister Reg);
260
261 /// Returns list of callee saved registers.
262 /// The function returns the updated CSR list (after taking into account
263 /// registers that are disabled from the CSR list).
264 const MCPhysReg *getCalleeSavedRegs() const;
265
266 /// Sets the updated Callee Saved Registers list.
267 /// Notice that it will override ant previously disabled/saved CSRs.
268 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
269
270 // Strictly for use by MachineInstr.cpp.
271 void addRegOperandToUseList(MachineOperand *MO);
272
273 // Strictly for use by MachineInstr.cpp.
274 void removeRegOperandFromUseList(MachineOperand *MO);
275
276 // Strictly for use by MachineInstr.cpp.
277 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
278
279 /// Verify the sanity of the use list for Reg.
280 void verifyUseList(Register Reg) const;
281
282 /// Verify the use list of all registers.
283 void verifyUseLists() const;
284
285 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
286 /// and uses of a register within the MachineFunction that corresponds to this
287 /// MachineRegisterInfo object.
288 template<bool Uses, bool Defs, bool SkipDebug,
289 bool ByOperand, bool ByInstr, bool ByBundle>
290 class defusechain_iterator;
291 template<bool Uses, bool Defs, bool SkipDebug,
292 bool ByOperand, bool ByInstr, bool ByBundle>
293 class defusechain_instr_iterator;
294
295 // Make it a friend so it can access getNextOperandForReg().
296 template<bool, bool, bool, bool, bool, bool>
297 friend class defusechain_iterator;
298 template<bool, bool, bool, bool, bool, bool>
299 friend class defusechain_instr_iterator;
300
301 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
302 /// register.
303 using reg_iterator =
304 defusechain_iterator<true, true, false, true, false, false>;
305 reg_iterator reg_begin(Register RegNo) const {
306 return reg_iterator(getRegUseDefListHead(RegNo));
307 }
308 static reg_iterator reg_end() { return reg_iterator(nullptr); }
309
310 inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
311 return make_range(x: reg_begin(RegNo: Reg), y: reg_end());
312 }
313
314 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
315 /// of the specified register, stepping by MachineInstr.
316 using reg_instr_iterator =
317 defusechain_instr_iterator<true, true, false, false, true, false>;
318 reg_instr_iterator reg_instr_begin(Register RegNo) const {
319 return reg_instr_iterator(getRegUseDefListHead(RegNo));
320 }
321 static reg_instr_iterator reg_instr_end() {
322 return reg_instr_iterator(nullptr);
323 }
324
325 inline iterator_range<reg_instr_iterator>
326 reg_instructions(Register Reg) const {
327 return make_range(x: reg_instr_begin(RegNo: Reg), y: reg_instr_end());
328 }
329
330 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
331 /// of the specified register, stepping by bundle.
332 using reg_bundle_iterator =
333 defusechain_instr_iterator<true, true, false, false, false, true>;
334 reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
335 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
336 }
337 static reg_bundle_iterator reg_bundle_end() {
338 return reg_bundle_iterator(nullptr);
339 }
340
341 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
342 return make_range(x: reg_bundle_begin(RegNo: Reg), y: reg_bundle_end());
343 }
344
345 /// reg_empty - Return true if there are no instructions using or defining the
346 /// specified register (it may be live-in).
347 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
348
349 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
350 /// of the specified register, skipping those marked as Debug.
351 using reg_nodbg_iterator =
352 defusechain_iterator<true, true, true, true, false, false>;
353 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const {
354 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
355 }
356 static reg_nodbg_iterator reg_nodbg_end() {
357 return reg_nodbg_iterator(nullptr);
358 }
359
360 inline iterator_range<reg_nodbg_iterator>
361 reg_nodbg_operands(Register Reg) const {
362 return make_range(x: reg_nodbg_begin(RegNo: Reg), y: reg_nodbg_end());
363 }
364
365 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
366 /// all defs and uses of the specified register, stepping by MachineInstr,
367 /// skipping those marked as Debug.
368 using reg_instr_nodbg_iterator =
369 defusechain_instr_iterator<true, true, true, false, true, false>;
370 reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
371 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
372 }
373 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
374 return reg_instr_nodbg_iterator(nullptr);
375 }
376
377 inline iterator_range<reg_instr_nodbg_iterator>
378 reg_nodbg_instructions(Register Reg) const {
379 return make_range(x: reg_instr_nodbg_begin(RegNo: Reg), y: reg_instr_nodbg_end());
380 }
381
382 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
383 /// all defs and uses of the specified register, stepping by bundle,
384 /// skipping those marked as Debug.
385 using reg_bundle_nodbg_iterator =
386 defusechain_instr_iterator<true, true, true, false, false, true>;
387 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
388 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
389 }
390 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
391 return reg_bundle_nodbg_iterator(nullptr);
392 }
393
394 inline iterator_range<reg_bundle_nodbg_iterator>
395 reg_nodbg_bundles(Register Reg) const {
396 return make_range(x: reg_bundle_nodbg_begin(RegNo: Reg), y: reg_bundle_nodbg_end());
397 }
398
399 /// reg_nodbg_empty - Return true if the only instructions using or defining
400 /// Reg are Debug instructions.
401 bool reg_nodbg_empty(Register RegNo) const {
402 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
403 }
404
405 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
406 using def_iterator =
407 defusechain_iterator<false, true, false, true, false, false>;
408 def_iterator def_begin(Register RegNo) const {
409 return def_iterator(getRegUseDefListHead(RegNo));
410 }
411 static def_iterator def_end() { return def_iterator(nullptr); }
412
413 inline iterator_range<def_iterator> def_operands(Register Reg) const {
414 return make_range(x: def_begin(RegNo: Reg), y: def_end());
415 }
416
417 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
418 /// specified register, stepping by MachineInst.
419 using def_instr_iterator =
420 defusechain_instr_iterator<false, true, false, false, true, false>;
421 def_instr_iterator def_instr_begin(Register RegNo) const {
422 return def_instr_iterator(getRegUseDefListHead(RegNo));
423 }
424 static def_instr_iterator def_instr_end() {
425 return def_instr_iterator(nullptr);
426 }
427
428 inline iterator_range<def_instr_iterator>
429 def_instructions(Register Reg) const {
430 return make_range(x: def_instr_begin(RegNo: Reg), y: def_instr_end());
431 }
432
433 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
434 /// specified register, stepping by bundle.
435 using def_bundle_iterator =
436 defusechain_instr_iterator<false, true, false, false, false, true>;
437 def_bundle_iterator def_bundle_begin(Register RegNo) const {
438 return def_bundle_iterator(getRegUseDefListHead(RegNo));
439 }
440 static def_bundle_iterator def_bundle_end() {
441 return def_bundle_iterator(nullptr);
442 }
443
444 inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
445 return make_range(x: def_bundle_begin(RegNo: Reg), y: def_bundle_end());
446 }
447
448 /// def_empty - Return true if there are no instructions defining the
449 /// specified register (it may be live-in).
450 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
451
452 StringRef getVRegName(Register Reg) const {
453 return VReg2Name.inBounds(n: Reg) ? StringRef(VReg2Name[Reg]) : "";
454 }
455
456 void insertVRegByName(StringRef Name, Register Reg) {
457 assert((Name.empty() || !VRegNames.contains(Name)) &&
458 "Named VRegs Must be Unique.");
459 if (!Name.empty()) {
460 VRegNames.insert(key: Name);
461 VReg2Name.grow(n: Reg);
462 VReg2Name[Reg] = Name.str();
463 }
464 }
465
466 /// Return true if there is exactly one operand defining the specified
467 /// register.
468 bool hasOneDef(Register RegNo) const {
469 return hasSingleElement(C: def_operands(Reg: RegNo));
470 }
471
472 /// Returns the defining operand if there is exactly one operand defining the
473 /// specified register, otherwise nullptr.
474 MachineOperand *getOneDef(Register Reg) const {
475 def_iterator DI = def_begin(RegNo: Reg);
476 if (DI == def_end()) // No defs.
477 return nullptr;
478
479 def_iterator OneDef = DI;
480 if (++DI == def_end())
481 return &*OneDef;
482 return nullptr; // Multiple defs.
483 }
484
485 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
486 using use_iterator =
487 defusechain_iterator<true, false, false, true, false, false>;
488 use_iterator use_begin(Register RegNo) const {
489 return use_iterator(getRegUseDefListHead(RegNo));
490 }
491 static use_iterator use_end() { return use_iterator(nullptr); }
492
493 inline iterator_range<use_iterator> use_operands(Register Reg) const {
494 return make_range(x: use_begin(RegNo: Reg), y: use_end());
495 }
496
497 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
498 /// specified register, stepping by MachineInstr.
499 using use_instr_iterator =
500 defusechain_instr_iterator<true, false, false, false, true, false>;
501 use_instr_iterator use_instr_begin(Register RegNo) const {
502 return use_instr_iterator(getRegUseDefListHead(RegNo));
503 }
504 static use_instr_iterator use_instr_end() {
505 return use_instr_iterator(nullptr);
506 }
507
508 inline iterator_range<use_instr_iterator>
509 use_instructions(Register Reg) const {
510 return make_range(x: use_instr_begin(RegNo: Reg), y: use_instr_end());
511 }
512
513 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
514 /// specified register, stepping by bundle.
515 using use_bundle_iterator =
516 defusechain_instr_iterator<true, false, false, false, false, true>;
517 use_bundle_iterator use_bundle_begin(Register RegNo) const {
518 return use_bundle_iterator(getRegUseDefListHead(RegNo));
519 }
520 static use_bundle_iterator use_bundle_end() {
521 return use_bundle_iterator(nullptr);
522 }
523
524 inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
525 return make_range(x: use_bundle_begin(RegNo: Reg), y: use_bundle_end());
526 }
527
528 /// use_empty - Return true if there are no instructions using the specified
529 /// register.
530 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
531
532 /// hasOneUse - Return true if there is exactly one instruction using the
533 /// specified register.
534 bool hasOneUse(Register RegNo) const {
535 return hasSingleElement(C: use_operands(Reg: RegNo));
536 }
537
538 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
539 /// specified register, skipping those marked as Debug.
540 using use_nodbg_iterator =
541 defusechain_iterator<true, false, true, true, false, false>;
542 use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
543 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
544 }
545 static use_nodbg_iterator use_nodbg_end() {
546 return use_nodbg_iterator(nullptr);
547 }
548
549 inline iterator_range<use_nodbg_iterator>
550 use_nodbg_operands(Register Reg) const {
551 return make_range(x: use_nodbg_begin(RegNo: Reg), y: use_nodbg_end());
552 }
553
554 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
555 /// all uses of the specified register, stepping by MachineInstr, skipping
556 /// those marked as Debug.
557 using use_instr_nodbg_iterator =
558 defusechain_instr_iterator<true, false, true, false, true, false>;
559 use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
560 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
561 }
562 static use_instr_nodbg_iterator use_instr_nodbg_end() {
563 return use_instr_nodbg_iterator(nullptr);
564 }
565
566 inline iterator_range<use_instr_nodbg_iterator>
567 use_nodbg_instructions(Register Reg) const {
568 return make_range(x: use_instr_nodbg_begin(RegNo: Reg), y: use_instr_nodbg_end());
569 }
570
571 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
572 /// all uses of the specified register, stepping by bundle, skipping
573 /// those marked as Debug.
574 using use_bundle_nodbg_iterator =
575 defusechain_instr_iterator<true, false, true, false, false, true>;
576 use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
577 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
578 }
579 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
580 return use_bundle_nodbg_iterator(nullptr);
581 }
582
583 inline iterator_range<use_bundle_nodbg_iterator>
584 use_nodbg_bundles(Register Reg) const {
585 return make_range(x: use_bundle_nodbg_begin(RegNo: Reg), y: use_bundle_nodbg_end());
586 }
587
588 /// use_nodbg_empty - Return true if there are no non-Debug instructions
589 /// using the specified register.
590 bool use_nodbg_empty(Register RegNo) const {
591 return use_nodbg_begin(RegNo) == use_nodbg_end();
592 }
593
594 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
595 /// use of the specified register.
596 bool hasOneNonDBGUse(Register RegNo) const;
597
598 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
599 /// instruction using the specified register. Said instruction may have
600 /// multiple uses.
601 bool hasOneNonDBGUser(Register RegNo) const;
602
603
604 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
605 /// non-debug user instructions.
606 bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
607
608 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
609 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
610 /// except that it also changes any definitions of the register as well.
611 ///
612 /// Note that it is usually necessary to first constrain ToReg's register
613 /// class and register bank to match the FromReg constraints using one of the
614 /// methods:
615 ///
616 /// constrainRegClass(ToReg, getRegClass(FromReg))
617 /// constrainRegAttrs(ToReg, FromReg)
618 /// RegisterBankInfo::constrainGenericRegister(ToReg,
619 /// *MRI.getRegClass(FromReg), MRI)
620 ///
621 /// These functions will return a falsy result if the virtual registers have
622 /// incompatible constraints.
623 ///
624 /// Note that if ToReg is a physical register the function will replace and
625 /// apply sub registers to ToReg in order to obtain a final/proper physical
626 /// register.
627 void replaceRegWith(Register FromReg, Register ToReg);
628
629 /// getVRegDef - Return the machine instr that defines the specified virtual
630 /// register or null if none is found. This assumes that the code is in SSA
631 /// form, so there should only be one definition.
632 MachineInstr *getVRegDef(Register Reg) const;
633
634 /// getUniqueVRegDef - Return the unique machine instr that defines the
635 /// specified virtual register or null if none is found. If there are
636 /// multiple definitions or no definition, return null.
637 MachineInstr *getUniqueVRegDef(Register Reg) const;
638
639 /// clearKillFlags - Iterate over all the uses of the given register and
640 /// clear the kill flag from the MachineOperand. This function is used by
641 /// optimization passes which extend register lifetimes and need only
642 /// preserve conservative kill flag information.
643 void clearKillFlags(Register Reg) const;
644
645 void dumpUses(Register RegNo) const;
646
647 /// Returns true if PhysReg is unallocatable and constant throughout the
648 /// function. Writing to a constant register has no effect.
649 bool isConstantPhysReg(MCRegister PhysReg) const;
650
651 /// Get an iterator over the pressure sets affected by the given physical or
652 /// virtual register. If RegUnit is physical, it must be a register unit (from
653 /// MCRegUnitIterator).
654 PSetIterator getPressureSets(Register RegUnit) const;
655
656 //===--------------------------------------------------------------------===//
657 // Virtual Register Info
658 //===--------------------------------------------------------------------===//
659
660 /// Return the register class of the specified virtual register.
661 /// This shouldn't be used directly unless \p Reg has a register class.
662 /// \see getRegClassOrNull when this might happen.
663 const TargetRegisterClass *getRegClass(Register Reg) const {
664 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) &&
665 "Register class not set, wrong accessor");
666 return cast<const TargetRegisterClass *>(Val: VRegInfo[Reg.id()].first);
667 }
668
669 /// Return the register class of \p Reg, or null if Reg has not been assigned
670 /// a register class yet.
671 ///
672 /// \note A null register class can only happen when these two
673 /// conditions are met:
674 /// 1. Generic virtual registers are created.
675 /// 2. The machine function has not completely been through the
676 /// instruction selection process.
677 /// None of this condition is possible without GlobalISel for now.
678 /// In other words, if GlobalISel is not used or if the query happens after
679 /// the select pass, using getRegClass is safe.
680 const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
681 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
682 return dyn_cast_if_present<const TargetRegisterClass *>(Val);
683 }
684
685 /// Return the register bank of \p Reg, or null if Reg has not been assigned
686 /// a register bank or has been assigned a register class.
687 /// \note It is possible to get the register bank from the register class via
688 /// RegisterBankInfo::getRegBankFromRegClass.
689 const RegisterBank *getRegBankOrNull(Register Reg) const {
690 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
691 return dyn_cast_if_present<const RegisterBank *>(Val);
692 }
693
694 /// Return the register bank or register class of \p Reg.
695 /// \note Before the register bank gets assigned (i.e., before the
696 /// RegBankSelect pass) \p Reg may not have either.
697 const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
698 return VRegInfo[Reg].first;
699 }
700
701 /// setRegClass - Set the register class of the specified virtual register.
702 void setRegClass(Register Reg, const TargetRegisterClass *RC);
703
704 /// Set the register bank to \p RegBank for \p Reg.
705 void setRegBank(Register Reg, const RegisterBank &RegBank);
706
707 void setRegClassOrRegBank(Register Reg,
708 const RegClassOrRegBank &RCOrRB){
709 VRegInfo[Reg].first = RCOrRB;
710 }
711
712 /// constrainRegClass - Constrain the register class of the specified virtual
713 /// register to be a common subclass of RC and the current register class,
714 /// but only if the new class has at least MinNumRegs registers. Return the
715 /// new register class, or NULL if no such class exists.
716 /// This should only be used when the constraint is known to be trivial, like
717 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
718 ///
719 /// \note Assumes that the register has a register class assigned.
720 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
721 /// InstructionSelect pass and constrainRegAttrs in every other pass,
722 /// including non-select passes of GlobalISel, instead.
723 const TargetRegisterClass *constrainRegClass(Register Reg,
724 const TargetRegisterClass *RC,
725 unsigned MinNumRegs = 0);
726
727 /// Constrain the register class or the register bank of the virtual register
728 /// \p Reg (and low-level type) to be a common subclass or a common bank of
729 /// both registers provided respectively (and a common low-level type). Do
730 /// nothing if any of the attributes (classes, banks, or low-level types) of
731 /// the registers are deemed incompatible, or if the resulting register will
732 /// have a class smaller than before and of size less than \p MinNumRegs.
733 /// Return true if such register attributes exist, false otherwise.
734 ///
735 /// \note Use this method instead of constrainRegClass and
736 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
737 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
738 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
739 unsigned MinNumRegs = 0);
740
741 /// recomputeRegClass - Try to find a legal super-class of Reg's register
742 /// class that still satisfies the constraints from the instructions using
743 /// Reg. Returns true if Reg was upgraded.
744 ///
745 /// This method can be used after constraints have been removed from a
746 /// virtual register, for example after removing instructions or splitting
747 /// the live range.
748 bool recomputeRegClass(Register Reg);
749
750 /// createVirtualRegister - Create and return a new virtual register in the
751 /// function with the specified register class.
752 Register createVirtualRegister(const TargetRegisterClass *RegClass,
753 StringRef Name = "");
754
755 /// All attributes(register class or bank and low-level type) a virtual
756 /// register can have.
757 struct VRegAttrs {
758 RegClassOrRegBank RCOrRB;
759 LLT Ty;
760 };
761
762 /// Returns register class or bank and low level type of \p Reg. Always safe
763 /// to use. Special values are returned when \p Reg does not have some of the
764 /// attributes.
765 VRegAttrs getVRegAttrs(Register Reg) {
766 return {.RCOrRB: getRegClassOrRegBank(Reg), .Ty: getType(Reg)};
767 }
768
769 /// Create and return a new virtual register in the function with the
770 /// specified register attributes(register class or bank and low level type).
771 Register createVirtualRegister(VRegAttrs RegAttr, StringRef Name = "");
772
773 /// Create and return a new virtual register in the function with the same
774 /// attributes as the given register.
775 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
776
777 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
778 /// (target independent) virtual register.
779 LLT getType(Register Reg) const {
780 if (Reg.isVirtual() && VRegToType.inBounds(n: Reg))
781 return VRegToType[Reg];
782 return LLT{};
783 }
784
785 /// Set the low-level type of \p VReg to \p Ty.
786 void setType(Register VReg, LLT Ty);
787
788 /// Create and return a new generic virtual register with low-level
789 /// type \p Ty.
790 Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
791
792 /// Remove all types associated to virtual registers (after instruction
793 /// selection and constraining of all generic virtual registers).
794 void clearVirtRegTypes();
795
796 /// Creates a new virtual register that has no register class, register bank
797 /// or size assigned yet. This is only allowed to be used
798 /// temporarily while constructing machine instructions. Most operations are
799 /// undefined on an incomplete register until one of setRegClass(),
800 /// setRegBank() or setSize() has been called on it.
801 Register createIncompleteVirtualRegister(StringRef Name = "");
802
803 /// getNumVirtRegs - Return the number of virtual registers created.
804 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
805
806 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
807 void clearVirtRegs();
808
809 /// setRegAllocationHint - Specify a register allocation hint for the
810 /// specified virtual register. This is typically used by target, and in case
811 /// of an earlier hint it will be overwritten.
812 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
813 assert(VReg.isVirtual());
814 RegAllocHints[VReg].first = Type;
815 RegAllocHints[VReg].second.clear();
816 RegAllocHints[VReg].second.push_back(Elt: PrefReg);
817 }
818
819 /// addRegAllocationHint - Add a register allocation hint to the hints
820 /// vector for VReg.
821 void addRegAllocationHint(Register VReg, Register PrefReg) {
822 assert(VReg.isVirtual());
823 RegAllocHints[VReg].second.push_back(Elt: PrefReg);
824 }
825
826 /// Specify the preferred (target independent) register allocation hint for
827 /// the specified virtual register.
828 void setSimpleHint(Register VReg, Register PrefReg) {
829 setRegAllocationHint(VReg, /*Type=*/Type: 0, PrefReg);
830 }
831
832 void clearSimpleHint(Register VReg) {
833 assert (!RegAllocHints[VReg].first &&
834 "Expected to clear a non-target hint!");
835 RegAllocHints[VReg].second.clear();
836 }
837
838 /// getRegAllocationHint - Return the register allocation hint for the
839 /// specified virtual register. If there are many hints, this returns the
840 /// one with the greatest weight.
841 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const {
842 assert(VReg.isVirtual());
843 Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
844 RegAllocHints[VReg.id()].second[0] : Register());
845 return {RegAllocHints[VReg.id()].first, BestHint};
846 }
847
848 /// getSimpleHint - same as getRegAllocationHint except it will only return
849 /// a target independent hint.
850 Register getSimpleHint(Register VReg) const {
851 assert(VReg.isVirtual());
852 std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg);
853 return Hint.first ? Register() : Hint.second;
854 }
855
856 /// getRegAllocationHints - Return a reference to the vector of all
857 /// register allocation hints for VReg.
858 const std::pair<unsigned, SmallVector<Register, 4>> &
859 getRegAllocationHints(Register VReg) const {
860 assert(VReg.isVirtual());
861 return RegAllocHints[VReg];
862 }
863
864 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
865 /// specified register as undefined which causes the DBG_VALUE to be
866 /// deleted during LiveDebugVariables analysis.
867 void markUsesInDebugValueAsUndef(Register Reg) const;
868
869 /// updateDbgUsersToReg - Update a collection of debug instructions
870 /// to refer to the designated register.
871 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg,
872 ArrayRef<MachineInstr *> Users) const {
873 // If this operand is a register, check whether it overlaps with OldReg.
874 // If it does, replace with NewReg.
875 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
876 if (Op.isReg() &&
877 getTargetRegisterInfo()->regsOverlap(RegA: Op.getReg(), RegB: OldReg))
878 Op.setReg(NewReg);
879 };
880
881 // Iterate through (possibly several) operands to DBG_VALUEs and update
882 // each. For DBG_PHIs, only one operand will be present.
883 for (MachineInstr *MI : Users) {
884 if (MI->isDebugValue()) {
885 for (auto &Op : MI->debug_operands())
886 UpdateOp(Op);
887 assert(MI->hasDebugOperandForReg(NewReg) &&
888 "Expected debug value to have some overlap with OldReg");
889 } else if (MI->isDebugPHI()) {
890 UpdateOp(MI->getOperand(i: 0));
891 } else {
892 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
893 }
894 }
895 }
896
897 /// Return true if the specified register is modified in this function.
898 /// This checks that no defining machine operands exist for the register or
899 /// any of its aliases. Definitions found on functions marked noreturn are
900 /// ignored, to consider them pass 'true' for optional parameter
901 /// SkipNoReturnDef. The register is also considered modified when it is set
902 /// in the UsedPhysRegMask.
903 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
904
905 /// Return true if the specified register is modified or read in this
906 /// function. This checks that no machine operands exist for the register or
907 /// any of its aliases. If SkipRegMaskTest is false, the register is
908 /// considered used when it is set in the UsedPhysRegMask.
909 bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
910
911 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
912 /// This corresponds to the bit mask attached to register mask operands.
913 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
914 UsedPhysRegMask.setBitsNotInMask(Mask: RegMask);
915 }
916
917 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
918
919 //===--------------------------------------------------------------------===//
920 // Reserved Register Info
921 //===--------------------------------------------------------------------===//
922 //
923 // The set of reserved registers must be invariant during register
924 // allocation. For example, the target cannot suddenly decide it needs a
925 // frame pointer when the register allocator has already used the frame
926 // pointer register for something else.
927 //
928 // These methods can be used by target hooks like hasFP() to avoid changing
929 // the reserved register set during register allocation.
930
931 /// freezeReservedRegs - Called by the register allocator to freeze the set
932 /// of reserved registers before allocation begins.
933 void freezeReservedRegs(const MachineFunction&);
934
935 /// reserveReg -- Mark a register as reserved so checks like isAllocatable
936 /// will not suggest using it. This should not be used during the middle
937 /// of a function walk, or when liveness info is available.
938 void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) {
939 assert(reservedRegsFrozen() &&
940 "Reserved registers haven't been frozen yet. ");
941 MCRegAliasIterator R(PhysReg, TRI, true);
942
943 for (; R.isValid(); ++R)
944 ReservedRegs.set(*R);
945 }
946
947 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
948 /// to ensure the set of reserved registers stays constant.
949 bool reservedRegsFrozen() const {
950 return !ReservedRegs.empty();
951 }
952
953 /// canReserveReg - Returns true if PhysReg can be used as a reserved
954 /// register. Any register can be reserved before freezeReservedRegs() is
955 /// called.
956 bool canReserveReg(MCRegister PhysReg) const {
957 return !reservedRegsFrozen() || ReservedRegs.test(Idx: PhysReg);
958 }
959
960 /// getReservedRegs - Returns a reference to the frozen set of reserved
961 /// registers. This method should always be preferred to calling
962 /// TRI::getReservedRegs() when possible.
963 const BitVector &getReservedRegs() const {
964 assert(reservedRegsFrozen() &&
965 "Reserved registers haven't been frozen yet. "
966 "Use TRI::getReservedRegs().");
967 return ReservedRegs;
968 }
969
970 /// isReserved - Returns true when PhysReg is a reserved register.
971 ///
972 /// Reserved registers may belong to an allocatable register class, but the
973 /// target has explicitly requested that they are not used.
974 bool isReserved(MCRegister PhysReg) const {
975 return getReservedRegs().test(Idx: PhysReg.id());
976 }
977
978 /// Returns true when the given register unit is considered reserved.
979 ///
980 /// Register units are considered reserved when for at least one of their
981 /// root registers, the root register and all super registers are reserved.
982 /// This currently iterates the register hierarchy and may be slower than
983 /// expected.
984 bool isReservedRegUnit(unsigned Unit) const;
985
986 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
987 /// register class and it hasn't been reserved.
988 ///
989 /// Allocatable registers may show up in the allocation order of some virtual
990 /// register, so a register allocator needs to track its liveness and
991 /// availability.
992 bool isAllocatable(MCRegister PhysReg) const {
993 return getTargetRegisterInfo()->isInAllocatableClass(RegNo: PhysReg) &&
994 !isReserved(PhysReg);
995 }
996
997 //===--------------------------------------------------------------------===//
998 // LiveIn Management
999 //===--------------------------------------------------------------------===//
1000
1001 /// addLiveIn - Add the specified register as a live-in. Note that it
1002 /// is an error to add the same register to the same set more than once.
1003 void addLiveIn(MCRegister Reg, Register vreg = Register()) {
1004 LiveIns.push_back(x: std::make_pair(x&: Reg, y&: vreg));
1005 }
1006
1007 // Iteration support for the live-ins set. It's kept in sorted order
1008 // by register number.
1009 using livein_iterator =
1010 std::vector<std::pair<MCRegister,Register>>::const_iterator;
1011 livein_iterator livein_begin() const { return LiveIns.begin(); }
1012 livein_iterator livein_end() const { return LiveIns.end(); }
1013 bool livein_empty() const { return LiveIns.empty(); }
1014
1015 ArrayRef<std::pair<MCRegister, Register>> liveins() const {
1016 return LiveIns;
1017 }
1018
1019 bool isLiveIn(Register Reg) const;
1020
1021 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
1022 /// corresponding live-in physical register.
1023 MCRegister getLiveInPhysReg(Register VReg) const;
1024
1025 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
1026 /// corresponding live-in virtual register.
1027 Register getLiveInVirtReg(MCRegister PReg) const;
1028
1029 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
1030 /// into the given entry block.
1031 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
1032 const TargetRegisterInfo &TRI,
1033 const TargetInstrInfo &TII);
1034
1035 /// Returns a mask covering all bits that can appear in lane masks of
1036 /// subregisters of the virtual register @p Reg.
1037 LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
1038
1039 /// defusechain_iterator - This class provides iterator support for machine
1040 /// operands in the function that use or define a specific register. If
1041 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1042 /// returns defs. If neither are true then you are silly and it always
1043 /// returns end(). If SkipDebug is true it skips uses marked Debug
1044 /// when incrementing.
1045 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1046 bool ByInstr, bool ByBundle>
1047 class defusechain_iterator {
1048 friend class MachineRegisterInfo;
1049
1050 public:
1051 using iterator_category = std::forward_iterator_tag;
1052 using value_type = MachineOperand;
1053 using difference_type = std::ptrdiff_t;
1054 using pointer = value_type *;
1055 using reference = value_type &;
1056
1057 private:
1058 MachineOperand *Op = nullptr;
1059
1060 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1061 // If the first node isn't one we're interested in, advance to one that
1062 // we are interested in.
1063 if (op) {
1064 if ((!ReturnUses && op->isUse()) ||
1065 (!ReturnDefs && op->isDef()) ||
1066 (SkipDebug && op->isDebug()))
1067 advance();
1068 }
1069 }
1070
1071 void advance() {
1072 assert(Op && "Cannot increment end iterator!");
1073 Op = getNextOperandForReg(MO: Op);
1074
1075 // All defs come before the uses, so stop def_iterator early.
1076 if (!ReturnUses) {
1077 if (Op) {
1078 if (Op->isUse())
1079 Op = nullptr;
1080 else
1081 assert(!Op->isDebug() && "Can't have debug defs");
1082 }
1083 } else {
1084 // If this is an operand we don't care about, skip it.
1085 while (Op && ((!ReturnDefs && Op->isDef()) ||
1086 (SkipDebug && Op->isDebug())))
1087 Op = getNextOperandForReg(MO: Op);
1088 }
1089 }
1090
1091 public:
1092 defusechain_iterator() = default;
1093
1094 bool operator==(const defusechain_iterator &x) const {
1095 return Op == x.Op;
1096 }
1097 bool operator!=(const defusechain_iterator &x) const {
1098 return !operator==(x);
1099 }
1100
1101 /// atEnd - return true if this iterator is equal to reg_end() on the value.
1102 bool atEnd() const { return Op == nullptr; }
1103
1104 // Iterator traversal: forward iteration only
1105 defusechain_iterator &operator++() { // Preincrement
1106 assert(Op && "Cannot increment end iterator!");
1107 if (ByOperand)
1108 advance();
1109 else if (ByInstr) {
1110 MachineInstr *P = Op->getParent();
1111 do {
1112 advance();
1113 } while (Op && Op->getParent() == P);
1114 } else if (ByBundle) {
1115 MachineBasicBlock::instr_iterator P =
1116 getBundleStart(I: Op->getParent()->getIterator());
1117 do {
1118 advance();
1119 } while (Op && getBundleStart(I: Op->getParent()->getIterator()) == P);
1120 }
1121
1122 return *this;
1123 }
1124 defusechain_iterator operator++(int) { // Postincrement
1125 defusechain_iterator tmp = *this; ++*this; return tmp;
1126 }
1127
1128 /// getOperandNo - Return the operand # of this MachineOperand in its
1129 /// MachineInstr.
1130 unsigned getOperandNo() const {
1131 assert(Op && "Cannot dereference end iterator!");
1132 return Op - &Op->getParent()->getOperand(i: 0);
1133 }
1134
1135 // Retrieve a reference to the current operand.
1136 MachineOperand &operator*() const {
1137 assert(Op && "Cannot dereference end iterator!");
1138 return *Op;
1139 }
1140
1141 MachineOperand *operator->() const {
1142 assert(Op && "Cannot dereference end iterator!");
1143 return Op;
1144 }
1145 };
1146
1147 /// defusechain_iterator - This class provides iterator support for machine
1148 /// operands in the function that use or define a specific register. If
1149 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1150 /// returns defs. If neither are true then you are silly and it always
1151 /// returns end(). If SkipDebug is true it skips uses marked Debug
1152 /// when incrementing.
1153 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1154 bool ByInstr, bool ByBundle>
1155 class defusechain_instr_iterator {
1156 friend class MachineRegisterInfo;
1157
1158 public:
1159 using iterator_category = std::forward_iterator_tag;
1160 using value_type = MachineInstr;
1161 using difference_type = std::ptrdiff_t;
1162 using pointer = value_type *;
1163 using reference = value_type &;
1164
1165 private:
1166 MachineOperand *Op = nullptr;
1167
1168 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1169 // If the first node isn't one we're interested in, advance to one that
1170 // we are interested in.
1171 if (op) {
1172 if ((!ReturnUses && op->isUse()) ||
1173 (!ReturnDefs && op->isDef()) ||
1174 (SkipDebug && op->isDebug()))
1175 advance();
1176 }
1177 }
1178
1179 void advance() {
1180 assert(Op && "Cannot increment end iterator!");
1181 Op = getNextOperandForReg(MO: Op);
1182
1183 // All defs come before the uses, so stop def_iterator early.
1184 if (!ReturnUses) {
1185 if (Op) {
1186 if (Op->isUse())
1187 Op = nullptr;
1188 else
1189 assert(!Op->isDebug() && "Can't have debug defs");
1190 }
1191 } else {
1192 // If this is an operand we don't care about, skip it.
1193 while (Op && ((!ReturnDefs && Op->isDef()) ||
1194 (SkipDebug && Op->isDebug())))
1195 Op = getNextOperandForReg(MO: Op);
1196 }
1197 }
1198
1199 public:
1200 defusechain_instr_iterator() = default;
1201
1202 bool operator==(const defusechain_instr_iterator &x) const {
1203 return Op == x.Op;
1204 }
1205 bool operator!=(const defusechain_instr_iterator &x) const {
1206 return !operator==(x);
1207 }
1208
1209 /// atEnd - return true if this iterator is equal to reg_end() on the value.
1210 bool atEnd() const { return Op == nullptr; }
1211
1212 // Iterator traversal: forward iteration only
1213 defusechain_instr_iterator &operator++() { // Preincrement
1214 assert(Op && "Cannot increment end iterator!");
1215 if (ByOperand)
1216 advance();
1217 else if (ByInstr) {
1218 MachineInstr *P = Op->getParent();
1219 do {
1220 advance();
1221 } while (Op && Op->getParent() == P);
1222 } else if (ByBundle) {
1223 MachineBasicBlock::instr_iterator P =
1224 getBundleStart(I: Op->getParent()->getIterator());
1225 do {
1226 advance();
1227 } while (Op && getBundleStart(I: Op->getParent()->getIterator()) == P);
1228 }
1229
1230 return *this;
1231 }
1232 defusechain_instr_iterator operator++(int) { // Postincrement
1233 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1234 }
1235
1236 // Retrieve a reference to the current operand.
1237 MachineInstr &operator*() const {
1238 assert(Op && "Cannot dereference end iterator!");
1239 if (ByBundle)
1240 return *getBundleStart(I: Op->getParent()->getIterator());
1241 return *Op->getParent();
1242 }
1243
1244 MachineInstr *operator->() const { return &operator*(); }
1245 };
1246};
1247
1248/// Iterate over the pressure sets affected by the given physical or virtual
1249/// register. If Reg is physical, it must be a register unit (from
1250/// MCRegUnitIterator).
1251class PSetIterator {
1252 const int *PSet = nullptr;
1253 unsigned Weight = 0;
1254
1255public:
1256 PSetIterator() = default;
1257
1258 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) {
1259 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1260 if (RegUnit.isVirtual()) {
1261 const TargetRegisterClass *RC = MRI->getRegClass(Reg: RegUnit);
1262 PSet = TRI->getRegClassPressureSets(RC);
1263 Weight = TRI->getRegClassWeight(RC).RegWeight;
1264 } else {
1265 PSet = TRI->getRegUnitPressureSets(RegUnit);
1266 Weight = TRI->getRegUnitWeight(RegUnit);
1267 }
1268 if (*PSet == -1)
1269 PSet = nullptr;
1270 }
1271
1272 bool isValid() const { return PSet; }
1273
1274 unsigned getWeight() const { return Weight; }
1275
1276 unsigned operator*() const { return *PSet; }
1277
1278 void operator++() {
1279 assert(isValid() && "Invalid PSetIterator.");
1280 ++PSet;
1281 if (*PSet == -1)
1282 PSet = nullptr;
1283 }
1284};
1285
1286inline PSetIterator
1287MachineRegisterInfo::getPressureSets(Register RegUnit) const {
1288 return PSetIterator(RegUnit, this);
1289}
1290
1291} // end namespace llvm
1292
1293#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
1294

source code of llvm/include/llvm/CodeGen/MachineRegisterInfo.h