1//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/IndexedMap.h"
19#include "llvm/ADT/PointerUnion.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/StringSet.h"
22#include "llvm/ADT/iterator_range.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBundle.h"
26#include "llvm/CodeGen/MachineOperand.h"
27#include "llvm/CodeGen/RegisterBank.h"
28#include "llvm/CodeGen/TargetRegisterInfo.h"
29#include "llvm/CodeGen/TargetSubtargetInfo.h"
30#include "llvm/MC/LaneBitmask.h"
31#include <cassert>
32#include <cstddef>
33#include <cstdint>
34#include <iterator>
35#include <memory>
36#include <utility>
37#include <vector>
38
39namespace llvm {
40
41class PSetIterator;
42
43/// Convenient type to represent either a register class or a register bank.
44using RegClassOrRegBank =
45 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
46
47/// MachineRegisterInfo - Keep track of information for virtual and physical
48/// registers, including vreg register classes, use/def chains for registers,
49/// etc.
50class MachineRegisterInfo {
51public:
52 class Delegate {
53 virtual void anchor();
54
55 public:
56 virtual ~Delegate() = default;
57
58 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
59 };
60
61private:
62 MachineFunction *MF;
63 Delegate *TheDelegate = nullptr;
64
65 /// True if subregister liveness is tracked.
66 const bool TracksSubRegLiveness;
67
68 /// VRegInfo - Information we keep for each virtual register.
69 ///
70 /// Each element in this list contains the register class of the vreg and the
71 /// start of the use/def list for the register.
72 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
73 VirtReg2IndexFunctor>
74 VRegInfo;
75
76 /// Map for recovering vreg name from vreg number.
77 /// This map is used by the MIR Printer.
78 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
79
80 /// StringSet that is used to unique vreg names.
81 StringSet<> VRegNames;
82
83 /// The flag is true upon \p UpdatedCSRs initialization
84 /// and false otherwise.
85 bool IsUpdatedCSRsInitialized = false;
86
87 /// Contains the updated callee saved register list.
88 /// As opposed to the static list defined in register info,
89 /// all registers that were disabled are removed from the list.
90 SmallVector<MCPhysReg, 16> UpdatedCSRs;
91
92 /// RegAllocHints - This vector records register allocation hints for
93 /// virtual registers. For each virtual register, it keeps a pair of hint
94 /// type and hints vector making up the allocation hints. Only the first
95 /// hint may be target specific, and in that case this is reflected by the
96 /// first member of the pair being non-zero. If the hinted register is
97 /// virtual, it means the allocator should prefer the physical register
98 /// allocated to it if any.
99 IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
100 VirtReg2IndexFunctor> RegAllocHints;
101
102 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
103 /// physical registers.
104 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
105
106 /// getRegUseDefListHead - Return the head pointer for the register use/def
107 /// list for the specified virtual or physical register.
108 MachineOperand *&getRegUseDefListHead(Register RegNo) {
109 if (RegNo.isVirtual())
110 return VRegInfo[RegNo.id()].second;
111 return PhysRegUseDefLists[RegNo.id()];
112 }
113
114 MachineOperand *getRegUseDefListHead(Register RegNo) const {
115 if (RegNo.isVirtual())
116 return VRegInfo[RegNo.id()].second;
117 return PhysRegUseDefLists[RegNo.id()];
118 }
119
120 /// Get the next element in the use-def chain.
121 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
122 assert(MO && MO->isReg() && "This is not a register operand!");
123 return MO->Contents.Reg.Next;
124 }
125
126 /// UsedPhysRegMask - Additional used physregs including aliases.
127 /// This bit vector represents all the registers clobbered by function calls.
128 BitVector UsedPhysRegMask;
129
130 /// ReservedRegs - This is a bit vector of reserved registers. The target
131 /// may change its mind about which registers should be reserved. This
132 /// vector is the frozen set of reserved registers when register allocation
133 /// started.
134 BitVector ReservedRegs;
135
136 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
137 /// Map generic virtual registers to their low-level type.
138 VRegToTypeMap VRegToType;
139
140 /// Keep track of the physical registers that are live in to the function.
141 /// Live in values are typically arguments in registers. LiveIn values are
142 /// allowed to have virtual registers associated with them, stored in the
143 /// second element.
144 std::vector<std::pair<MCRegister, Register>> LiveIns;
145
146public:
147 explicit MachineRegisterInfo(MachineFunction *MF);
148 MachineRegisterInfo(const MachineRegisterInfo &) = delete;
149 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
150
151 const TargetRegisterInfo *getTargetRegisterInfo() const {
152 return MF->getSubtarget().getRegisterInfo();
153 }
154
155 void resetDelegate(Delegate *delegate) {
156 // Ensure another delegate does not take over unless the current
157 // delegate first unattaches itself. If we ever need to multicast
158 // notifications, we will need to change to using a list.
159 assert(TheDelegate == delegate &&
160 "Only the current delegate can perform reset!");
161 TheDelegate = nullptr;
162 }
163
164 void setDelegate(Delegate *delegate) {
165 assert(delegate && !TheDelegate &&
166 "Attempted to set delegate to null, or to change it without "
167 "first resetting it!");
168
169 TheDelegate = delegate;
170 }
171
172 //===--------------------------------------------------------------------===//
173 // Function State
174 //===--------------------------------------------------------------------===//
175
176 // isSSA - Returns true when the machine function is in SSA form. Early
177 // passes require the machine function to be in SSA form where every virtual
178 // register has a single defining instruction.
179 //
180 // The TwoAddressInstructionPass and PHIElimination passes take the machine
181 // function out of SSA form when they introduce multiple defs per virtual
182 // register.
183 bool isSSA() const {
184 return MF->getProperties().hasProperty(
185 MachineFunctionProperties::Property::IsSSA);
186 }
187
188 // leaveSSA - Indicates that the machine function is no longer in SSA form.
189 void leaveSSA() {
190 MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
191 }
192
193 /// tracksLiveness - Returns true when tracking register liveness accurately.
194 /// (see MachineFUnctionProperties::Property description for details)
195 bool tracksLiveness() const {
196 return MF->getProperties().hasProperty(
197 MachineFunctionProperties::Property::TracksLiveness);
198 }
199
200 /// invalidateLiveness - Indicates that register liveness is no longer being
201 /// tracked accurately.
202 ///
203 /// This should be called by late passes that invalidate the liveness
204 /// information.
205 void invalidateLiveness() {
206 MF->getProperties().reset(
207 MachineFunctionProperties::Property::TracksLiveness);
208 }
209
210 /// Returns true if liveness for register class @p RC should be tracked at
211 /// the subregister level.
212 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
213 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
214 }
215 bool shouldTrackSubRegLiveness(Register VReg) const {
216 assert(VReg.isVirtual() && "Must pass a VReg");
217 return shouldTrackSubRegLiveness(*getRegClass(VReg));
218 }
219 bool subRegLivenessEnabled() const {
220 return TracksSubRegLiveness;
221 }
222
223 //===--------------------------------------------------------------------===//
224 // Register Info
225 //===--------------------------------------------------------------------===//
226
227 /// Returns true if the updated CSR list was initialized and false otherwise.
228 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
229
230 /// Returns true if a register can be used as an argument to a function.
231 bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
232
233 /// Returns true if a register is a fixed register.
234 bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
235
236 /// Returns true if a register is a general purpose register.
237 bool isGeneralPurposeRegister(const MachineFunction &MF,
238 MCRegister Reg) const;
239
240 /// Disables the register from the list of CSRs.
241 /// I.e. the register will not appear as part of the CSR mask.
242 /// \see UpdatedCalleeSavedRegs.
243 void disableCalleeSavedRegister(MCRegister Reg);
244
245 /// Returns list of callee saved registers.
246 /// The function returns the updated CSR list (after taking into account
247 /// registers that are disabled from the CSR list).
248 const MCPhysReg *getCalleeSavedRegs() const;
249
250 /// Sets the updated Callee Saved Registers list.
251 /// Notice that it will override ant previously disabled/saved CSRs.
252 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
253
254 // Strictly for use by MachineInstr.cpp.
255 void addRegOperandToUseList(MachineOperand *MO);
256
257 // Strictly for use by MachineInstr.cpp.
258 void removeRegOperandFromUseList(MachineOperand *MO);
259
260 // Strictly for use by MachineInstr.cpp.
261 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
262
263 /// Verify the sanity of the use list for Reg.
264 void verifyUseList(Register Reg) const;
265
266 /// Verify the use list of all registers.
267 void verifyUseLists() const;
268
269 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
270 /// and uses of a register within the MachineFunction that corresponds to this
271 /// MachineRegisterInfo object.
272 template<bool Uses, bool Defs, bool SkipDebug,
273 bool ByOperand, bool ByInstr, bool ByBundle>
274 class defusechain_iterator;
275 template<bool Uses, bool Defs, bool SkipDebug,
276 bool ByOperand, bool ByInstr, bool ByBundle>
277 class defusechain_instr_iterator;
278
279 // Make it a friend so it can access getNextOperandForReg().
280 template<bool, bool, bool, bool, bool, bool>
281 friend class defusechain_iterator;
282 template<bool, bool, bool, bool, bool, bool>
283 friend class defusechain_instr_iterator;
284
285 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
286 /// register.
287 using reg_iterator =
288 defusechain_iterator<true, true, false, true, false, false>;
289 reg_iterator reg_begin(Register RegNo) const {
290 return reg_iterator(getRegUseDefListHead(RegNo));
291 }
292 static reg_iterator reg_end() { return reg_iterator(nullptr); }
293
294 inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
295 return make_range(reg_begin(Reg), reg_end());
296 }
297
298 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
299 /// of the specified register, stepping by MachineInstr.
300 using reg_instr_iterator =
301 defusechain_instr_iterator<true, true, false, false, true, false>;
302 reg_instr_iterator reg_instr_begin(Register RegNo) const {
303 return reg_instr_iterator(getRegUseDefListHead(RegNo));
304 }
305 static reg_instr_iterator reg_instr_end() {
306 return reg_instr_iterator(nullptr);
307 }
308
309 inline iterator_range<reg_instr_iterator>
310 reg_instructions(Register Reg) const {
311 return make_range(reg_instr_begin(Reg), reg_instr_end());
312 }
313
314 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
315 /// of the specified register, stepping by bundle.
316 using reg_bundle_iterator =
317 defusechain_instr_iterator<true, true, false, false, false, true>;
318 reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
319 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
320 }
321 static reg_bundle_iterator reg_bundle_end() {
322 return reg_bundle_iterator(nullptr);
323 }
324
325 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
326 return make_range(reg_bundle_begin(Reg), reg_bundle_end());
327 }
328
329 /// reg_empty - Return true if there are no instructions using or defining the
330 /// specified register (it may be live-in).
331 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
332
333 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
334 /// of the specified register, skipping those marked as Debug.
335 using reg_nodbg_iterator =
336 defusechain_iterator<true, true, true, true, false, false>;
337 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const {
338 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
339 }
340 static reg_nodbg_iterator reg_nodbg_end() {
341 return reg_nodbg_iterator(nullptr);
342 }
343
344 inline iterator_range<reg_nodbg_iterator>
345 reg_nodbg_operands(Register Reg) const {
346 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
347 }
348
349 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
350 /// all defs and uses of the specified register, stepping by MachineInstr,
351 /// skipping those marked as Debug.
352 using reg_instr_nodbg_iterator =
353 defusechain_instr_iterator<true, true, true, false, true, false>;
354 reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
355 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
356 }
357 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
358 return reg_instr_nodbg_iterator(nullptr);
359 }
360
361 inline iterator_range<reg_instr_nodbg_iterator>
362 reg_nodbg_instructions(Register Reg) const {
363 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
364 }
365
366 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
367 /// all defs and uses of the specified register, stepping by bundle,
368 /// skipping those marked as Debug.
369 using reg_bundle_nodbg_iterator =
370 defusechain_instr_iterator<true, true, true, false, false, true>;
371 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
372 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
373 }
374 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
375 return reg_bundle_nodbg_iterator(nullptr);
376 }
377
378 inline iterator_range<reg_bundle_nodbg_iterator>
379 reg_nodbg_bundles(Register Reg) const {
380 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
381 }
382
383 /// reg_nodbg_empty - Return true if the only instructions using or defining
384 /// Reg are Debug instructions.
385 bool reg_nodbg_empty(Register RegNo) const {
386 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
387 }
388
389 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
390 using def_iterator =
391 defusechain_iterator<false, true, false, true, false, false>;
392 def_iterator def_begin(Register RegNo) const {
393 return def_iterator(getRegUseDefListHead(RegNo));
394 }
395 static def_iterator def_end() { return def_iterator(nullptr); }
396
397 inline iterator_range<def_iterator> def_operands(Register Reg) const {
398 return make_range(def_begin(Reg), def_end());
399 }
400
401 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
402 /// specified register, stepping by MachineInst.
403 using def_instr_iterator =
404 defusechain_instr_iterator<false, true, false, false, true, false>;
405 def_instr_iterator def_instr_begin(Register RegNo) const {
406 return def_instr_iterator(getRegUseDefListHead(RegNo));
407 }
408 static def_instr_iterator def_instr_end() {
409 return def_instr_iterator(nullptr);
410 }
411
412 inline iterator_range<def_instr_iterator>
413 def_instructions(Register Reg) const {
414 return make_range(def_instr_begin(Reg), def_instr_end());
415 }
416
417 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
418 /// specified register, stepping by bundle.
419 using def_bundle_iterator =
420 defusechain_instr_iterator<false, true, false, false, false, true>;
421 def_bundle_iterator def_bundle_begin(Register RegNo) const {
422 return def_bundle_iterator(getRegUseDefListHead(RegNo));
423 }
424 static def_bundle_iterator def_bundle_end() {
425 return def_bundle_iterator(nullptr);
426 }
427
428 inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
429 return make_range(def_bundle_begin(Reg), def_bundle_end());
430 }
431
432 /// def_empty - Return true if there are no instructions defining the
433 /// specified register (it may be live-in).
434 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
435
436 StringRef getVRegName(Register Reg) const {
437 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
438 }
439
440 void insertVRegByName(StringRef Name, Register Reg) {
441 assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
442 "Named VRegs Must be Unique.");
443 if (!Name.empty()) {
444 VRegNames.insert(Name);
445 VReg2Name.grow(Reg);
446 VReg2Name[Reg] = Name.str();
447 }
448 }
449
450 /// Return true if there is exactly one operand defining the specified
451 /// register.
452 bool hasOneDef(Register RegNo) const {
453 return hasSingleElement(def_operands(RegNo));
454 }
455
456 /// Returns the defining operand if there is exactly one operand defining the
457 /// specified register, otherwise nullptr.
458 MachineOperand *getOneDef(Register Reg) const {
459 def_iterator DI = def_begin(Reg);
460 if (DI == def_end()) // No defs.
461 return nullptr;
462
463 def_iterator OneDef = DI;
464 if (++DI == def_end())
465 return &*OneDef;
466 return nullptr; // Multiple defs.
467 }
468
469 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
470 using use_iterator =
471 defusechain_iterator<true, false, false, true, false, false>;
472 use_iterator use_begin(Register RegNo) const {
473 return use_iterator(getRegUseDefListHead(RegNo));
474 }
475 static use_iterator use_end() { return use_iterator(nullptr); }
476
477 inline iterator_range<use_iterator> use_operands(Register Reg) const {
478 return make_range(use_begin(Reg), use_end());
479 }
480
481 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
482 /// specified register, stepping by MachineInstr.
483 using use_instr_iterator =
484 defusechain_instr_iterator<true, false, false, false, true, false>;
485 use_instr_iterator use_instr_begin(Register RegNo) const {
486 return use_instr_iterator(getRegUseDefListHead(RegNo));
487 }
488 static use_instr_iterator use_instr_end() {
489 return use_instr_iterator(nullptr);
490 }
491
492 inline iterator_range<use_instr_iterator>
493 use_instructions(Register Reg) const {
494 return make_range(use_instr_begin(Reg), use_instr_end());
495 }
496
497 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
498 /// specified register, stepping by bundle.
499 using use_bundle_iterator =
500 defusechain_instr_iterator<true, false, false, false, false, true>;
501 use_bundle_iterator use_bundle_begin(Register RegNo) const {
502 return use_bundle_iterator(getRegUseDefListHead(RegNo));
503 }
504 static use_bundle_iterator use_bundle_end() {
505 return use_bundle_iterator(nullptr);
506 }
507
508 inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
509 return make_range(use_bundle_begin(Reg), use_bundle_end());
510 }
511
512 /// use_empty - Return true if there are no instructions using the specified
513 /// register.
514 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
515
516 /// hasOneUse - Return true if there is exactly one instruction using the
517 /// specified register.
518 bool hasOneUse(Register RegNo) const {
519 return hasSingleElement(use_operands(RegNo));
520 }
521
522 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
523 /// specified register, skipping those marked as Debug.
524 using use_nodbg_iterator =
525 defusechain_iterator<true, false, true, true, false, false>;
526 use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
527 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
528 }
529 static use_nodbg_iterator use_nodbg_end() {
530 return use_nodbg_iterator(nullptr);
531 }
532
533 inline iterator_range<use_nodbg_iterator>
534 use_nodbg_operands(Register Reg) const {
535 return make_range(use_nodbg_begin(Reg), use_nodbg_end());
536 }
537
538 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
539 /// all uses of the specified register, stepping by MachineInstr, skipping
540 /// those marked as Debug.
541 using use_instr_nodbg_iterator =
542 defusechain_instr_iterator<true, false, true, false, true, false>;
543 use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
544 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
545 }
546 static use_instr_nodbg_iterator use_instr_nodbg_end() {
547 return use_instr_nodbg_iterator(nullptr);
548 }
549
550 inline iterator_range<use_instr_nodbg_iterator>
551 use_nodbg_instructions(Register Reg) const {
552 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
553 }
554
555 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
556 /// all uses of the specified register, stepping by bundle, skipping
557 /// those marked as Debug.
558 using use_bundle_nodbg_iterator =
559 defusechain_instr_iterator<true, false, true, false, false, true>;
560 use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
561 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
562 }
563 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
564 return use_bundle_nodbg_iterator(nullptr);
565 }
566
567 inline iterator_range<use_bundle_nodbg_iterator>
568 use_nodbg_bundles(Register Reg) const {
569 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
570 }
571
572 /// use_nodbg_empty - Return true if there are no non-Debug instructions
573 /// using the specified register.
574 bool use_nodbg_empty(Register RegNo) const {
575 return use_nodbg_begin(RegNo) == use_nodbg_end();
576 }
577
578 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
579 /// use of the specified register.
580 bool hasOneNonDBGUse(Register RegNo) const;
581
582 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
583 /// instruction using the specified register. Said instruction may have
584 /// multiple uses.
585 bool hasOneNonDBGUser(Register RegNo) const;
586
587
588 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
589 /// non-debug user instructions.
590 bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
591
592 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
593 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
594 /// except that it also changes any definitions of the register as well.
595 ///
596 /// Note that it is usually necessary to first constrain ToReg's register
597 /// class and register bank to match the FromReg constraints using one of the
598 /// methods:
599 ///
600 /// constrainRegClass(ToReg, getRegClass(FromReg))
601 /// constrainRegAttrs(ToReg, FromReg)
602 /// RegisterBankInfo::constrainGenericRegister(ToReg,
603 /// *MRI.getRegClass(FromReg), MRI)
604 ///
605 /// These functions will return a falsy result if the virtual registers have
606 /// incompatible constraints.
607 ///
608 /// Note that if ToReg is a physical register the function will replace and
609 /// apply sub registers to ToReg in order to obtain a final/proper physical
610 /// register.
611 void replaceRegWith(Register FromReg, Register ToReg);
612
613 /// getVRegDef - Return the machine instr that defines the specified virtual
614 /// register or null if none is found. This assumes that the code is in SSA
615 /// form, so there should only be one definition.
616 MachineInstr *getVRegDef(Register Reg) const;
617
618 /// getUniqueVRegDef - Return the unique machine instr that defines the
619 /// specified virtual register or null if none is found. If there are
620 /// multiple definitions or no definition, return null.
621 MachineInstr *getUniqueVRegDef(Register Reg) const;
622
623 /// clearKillFlags - Iterate over all the uses of the given register and
624 /// clear the kill flag from the MachineOperand. This function is used by
625 /// optimization passes which extend register lifetimes and need only
626 /// preserve conservative kill flag information.
627 void clearKillFlags(Register Reg) const;
628
629 void dumpUses(Register RegNo) const;
630
631 /// Returns true if PhysReg is unallocatable and constant throughout the
632 /// function. Writing to a constant register has no effect.
633 bool isConstantPhysReg(MCRegister PhysReg) const;
634
635 /// Get an iterator over the pressure sets affected by the given physical or
636 /// virtual register. If RegUnit is physical, it must be a register unit (from
637 /// MCRegUnitIterator).
638 PSetIterator getPressureSets(Register RegUnit) const;
639
640 //===--------------------------------------------------------------------===//
641 // Virtual Register Info
642 //===--------------------------------------------------------------------===//
643
644 /// Return the register class of the specified virtual register.
645 /// This shouldn't be used directly unless \p Reg has a register class.
646 /// \see getRegClassOrNull when this might happen.
647 const TargetRegisterClass *getRegClass(Register Reg) const {
648 assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() &&
649 "Register class not set, wrong accessor");
650 return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>();
651 }
652
653 /// Return the register class of \p Reg, or null if Reg has not been assigned
654 /// a register class yet.
655 ///
656 /// \note A null register class can only happen when these two
657 /// conditions are met:
658 /// 1. Generic virtual registers are created.
659 /// 2. The machine function has not completely been through the
660 /// instruction selection process.
661 /// None of this condition is possible without GlobalISel for now.
662 /// In other words, if GlobalISel is not used or if the query happens after
663 /// the select pass, using getRegClass is safe.
664 const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
665 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
666 return Val.dyn_cast<const TargetRegisterClass *>();
667 }
668
669 /// Return the register bank of \p Reg, or null if Reg has not been assigned
670 /// a register bank or has been assigned a register class.
671 /// \note It is possible to get the register bank from the register class via
672 /// RegisterBankInfo::getRegBankFromRegClass.
673 const RegisterBank *getRegBankOrNull(Register Reg) const {
674 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
675 return Val.dyn_cast<const RegisterBank *>();
676 }
677
678 /// Return the register bank or register class of \p Reg.
679 /// \note Before the register bank gets assigned (i.e., before the
680 /// RegBankSelect pass) \p Reg may not have either.
681 const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
682 return VRegInfo[Reg].first;
683 }
684
685 /// setRegClass - Set the register class of the specified virtual register.
686 void setRegClass(Register Reg, const TargetRegisterClass *RC);
687
688 /// Set the register bank to \p RegBank for \p Reg.
689 void setRegBank(Register Reg, const RegisterBank &RegBank);
690
691 void setRegClassOrRegBank(Register Reg,
692 const RegClassOrRegBank &RCOrRB){
693 VRegInfo[Reg].first = RCOrRB;
694 }
695
696 /// constrainRegClass - Constrain the register class of the specified virtual
697 /// register to be a common subclass of RC and the current register class,
698 /// but only if the new class has at least MinNumRegs registers. Return the
699 /// new register class, or NULL if no such class exists.
700 /// This should only be used when the constraint is known to be trivial, like
701 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
702 ///
703 /// \note Assumes that the register has a register class assigned.
704 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
705 /// InstructionSelect pass and constrainRegAttrs in every other pass,
706 /// including non-select passes of GlobalISel, instead.
707 const TargetRegisterClass *constrainRegClass(Register Reg,
708 const TargetRegisterClass *RC,
709 unsigned MinNumRegs = 0);
710
711 /// Constrain the register class or the register bank of the virtual register
712 /// \p Reg (and low-level type) to be a common subclass or a common bank of
713 /// both registers provided respectively (and a common low-level type). Do
714 /// nothing if any of the attributes (classes, banks, or low-level types) of
715 /// the registers are deemed incompatible, or if the resulting register will
716 /// have a class smaller than before and of size less than \p MinNumRegs.
717 /// Return true if such register attributes exist, false otherwise.
718 ///
719 /// \note Use this method instead of constrainRegClass and
720 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
721 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
722 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
723 unsigned MinNumRegs = 0);
724
725 /// recomputeRegClass - Try to find a legal super-class of Reg's register
726 /// class that still satisfies the constraints from the instructions using
727 /// Reg. Returns true if Reg was upgraded.
728 ///
729 /// This method can be used after constraints have been removed from a
730 /// virtual register, for example after removing instructions or splitting
731 /// the live range.
732 bool recomputeRegClass(Register Reg);
733
734 /// createVirtualRegister - Create and return a new virtual register in the
735 /// function with the specified register class.
736 Register createVirtualRegister(const TargetRegisterClass *RegClass,
737 StringRef Name = "");
738
739 /// Create and return a new virtual register in the function with the same
740 /// attributes as the given register.
741 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
742
743 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
744 /// (target independent) virtual register.
745 LLT getType(Register Reg) const {
746 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
747 return VRegToType[Reg];
748 return LLT{};
749 }
750
751 /// Set the low-level type of \p VReg to \p Ty.
752 void setType(Register VReg, LLT Ty);
753
754 /// Create and return a new generic virtual register with low-level
755 /// type \p Ty.
756 Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
757
758 /// Remove all types associated to virtual registers (after instruction
759 /// selection and constraining of all generic virtual registers).
760 void clearVirtRegTypes();
761
762 /// Creates a new virtual register that has no register class, register bank
763 /// or size assigned yet. This is only allowed to be used
764 /// temporarily while constructing machine instructions. Most operations are
765 /// undefined on an incomplete register until one of setRegClass(),
766 /// setRegBank() or setSize() has been called on it.
767 Register createIncompleteVirtualRegister(StringRef Name = "");
768
769 /// getNumVirtRegs - Return the number of virtual registers created.
770 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
771
772 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
773 void clearVirtRegs();
774
775 /// setRegAllocationHint - Specify a register allocation hint for the
776 /// specified virtual register. This is typically used by target, and in case
777 /// of an earlier hint it will be overwritten.
778 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
779 assert(VReg.isVirtual());
780 RegAllocHints[VReg].first = Type;
781 RegAllocHints[VReg].second.clear();
782 RegAllocHints[VReg].second.push_back(PrefReg);
783 }
784
785 /// addRegAllocationHint - Add a register allocation hint to the hints
786 /// vector for VReg.
787 void addRegAllocationHint(Register VReg, Register PrefReg) {
788 assert(Register::isVirtualRegister(VReg));
789 RegAllocHints[VReg].second.push_back(PrefReg);
790 }
791
792 /// Specify the preferred (target independent) register allocation hint for
793 /// the specified virtual register.
794 void setSimpleHint(Register VReg, Register PrefReg) {
795 setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
796 }
797
798 void clearSimpleHint(Register VReg) {
799 assert (!RegAllocHints[VReg].first &&
800 "Expected to clear a non-target hint!");
801 RegAllocHints[VReg].second.clear();
802 }
803
804 /// getRegAllocationHint - Return the register allocation hint for the
805 /// specified virtual register. If there are many hints, this returns the
806 /// one with the greatest weight.
807 std::pair<Register, Register>
808 getRegAllocationHint(Register VReg) const {
809 assert(VReg.isVirtual());
810 Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
811 RegAllocHints[VReg.id()].second[0] : Register());
812 return std::pair<Register, Register>(RegAllocHints[VReg.id()].first,
813 BestHint);
814 }
815
816 /// getSimpleHint - same as getRegAllocationHint except it will only return
817 /// a target independent hint.
818 Register getSimpleHint(Register VReg) const {
819 assert(VReg.isVirtual());
820 std::pair<Register, Register> Hint = getRegAllocationHint(VReg);
821 return Hint.first ? Register() : Hint.second;
822 }
823
824 /// getRegAllocationHints - Return a reference to the vector of all
825 /// register allocation hints for VReg.
826 const std::pair<Register, SmallVector<Register, 4>>
827 &getRegAllocationHints(Register VReg) const {
828 assert(VReg.isVirtual());
829 return RegAllocHints[VReg];
830 }
831
832 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
833 /// specified register as undefined which causes the DBG_VALUE to be
834 /// deleted during LiveDebugVariables analysis.
835 void markUsesInDebugValueAsUndef(Register Reg) const;
836
837 /// updateDbgUsersToReg - Update a collection of debug instructions
838 /// to refer to the designated register.
839 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg,
840 ArrayRef<MachineInstr *> Users) const {
841 // If this operand is a register, check whether it overlaps with OldReg.
842 // If it does, replace with NewReg.
843 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
844 if (Op.isReg() &&
845 getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
846 Op.setReg(NewReg);
847 };
848
849 // Iterate through (possibly several) operands to DBG_VALUEs and update
850 // each. For DBG_PHIs, only one operand will be present.
851 for (MachineInstr *MI : Users) {
852 if (MI->isDebugValue()) {
853 for (auto &Op : MI->debug_operands())
854 UpdateOp(Op);
855 assert(MI->hasDebugOperandForReg(NewReg) &&
856 "Expected debug value to have some overlap with OldReg");
857 } else if (MI->isDebugPHI()) {
858 UpdateOp(MI->getOperand(0));
859 } else {
860 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
861 }
862 }
863 }
864
865 /// Return true if the specified register is modified in this function.
866 /// This checks that no defining machine operands exist for the register or
867 /// any of its aliases. Definitions found on functions marked noreturn are
868 /// ignored, to consider them pass 'true' for optional parameter
869 /// SkipNoReturnDef. The register is also considered modified when it is set
870 /// in the UsedPhysRegMask.
871 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
872
873 /// Return true if the specified register is modified or read in this
874 /// function. This checks that no machine operands exist for the register or
875 /// any of its aliases. If SkipRegMaskTest is false, the register is
876 /// considered used when it is set in the UsedPhysRegMask.
877 bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
878
879 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
880 /// This corresponds to the bit mask attached to register mask operands.
881 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
882 UsedPhysRegMask.setBitsNotInMask(RegMask);
883 }
884
885 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
886
887 //===--------------------------------------------------------------------===//
888 // Reserved Register Info
889 //===--------------------------------------------------------------------===//
890 //
891 // The set of reserved registers must be invariant during register
892 // allocation. For example, the target cannot suddenly decide it needs a
893 // frame pointer when the register allocator has already used the frame
894 // pointer register for something else.
895 //
896 // These methods can be used by target hooks like hasFP() to avoid changing
897 // the reserved register set during register allocation.
898
899 /// freezeReservedRegs - Called by the register allocator to freeze the set
900 /// of reserved registers before allocation begins.
901 void freezeReservedRegs(const MachineFunction&);
902
903 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
904 /// to ensure the set of reserved registers stays constant.
905 bool reservedRegsFrozen() const {
906 return !ReservedRegs.empty();
907 }
908
909 /// canReserveReg - Returns true if PhysReg can be used as a reserved
910 /// register. Any register can be reserved before freezeReservedRegs() is
911 /// called.
912 bool canReserveReg(MCRegister PhysReg) const {
913 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
914 }
915
916 /// getReservedRegs - Returns a reference to the frozen set of reserved
917 /// registers. This method should always be preferred to calling
918 /// TRI::getReservedRegs() when possible.
919 const BitVector &getReservedRegs() const {
920 assert(reservedRegsFrozen() &&
921 "Reserved registers haven't been frozen yet. "
922 "Use TRI::getReservedRegs().");
923 return ReservedRegs;
924 }
925
926 /// isReserved - Returns true when PhysReg is a reserved register.
927 ///
928 /// Reserved registers may belong to an allocatable register class, but the
929 /// target has explicitly requested that they are not used.
930 bool isReserved(MCRegister PhysReg) const {
931 return getReservedRegs().test(PhysReg.id());
932 }
933
934 /// Returns true when the given register unit is considered reserved.
935 ///
936 /// Register units are considered reserved when for at least one of their
937 /// root registers, the root register and all super registers are reserved.
938 /// This currently iterates the register hierarchy and may be slower than
939 /// expected.
940 bool isReservedRegUnit(unsigned Unit) const;
941
942 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
943 /// register class and it hasn't been reserved.
944 ///
945 /// Allocatable registers may show up in the allocation order of some virtual
946 /// register, so a register allocator needs to track its liveness and
947 /// availability.
948 bool isAllocatable(MCRegister PhysReg) const {
949 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
950 !isReserved(PhysReg);
951 }
952
953 //===--------------------------------------------------------------------===//
954 // LiveIn Management
955 //===--------------------------------------------------------------------===//
956
957 /// addLiveIn - Add the specified register as a live-in. Note that it
958 /// is an error to add the same register to the same set more than once.
959 void addLiveIn(MCRegister Reg, Register vreg = Register()) {
960 LiveIns.push_back(std::make_pair(Reg, vreg));
961 }
962
963 // Iteration support for the live-ins set. It's kept in sorted order
964 // by register number.
965 using livein_iterator =
966 std::vector<std::pair<MCRegister,Register>>::const_iterator;
967 livein_iterator livein_begin() const { return LiveIns.begin(); }
968 livein_iterator livein_end() const { return LiveIns.end(); }
969 bool livein_empty() const { return LiveIns.empty(); }
970
971 ArrayRef<std::pair<MCRegister, Register>> liveins() const {
972 return LiveIns;
973 }
974
975 bool isLiveIn(Register Reg) const;
976
977 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
978 /// corresponding live-in physical register.
979 MCRegister getLiveInPhysReg(Register VReg) const;
980
981 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
982 /// corresponding live-in virtual register.
983 Register getLiveInVirtReg(MCRegister PReg) const;
984
985 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
986 /// into the given entry block.
987 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
988 const TargetRegisterInfo &TRI,
989 const TargetInstrInfo &TII);
990
991 /// Returns a mask covering all bits that can appear in lane masks of
992 /// subregisters of the virtual register @p Reg.
993 LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
994
995 /// defusechain_iterator - This class provides iterator support for machine
996 /// operands in the function that use or define a specific register. If
997 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
998 /// returns defs. If neither are true then you are silly and it always
999 /// returns end(). If SkipDebug is true it skips uses marked Debug
1000 /// when incrementing.
1001 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1002 bool ByInstr, bool ByBundle>
1003 class defusechain_iterator {
1004 friend class MachineRegisterInfo;
1005
1006 public:
1007 using iterator_category = std::forward_iterator_tag;
1008 using value_type = MachineOperand;
1009 using difference_type = std::ptrdiff_t;
1010 using pointer = value_type *;
1011 using reference = value_type &;
1012
1013 private:
1014 MachineOperand *Op = nullptr;
1015
1016 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1017 // If the first node isn't one we're interested in, advance to one that
1018 // we are interested in.
1019 if (op) {
1020 if ((!ReturnUses && op->isUse()) ||
1021 (!ReturnDefs && op->isDef()) ||
1022 (SkipDebug && op->isDebug()))
1023 advance();
1024 }
1025 }
1026
1027 void advance() {
1028 assert(Op && "Cannot increment end iterator!");
1029 Op = getNextOperandForReg(Op);
1030
1031 // All defs come before the uses, so stop def_iterator early.
1032 if (!ReturnUses) {
1033 if (Op) {
1034 if (Op->isUse())
1035 Op = nullptr;
1036 else
1037 assert(!Op->isDebug() && "Can't have debug defs");
1038 }
1039 } else {
1040 // If this is an operand we don't care about, skip it.
1041 while (Op && ((!ReturnDefs && Op->isDef()) ||
1042 (SkipDebug && Op->isDebug())))
1043 Op = getNextOperandForReg(Op);
1044 }
1045 }
1046
1047 public:
1048 defusechain_iterator() = default;
1049
1050 bool operator==(const defusechain_iterator &x) const {
1051 return Op == x.Op;
1052 }
1053 bool operator!=(const defusechain_iterator &x) const {
1054 return !operator==(x);
1055 }
1056
1057 /// atEnd - return true if this iterator is equal to reg_end() on the value.
1058 bool atEnd() const { return Op == nullptr; }
1059
1060 // Iterator traversal: forward iteration only
1061 defusechain_iterator &operator++() { // Preincrement
1062 assert(Op && "Cannot increment end iterator!");
1063 if (ByOperand)
1064 advance();
1065 else if (ByInstr) {
1066 MachineInstr *P = Op->getParent();
1067 do {
1068 advance();
1069 } while (Op && Op->getParent() == P);
1070 } else if (ByBundle) {
1071 MachineBasicBlock::instr_iterator P =
1072 getBundleStart(Op->getParent()->getIterator());
1073 do {
1074 advance();
1075 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1076 }
1077
1078 return *this;
1079 }
1080 defusechain_iterator operator++(int) { // Postincrement
1081 defusechain_iterator tmp = *this; ++*this; return tmp;
1082 }
1083
1084 /// getOperandNo - Return the operand # of this MachineOperand in its
1085 /// MachineInstr.
1086 unsigned getOperandNo() const {
1087 assert(Op && "Cannot dereference end iterator!");
1088 return Op - &Op->getParent()->getOperand(0);
1089 }
1090
1091 // Retrieve a reference to the current operand.
1092 MachineOperand &operator*() const {
1093 assert(Op && "Cannot dereference end iterator!");
1094 return *Op;
1095 }
1096
1097 MachineOperand *operator->() const {
1098 assert(Op && "Cannot dereference end iterator!");
1099 return Op;
1100 }
1101 };
1102
1103 /// defusechain_iterator - This class provides iterator support for machine
1104 /// operands in the function that use or define a specific register. If
1105 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1106 /// returns defs. If neither are true then you are silly and it always
1107 /// returns end(). If SkipDebug is true it skips uses marked Debug
1108 /// when incrementing.
1109 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1110 bool ByInstr, bool ByBundle>
1111 class defusechain_instr_iterator {
1112 friend class MachineRegisterInfo;
1113
1114 public:
1115 using iterator_category = std::forward_iterator_tag;
1116 using value_type = MachineInstr;
1117 using difference_type = std::ptrdiff_t;
1118 using pointer = value_type *;
1119 using reference = value_type &;
1120
1121 private:
1122 MachineOperand *Op = nullptr;
1123
1124 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1125 // If the first node isn't one we're interested in, advance to one that
1126 // we are interested in.
1127 if (op) {
1128 if ((!ReturnUses && op->isUse()) ||
1129 (!ReturnDefs && op->isDef()) ||
1130 (SkipDebug && op->isDebug()))
1131 advance();
1132 }
1133 }
1134
1135 void advance() {
1136 assert(Op && "Cannot increment end iterator!");
1137 Op = getNextOperandForReg(Op);
1138
1139 // All defs come before the uses, so stop def_iterator early.
1140 if (!ReturnUses) {
1141 if (Op) {
1142 if (Op->isUse())
1143 Op = nullptr;
1144 else
1145 assert(!Op->isDebug() && "Can't have debug defs");
1146 }
1147 } else {
1148 // If this is an operand we don't care about, skip it.
1149 while (Op && ((!ReturnDefs && Op->isDef()) ||
1150 (SkipDebug && Op->isDebug())))
1151 Op = getNextOperandForReg(Op);
1152 }
1153 }
1154
1155 public:
1156 defusechain_instr_iterator() = default;
1157
1158 bool operator==(const defusechain_instr_iterator &x) const {
1159 return Op == x.Op;
1160 }
1161 bool operator!=(const defusechain_instr_iterator &x) const {
1162 return !operator==(x);
1163 }
1164
1165 /// atEnd - return true if this iterator is equal to reg_end() on the value.
1166 bool atEnd() const { return Op == nullptr; }
1167
1168 // Iterator traversal: forward iteration only
1169 defusechain_instr_iterator &operator++() { // Preincrement
1170 assert(Op && "Cannot increment end iterator!");
1171 if (ByOperand)
1172 advance();
1173 else if (ByInstr) {
1174 MachineInstr *P = Op->getParent();
1175 do {
1176 advance();
1177 } while (Op && Op->getParent() == P);
1178 } else if (ByBundle) {
1179 MachineBasicBlock::instr_iterator P =
1180 getBundleStart(Op->getParent()->getIterator());
1181 do {
1182 advance();
1183 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1184 }
1185
1186 return *this;
1187 }
1188 defusechain_instr_iterator operator++(int) { // Postincrement
1189 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1190 }
1191
1192 // Retrieve a reference to the current operand.
1193 MachineInstr &operator*() const {
1194 assert(Op && "Cannot dereference end iterator!");
1195 if (ByBundle)
1196 return *getBundleStart(Op->getParent()->getIterator());
1197 return *Op->getParent();
1198 }
1199
1200 MachineInstr *operator->() const { return &operator*(); }
1201 };
1202};
1203
1204/// Iterate over the pressure sets affected by the given physical or virtual
1205/// register. If Reg is physical, it must be a register unit (from
1206/// MCRegUnitIterator).
1207class PSetIterator {
1208 const int *PSet = nullptr;
1209 unsigned Weight = 0;
1210
1211public:
1212 PSetIterator() = default;
1213
1214 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) {
1215 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1216 if (RegUnit.isVirtual()) {
1217 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1218 PSet = TRI->getRegClassPressureSets(RC);
1219 Weight = TRI->getRegClassWeight(RC).RegWeight;
1220 } else {
1221 PSet = TRI->getRegUnitPressureSets(RegUnit);
1222 Weight = TRI->getRegUnitWeight(RegUnit);
1223 }
1224 if (*PSet == -1)
1225 PSet = nullptr;
1226 }
1227
1228 bool isValid() const { return PSet; }
1229
1230 unsigned getWeight() const { return Weight; }
1231
1232 unsigned operator*() const { return *PSet; }
1233
1234 void operator++() {
1235 assert(isValid() && "Invalid PSetIterator.");
1236 ++PSet;
1237 if (*PSet == -1)
1238 PSet = nullptr;
1239 }
1240};
1241
1242inline PSetIterator
1243MachineRegisterInfo::getPressureSets(Register RegUnit) const {
1244 return PSetIterator(RegUnit, this);
1245}
1246
1247} // end namespace llvm
1248
1249#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
1250

source code of llvm/include/llvm/CodeGen/MachineRegisterInfo.h