1	//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//
7	//===----------------------------------------------------------------------===//
8	//
9	// This file describes the target machine instruction set to the code generator.
10	//
11	//===----------------------------------------------------------------------===//
12
13	#ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14	#define LLVM_CODEGEN_TARGETINSTRINFO_H
15
16	#include "llvm/ADT/ArrayRef.h"
17	#include "llvm/ADT/DenseMap.h"
18	#include "llvm/ADT/DenseMapInfo.h"
19	#include "llvm/ADT/Uniformity.h"
20	#include "llvm/CodeGen/MIRFormatter.h"
21	#include "llvm/CodeGen/MachineBasicBlock.h"
22	#include "llvm/CodeGen/MachineCycleAnalysis.h"
23	#include "llvm/CodeGen/MachineFunction.h"
24	#include "llvm/CodeGen/MachineInstr.h"
25	#include "llvm/CodeGen/MachineInstrBuilder.h"
26	#include "llvm/CodeGen/MachineOperand.h"
27	#include "llvm/CodeGen/MachineOutliner.h"
28	#include "llvm/CodeGen/RegisterClassInfo.h"
29	#include "llvm/CodeGen/VirtRegMap.h"
30	#include "llvm/MC/MCInstrInfo.h"
31	#include "llvm/Support/BranchProbability.h"
32	#include "llvm/Support/ErrorHandling.h"
33	#include <cassert>
34	#include <cstddef>
35	#include <cstdint>
36	#include <utility>
37	#include <vector>
38
39	namespace llvm {
40
41	class DFAPacketizer;
42	class InstrItineraryData;
43	class LiveIntervals;
44	class LiveVariables;
45	class MachineLoop;
46	class MachineMemOperand;
47	class MachineRegisterInfo;
48	class MCAsmInfo;
49	class MCInst;
50	struct MCSchedModel;
51	class Module;
52	class ScheduleDAG;
53	class ScheduleDAGMI;
54	class ScheduleHazardRecognizer;
55	class SDNode;
56	class SelectionDAG;
57	class SMSchedule;
58	class SwingSchedulerDAG;
59	class RegScavenger;
60	class TargetRegisterClass;
61	class TargetRegisterInfo;
62	class TargetSchedModel;
63	class TargetSubtargetInfo;
64	enum class MachineCombinerPattern;
65	enum class MachineTraceStrategy;
66
67	template <class T> class SmallVectorImpl;
68
69	using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
70
71	struct DestSourcePair {
72	const MachineOperand *Destination;
73	const MachineOperand *Source;
74
75	DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
76	: Destination(&Dest), Source(&Src) {}
77	};
78
79	/// Used to describe a register and immediate addition.
80	struct RegImmPair {
81	Register Reg;
82	int64_t Imm;
83
84	RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
85	};
86
87	/// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
88	/// It holds the register values, the scale value and the displacement.
89	/// It also holds a descriptor for the expression used to calculate the address
90	/// from the operands.
91	struct ExtAddrMode {
92	enum class Formula {
93	Basic = 0, // BaseReg + ScaledReg * Scale + Displacement
94	SExtScaledReg = 1, // BaseReg + sext(ScaledReg) * Scale + Displacement
95	ZExtScaledReg = 2 // BaseReg + zext(ScaledReg) * Scale + Displacement
96	};
97
98	Register BaseReg;
99	Register ScaledReg;
100	int64_t Scale = 0;
101	int64_t Displacement = 0;
102	Formula Form = Formula::Basic;
103	ExtAddrMode() = default;
104	};
105
106	//---------------------------------------------------------------------------
107	///
108	/// TargetInstrInfo - Interface to description of machine instruction set
109	///
110	class TargetInstrInfo : public MCInstrInfo {
111	public:
112	TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
113	unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
114	: CallFrameSetupOpcode(CFSetupOpcode),
115	CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
116	ReturnOpcode(ReturnOpcode) {}
117	TargetInstrInfo(const TargetInstrInfo &) = delete;
118	TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
119	virtual ~TargetInstrInfo();
120
121	static bool isGenericOpcode(unsigned Opc) {
122	return Opc <= TargetOpcode::GENERIC_OP_END;
123	}
124
125	static bool isGenericAtomicRMWOpcode(unsigned Opc) {
126	return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
127	Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
128	}
129
130	/// Given a machine instruction descriptor, returns the register
131	/// class constraint for OpNum, or NULL.
132	virtual
133	const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
134	const TargetRegisterInfo *TRI,
135	const MachineFunction &MF) const;
136
137	/// Return true if the instruction is trivially rematerializable, meaning it
138	/// has no side effects and requires no operands that aren't always available.
139	/// This means the only allowed uses are constants and unallocatable physical
140	/// registers so that the instructions result is independent of the place
141	/// in the function.
142	bool isTriviallyReMaterializable(const MachineInstr &MI) const {
143	return (MI.getOpcode() == TargetOpcode::IMPLICIT_DEF &&
144	MI.getNumOperands() == 1) ||
145	(MI.getDesc().isRematerializable() &&
146	isReallyTriviallyReMaterializable(MI));
147	}
148
149	/// Given \p MO is a PhysReg use return if it can be ignored for the purpose
150	/// of instruction rematerialization or sinking.
151	virtual bool isIgnorableUse(const MachineOperand &MO) const {
152	return false;
153	}
154
155	virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
156	MachineCycleInfo *CI) const {
157	return true;
158	}
159
160	protected:
161	/// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
162	/// set, this hook lets the target specify whether the instruction is actually
163	/// trivially rematerializable, taking into consideration its operands. This
164	/// predicate must return false if the instruction has any side effects other
165	/// than producing a value, or if it requres any address registers that are
166	/// not always available.
167	virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const;
168
169	/// This method commutes the operands of the given machine instruction MI.
170	/// The operands to be commuted are specified by their indices OpIdx1 and
171	/// OpIdx2.
172	///
173	/// If a target has any instructions that are commutable but require
174	/// converting to different instructions or making non-trivial changes
175	/// to commute them, this method can be overloaded to do that.
176	/// The default implementation simply swaps the commutable operands.
177	///
178	/// If NewMI is false, MI is modified in place and returned; otherwise, a
179	/// new machine instruction is created and returned.
180	///
181	/// Do not call this method for a non-commutable instruction.
182	/// Even though the instruction is commutable, the method may still
183	/// fail to commute the operands, null pointer is returned in such cases.
184	virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
185	unsigned OpIdx1,
186	unsigned OpIdx2) const;
187
188	/// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
189	/// operand indices to (ResultIdx1, ResultIdx2).
190	/// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
191	/// predefined to some indices or be undefined (designated by the special
192	/// value 'CommuteAnyOperandIndex').
193	/// The predefined result indices cannot be re-defined.
194	/// The function returns true iff after the result pair redefinition
195	/// the fixed result pair is equal to or equivalent to the source pair of
196	/// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
197	/// the pairs (x,y) and (y,x) are equivalent.
198	static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
199	unsigned CommutableOpIdx1,
200	unsigned CommutableOpIdx2);
201
202	public:
203	/// These methods return the opcode of the frame setup/destroy instructions
204	/// if they exist (-1 otherwise). Some targets use pseudo instructions in
205	/// order to abstract away the difference between operating with a frame
206	/// pointer and operating without, through the use of these two instructions.
207	///
208	unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
209	unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
210
211	/// Returns true if the argument is a frame pseudo instruction.
212	bool isFrameInstr(const MachineInstr &I) const {
213	return I.getOpcode() == getCallFrameSetupOpcode() ||
214	I.getOpcode() == getCallFrameDestroyOpcode();
215	}
216
217	/// Returns true if the argument is a frame setup pseudo instruction.
218	bool isFrameSetup(const MachineInstr &I) const {
219	return I.getOpcode() == getCallFrameSetupOpcode();
220	}
221
222	/// Returns size of the frame associated with the given frame instruction.
223	/// For frame setup instruction this is frame that is set up space set up
224	/// after the instruction. For frame destroy instruction this is the frame
225	/// freed by the caller.
226	/// Note, in some cases a call frame (or a part of it) may be prepared prior
227	/// to the frame setup instruction. It occurs in the calls that involve
228	/// inalloca arguments. This function reports only the size of the frame part
229	/// that is set up between the frame setup and destroy pseudo instructions.
230	int64_t getFrameSize(const MachineInstr &I) const {
231	assert(isFrameInstr(I) && "Not a frame instruction");
232	assert(I.getOperand(0).getImm() >= 0);
233	return I.getOperand(i: 0).getImm();
234	}
235
236	/// Returns the total frame size, which is made up of the space set up inside
237	/// the pair of frame start-stop instructions and the space that is set up
238	/// prior to the pair.
239	int64_t getFrameTotalSize(const MachineInstr &I) const {
240	if (isFrameSetup(I)) {
241	assert(I.getOperand(1).getImm() >= 0 &&
242	"Frame size must not be negative");
243	return getFrameSize(I) + I.getOperand(i: 1).getImm();
244	}
245	return getFrameSize(I);
246	}
247
248	unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
249	unsigned getReturnOpcode() const { return ReturnOpcode; }
250
251	/// Returns the actual stack pointer adjustment made by an instruction
252	/// as part of a call sequence. By default, only call frame setup/destroy
253	/// instructions adjust the stack, but targets may want to override this
254	/// to enable more fine-grained adjustment, or adjust by a different value.
255	virtual int getSPAdjust(const MachineInstr &MI) const;
256
257	/// Return true if the instruction is a "coalescable" extension instruction.
258	/// That is, it's like a copy where it's legal for the source to overlap the
259	/// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
260	/// expected the pre-extension value is available as a subreg of the result
261	/// register. This also returns the sub-register index in SubIdx.
262	virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
263	Register &DstReg, unsigned &SubIdx) const {
264	return false;
265	}
266
267	/// If the specified machine instruction is a direct
268	/// load from a stack slot, return the virtual or physical register number of
269	/// the destination along with the FrameIndex of the loaded stack slot. If
270	/// not, return 0. This predicate must return 0 if the instruction has
271	/// any side effects other than loading from the stack slot.
272	virtual Register isLoadFromStackSlot(const MachineInstr &MI,
273	int &FrameIndex) const {
274	return 0;
275	}
276
277	/// Optional extension of isLoadFromStackSlot that returns the number of
278	/// bytes loaded from the stack. This must be implemented if a backend
279	/// supports partial stack slot spills/loads to further disambiguate
280	/// what the load does.
281	virtual Register isLoadFromStackSlot(const MachineInstr &MI,
282	int &FrameIndex,
283	unsigned &MemBytes) const {
284	MemBytes = 0;
285	return isLoadFromStackSlot(MI, FrameIndex);
286	}
287
288	/// Check for post-frame ptr elimination stack locations as well.
289	/// This uses a heuristic so it isn't reliable for correctness.
290	virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
291	int &FrameIndex) const {
292	return 0;
293	}
294
295	/// If the specified machine instruction has a load from a stack slot,
296	/// return true along with the FrameIndices of the loaded stack slot and the
297	/// machine mem operands containing the reference.
298	/// If not, return false. Unlike isLoadFromStackSlot, this returns true for
299	/// any instructions that loads from the stack. This is just a hint, as some
300	/// cases may be missed.
301	virtual bool hasLoadFromStackSlot(
302	const MachineInstr &MI,
303	SmallVectorImpl<const MachineMemOperand *> &Accesses) const;
304
305	/// If the specified machine instruction is a direct
306	/// store to a stack slot, return the virtual or physical register number of
307	/// the source reg along with the FrameIndex of the loaded stack slot. If
308	/// not, return 0. This predicate must return 0 if the instruction has
309	/// any side effects other than storing to the stack slot.
310	virtual Register isStoreToStackSlot(const MachineInstr &MI,
311	int &FrameIndex) const {
312	return 0;
313	}
314
315	/// Optional extension of isStoreToStackSlot that returns the number of
316	/// bytes stored to the stack. This must be implemented if a backend
317	/// supports partial stack slot spills/loads to further disambiguate
318	/// what the store does.
319	virtual Register isStoreToStackSlot(const MachineInstr &MI,
320	int &FrameIndex,
321	unsigned &MemBytes) const {
322	MemBytes = 0;
323	return isStoreToStackSlot(MI, FrameIndex);
324	}
325
326	/// Check for post-frame ptr elimination stack locations as well.
327	/// This uses a heuristic, so it isn't reliable for correctness.
328	virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI,
329	int &FrameIndex) const {
330	return 0;
331	}
332
333	/// If the specified machine instruction has a store to a stack slot,
334	/// return true along with the FrameIndices of the loaded stack slot and the
335	/// machine mem operands containing the reference.
336	/// If not, return false. Unlike isStoreToStackSlot,
337	/// this returns true for any instructions that stores to the
338	/// stack. This is just a hint, as some cases may be missed.
339	virtual bool hasStoreToStackSlot(
340	const MachineInstr &MI,
341	SmallVectorImpl<const MachineMemOperand *> &Accesses) const;
342
343	/// Return true if the specified machine instruction
344	/// is a copy of one stack slot to another and has no other effect.
345	/// Provide the identity of the two frame indices.
346	virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
347	int &SrcFrameIndex) const {
348	return false;
349	}
350
351	/// Compute the size in bytes and offset within a stack slot of a spilled
352	/// register or subregister.
353	///
354	/// \param [out] Size in bytes of the spilled value.
355	/// \param [out] Offset in bytes within the stack slot.
356	/// \returns true if both Size and Offset are successfully computed.
357	///
358	/// Not all subregisters have computable spill slots. For example,
359	/// subregisters registers may not be byte-sized, and a pair of discontiguous
360	/// subregisters has no single offset.
361	///
362	/// Targets with nontrivial bigendian implementations may need to override
363	/// this, particularly to support spilled vector registers.
364	virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
365	unsigned &Size, unsigned &Offset,
366	const MachineFunction &MF) const;
367
368	/// Return true if the given instruction is terminator that is unspillable,
369	/// according to isUnspillableTerminatorImpl.
370	bool isUnspillableTerminator(const MachineInstr *MI) const {
371	return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
372	}
373
374	/// Returns the size in bytes of the specified MachineInstr, or ~0U
375	/// when this function is not implemented by a target.
376	virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
377	return ~0U;
378	}
379
380	/// Return true if the instruction is as cheap as a move instruction.
381	///
382	/// Targets for different archs need to override this, and different
383	/// micro-architectures can also be finely tuned inside.
384	virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
385	return MI.isAsCheapAsAMove();
386	}
387
388	/// Return true if the instruction should be sunk by MachineSink.
389	///
390	/// MachineSink determines on its own whether the instruction is safe to sink;
391	/// this gives the target a hook to override the default behavior with regards
392	/// to which instructions should be sunk.
393	virtual bool shouldSink(const MachineInstr &MI) const { return true; }
394
395	/// Return false if the instruction should not be hoisted by MachineLICM.
396	///
397	/// MachineLICM determines on its own whether the instruction is safe to
398	/// hoist; this gives the target a hook to extend this assessment and prevent
399	/// an instruction being hoisted from a given loop for target specific
400	/// reasons.
401	virtual bool shouldHoist(const MachineInstr &MI,
402	const MachineLoop *FromLoop) const {
403	return true;
404	}
405
406	/// Re-issue the specified 'original' instruction at the
407	/// specific location targeting a new destination register.
408	/// The register in Orig->getOperand(0).getReg() will be substituted by
409	/// DestReg:SubIdx. Any existing subreg index is preserved or composed with
410	/// SubIdx.
411	virtual void reMaterialize(MachineBasicBlock &MBB,
412	MachineBasicBlock::iterator MI, Register DestReg,
413	unsigned SubIdx, const MachineInstr &Orig,
414	const TargetRegisterInfo &TRI) const;
415
416	/// Clones instruction or the whole instruction bundle \p Orig and
417	/// insert into \p MBB before \p InsertBefore. The target may update operands
418	/// that are required to be unique.
419	///
420	/// \p Orig must not return true for MachineInstr::isNotDuplicable().
421	virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
422	MachineBasicBlock::iterator InsertBefore,
423	const MachineInstr &Orig) const;
424
425	/// This method must be implemented by targets that
426	/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
427	/// may be able to convert a two-address instruction into one or more true
428	/// three-address instructions on demand. This allows the X86 target (for
429	/// example) to convert ADD and SHL instructions into LEA instructions if they
430	/// would require register copies due to two-addressness.
431	///
432	/// This method returns a null pointer if the transformation cannot be
433	/// performed, otherwise it returns the last new instruction.
434	///
435	/// If \p LIS is not nullptr, the LiveIntervals info should be updated for
436	/// replacing \p MI with new instructions, even though this function does not
437	/// remove MI.
438	virtual MachineInstr *convertToThreeAddress(MachineInstr &MI,
439	LiveVariables *LV,
440	LiveIntervals *LIS) const {
441	return nullptr;
442	}
443
444	// This constant can be used as an input value of operand index passed to
445	// the method findCommutedOpIndices() to tell the method that the
446	// corresponding operand index is not pre-defined and that the method
447	// can pick any commutable operand.
448	static const unsigned CommuteAnyOperandIndex = ~0U;
449
450	/// This method commutes the operands of the given machine instruction MI.
451	///
452	/// The operands to be commuted are specified by their indices OpIdx1 and
453	/// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
454	/// 'CommuteAnyOperandIndex', which means that the method is free to choose
455	/// any arbitrarily chosen commutable operand. If both arguments are set to
456	/// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
457	/// operands; then commutes them if such operands could be found.
458	///
459	/// If NewMI is false, MI is modified in place and returned; otherwise, a
460	/// new machine instruction is created and returned.
461	///
462	/// Do not call this method for a non-commutable instruction or
463	/// for non-commuable operands.
464	/// Even though the instruction is commutable, the method may still
465	/// fail to commute the operands, null pointer is returned in such cases.
466	MachineInstr *
467	commuteInstruction(MachineInstr &MI, bool NewMI = false,
468	unsigned OpIdx1 = CommuteAnyOperandIndex,
469	unsigned OpIdx2 = CommuteAnyOperandIndex) const;
470
471	/// Returns true iff the routine could find two commutable operands in the
472	/// given machine instruction.
473	/// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
474	/// If any of the INPUT values is set to the special value
475	/// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
476	/// operand, then returns its index in the corresponding argument.
477	/// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
478	/// looks for 2 commutable operands.
479	/// If INPUT values refer to some operands of MI, then the method simply
480	/// returns true if the corresponding operands are commutable and returns
481	/// false otherwise.
482	///
483	/// For example, calling this method this way:
484	/// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
485	/// findCommutedOpIndices(MI, Op1, Op2);
486	/// can be interpreted as a query asking to find an operand that would be
487	/// commutable with the operand#1.
488	virtual bool findCommutedOpIndices(const MachineInstr &MI,
489	unsigned &SrcOpIdx1,
490	unsigned &SrcOpIdx2) const;
491
492	/// Returns true if the target has a preference on the operands order of
493	/// the given machine instruction. And specify if \p Commute is required to
494	/// get the desired operands order.
495	virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
496	return false;
497	}
498
499	/// A pair composed of a register and a sub-register index.
500	/// Used to give some type checking when modeling Reg:SubReg.
501	struct RegSubRegPair {
502	Register Reg;
503	unsigned SubReg;
504
505	RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
506	: Reg(Reg), SubReg(SubReg) {}
507
508	bool operator==(const RegSubRegPair& P) const {
509	return Reg == P.Reg && SubReg == P.SubReg;
510	}
511	bool operator!=(const RegSubRegPair& P) const {
512	return !(*this == P);
513	}
514	};
515
516	/// A pair composed of a pair of a register and a sub-register index,
517	/// and another sub-register index.
518	/// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
519	struct RegSubRegPairAndIdx : RegSubRegPair {
520	unsigned SubIdx;
521
522	RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
523	unsigned SubIdx = 0)
524	: RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
525	};
526
527	/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
528	/// and \p DefIdx.
529	/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
530	/// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
531	/// flag are not added to this list.
532	/// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
533	/// two elements:
534	/// - %1:sub1, sub0
535	/// - %2<:0>, sub1
536	///
537	/// \returns true if it is possible to build such an input sequence
538	/// with the pair \p MI, \p DefIdx. False otherwise.
539	///
540	/// \pre MI.isRegSequence() or MI.isRegSequenceLike().
541	///
542	/// \note The generic implementation does not provide any support for
543	/// MI.isRegSequenceLike(). In other words, one has to override
544	/// getRegSequenceLikeInputs for target specific instructions.
545	bool
546	getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
547	SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
548
549	/// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
550	/// and \p DefIdx.
551	/// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
552	/// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
553	/// - %1:sub1, sub0
554	///
555	/// \returns true if it is possible to build such an input sequence
556	/// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
557	/// False otherwise.
558	///
559	/// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
560	///
561	/// \note The generic implementation does not provide any support for
562	/// MI.isExtractSubregLike(). In other words, one has to override
563	/// getExtractSubregLikeInputs for target specific instructions.
564	bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
565	RegSubRegPairAndIdx &InputReg) const;
566
567	/// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
568	/// and \p DefIdx.
569	/// \p [out] BaseReg and \p [out] InsertedReg contain
570	/// the equivalent inputs of INSERT_SUBREG.
571	/// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
572	/// - BaseReg: %0:sub0
573	/// - InsertedReg: %1:sub1, sub3
574	///
575	/// \returns true if it is possible to build such an input sequence
576	/// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
577	/// False otherwise.
578	///
579	/// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
580	///
581	/// \note The generic implementation does not provide any support for
582	/// MI.isInsertSubregLike(). In other words, one has to override
583	/// getInsertSubregLikeInputs for target specific instructions.
584	bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
585	RegSubRegPair &BaseReg,
586	RegSubRegPairAndIdx &InsertedReg) const;
587
588	/// Return true if two machine instructions would produce identical values.
589	/// By default, this is only true when the two instructions
590	/// are deemed identical except for defs. If this function is called when the
591	/// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
592	/// aggressive checks.
593	virtual bool produceSameValue(const MachineInstr &MI0,
594	const MachineInstr &MI1,
595	const MachineRegisterInfo *MRI = nullptr) const;
596
597	/// \returns true if a branch from an instruction with opcode \p BranchOpc
598	/// bytes is capable of jumping to a position \p BrOffset bytes away.
599	virtual bool isBranchOffsetInRange(unsigned BranchOpc,
600	int64_t BrOffset) const {
601	llvm_unreachable("target did not implement");
602	}
603
604	/// \returns The block that branch instruction \p MI jumps to.
605	virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
606	llvm_unreachable("target did not implement");
607	}
608
609	/// Insert an unconditional indirect branch at the end of \p MBB to \p
610	/// NewDestBB. Optionally, insert the clobbered register restoring in \p
611	/// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
612	/// the offset of the position to insert the new branch.
613	virtual void insertIndirectBranch(MachineBasicBlock &MBB,
614	MachineBasicBlock &NewDestBB,
615	MachineBasicBlock &RestoreBB,
616	const DebugLoc &DL, int64_t BrOffset = 0,
617	RegScavenger *RS = nullptr) const {
618	llvm_unreachable("target did not implement");
619	}
620
621	/// Analyze the branching code at the end of MBB, returning
622	/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
623	/// implemented for a target). Upon success, this returns false and returns
624	/// with the following information in various cases:
625	///
626	/// 1. If this block ends with no branches (it just falls through to its succ)
627	/// just return false, leaving TBB/FBB null.
628	/// 2. If this block ends with only an unconditional branch, it sets TBB to be
629	/// the destination block.
630	/// 3. If this block ends with a conditional branch and it falls through to a
631	/// successor block, it sets TBB to be the branch destination block and a
632	/// list of operands that evaluate the condition. These operands can be
633	/// passed to other TargetInstrInfo methods to create new branches.
634	/// 4. If this block ends with a conditional branch followed by an
635	/// unconditional branch, it returns the 'true' destination in TBB, the
636	/// 'false' destination in FBB, and a list of operands that evaluate the
637	/// condition. These operands can be passed to other TargetInstrInfo
638	/// methods to create new branches.
639	///
640	/// Note that removeBranch and insertBranch must be implemented to support
641	/// cases where this method returns success.
642	///
643	/// If AllowModify is true, then this routine is allowed to modify the basic
644	/// block (e.g. delete instructions after the unconditional branch).
645	///
646	/// The CFG information in MBB.Predecessors and MBB.Successors must be valid
647	/// before calling this function.
648	virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
649	MachineBasicBlock *&FBB,
650	SmallVectorImpl<MachineOperand> &Cond,
651	bool AllowModify = false) const {
652	return true;
653	}
654
655	/// Represents a predicate at the MachineFunction level. The control flow a
656	/// MachineBranchPredicate represents is:
657	///
658	/// Reg = LHS `Predicate` RHS == ConditionDef
659	/// if Reg then goto TrueDest else goto FalseDest
660	///
661	struct MachineBranchPredicate {
662	enum ComparePredicate {
663	PRED_EQ, // True if two values are equal
664	PRED_NE, // True if two values are not equal
665	PRED_INVALID // Sentinel value
666	};
667
668	ComparePredicate Predicate = PRED_INVALID;
669	MachineOperand LHS = MachineOperand::CreateImm(Val: 0);
670	MachineOperand RHS = MachineOperand::CreateImm(Val: 0);
671	MachineBasicBlock *TrueDest = nullptr;
672	MachineBasicBlock *FalseDest = nullptr;
673	MachineInstr *ConditionDef = nullptr;
674
675	/// SingleUseCondition is true if ConditionDef is dead except for the
676	/// branch(es) at the end of the basic block.
677	///
678	bool SingleUseCondition = false;
679
680	explicit MachineBranchPredicate() = default;
681	};
682
683	/// Analyze the branching code at the end of MBB and parse it into the
684	/// MachineBranchPredicate structure if possible. Returns false on success
685	/// and true on failure.
686	///
687	/// If AllowModify is true, then this routine is allowed to modify the basic
688	/// block (e.g. delete instructions after the unconditional branch).
689	///
690	virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
691	MachineBranchPredicate &MBP,
692	bool AllowModify = false) const {
693	return true;
694	}
695
696	/// Remove the branching code at the end of the specific MBB.
697	/// This is only invoked in cases where analyzeBranch returns success. It
698	/// returns the number of instructions that were removed.
699	/// If \p BytesRemoved is non-null, report the change in code size from the
700	/// removed instructions.
701	virtual unsigned removeBranch(MachineBasicBlock &MBB,
702	int *BytesRemoved = nullptr) const {
703	llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
704	}
705
706	/// Insert branch code into the end of the specified MachineBasicBlock. The
707	/// operands to this method are the same as those returned by analyzeBranch.
708	/// This is only invoked in cases where analyzeBranch returns success. It
709	/// returns the number of instructions inserted. If \p BytesAdded is non-null,
710	/// report the change in code size from the added instructions.
711	///
712	/// It is also invoked by tail merging to add unconditional branches in
713	/// cases where analyzeBranch doesn't apply because there was no original
714	/// branch to analyze. At least this much must be implemented, else tail
715	/// merging needs to be disabled.
716	///
717	/// The CFG information in MBB.Predecessors and MBB.Successors must be valid
718	/// before calling this function.
719	virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
720	MachineBasicBlock *FBB,
721	ArrayRef<MachineOperand> Cond,
722	const DebugLoc &DL,
723	int *BytesAdded = nullptr) const {
724	llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
725	}
726
727	unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
728	MachineBasicBlock *DestBB,
729	const DebugLoc &DL,
730	int *BytesAdded = nullptr) const {
731	return insertBranch(MBB, TBB: DestBB, FBB: nullptr, Cond: ArrayRef<MachineOperand>(), DL,
732	BytesAdded);
733	}
734
735	/// Object returned by analyzeLoopForPipelining. Allows software pipelining
736	/// implementations to query attributes of the loop being pipelined and to
737	/// apply target-specific updates to the loop once pipelining is complete.
738	class PipelinerLoopInfo {
739	public:
740	virtual ~PipelinerLoopInfo();
741	/// Return true if the given instruction should not be pipelined and should
742	/// be ignored. An example could be a loop comparison, or induction variable
743	/// update with no users being pipelined.
744	virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
745
746	/// Return true if the proposed schedule should used. Otherwise return
747	/// false to not pipeline the loop. This function should be used to ensure
748	/// that pipelined loops meet target-specific quality heuristics.
749	virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS) {
750	return true;
751	}
752
753	/// Create a condition to determine if the trip count of the loop is greater
754	/// than TC, where TC is always one more than for the previous prologue or
755	/// 0 if this is being called for the outermost prologue.
756	///
757	/// If the trip count is statically known to be greater than TC, return
758	/// true. If the trip count is statically known to be not greater than TC,
759	/// return false. Otherwise return nullopt and fill out Cond with the test
760	/// condition.
761	///
762	/// Note: This hook is guaranteed to be called from the innermost to the
763	/// outermost prologue of the loop being software pipelined.
764	virtual std::optional<bool>
765	createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
766	SmallVectorImpl<MachineOperand> &Cond) = 0;
767
768	/// Modify the loop such that the trip count is
769	/// OriginalTC + TripCountAdjust.
770	virtual void adjustTripCount(int TripCountAdjust) = 0;
771
772	/// Called when the loop's preheader has been modified to NewPreheader.
773	virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
774
775	/// Called when the loop is being removed. Any instructions in the preheader
776	/// should be removed.
777	///
778	/// Once this function is called, no other functions on this object are
779	/// valid; the loop has been removed.
780	virtual void disposed() = 0;
781	};
782
783	/// Analyze loop L, which must be a single-basic-block loop, and if the
784	/// conditions can be understood enough produce a PipelinerLoopInfo object.
785	virtual std::unique_ptr<PipelinerLoopInfo>
786	analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
787	return nullptr;
788	}
789
790	/// Analyze the loop code, return true if it cannot be understood. Upon
791	/// success, this function returns false and returns information about the
792	/// induction variable and compare instruction used at the end.
793	virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
794	MachineInstr *&CmpInst) const {
795	return true;
796	}
797
798	/// Generate code to reduce the loop iteration by one and check if the loop
799	/// is finished. Return the value/register of the new loop count. We need
800	/// this function when peeling off one or more iterations of a loop. This
801	/// function assumes the nth iteration is peeled first.
802	virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
803	MachineBasicBlock &PreHeader,
804	MachineInstr *IndVar, MachineInstr &Cmp,
805	SmallVectorImpl<MachineOperand> &Cond,
806	SmallVectorImpl<MachineInstr *> &PrevInsts,
807	unsigned Iter, unsigned MaxIter) const {
808	llvm_unreachable("Target didn't implement ReduceLoopCount");
809	}
810
811	/// Delete the instruction OldInst and everything after it, replacing it with
812	/// an unconditional branch to NewDest. This is used by the tail merging pass.
813	virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
814	MachineBasicBlock *NewDest) const;
815
816	/// Return true if it's legal to split the given basic
817	/// block at the specified instruction (i.e. instruction would be the start
818	/// of a new basic block).
819	virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
820	MachineBasicBlock::iterator MBBI) const {
821	return true;
822	}
823
824	/// Return true if it's profitable to predicate
825	/// instructions with accumulated instruction latency of "NumCycles"
826	/// of the specified basic block, where the probability of the instructions
827	/// being executed is given by Probability, and Confidence is a measure
828	/// of our confidence that it will be properly predicted.
829	virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
830	unsigned ExtraPredCycles,
831	BranchProbability Probability) const {
832	return false;
833	}
834
835	/// Second variant of isProfitableToIfCvt. This one
836	/// checks for the case where two basic blocks from true and false path
837	/// of a if-then-else (diamond) are predicated on mutually exclusive
838	/// predicates, where the probability of the true path being taken is given
839	/// by Probability, and Confidence is a measure of our confidence that it
840	/// will be properly predicted.
841	virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
842	unsigned ExtraTCycles,
843	MachineBasicBlock &FMBB, unsigned NumFCycles,
844	unsigned ExtraFCycles,
845	BranchProbability Probability) const {
846	return false;
847	}
848
849	/// Return true if it's profitable for if-converter to duplicate instructions
850	/// of specified accumulated instruction latencies in the specified MBB to
851	/// enable if-conversion.
852	/// The probability of the instructions being executed is given by
853	/// Probability, and Confidence is a measure of our confidence that it
854	/// will be properly predicted.
855	virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
856	unsigned NumCycles,
857	BranchProbability Probability) const {
858	return false;
859	}
860
861	/// Return the increase in code size needed to predicate a contiguous run of
862	/// NumInsts instructions.
863	virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
864	unsigned NumInsts) const {
865	return 0;
866	}
867
868	/// Return an estimate for the code size reduction (in bytes) which will be
869	/// caused by removing the given branch instruction during if-conversion.
870	virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
871	return getInstSizeInBytes(MI);
872	}
873
874	/// Return true if it's profitable to unpredicate
875	/// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
876	/// exclusive predicates.
877	/// e.g.
878	/// subeq r0, r1, #1
879	/// addne r0, r1, #1
880	/// =>
881	/// sub r0, r1, #1
882	/// addne r0, r1, #1
883	///
884	/// This may be profitable is conditional instructions are always executed.
885	virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
886	MachineBasicBlock &FMBB) const {
887	return false;
888	}
889
890	/// Return true if it is possible to insert a select
891	/// instruction that chooses between TrueReg and FalseReg based on the
892	/// condition code in Cond.
893	///
894	/// When successful, also return the latency in cycles from TrueReg,
895	/// FalseReg, and Cond to the destination register. In most cases, a select
896	/// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
897	///
898	/// Some x86 implementations have 2-cycle cmov instructions.
899	///
900	/// @param MBB Block where select instruction would be inserted.
901	/// @param Cond Condition returned by analyzeBranch.
902	/// @param DstReg Virtual dest register that the result should write to.
903	/// @param TrueReg Virtual register to select when Cond is true.
904	/// @param FalseReg Virtual register to select when Cond is false.
905	/// @param CondCycles Latency from Cond+Branch to select output.
906	/// @param TrueCycles Latency from TrueReg to select output.
907	/// @param FalseCycles Latency from FalseReg to select output.
908	virtual bool canInsertSelect(const MachineBasicBlock &MBB,
909	ArrayRef<MachineOperand> Cond, Register DstReg,
910	Register TrueReg, Register FalseReg,
911	int &CondCycles, int &TrueCycles,
912	int &FalseCycles) const {
913	return false;
914	}
915
916	/// Insert a select instruction into MBB before I that will copy TrueReg to
917	/// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
918	///
919	/// This function can only be called after canInsertSelect() returned true.
920	/// The condition in Cond comes from analyzeBranch, and it can be assumed
921	/// that the same flags or registers required by Cond are available at the
922	/// insertion point.
923	///
924	/// @param MBB Block where select instruction should be inserted.
925	/// @param I Insertion point.
926	/// @param DL Source location for debugging.
927	/// @param DstReg Virtual register to be defined by select instruction.
928	/// @param Cond Condition as computed by analyzeBranch.
929	/// @param TrueReg Virtual register to copy when Cond is true.
930	/// @param FalseReg Virtual register to copy when Cons is false.
931	virtual void insertSelect(MachineBasicBlock &MBB,
932	MachineBasicBlock::iterator I, const DebugLoc &DL,
933	Register DstReg, ArrayRef<MachineOperand> Cond,
934	Register TrueReg, Register FalseReg) const {
935	llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
936	}
937
938	/// Analyze the given select instruction, returning true if
939	/// it cannot be understood. It is assumed that MI->isSelect() is true.
940	///
941	/// When successful, return the controlling condition and the operands that
942	/// determine the true and false result values.
943	///
944	/// Result = SELECT Cond, TrueOp, FalseOp
945	///
946	/// Some targets can optimize select instructions, for example by predicating
947	/// the instruction defining one of the operands. Such targets should set
948	/// Optimizable.
949	///
950	/// @param MI Select instruction to analyze.
951	/// @param Cond Condition controlling the select.
952	/// @param TrueOp Operand number of the value selected when Cond is true.
953	/// @param FalseOp Operand number of the value selected when Cond is false.
954	/// @param Optimizable Returned as true if MI is optimizable.
955	/// @returns False on success.
956	virtual bool analyzeSelect(const MachineInstr &MI,
957	SmallVectorImpl<MachineOperand> &Cond,
958	unsigned &TrueOp, unsigned &FalseOp,
959	bool &Optimizable) const {
960	assert(MI.getDesc().isSelect() && "MI must be a select instruction");
961	return true;
962	}
963
964	/// Given a select instruction that was understood by
965	/// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
966	/// merging it with one of its operands. Returns NULL on failure.
967	///
968	/// When successful, returns the new select instruction. The client is
969	/// responsible for deleting MI.
970	///
971	/// If both sides of the select can be optimized, PreferFalse is used to pick
972	/// a side.
973	///
974	/// @param MI Optimizable select instruction.
975	/// @param NewMIs Set that record all MIs in the basic block up to \p
976	/// MI. Has to be updated with any newly created MI or deleted ones.
977	/// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
978	/// @returns Optimized instruction or NULL.
979	virtual MachineInstr *optimizeSelect(MachineInstr &MI,
980	SmallPtrSetImpl<MachineInstr *> &NewMIs,
981	bool PreferFalse = false) const {
982	// This function must be implemented if Optimizable is ever set.
983	llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
984	}
985
986	/// Emit instructions to copy a pair of physical registers.
987	///
988	/// This function should support copies within any legal register class as
989	/// well as any cross-class copies created during instruction selection.
990	///
991	/// The source and destination registers may overlap, which may require a
992	/// careful implementation when multiple copy instructions are required for
993	/// large registers. See for example the ARM target.
994	virtual void copyPhysReg(MachineBasicBlock &MBB,
995	MachineBasicBlock::iterator MI, const DebugLoc &DL,
996	MCRegister DestReg, MCRegister SrcReg,
997	bool KillSrc) const {
998	llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
999	}
1000
1001	/// Allow targets to tell MachineVerifier whether a specific register
1002	/// MachineOperand can be used as part of PC-relative addressing.
1003	/// PC-relative addressing modes in many CISC architectures contain
1004	/// (non-PC) registers as offsets or scaling values, which inherently
1005	/// tags the corresponding MachineOperand with OPERAND_PCREL.
1006	///
1007	/// @param MO The MachineOperand in question. MO.isReg() should always
1008	/// be true.
1009	/// @return Whether this operand is allowed to be used PC-relatively.
1010	virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
1011	return false;
1012	}
1013
1014	/// Return an index for MachineJumpTableInfo if \p insn is an indirect jump
1015	/// using a jump table, otherwise -1.
1016	virtual int getJumpTableIndex(const MachineInstr &MI) const { return -1; }
1017
1018	protected:
1019	/// Target-dependent implementation for IsCopyInstr.
1020	/// If the specific machine instruction is a instruction that moves/copies
1021	/// value from one register to another register return destination and source
1022	/// registers as machine operands.
1023	virtual std::optional<DestSourcePair>
1024	isCopyInstrImpl(const MachineInstr &MI) const {
1025	return std::nullopt;
1026	}
1027
1028	virtual std::optional<DestSourcePair>
1029	isCopyLikeInstrImpl(const MachineInstr &MI) const {
1030	return std::nullopt;
1031	}
1032
1033	/// Return true if the given terminator MI is not expected to spill. This
1034	/// sets the live interval as not spillable and adjusts phi node lowering to
1035	/// not introduce copies after the terminator. Use with care, these are
1036	/// currently used for hardware loop intrinsics in very controlled situations,
1037	/// created prior to registry allocation in loops that only have single phi
1038	/// users for the terminators value. They may run out of registers if not used
1039	/// carefully.
1040	virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
1041	return false;
1042	}
1043
1044	public:
1045	/// If the specific machine instruction is a instruction that moves/copies
1046	/// value from one register to another register return destination and source
1047	/// registers as machine operands.
1048	/// For COPY-instruction the method naturally returns destination and source
1049	/// registers as machine operands, for all other instructions the method calls
1050	/// target-dependent implementation.
1051	std::optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
1052	if (MI.isCopy()) {
1053	return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
1054	}
1055	return isCopyInstrImpl(MI);
1056	}
1057
1058	// Similar to `isCopyInstr`, but adds non-copy semantics on MIR, but
1059	// ultimately generates a copy instruction.
1060	std::optional<DestSourcePair> isCopyLikeInstr(const MachineInstr &MI) const {
1061	if (auto IsCopyInstr = isCopyInstr(MI))
1062	return IsCopyInstr;
1063	return isCopyLikeInstrImpl(MI);
1064	}
1065
1066	bool isFullCopyInstr(const MachineInstr &MI) const {
1067	auto DestSrc = isCopyInstr(MI);
1068	if (!DestSrc)
1069	return false;
1070
1071	const MachineOperand *DestRegOp = DestSrc->Destination;
1072	const MachineOperand *SrcRegOp = DestSrc->Source;
1073	return !DestRegOp->getSubReg() && !SrcRegOp->getSubReg();
1074	}
1075
1076	/// If the specific machine instruction is an instruction that adds an
1077	/// immediate value and a register, and stores the result in the given
1078	/// register \c Reg, return a pair of the source register and the offset
1079	/// which has been added.
1080	virtual std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
1081	Register Reg) const {
1082	return std::nullopt;
1083	}
1084
1085	/// Returns true if MI is an instruction that defines Reg to have a constant
1086	/// value and the value is recorded in ImmVal. The ImmVal is a result that
1087	/// should be interpreted as modulo size of Reg.
1088	virtual bool getConstValDefinedInReg(const MachineInstr &MI,
1089	const Register Reg,
1090	int64_t &ImmVal) const {
1091	return false;
1092	}
1093
1094	/// Store the specified register of the given register class to the specified
1095	/// stack frame index. The store instruction is to be added to the given
1096	/// machine basic block before the specified machine instruction. If isKill
1097	/// is true, the register operand is the last use and must be marked kill. If
1098	/// \p SrcReg is being directly spilled as part of assigning a virtual
1099	/// register, \p VReg is the register being assigned. This additional register
1100	/// argument is needed for certain targets when invoked from RegAllocFast to
1101	/// map the spilled physical register to its virtual register. A null register
1102	/// can be passed elsewhere.
1103	virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
1104	MachineBasicBlock::iterator MI,
1105	Register SrcReg, bool isKill, int FrameIndex,
1106	const TargetRegisterClass *RC,
1107	const TargetRegisterInfo *TRI,
1108	Register VReg) const {
1109	llvm_unreachable("Target didn't implement "
1110	"TargetInstrInfo::storeRegToStackSlot!");
1111	}
1112
1113	/// Load the specified register of the given register class from the specified
1114	/// stack frame index. The load instruction is to be added to the given
1115	/// machine basic block before the specified machine instruction. If \p
1116	/// DestReg is being directly reloaded as part of assigning a virtual
1117	/// register, \p VReg is the register being assigned. This additional register
1118	/// argument is needed for certain targets when invoked from RegAllocFast to
1119	/// map the loaded physical register to its virtual register. A null register
1120	/// can be passed elsewhere.
1121	virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
1122	MachineBasicBlock::iterator MI,
1123	Register DestReg, int FrameIndex,
1124	const TargetRegisterClass *RC,
1125	const TargetRegisterInfo *TRI,
1126	Register VReg) const {
1127	llvm_unreachable("Target didn't implement "
1128	"TargetInstrInfo::loadRegFromStackSlot!");
1129	}
1130
1131	/// This function is called for all pseudo instructions
1132	/// that remain after register allocation. Many pseudo instructions are
1133	/// created to help register allocation. This is the place to convert them
1134	/// into real instructions. The target can edit MI in place, or it can insert
1135	/// new instructions and erase MI. The function should return true if
1136	/// anything was changed.
1137	virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1138
1139	/// Check whether the target can fold a load that feeds a subreg operand
1140	/// (or a subreg operand that feeds a store).
1141	/// For example, X86 may want to return true if it can fold
1142	/// movl (%esp), %eax
1143	/// subb, %al, ...
1144	/// Into:
1145	/// subb (%esp), ...
1146	///
1147	/// Ideally, we'd like the target implementation of foldMemoryOperand() to
1148	/// reject subregs - but since this behavior used to be enforced in the
1149	/// target-independent code, moving this responsibility to the targets
1150	/// has the potential of causing nasty silent breakage in out-of-tree targets.
1151	virtual bool isSubregFoldable() const { return false; }
1152
1153	/// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1154	/// operands which can't be folded into stack references. Operands outside
1155	/// of the range are most likely foldable but it is not guaranteed.
1156	/// These instructions are unique in that stack references for some operands
1157	/// have the same execution cost (e.g. none) as the unfolded register forms.
1158	/// The ranged return is guaranteed to include all operands which can't be
1159	/// folded at zero cost.
1160	virtual std::pair<unsigned, unsigned>
1161	getPatchpointUnfoldableRange(const MachineInstr &MI) const;
1162
1163	/// Attempt to fold a load or store of the specified stack
1164	/// slot into the specified machine instruction for the specified operand(s).
1165	/// If this is possible, a new instruction is returned with the specified
1166	/// operand folded, otherwise NULL is returned.
1167	/// The new instruction is inserted before MI, and the client is responsible
1168	/// for removing the old instruction.
1169	/// If VRM is passed, the assigned physregs can be inspected by target to
1170	/// decide on using an opcode (note that those assignments can still change).
1171	MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
1172	int FI,
1173	LiveIntervals *LIS = nullptr,
1174	VirtRegMap *VRM = nullptr) const;
1175
1176	/// Same as the previous version except it allows folding of any load and
1177	/// store from / to any address, not just from a specific stack slot.
1178	MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
1179	MachineInstr &LoadMI,
1180	LiveIntervals *LIS = nullptr) const;
1181
1182	/// This function defines the logic to lower COPY instruction to
1183	/// target specific instruction(s).
1184	void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const;
1185
1186	/// Return true when there is potentially a faster code sequence
1187	/// for an instruction chain ending in \p Root. All potential patterns are
1188	/// returned in the \p Pattern vector. Pattern should be sorted in priority
1189	/// order since the pattern evaluator stops checking as soon as it finds a
1190	/// faster sequence.
1191	/// \param Root - Instruction that could be combined with one of its operands
1192	/// \param Patterns - Vector of possible combination patterns
1193	virtual bool
1194	getMachineCombinerPatterns(MachineInstr &Root,
1195	SmallVectorImpl<MachineCombinerPattern> &Patterns,
1196	bool DoRegPressureReduce) const;
1197
1198	/// Return true if target supports reassociation of instructions in machine
1199	/// combiner pass to reduce register pressure for a given BB.
1200	virtual bool
1201	shouldReduceRegisterPressure(const MachineBasicBlock *MBB,
1202	const RegisterClassInfo *RegClassInfo) const {
1203	return false;
1204	}
1205
1206	/// Fix up the placeholder we may add in genAlternativeCodeSequence().
1207	virtual void
1208	finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
1209	SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1210
1211	/// Return true when a code sequence can improve throughput. It
1212	/// should be called only for instructions in loops.
1213	/// \param Pattern - combiner pattern
1214	virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
1215
1216	/// Return true if the input \P Inst is part of a chain of dependent ops
1217	/// that are suitable for reassociation, otherwise return false.
1218	/// If the instruction's operands must be commuted to have a previous
1219	/// instruction of the same type define the first source operand, \P Commuted
1220	/// will be set to true.
1221	bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1222
1223	/// Return true when \P Inst is both associative and commutative. If \P Invert
1224	/// is true, then the inverse of \P Inst operation must be tested.
1225	virtual bool isAssociativeAndCommutative(const MachineInstr &Inst,
1226	bool Invert = false) const {
1227	return false;
1228	}
1229
1230	/// Return the inverse operation opcode if it exists for \P Opcode (e.g. add
1231	/// for sub and vice versa).
1232	virtual std::optional<unsigned> getInverseOpcode(unsigned Opcode) const {
1233	return std::nullopt;
1234	}
1235
1236	/// Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
1237	bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
1238
1239	/// Return true when \P Inst has reassociable operands in the same \P MBB.
1240	virtual bool hasReassociableOperands(const MachineInstr &Inst,
1241	const MachineBasicBlock *MBB) const;
1242
1243	/// Return true when \P Inst has reassociable sibling.
1244	virtual bool hasReassociableSibling(const MachineInstr &Inst,
1245	bool &Commuted) const;
1246
1247	/// When getMachineCombinerPatterns() finds patterns, this function generates
1248	/// the instructions that could replace the original code sequence. The client
1249	/// has to decide whether the actual replacement is beneficial or not.
1250	/// \param Root - Instruction that could be combined with one of its operands
1251	/// \param Pattern - Combination pattern for Root
1252	/// \param InsInstrs - Vector of new instructions that implement P
1253	/// \param DelInstrs - Old instructions, including Root, that could be
1254	/// replaced by InsInstr
1255	/// \param InstIdxForVirtReg - map of virtual register to instruction in
1256	/// InsInstr that defines it
1257	virtual void genAlternativeCodeSequence(
1258	MachineInstr &Root, MachineCombinerPattern Pattern,
1259	SmallVectorImpl<MachineInstr *> &InsInstrs,
1260	SmallVectorImpl<MachineInstr *> &DelInstrs,
1261	DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1262
1263	/// When calculate the latency of the root instruction, accumulate the
1264	/// latency of the sequence to the root latency.
1265	/// \param Root - Instruction that could be combined with one of its operands
1266	virtual bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const {
1267	return true;
1268	}
1269
1270	/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1271	/// reduce critical path length.
1272	void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1273	MachineCombinerPattern Pattern,
1274	SmallVectorImpl<MachineInstr *> &InsInstrs,
1275	SmallVectorImpl<MachineInstr *> &DelInstrs,
1276	DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1277
1278	/// Reassociation of some instructions requires inverse operations (e.g.
1279	/// (X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes
1280	/// (new root opcode, new prev opcode) that must be used to reassociate \P
1281	/// Root and \P Prev accoring to \P Pattern.
1282	std::pair<unsigned, unsigned>
1283	getReassociationOpcodes(MachineCombinerPattern Pattern,
1284	const MachineInstr &Root,
1285	const MachineInstr &Prev) const;
1286
1287	/// The limit on resource length extension we accept in MachineCombiner Pass.
1288	virtual int getExtendResourceLenLimit() const { return 0; }
1289
1290	/// This is an architecture-specific helper function of reassociateOps.
1291	/// Set special operand attributes for new instructions after reassociation.
1292	virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1293	MachineInstr &NewMI1,
1294	MachineInstr &NewMI2) const {}
1295
1296	/// Return true when a target supports MachineCombiner.
1297	virtual bool useMachineCombiner() const { return false; }
1298
1299	/// Return a strategy that MachineCombiner must use when creating traces.
1300	virtual MachineTraceStrategy getMachineCombinerTraceStrategy() const;
1301
1302	/// Return true if the given SDNode can be copied during scheduling
1303	/// even if it has glue.
1304	virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1305
1306	protected:
1307	/// Target-dependent implementation for foldMemoryOperand.
1308	/// Target-independent code in foldMemoryOperand will
1309	/// take care of adding a MachineMemOperand to the newly created instruction.
1310	/// The instruction and any auxiliary instructions necessary will be inserted
1311	/// at InsertPt.
1312	virtual MachineInstr *
1313	foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1314	ArrayRef<unsigned> Ops,
1315	MachineBasicBlock::iterator InsertPt, int FrameIndex,
1316	LiveIntervals *LIS = nullptr,
1317	VirtRegMap *VRM = nullptr) const {
1318	return nullptr;
1319	}
1320
1321	/// Target-dependent implementation for foldMemoryOperand.
1322	/// Target-independent code in foldMemoryOperand will
1323	/// take care of adding a MachineMemOperand to the newly created instruction.
1324	/// The instruction and any auxiliary instructions necessary will be inserted
1325	/// at InsertPt.
1326	virtual MachineInstr *foldMemoryOperandImpl(
1327	MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1328	MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1329	LiveIntervals *LIS = nullptr) const {
1330	return nullptr;
1331	}
1332
1333	/// Target-dependent implementation of getRegSequenceInputs.
1334	///
1335	/// \returns true if it is possible to build the equivalent
1336	/// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1337	///
1338	/// \pre MI.isRegSequenceLike().
1339	///
1340	/// \see TargetInstrInfo::getRegSequenceInputs.
1341	virtual bool getRegSequenceLikeInputs(
1342	const MachineInstr &MI, unsigned DefIdx,
1343	SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1344	return false;
1345	}
1346
1347	/// Target-dependent implementation of getExtractSubregInputs.
1348	///
1349	/// \returns true if it is possible to build the equivalent
1350	/// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1351	///
1352	/// \pre MI.isExtractSubregLike().
1353	///
1354	/// \see TargetInstrInfo::getExtractSubregInputs.
1355	virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1356	unsigned DefIdx,
1357	RegSubRegPairAndIdx &InputReg) const {
1358	return false;
1359	}
1360
1361	/// Target-dependent implementation of getInsertSubregInputs.
1362	///
1363	/// \returns true if it is possible to build the equivalent
1364	/// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1365	///
1366	/// \pre MI.isInsertSubregLike().
1367	///
1368	/// \see TargetInstrInfo::getInsertSubregInputs.
1369	virtual bool
1370	getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1371	RegSubRegPair &BaseReg,
1372	RegSubRegPairAndIdx &InsertedReg) const {
1373	return false;
1374	}
1375
1376	public:
1377	/// unfoldMemoryOperand - Separate a single instruction which folded a load or
1378	/// a store or a load and a store into two or more instruction. If this is
1379	/// possible, returns true as well as the new instructions by reference.
1380	virtual bool
1381	unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1382	bool UnfoldLoad, bool UnfoldStore,
1383	SmallVectorImpl<MachineInstr *> &NewMIs) const {
1384	return false;
1385	}
1386
1387	virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1388	SmallVectorImpl<SDNode *> &NewNodes) const {
1389	return false;
1390	}
1391
1392	/// Returns the opcode of the would be new
1393	/// instruction after load / store are unfolded from an instruction of the
1394	/// specified opcode. It returns zero if the specified unfolding is not
1395	/// possible. If LoadRegIndex is non-null, it is filled in with the operand
1396	/// index of the operand which will hold the register holding the loaded
1397	/// value.
1398	virtual unsigned
1399	getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1400	unsigned *LoadRegIndex = nullptr) const {
1401	return 0;
1402	}
1403
1404	/// This is used by the pre-regalloc scheduler to determine if two loads are
1405	/// loading from the same base address. It should only return true if the base
1406	/// pointers are the same and the only differences between the two addresses
1407	/// are the offset. It also returns the offsets by reference.
1408	virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1409	int64_t &Offset1,
1410	int64_t &Offset2) const {
1411	return false;
1412	}
1413
1414	/// This is a used by the pre-regalloc scheduler to determine (in conjunction
1415	/// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1416	/// On some targets if two loads are loading from
1417	/// addresses in the same cache line, it's better if they are scheduled
1418	/// together. This function takes two integers that represent the load offsets
1419	/// from the common base address. It returns true if it decides it's desirable
1420	/// to schedule the two loads together. "NumLoads" is the number of loads that
1421	/// have already been scheduled after Load1.
1422	virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1423	int64_t Offset1, int64_t Offset2,
1424	unsigned NumLoads) const {
1425	return false;
1426	}
1427
1428	/// Get the base operand and byte offset of an instruction that reads/writes
1429	/// memory. This is a convenience function for callers that are only prepared
1430	/// to handle a single base operand.
1431	/// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style
1432	/// abstraction that supports negative offsets.
1433	bool getMemOperandWithOffset(const MachineInstr &MI,
1434	const MachineOperand *&BaseOp, int64_t &Offset,
1435	bool &OffsetIsScalable,
1436	const TargetRegisterInfo *TRI) const;
1437
1438	/// Get zero or more base operands and the byte offset of an instruction that
1439	/// reads/writes memory. Note that there may be zero base operands if the
1440	/// instruction accesses a constant address.
1441	/// It returns false if MI does not read/write memory.
1442	/// It returns false if base operands and offset could not be determined.
1443	/// It is not guaranteed to always recognize base operands and offsets in all
1444	/// cases.
1445	/// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style
1446	/// abstraction that supports negative offsets.
1447	virtual bool getMemOperandsWithOffsetWidth(
1448	const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
1449	int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1450	const TargetRegisterInfo *TRI) const {
1451	return false;
1452	}
1453
1454	/// Return true if the instruction contains a base register and offset. If
1455	/// true, the function also sets the operand position in the instruction
1456	/// for the base register and offset.
1457	virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1458	unsigned &BasePos,
1459	unsigned &OffsetPos) const {
1460	return false;
1461	}
1462
1463	/// Target dependent implementation to get the values constituting the address
1464	/// MachineInstr that is accessing memory. These values are returned as a
1465	/// struct ExtAddrMode which contains all relevant information to make up the
1466	/// address.
1467	virtual std::optional<ExtAddrMode>
1468	getAddrModeFromMemoryOp(const MachineInstr &MemI,
1469	const TargetRegisterInfo *TRI) const {
1470	return std::nullopt;
1471	}
1472
1473	/// Check if it's possible and beneficial to fold the addressing computation
1474	/// `AddrI` into the addressing mode of the load/store instruction `MemI`. The
1475	/// memory instruction is a user of the virtual register `Reg`, which in turn
1476	/// is the ultimate destination of zero or more COPY instructions from the
1477	/// output register of `AddrI`.
1478	/// Return the adddressing mode after folding in `AM`.
1479	virtual bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
1480	const MachineInstr &AddrI,
1481	ExtAddrMode &AM) const {
1482	return false;
1483	}
1484
1485	/// Emit a load/store instruction with the same value register as `MemI`, but
1486	/// using the address from `AM`. The addressing mode must have been obtained
1487	/// from `canFoldIntoAddr` for the same memory instruction.
1488	virtual MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
1489	const ExtAddrMode &AM) const {
1490	llvm_unreachable("target did not implement emitLdStWithAddr()");
1491	}
1492
1493	/// Returns true if MI's Def is NullValueReg, and the MI
1494	/// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1495	/// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1496	/// function can return true even if becomes zero. Specifically cases such as
1497	/// NullValueReg = shl NullValueReg, 63.
1498	virtual bool preservesZeroValueInReg(const MachineInstr *MI,
1499	const Register NullValueReg,
1500	const TargetRegisterInfo *TRI) const {
1501	return false;
1502	}
1503
1504	/// If the instruction is an increment of a constant value, return the amount.
1505	virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1506	return false;
1507	}
1508
1509	/// Returns true if the two given memory operations should be scheduled
1510	/// adjacent. Note that you have to add:
1511	/// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1512	/// or
1513	/// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1514	/// to TargetPassConfig::createMachineScheduler() to have an effect.
1515	///
1516	/// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1517	/// \p Offset1 and \p Offset2 are the byte offsets for the memory
1518	/// operations.
1519	/// \p OffsetIsScalable1 and \p OffsetIsScalable2 indicate if the offset is
1520	/// scaled by a runtime quantity.
1521	/// \p ClusterSize is the number of operations in the resulting load/store
1522	/// cluster if this hook returns true.
1523	/// \p NumBytes is the number of bytes that will be loaded from all the
1524	/// clustered loads if this hook returns true.
1525	virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
1526	int64_t Offset1, bool OffsetIsScalable1,
1527	ArrayRef<const MachineOperand *> BaseOps2,
1528	int64_t Offset2, bool OffsetIsScalable2,
1529	unsigned ClusterSize,
1530	unsigned NumBytes) const {
1531	llvm_unreachable("target did not implement shouldClusterMemOps()");
1532	}
1533
1534	/// Reverses the branch condition of the specified condition list,
1535	/// returning false on success and true if it cannot be reversed.
1536	virtual bool
1537	reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1538	return true;
1539	}
1540
1541	/// Insert a noop into the instruction stream at the specified point.
1542	virtual void insertNoop(MachineBasicBlock &MBB,
1543	MachineBasicBlock::iterator MI) const;
1544
1545	/// Insert noops into the instruction stream at the specified point.
1546	virtual void insertNoops(MachineBasicBlock &MBB,
1547	MachineBasicBlock::iterator MI,
1548	unsigned Quantity) const;
1549
1550	/// Return the noop instruction to use for a noop.
1551	virtual MCInst getNop() const;
1552
1553	/// Return true for post-incremented instructions.
1554	virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1555
1556	/// Returns true if the instruction is already predicated.
1557	virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1558
1559	/// Assumes the instruction is already predicated and returns true if the
1560	/// instruction can be predicated again.
1561	virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const {
1562	assert(isPredicated(MI) && "Instruction is not predicated");
1563	return false;
1564	}
1565
1566	// Returns a MIRPrinter comment for this machine operand.
1567	virtual std::string
1568	createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
1569	unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1570
1571	/// Returns true if the instruction is a
1572	/// terminator instruction that has not been predicated.
1573	bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1574
1575	/// Returns true if MI is an unconditional tail call.
1576	virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1577	return false;
1578	}
1579
1580	/// Returns true if the tail call can be made conditional on BranchCond.
1581	virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1582	const MachineInstr &TailCall) const {
1583	return false;
1584	}
1585
1586	/// Replace the conditional branch in MBB with a conditional tail call.
1587	virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1588	SmallVectorImpl<MachineOperand> &Cond,
1589	const MachineInstr &TailCall) const {
1590	llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1591	}
1592
1593	/// Convert the instruction into a predicated instruction.
1594	/// It returns true if the operation was successful.
1595	virtual bool PredicateInstruction(MachineInstr &MI,
1596	ArrayRef<MachineOperand> Pred) const;
1597
1598	/// Returns true if the first specified predicate
1599	/// subsumes the second, e.g. GE subsumes GT.
1600	virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1601	ArrayRef<MachineOperand> Pred2) const {
1602	return false;
1603	}
1604
1605	/// If the specified instruction defines any predicate
1606	/// or condition code register(s) used for predication, returns true as well
1607	/// as the definition predicate(s) by reference.
1608	/// SkipDead should be set to false at any point that dead
1609	/// predicate instructions should be considered as being defined.
1610	/// A dead predicate instruction is one that is guaranteed to be removed
1611	/// after a call to PredicateInstruction.
1612	virtual bool ClobbersPredicate(MachineInstr &MI,
1613	std::vector<MachineOperand> &Pred,
1614	bool SkipDead) const {
1615	return false;
1616	}
1617
1618	/// Return true if the specified instruction can be predicated.
1619	/// By default, this returns true for every instruction with a
1620	/// PredicateOperand.
1621	virtual bool isPredicable(const MachineInstr &MI) const {
1622	return MI.getDesc().isPredicable();
1623	}
1624
1625	/// Return true if it's safe to move a machine
1626	/// instruction that defines the specified register class.
1627	virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1628	return true;
1629	}
1630
1631	/// Test if the given instruction should be considered a scheduling boundary.
1632	/// This primarily includes labels and terminators.
1633	virtual bool isSchedulingBoundary(const MachineInstr &MI,
1634	const MachineBasicBlock *MBB,
1635	const MachineFunction &MF) const;
1636
1637	/// Measure the specified inline asm to determine an approximation of its
1638	/// length.
1639	virtual unsigned getInlineAsmLength(
1640	const char *Str, const MCAsmInfo &MAI,
1641	const TargetSubtargetInfo *STI = nullptr) const;
1642
1643	/// Allocate and return a hazard recognizer to use for this target when
1644	/// scheduling the machine instructions before register allocation.
1645	virtual ScheduleHazardRecognizer *
1646	CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1647	const ScheduleDAG *DAG) const;
1648
1649	/// Allocate and return a hazard recognizer to use for this target when
1650	/// scheduling the machine instructions before register allocation.
1651	virtual ScheduleHazardRecognizer *
1652	CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1653	const ScheduleDAGMI *DAG) const;
1654
1655	/// Allocate and return a hazard recognizer to use for this target when
1656	/// scheduling the machine instructions after register allocation.
1657	virtual ScheduleHazardRecognizer *
1658	CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1659	const ScheduleDAG *DAG) const;
1660
1661	/// Allocate and return a hazard recognizer to use for by non-scheduling
1662	/// passes.
1663	virtual ScheduleHazardRecognizer *
1664	CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1665	return nullptr;
1666	}
1667
1668	/// Provide a global flag for disabling the PreRA hazard recognizer that
1669	/// targets may choose to honor.
1670	bool usePreRAHazardRecognizer() const;
1671
1672	/// For a comparison instruction, return the source registers
1673	/// in SrcReg and SrcReg2 if having two register operands, and the value it
1674	/// compares against in CmpValue. Return true if the comparison instruction
1675	/// can be analyzed.
1676	virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1677	Register &SrcReg2, int64_t &Mask,
1678	int64_t &Value) const {
1679	return false;
1680	}
1681
1682	/// See if the comparison instruction can be converted
1683	/// into something more efficient. E.g., on ARM most instructions can set the
1684	/// flags register, obviating the need for a separate CMP.
1685	virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1686	Register SrcReg2, int64_t Mask,
1687	int64_t Value,
1688	const MachineRegisterInfo *MRI) const {
1689	return false;
1690	}
1691	virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1692
1693	/// Try to remove the load by folding it to a register operand at the use.
1694	/// We fold the load instructions if and only if the
1695	/// def and use are in the same BB. We only look at one load and see
1696	/// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1697	/// defined by the load we are trying to fold. DefMI returns the machine
1698	/// instruction that defines FoldAsLoadDefReg, and the function returns
1699	/// the machine instruction generated due to folding.
1700	virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1701	const MachineRegisterInfo *MRI,
1702	Register &FoldAsLoadDefReg,
1703	MachineInstr *&DefMI) const {
1704	return nullptr;
1705	}
1706
1707	/// 'Reg' is known to be defined by a move immediate instruction,
1708	/// try to fold the immediate into the use instruction.
1709	/// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1710	/// then the caller may assume that DefMI has been erased from its parent
1711	/// block. The caller may assume that it will not be erased by this
1712	/// function otherwise.
1713	virtual bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1714	Register Reg, MachineRegisterInfo *MRI) const {
1715	return false;
1716	}
1717
1718	/// Return the number of u-operations the given machine
1719	/// instruction will be decoded to on the target cpu. The itinerary's
1720	/// IssueWidth is the number of microops that can be dispatched each
1721	/// cycle. An instruction with zero microops takes no dispatch resources.
1722	virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1723	const MachineInstr &MI) const;
1724
1725	/// Return true for pseudo instructions that don't consume any
1726	/// machine resources in their current form. These are common cases that the
1727	/// scheduler should consider free, rather than conservatively handling them
1728	/// as instructions with no itinerary.
1729	bool isZeroCost(unsigned Opcode) const {
1730	return Opcode <= TargetOpcode::COPY;
1731	}
1732
1733	virtual std::optional<unsigned>
1734	getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode,
1735	unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1736
1737	/// Compute and return the use operand latency of a given pair of def and use.
1738	/// In most cases, the static scheduling itinerary was enough to determine the
1739	/// operand latency. But it may not be possible for instructions with variable
1740	/// number of defs / uses.
1741	///
1742	/// This is a raw interface to the itinerary that may be directly overridden
1743	/// by a target. Use computeOperandLatency to get the best estimate of
1744	/// latency.
1745	virtual std::optional<unsigned>
1746	getOperandLatency(const InstrItineraryData *ItinData,
1747	const MachineInstr &DefMI, unsigned DefIdx,
1748	const MachineInstr &UseMI, unsigned UseIdx) const;
1749
1750	/// Compute the instruction latency of a given instruction.
1751	/// If the instruction has higher cost when predicated, it's returned via
1752	/// PredCost.
1753	virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1754	const MachineInstr &MI,
1755	unsigned *PredCost = nullptr) const;
1756
1757	virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1758
1759	virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1760	SDNode *Node) const;
1761
1762	/// Return the default expected latency for a def based on its opcode.
1763	unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1764	const MachineInstr &DefMI) const;
1765
1766	/// Return true if this opcode has high latency to its result.
1767	virtual bool isHighLatencyDef(int opc) const { return false; }
1768
1769	/// Compute operand latency between a def of 'Reg'
1770	/// and a use in the current loop. Return true if the target considered
1771	/// it 'high'. This is used by optimization passes such as machine LICM to
1772	/// determine whether it makes sense to hoist an instruction out even in a
1773	/// high register pressure situation.
1774	virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1775	const MachineRegisterInfo *MRI,
1776	const MachineInstr &DefMI, unsigned DefIdx,
1777	const MachineInstr &UseMI,
1778	unsigned UseIdx) const {
1779	return false;
1780	}
1781
1782	/// Compute operand latency of a def of 'Reg'. Return true
1783	/// if the target considered it 'low'.
1784	virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1785	const MachineInstr &DefMI,
1786	unsigned DefIdx) const;
1787
1788	/// Perform target-specific instruction verification.
1789	virtual bool verifyInstruction(const MachineInstr &MI,
1790	StringRef &ErrInfo) const {
1791	return true;
1792	}
1793
1794	/// Return the current execution domain and bit mask of
1795	/// possible domains for instruction.
1796	///
1797	/// Some micro-architectures have multiple execution domains, and multiple
1798	/// opcodes that perform the same operation in different domains. For
1799	/// example, the x86 architecture provides the por, orps, and orpd
1800	/// instructions that all do the same thing. There is a latency penalty if a
1801	/// register is written in one domain and read in another.
1802	///
1803	/// This function returns a pair (domain, mask) containing the execution
1804	/// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1805	/// function can be used to change the opcode to one of the domains in the
1806	/// bit mask. Instructions whose execution domain can't be changed should
1807	/// return a 0 mask.
1808	///
1809	/// The execution domain numbers don't have any special meaning except domain
1810	/// 0 is used for instructions that are not associated with any interesting
1811	/// execution domain.
1812	///
1813	virtual std::pair<uint16_t, uint16_t>
1814	getExecutionDomain(const MachineInstr &MI) const {
1815	return std::make_pair(x: 0, y: 0);
1816	}
1817
1818	/// Change the opcode of MI to execute in Domain.
1819	///
1820	/// The bit (1 << Domain) must be set in the mask returned from
1821	/// getExecutionDomain(MI).
1822	virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1823
1824	/// Returns the preferred minimum clearance
1825	/// before an instruction with an unwanted partial register update.
1826	///
1827	/// Some instructions only write part of a register, and implicitly need to
1828	/// read the other parts of the register. This may cause unwanted stalls
1829	/// preventing otherwise unrelated instructions from executing in parallel in
1830	/// an out-of-order CPU.
1831	///
1832	/// For example, the x86 instruction cvtsi2ss writes its result to bits
1833	/// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1834	/// the instruction needs to wait for the old value of the register to become
1835	/// available:
1836	///
1837	/// addps %xmm1, %xmm0
1838	/// movaps %xmm0, (%rax)
1839	/// cvtsi2ss %rbx, %xmm0
1840	///
1841	/// In the code above, the cvtsi2ss instruction needs to wait for the addps
1842	/// instruction before it can issue, even though the high bits of %xmm0
1843	/// probably aren't needed.
1844	///
1845	/// This hook returns the preferred clearance before MI, measured in
1846	/// instructions. Other defs of MI's operand OpNum are avoided in the last N
1847	/// instructions before MI. It should only return a positive value for
1848	/// unwanted dependencies. If the old bits of the defined register have
1849	/// useful values, or if MI is determined to otherwise read the dependency,
1850	/// the hook should return 0.
1851	///
1852	/// The unwanted dependency may be handled by:
1853	///
1854	/// 1. Allocating the same register for an MI def and use. That makes the
1855	/// unwanted dependency identical to a required dependency.
1856	///
1857	/// 2. Allocating a register for the def that has no defs in the previous N
1858	/// instructions.
1859	///
1860	/// 3. Calling breakPartialRegDependency() with the same arguments. This
1861	/// allows the target to insert a dependency breaking instruction.
1862	///
1863	virtual unsigned
1864	getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1865	const TargetRegisterInfo *TRI) const {
1866	// The default implementation returns 0 for no partial register dependency.
1867	return 0;
1868	}
1869
1870	/// Return the minimum clearance before an instruction that reads an
1871	/// unused register.
1872	///
1873	/// For example, AVX instructions may copy part of a register operand into
1874	/// the unused high bits of the destination register.
1875	///
1876	/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1877	///
1878	/// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1879	/// false dependence on any previous write to %xmm0.
1880	///
1881	/// This hook works similarly to getPartialRegUpdateClearance, except that it
1882	/// does not take an operand index. Instead sets \p OpNum to the index of the
1883	/// unused register.
1884	virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1885	const TargetRegisterInfo *TRI) const {
1886	// The default implementation returns 0 for no undef register dependency.
1887	return 0;
1888	}
1889
1890	/// Insert a dependency-breaking instruction
1891	/// before MI to eliminate an unwanted dependency on OpNum.
1892	///
1893	/// If it wasn't possible to avoid a def in the last N instructions before MI
1894	/// (see getPartialRegUpdateClearance), this hook will be called to break the
1895	/// unwanted dependency.
1896	///
1897	/// On x86, an xorps instruction can be used as a dependency breaker:
1898	///
1899	/// addps %xmm1, %xmm0
1900	/// movaps %xmm0, (%rax)
1901	/// xorps %xmm0, %xmm0
1902	/// cvtsi2ss %rbx, %xmm0
1903	///
1904	/// An <imp-kill> operand should be added to MI if an instruction was
1905	/// inserted. This ties the instructions together in the post-ra scheduler.
1906	///
1907	virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1908	const TargetRegisterInfo *TRI) const {}
1909
1910	/// Create machine specific model for scheduling.
1911	virtual DFAPacketizer *
1912	CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1913	return nullptr;
1914	}
1915
1916	/// Sometimes, it is possible for the target
1917	/// to tell, even without aliasing information, that two MIs access different
1918	/// memory addresses. This function returns true if two MIs access different
1919	/// memory addresses and false otherwise.
1920	///
1921	/// Assumes any physical registers used to compute addresses have the same
1922	/// value for both instructions. (This is the most useful assumption for
1923	/// post-RA scheduling.)
1924	///
1925	/// See also MachineInstr::mayAlias, which is implemented on top of this
1926	/// function.
1927	virtual bool
1928	areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
1929	const MachineInstr &MIb) const {
1930	assert(MIa.mayLoadOrStore() &&
1931	"MIa must load from or modify a memory location");
1932	assert(MIb.mayLoadOrStore() &&
1933	"MIb must load from or modify a memory location");
1934	return false;
1935	}
1936
1937	/// Return the value to use for the MachineCSE's LookAheadLimit,
1938	/// which is a heuristic used for CSE'ing phys reg defs.
1939	virtual unsigned getMachineCSELookAheadLimit() const {
1940	// The default lookahead is small to prevent unprofitable quadratic
1941	// behavior.
1942	return 5;
1943	}
1944
1945	/// Return the maximal number of alias checks on memory operands. For
1946	/// instructions with more than one memory operands, the alias check on a
1947	/// single MachineInstr pair has quadratic overhead and results in
1948	/// unacceptable performance in the worst case. The limit here is to clamp
1949	/// that maximal checks performed. Usually, that's the product of memory
1950	/// operand numbers from that pair of MachineInstr to be checked. For
1951	/// instance, with two MachineInstrs with 4 and 5 memory operands
1952	/// correspondingly, a total of 20 checks are required. With this limit set to
1953	/// 16, their alias check is skipped. We choose to limit the product instead
1954	/// of the individual instruction as targets may have special MachineInstrs
1955	/// with a considerably high number of memory operands, such as `ldm` in ARM.
1956	/// Setting this limit per MachineInstr would result in either too high
1957	/// overhead or too rigid restriction.
1958	virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1959
1960	/// Return an array that contains the ids of the target indices (used for the
1961	/// TargetIndex machine operand) and their names.
1962	///
1963	/// MIR Serialization is able to serialize only the target indices that are
1964	/// defined by this method.
1965	virtual ArrayRef<std::pair<int, const char *>>
1966	getSerializableTargetIndices() const {
1967	return std::nullopt;
1968	}
1969
1970	/// Decompose the machine operand's target flags into two values - the direct
1971	/// target flag value and any of bit flags that are applied.
1972	virtual std::pair<unsigned, unsigned>
1973	decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1974	return std::make_pair(x: 0u, y: 0u);
1975	}
1976
1977	/// Return an array that contains the direct target flag values and their
1978	/// names.
1979	///
1980	/// MIR Serialization is able to serialize only the target flags that are
1981	/// defined by this method.
1982	virtual ArrayRef<std::pair<unsigned, const char *>>
1983	getSerializableDirectMachineOperandTargetFlags() const {
1984	return std::nullopt;
1985	}
1986
1987	/// Return an array that contains the bitmask target flag values and their
1988	/// names.
1989	///
1990	/// MIR Serialization is able to serialize only the target flags that are
1991	/// defined by this method.
1992	virtual ArrayRef<std::pair<unsigned, const char *>>
1993	getSerializableBitmaskMachineOperandTargetFlags() const {
1994	return std::nullopt;
1995	}
1996
1997	/// Return an array that contains the MMO target flag values and their
1998	/// names.
1999	///
2000	/// MIR Serialization is able to serialize only the MMO target flags that are
2001	/// defined by this method.
2002	virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
2003	getSerializableMachineMemOperandTargetFlags() const {
2004	return std::nullopt;
2005	}
2006
2007	/// Determines whether \p Inst is a tail call instruction. Override this
2008	/// method on targets that do not properly set MCID::Return and MCID::Call on
2009	/// tail call instructions."
2010	virtual bool isTailCall(const MachineInstr &Inst) const {
2011	return Inst.isReturn() && Inst.isCall();
2012	}
2013
2014	/// True if the instruction is bound to the top of its basic block and no
2015	/// other instructions shall be inserted before it. This can be implemented
2016	/// to prevent register allocator to insert spills for \p Reg before such
2017	/// instructions.
2018	virtual bool isBasicBlockPrologue(const MachineInstr &MI,
2019	Register Reg = Register()) const {
2020	return false;
2021	}
2022
2023	/// Allows targets to use appropriate copy instruction while spilitting live
2024	/// range of a register in register allocation.
2025	virtual unsigned getLiveRangeSplitOpcode(Register Reg,
2026	const MachineFunction &MF) const {
2027	return TargetOpcode::COPY;
2028	}
2029
2030	/// During PHI eleimination lets target to make necessary checks and
2031	/// insert the copy to the PHI destination register in a target specific
2032	/// manner.
2033	virtual MachineInstr *createPHIDestinationCopy(
2034	MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
2035	const DebugLoc &DL, Register Src, Register Dst) const {
2036	return BuildMI(BB&: MBB, I: InsPt, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: Dst)
2037	.addReg(RegNo: Src);
2038	}
2039
2040	/// During PHI eleimination lets target to make necessary checks and
2041	/// insert the copy to the PHI destination register in a target specific
2042	/// manner.
2043	virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
2044	MachineBasicBlock::iterator InsPt,
2045	const DebugLoc &DL, Register Src,
2046	unsigned SrcSubReg,
2047	Register Dst) const {
2048	return BuildMI(BB&: MBB, I: InsPt, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: Dst)
2049	.addReg(RegNo: Src, flags: 0, SubReg: SrcSubReg);
2050	}
2051
2052	/// Returns a \p outliner::OutlinedFunction struct containing target-specific
2053	/// information for a set of outlining candidates. Returns std::nullopt if the
2054	/// candidates are not suitable for outlining.
2055	virtual std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
2056	std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
2057	llvm_unreachable(
2058	"Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
2059	}
2060
2061	/// Optional target hook to create the LLVM IR attributes for the outlined
2062	/// function. If overridden, the overriding function must call the default
2063	/// implementation.
2064	virtual void mergeOutliningCandidateAttributes(
2065	Function &F, std::vector<outliner::Candidate> &Candidates) const;
2066
2067	protected:
2068	/// Target-dependent implementation for getOutliningTypeImpl.
2069	virtual outliner::InstrType
2070	getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
2071	llvm_unreachable(
2072	"Target didn't implement TargetInstrInfo::getOutliningTypeImpl!");
2073	}
2074
2075	public:
2076	/// Returns how or if \p MIT should be outlined. \p Flags is the
2077	/// target-specific information returned by isMBBSafeToOutlineFrom.
2078	outliner::InstrType
2079	getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const;
2080
2081	/// Optional target hook that returns true if \p MBB is safe to outline from,
2082	/// and returns any target-specific information in \p Flags.
2083	virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
2084	unsigned &Flags) const;
2085
2086	/// Optional target hook which partitions \p MBB into outlinable ranges for
2087	/// instruction mapping purposes. Each range is defined by two iterators:
2088	/// [start, end).
2089	///
2090	/// Ranges are expected to be ordered top-down. That is, ranges closer to the
2091	/// top of the block should come before ranges closer to the end of the block.
2092	///
2093	/// Ranges cannot overlap.
2094	///
2095	/// If an entire block is mappable, then its range is [MBB.begin(), MBB.end())
2096	///
2097	/// All instructions not present in an outlinable range are considered
2098	/// illegal.
2099	virtual SmallVector<
2100	std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
2101	getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const {
2102	return {std::make_pair(x: MBB.begin(), y: MBB.end())};
2103	}
2104
2105	/// Insert a custom frame for outlined functions.
2106	virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
2107	const outliner::OutlinedFunction &OF) const {
2108	llvm_unreachable(
2109	"Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
2110	}
2111
2112	/// Insert a call to an outlined function into the program.
2113	/// Returns an iterator to the spot where we inserted the call. This must be
2114	/// implemented by the target.
2115	virtual MachineBasicBlock::iterator
2116	insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
2117	MachineBasicBlock::iterator &It, MachineFunction &MF,
2118	outliner::Candidate &C) const {
2119	llvm_unreachable(
2120	"Target didn't implement TargetInstrInfo::insertOutlinedCall!");
2121	}
2122
2123	/// Insert an architecture-specific instruction to clear a register. If you
2124	/// need to avoid sideeffects (e.g. avoid XOR on x86, which sets EFLAGS), set
2125	/// \p AllowSideEffects to \p false.
2126	virtual void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
2127	MachineBasicBlock::iterator Iter,
2128	DebugLoc &DL,
2129	bool AllowSideEffects = true) const {
2130	#if 0
2131	// FIXME: This should exist once all platforms that use stack protectors
2132	// implements it.
2133	llvm_unreachable(
2134	"Target didn't implement TargetInstrInfo::buildClearRegister!");
2135	#endif
2136	}
2137
2138	/// Return true if the function can safely be outlined from.
2139	/// A function \p MF is considered safe for outlining if an outlined function
2140	/// produced from instructions in F will produce a program which produces the
2141	/// same output for any set of given inputs.
2142	virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
2143	bool OutlineFromLinkOnceODRs) const {
2144	llvm_unreachable("Target didn't implement "
2145	"TargetInstrInfo::isFunctionSafeToOutlineFrom!");
2146	}
2147
2148	/// Return true if the function should be outlined from by default.
2149	virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const {
2150	return false;
2151	}
2152
2153	/// Return true if the function is a viable candidate for machine function
2154	/// splitting. The criteria for if a function can be split may vary by target.
2155	virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const;
2156
2157	/// Return true if the MachineBasicBlock can safely be split to the cold
2158	/// section. On AArch64, certain instructions may cause a block to be unsafe
2159	/// to split to the cold section.
2160	virtual bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const {
2161	return true;
2162	}
2163
2164	/// Produce the expression describing the \p MI loading a value into
2165	/// the physical register \p Reg. This hook should only be used with
2166	/// \p MIs belonging to VReg-less functions.
2167	virtual std::optional<ParamLoadedValue>
2168	describeLoadedValue(const MachineInstr &MI, Register Reg) const;
2169
2170	/// Given the generic extension instruction \p ExtMI, returns true if this
2171	/// extension is a likely candidate for being folded into an another
2172	/// instruction.
2173	virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI,
2174	MachineRegisterInfo &MRI) const {
2175	return false;
2176	}
2177
2178	/// Return MIR formatter to format/parse MIR operands. Target can override
2179	/// this virtual function and return target specific MIR formatter.
2180	virtual const MIRFormatter *getMIRFormatter() const {
2181	if (!Formatter.get())
2182	Formatter = std::make_unique<MIRFormatter>();
2183	return Formatter.get();
2184	}
2185
2186	/// Returns the target-specific default value for tail duplication.
2187	/// This value will be used if the tail-dup-placement-threshold argument is
2188	/// not provided.
2189	virtual unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const {
2190	return OptLevel >= CodeGenOptLevel::Aggressive ? 4 : 2;
2191	}
2192
2193	/// Returns the callee operand from the given \p MI.
2194	virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
2195	return MI.getOperand(i: 0);
2196	}
2197
2198	/// Return the uniformity behavior of the given instruction.
2199	virtual InstructionUniformity
2200	getInstructionUniformity(const MachineInstr &MI) const {
2201	return InstructionUniformity::Default;
2202	}
2203
2204	/// Returns true if the given \p MI defines a TargetIndex operand that can be
2205	/// tracked by their offset, can have values, and can have debug info
2206	/// associated with it. If so, sets \p Index and \p Offset of the target index
2207	/// operand.
2208	virtual bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index,
2209	int64_t &Offset) const {
2210	return false;
2211	}
2212
2213	// Get the call frame size just before MI.
2214	unsigned getCallFrameSizeAt(MachineInstr &MI) const;
2215
2216	/// Fills in the necessary MachineOperands to refer to a frame index.
2217	/// The best way to understand this is to print `asm(""::"m"(x));` after
2218	/// finalize-isel. Example:
2219	/// INLINEASM ... 262190 /* mem:m */, %stack.0.x.addr, 1, $noreg, 0, $noreg
2220	/// we would add placeholders for: ^ ^ ^ ^
2221	virtual void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
2222	int FI) const {
2223	llvm_unreachable("unknown number of operands necessary");
2224	}
2225
2226	private:
2227	mutable std::unique_ptr<MIRFormatter> Formatter;
2228	unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
2229	unsigned CatchRetOpcode;
2230	unsigned ReturnOpcode;
2231	};
2232
2233	/// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2234	template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
2235	using RegInfo = DenseMapInfo<unsigned>;
2236
2237	static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
2238	return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2239	RegInfo::getEmptyKey());
2240	}
2241
2242	static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
2243	return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2244	RegInfo::getTombstoneKey());
2245	}
2246
2247	/// Reuse getHashValue implementation from
2248	/// std::pair<unsigned, unsigned>.
2249	static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2250	std::pair<unsigned, unsigned> PairVal = std::make_pair(x: Val.Reg, y: Val.SubReg);
2251	return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2252	}
2253
2254	static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
2255	const TargetInstrInfo::RegSubRegPair &RHS) {
2256	return RegInfo::isEqual(LHS: LHS.Reg, RHS: RHS.Reg) &&
2257	RegInfo::isEqual(LHS: LHS.SubReg, RHS: RHS.SubReg);
2258	}
2259	};
2260
2261	} // end namespace llvm
2262
2263	#endif // LLVM_CODEGEN_TARGETINSTRINFO_H
2264