1//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/StringRef.h"
21#include "llvm/ADT/iterator_range.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/RegisterBank.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/MC/LaneBitmask.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/Support/Compiler.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/MathExtras.h"
30#include "llvm/Support/Printable.h"
31#include <cassert>
32#include <cstdint>
33
34namespace llvm {
35
36class BitVector;
37class DIExpression;
38class LiveRegMatrix;
39class MachineFunction;
40class MachineInstr;
41class RegScavenger;
42class VirtRegMap;
43class LiveIntervals;
44class LiveInterval;
45class TargetRegisterClass {
46public:
47 using iterator = const MCPhysReg *;
48 using const_iterator = const MCPhysReg *;
49
50 // Instance variables filled by tablegen, do not use!
51 const MCRegisterClass *MC;
52 const uint32_t *SubClassMask;
53 const uint16_t *SuperRegIndices;
54 const LaneBitmask LaneMask;
55 /// Classes with a higher priority value are assigned first by register
56 /// allocators using a greedy heuristic. The value is in the range [0,31].
57 const uint8_t AllocationPriority;
58
59 // Change allocation priority heuristic used by greedy.
60 const bool GlobalPriority;
61
62 /// Configurable target specific flags.
63 const uint8_t TSFlags;
64 /// Whether the class supports two (or more) disjunct subregister indices.
65 const bool HasDisjunctSubRegs;
66 /// Whether a combination of subregisters can cover every register in the
67 /// class. See also the CoveredBySubRegs description in Target.td.
68 const bool CoveredBySubRegs;
69 const unsigned *SuperClasses;
70 const uint16_t SuperClassesSize;
71 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction &, bool Rev);
72
73 /// Return the register class ID number.
74 unsigned getID() const { return MC->getID(); }
75
76 /// begin/end - Return all of the registers in this class.
77 ///
78 iterator begin() const { return MC->begin(); }
79 iterator end() const { return MC->end(); }
80
81 /// Return the number of registers in this class.
82 unsigned getNumRegs() const { return MC->getNumRegs(); }
83
84 ArrayRef<MCPhysReg> getRegisters() const {
85 return ArrayRef(begin(), getNumRegs());
86 }
87
88 /// Return the specified register in the class.
89 MCRegister getRegister(unsigned i) const {
90 return MC->getRegister(i);
91 }
92
93 /// Return true if the specified register is included in this register class.
94 /// This does not include virtual registers.
95 bool contains(Register Reg) const {
96 /// FIXME: Historically this function has returned false when given vregs
97 /// but it should probably only receive physical registers
98 if (!Reg.isPhysical())
99 return false;
100 return MC->contains(Reg: Reg.asMCReg());
101 }
102
103 /// Return true if both registers are in this class.
104 bool contains(Register Reg1, Register Reg2) const {
105 /// FIXME: Historically this function has returned false when given a vregs
106 /// but it should probably only receive physical registers
107 if (!Reg1.isPhysical() || !Reg2.isPhysical())
108 return false;
109 return MC->contains(Reg1: Reg1.asMCReg(), Reg2: Reg2.asMCReg());
110 }
111
112 /// Return the cost of copying a value between two registers in this class.
113 /// A negative number means the register class is very expensive
114 /// to copy e.g. status flag register classes.
115 int getCopyCost() const { return MC->getCopyCost(); }
116
117 /// Return true if this register class may be used to create virtual
118 /// registers.
119 bool isAllocatable() const { return MC->isAllocatable(); }
120
121 /// Return true if this register class has a defined BaseClassOrder.
122 bool isBaseClass() const { return MC->isBaseClass(); }
123
124 /// Return true if the specified TargetRegisterClass
125 /// is a proper sub-class of this TargetRegisterClass.
126 bool hasSubClass(const TargetRegisterClass *RC) const {
127 return RC != this && hasSubClassEq(RC);
128 }
129
130 /// Returns true if RC is a sub-class of or equal to this class.
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
133 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
134 }
135
136 /// Return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(RC: this);
140 }
141
142 /// Returns true if RC is a super-class of or equal to this class.
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
144 return RC->hasSubClassEq(RC: this);
145 }
146
147 /// Returns a bit vector of subclasses, including this one.
148 /// The vector is indexed by class IDs.
149 ///
150 /// To use it, consider the returned array as a chunk of memory that
151 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
152 /// contains a bitset of the ID of the subclasses in big-endian style.
153
154 /// I.e., the representation of the memory from left to right at the
155 /// bit level looks like:
156 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
157 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
158 /// Where the number represents the class ID and XXX bits that
159 /// should be ignored.
160 ///
161 /// See the implementation of hasSubClassEq for an example of how it
162 /// can be used.
163 const uint32_t *getSubClassMask() const {
164 return SubClassMask;
165 }
166
167 /// Returns a 0-terminated list of sub-register indices that project some
168 /// super-register class into this register class. The list has an entry for
169 /// each Idx such that:
170 ///
171 /// There exists SuperRC where:
172 /// For all Reg in SuperRC:
173 /// this->contains(Reg:Idx)
174 const uint16_t *getSuperRegIndices() const {
175 return SuperRegIndices;
176 }
177
178 /// Returns a list of super-classes. The
179 /// classes are ordered by ID which is also a topological ordering from large
180 /// to small classes. The list does NOT include the current class.
181 ArrayRef<unsigned> superclasses() const {
182 return ArrayRef(SuperClasses, SuperClassesSize);
183 }
184
185 /// Return true if this TargetRegisterClass is a subset
186 /// class of at least one other TargetRegisterClass.
187 bool isASubClass() const { return SuperClasses != nullptr; }
188
189 /// Returns the preferred order for allocating registers from this register
190 /// class in MF. The raw order comes directly from the .td file and may
191 /// include reserved registers that are not allocatable.
192 /// Register allocators should also make sure to allocate
193 /// callee-saved registers only after all the volatiles are used. The
194 /// RegisterClassInfo class provides filtered allocation orders with
195 /// callee-saved registers moved to the end.
196 ///
197 /// The MachineFunction argument can be used to tune the allocatable
198 /// registers based on the characteristics of the function, subtarget, or
199 /// other criteria.
200 ///
201 /// By default, this method returns all registers in the class.
202 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF,
203 bool Rev = false) const {
204 return OrderFunc ? OrderFunc(MF, Rev) : getRegisters();
205 }
206
207 /// Returns the combination of all lane masks of register in this class.
208 /// The lane masks of the registers are the combination of all lane masks
209 /// of their subregisters. Returns 1 if there are no subregisters.
210 LaneBitmask getLaneMask() const {
211 return LaneMask;
212 }
213};
214
215/// Extra information, not in MCRegisterDesc, about registers.
216/// These are used by codegen, not by MC.
217struct TargetRegisterInfoDesc {
218 const uint8_t *CostPerUse; // Extra cost of instructions using register.
219 unsigned NumCosts; // Number of cost values associated with each register.
220 const bool
221 *InAllocatableClass; // Register belongs to an allocatable regclass.
222};
223
224/// Each TargetRegisterClass has a per register weight, and weight
225/// limit which must be less than the limits of its pressure sets.
226struct RegClassWeight {
227 unsigned RegWeight;
228 unsigned WeightLimit;
229};
230
231/// TargetRegisterInfo base class - We assume that the target defines a static
232/// array of TargetRegisterDesc objects that represent all of the machine
233/// registers that the target has. As such, we simply have to track a pointer
234/// to this array so that we can turn register number into a register
235/// descriptor.
236///
237class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
238public:
239 using regclass_iterator = const TargetRegisterClass * const *;
240 using vt_iterator = const MVT::SimpleValueType *;
241 struct RegClassInfo {
242 unsigned RegSize, SpillSize, SpillAlignment;
243 unsigned VTListOffset;
244 };
245
246 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
247 /// index, -1 in any being invalid.
248 struct SubRegCoveredBits {
249 uint16_t Offset;
250 uint16_t Size;
251 };
252
253private:
254 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
255 const char *const *SubRegIndexNames; // Names of subreg indexes.
256 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
257 // bit ranges array.
258
259 // Pointer to array of lane masks, one per sub-reg index.
260 const LaneBitmask *SubRegIndexLaneMasks;
261
262 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
263 LaneBitmask CoveringLanes;
264 const RegClassInfo *const RCInfos;
265 const MVT::SimpleValueType *const RCVTLists;
266 unsigned HwMode;
267
268protected:
269 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB,
270 regclass_iterator RCE, const char *const *SRINames,
271 const SubRegCoveredBits *SubIdxRanges,
272 const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes,
273 const RegClassInfo *const RCIs,
274 const MVT::SimpleValueType *const RCVTLists,
275 unsigned Mode = 0);
276 virtual ~TargetRegisterInfo();
277
278public:
279 /// Return the number of registers for the function. (may overestimate)
280 virtual unsigned getNumSupportedRegs(const MachineFunction &) const {
281 return getNumRegs();
282 }
283
284 // Register numbers can represent physical registers, virtual registers, and
285 // sometimes stack slots. The unsigned values are divided into these ranges:
286 //
287 // 0 Not a register, can be used as a sentinel.
288 // [1;2^30) Physical registers assigned by TableGen.
289 // [2^30;2^31) Stack slots. (Rarely used.)
290 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
291 //
292 // Further sentinels can be allocated from the small negative integers.
293 // DenseMapInfo<unsigned> uses -1u and -2u.
294
295 /// Return the size in bits of a register from class RC.
296 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const {
297 return TypeSize::getFixed(ExactSize: getRegClassInfo(RC).RegSize);
298 }
299
300 /// Return the size in bytes of the stack slot allocated to hold a spilled
301 /// copy of a register from class RC.
302 unsigned getSpillSize(const TargetRegisterClass &RC) const {
303 return getRegClassInfo(RC).SpillSize / 8;
304 }
305
306 /// Return the minimum required alignment in bytes for a spill slot for
307 /// a register of this class.
308 Align getSpillAlign(const TargetRegisterClass &RC) const {
309 return Align(getRegClassInfo(RC).SpillAlignment / 8);
310 }
311
312 /// Return true if the given TargetRegisterClass has the ValueType T.
313 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
314 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
315 if (MVT(*I) == T)
316 return true;
317 return false;
318 }
319
320 /// Return true if the given TargetRegisterClass is compatible with LLT T.
321 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const {
322 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
323 MVT VT(*I);
324 if (VT == MVT::Untyped)
325 return true;
326
327 if (LLT(VT) == T)
328 return true;
329 }
330 return false;
331 }
332
333 /// Loop over all of the value types that can be represented by values
334 /// in the given register class.
335 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
336 return &RCVTLists[getRegClassInfo(RC).VTListOffset];
337 }
338
339 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
340 vt_iterator I = legalclasstypes_begin(RC);
341 while (*I != MVT::Other)
342 ++I;
343 return I;
344 }
345
346 /// Returns the Register Class of a physical register of the given type,
347 /// picking the most sub register class of the right type that contains this
348 /// physreg.
349 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
350 MVT VT = MVT::Other) const;
351
352 /// Returns the common Register Class of two physical registers of the given
353 /// type, picking the most sub register class of the right type that contains
354 /// these two physregs.
355 const TargetRegisterClass *
356 getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2,
357 MVT VT = MVT::Other) const;
358
359 /// Returns the Register Class of a physical register of the given type,
360 /// picking the most sub register class of the right type that contains this
361 /// physreg. If there is no register class compatible with the given type,
362 /// returns nullptr.
363 const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
364 LLT Ty = LLT()) const;
365
366 /// Returns the common Register Class of two physical registers of the given
367 /// type, picking the most sub register class of the right type that contains
368 /// these two physregs. If there is no register class compatible with the
369 /// given type, returns nullptr.
370 const TargetRegisterClass *
371 getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
372 LLT Ty = LLT()) const;
373
374 /// Return the maximal subclass of the given register class that is
375 /// allocatable or NULL.
376 const TargetRegisterClass *
377 getAllocatableClass(const TargetRegisterClass *RC) const;
378
379 /// Returns a bitset indexed by register number indicating if a register is
380 /// allocatable or not. If a register class is specified, returns the subset
381 /// for the class.
382 BitVector getAllocatableSet(const MachineFunction &MF,
383 const TargetRegisterClass *RC = nullptr) const;
384
385 /// Get a list of cost values for all registers that correspond to the index
386 /// returned by RegisterCostTableIndex.
387 ArrayRef<uint8_t> getRegisterCosts(const MachineFunction &MF) const {
388 unsigned Idx = getRegisterCostTableIndex(MF);
389 unsigned NumRegs = getNumRegs();
390 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
391
392 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
393 }
394
395 /// Return true if the register is in the allocation of any register class.
396 bool isInAllocatableClass(MCRegister RegNo) const {
397 return InfoDesc->InAllocatableClass[RegNo];
398 }
399
400 /// Return the human-readable symbolic target-specific
401 /// name for the specified SubRegIndex.
402 const char *getSubRegIndexName(unsigned SubIdx) const {
403 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
404 "This is not a subregister index");
405 return SubRegIndexNames[SubIdx-1];
406 }
407
408 /// Get the size of the bit range covered by a sub-register index.
409 /// If the index isn't continuous, return the sum of the sizes of its parts.
410 /// If the index is used to access subregisters of different sizes, return -1.
411 unsigned getSubRegIdxSize(unsigned Idx) const;
412
413 /// Get the offset of the bit range covered by a sub-register index.
414 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
415 /// access sub-registers at different offsets), return -1.
416 unsigned getSubRegIdxOffset(unsigned Idx) const;
417
418 /// Return a bitmask representing the parts of a register that are covered by
419 /// SubIdx \see LaneBitmask.
420 ///
421 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
422 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
423 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
424 return SubRegIndexLaneMasks[SubIdx];
425 }
426
427 /// Try to find one or more subregister indexes to cover \p LaneMask.
428 ///
429 /// If this is possible, returns true and appends the best matching set of
430 /// indexes to \p Indexes. If this is not possible, returns false.
431 bool getCoveringSubRegIndexes(const TargetRegisterClass *RC,
432 LaneBitmask LaneMask,
433 SmallVectorImpl<unsigned> &Indexes) const;
434
435 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
436 /// used to determine if sub-registers overlap - they can't be used to
437 /// determine if a set of sub-registers completely cover another
438 /// sub-register.
439 ///
440 /// The X86 general purpose registers have two lanes corresponding to the
441 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
442 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
443 /// sub_32bit sub-register.
444 ///
445 /// On the other hand, the ARM NEON lanes fully cover their registers: The
446 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
447 /// This is related to the CoveredBySubRegs property on register definitions.
448 ///
449 /// This function returns a bit mask of lanes that completely cover their
450 /// sub-registers. More precisely, given:
451 ///
452 /// Covering = getCoveringLanes();
453 /// MaskA = getSubRegIndexLaneMask(SubA);
454 /// MaskB = getSubRegIndexLaneMask(SubB);
455 ///
456 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
457 /// SubB.
458 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
459
460 /// Returns true if the two registers are equal or alias each other.
461 /// The registers may be virtual registers.
462 bool regsOverlap(Register RegA, Register RegB) const {
463 if (RegA == RegB)
464 return true;
465 if (RegA.isPhysical() && RegB.isPhysical())
466 return MCRegisterInfo::regsOverlap(RegA: RegA.asMCReg(), RegB: RegB.asMCReg());
467 return false;
468 }
469
470 /// Returns true if Reg contains RegUnit.
471 bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const {
472 return llvm::is_contained(Range: regunits(Reg), Element: RegUnit);
473 }
474
475 /// Returns the original SrcReg unless it is the target of a copy-like
476 /// operation, in which case we chain backwards through all such operations
477 /// to the ultimate source register. If a physical register is encountered,
478 /// we stop the search.
479 virtual Register lookThruCopyLike(Register SrcReg,
480 const MachineRegisterInfo *MRI) const;
481
482 /// Find the original SrcReg unless it is the target of a copy-like operation,
483 /// in which case we chain backwards through all such operations to the
484 /// ultimate source register. If a physical register is encountered, we stop
485 /// the search.
486 /// Return the original SrcReg if all the definitions in the chain only have
487 /// one user and not a physical register.
488 virtual Register
489 lookThruSingleUseCopyChain(Register SrcReg,
490 const MachineRegisterInfo *MRI) const;
491
492 /// Return a null-terminated list of all of the callee-saved registers on
493 /// this target. The register should be in the order of desired callee-save
494 /// stack frame offset. The first register is closest to the incoming stack
495 /// pointer if stack grows down, and vice versa.
496 /// Notice: This function does not take into account disabled CSRs.
497 /// In most cases you will want to use instead the function
498 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
499 virtual const MCPhysReg*
500 getCalleeSavedRegs(const MachineFunction *MF) const = 0;
501
502 /// Return a null-terminated list of all of the callee-saved registers on
503 /// this target when IPRA is on. The list should include any non-allocatable
504 /// registers that the backend uses and assumes will be saved by all calling
505 /// conventions. This is typically the ISA-standard frame pointer, but could
506 /// include the thread pointer, TOC pointer, or base pointer for different
507 /// targets.
508 virtual const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const {
509 return nullptr;
510 }
511
512 /// Return a mask of call-preserved registers for the given calling convention
513 /// on the current function. The mask should include all call-preserved
514 /// aliases. This is used by the register allocator to determine which
515 /// registers can be live across a call.
516 ///
517 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
518 /// A set bit indicates that all bits of the corresponding register are
519 /// preserved across the function call. The bit mask is expected to be
520 /// sub-register complete, i.e. if A is preserved, so are all its
521 /// sub-registers.
522 ///
523 /// Bits are numbered from the LSB, so the bit for physical register Reg can
524 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
525 ///
526 /// A NULL pointer means that no register mask will be used, and call
527 /// instructions should use implicit-def operands to indicate call clobbered
528 /// registers.
529 ///
530 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
531 CallingConv::ID) const {
532 // The default mask clobbers everything. All targets should override.
533 return nullptr;
534 }
535
536 /// Return a register mask for the registers preserved by the unwinder,
537 /// or nullptr if no custom mask is needed.
538 virtual const uint32_t *
539 getCustomEHPadPreservedMask(const MachineFunction &MF) const {
540 return nullptr;
541 }
542
543 /// Return a register mask that clobbers everything.
544 virtual const uint32_t *getNoPreservedMask() const {
545 llvm_unreachable("target does not provide no preserved mask");
546 }
547
548 /// Return a list of all of the registers which are clobbered "inside" a call
549 /// to the given function. For example, these might be needed for PLT
550 /// sequences of long-branch veneers.
551 virtual ArrayRef<MCPhysReg>
552 getIntraCallClobberedRegs(const MachineFunction *MF) const {
553 return {};
554 }
555
556 /// Return true if all bits that are set in mask \p mask0 are also set in
557 /// \p mask1.
558 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
559
560 /// Return all the call-preserved register masks defined for this target.
561 virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
562 virtual ArrayRef<const char *> getRegMaskNames() const = 0;
563
564 /// Returns a bitset indexed by physical register number indicating if a
565 /// register is a special register that has particular uses and should be
566 /// considered unavailable at all times, e.g. stack pointer, return address.
567 /// A reserved register:
568 /// - is not allocatable
569 /// - is considered always live
570 /// - is ignored by liveness tracking
571 /// It is often necessary to reserve the super registers of a reserved
572 /// register as well, to avoid them getting allocated indirectly. You may use
573 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
574 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
575
576 /// Returns either a string explaining why the given register is reserved for
577 /// this function, or an empty optional if no explanation has been written.
578 /// The absence of an explanation does not mean that the register is not
579 /// reserved (meaning, you should check that PhysReg is in fact reserved
580 /// before calling this).
581 virtual std::optional<std::string>
582 explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const {
583 return {};
584 }
585
586 /// Returns false if we can't guarantee that Physreg, specified as an IR asm
587 /// clobber constraint, will be preserved across the statement.
588 virtual bool isAsmClobberable(const MachineFunction &MF,
589 MCRegister PhysReg) const {
590 return true;
591 }
592
593 /// Returns true if PhysReg cannot be written to in inline asm statements.
594 virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
595 MCRegister PhysReg) const {
596 return false;
597 }
598
599 /// Returns true if PhysReg is unallocatable and constant throughout the
600 /// function. Used by MachineRegisterInfo::isConstantPhysReg().
601 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
602
603 /// Returns true if the register class is considered divergent.
604 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
605 return false;
606 }
607
608 /// Returns true if the register is considered uniform.
609 virtual bool isUniformReg(const MachineRegisterInfo &MRI,
610 const RegisterBankInfo &RBI, Register Reg) const {
611 return false;
612 }
613
614 /// Returns true if MachineLoopInfo should analyze the given physreg
615 /// for loop invariance.
616 virtual bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const {
617 return false;
618 }
619
620 /// Physical registers that may be modified within a function but are
621 /// guaranteed to be restored before any uses. This is useful for targets that
622 /// have call sequences where a GOT register may be updated by the caller
623 /// prior to a call and is guaranteed to be restored (also by the caller)
624 /// after the call.
625 virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
626 const MachineFunction &MF) const {
627 return false;
628 }
629
630 /// This is a wrapper around getCallPreservedMask().
631 /// Return true if the register is preserved after the call.
632 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
633 const MachineFunction &MF) const;
634
635 /// Returns true if PhysReg can be used as an argument to a function.
636 virtual bool isArgumentRegister(const MachineFunction &MF,
637 MCRegister PhysReg) const {
638 return false;
639 }
640
641 /// Returns true if PhysReg is a fixed register.
642 virtual bool isFixedRegister(const MachineFunction &MF,
643 MCRegister PhysReg) const {
644 return false;
645 }
646
647 /// Returns true if PhysReg is a general purpose register.
648 virtual bool isGeneralPurposeRegister(const MachineFunction &MF,
649 MCRegister PhysReg) const {
650 return false;
651 }
652
653 /// Returns true if RC is a class/subclass of general purpose register.
654 virtual bool
655 isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
656 return false;
657 }
658
659 /// Prior to adding the live-out mask to a stackmap or patchpoint
660 /// instruction, provide the target the opportunity to adjust it (mainly to
661 /// remove pseudo-registers that should be ignored).
662 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
663
664 /// Return a super-register of the specified register
665 /// Reg so its sub-register of index SubIdx is Reg.
666 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
667 const TargetRegisterClass *RC) const {
668 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC: RC->MC);
669 }
670
671 /// Return a subclass of the specified register
672 /// class A so that each register in it has a sub-register of the
673 /// specified sub-register index which is in the specified register class B.
674 ///
675 /// TableGen will synthesize missing A sub-classes.
676 virtual const TargetRegisterClass *
677 getMatchingSuperRegClass(const TargetRegisterClass *A,
678 const TargetRegisterClass *B, unsigned Idx) const;
679
680 // For a copy-like instruction that defines a register of class DefRC with
681 // subreg index DefSubReg, reading from another source with class SrcRC and
682 // subregister SrcSubReg return true if this is a preferable copy
683 // instruction or an earlier use should be used.
684 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
685 unsigned DefSubReg,
686 const TargetRegisterClass *SrcRC,
687 unsigned SrcSubReg) const;
688
689 /// Returns the largest legal sub-class of RC that
690 /// supports the sub-register index Idx.
691 /// If no such sub-class exists, return NULL.
692 /// If all registers in RC already have an Idx sub-register, return RC.
693 ///
694 /// TableGen generates a version of this function that is good enough in most
695 /// cases. Targets can override if they have constraints that TableGen
696 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
697 /// supported by the full GR32 register class in 64-bit mode, but only by the
698 /// GR32_ABCD regiister class in 32-bit mode.
699 ///
700 /// TableGen will synthesize missing RC sub-classes.
701 virtual const TargetRegisterClass *
702 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
703 assert(Idx == 0 && "Target has no sub-registers");
704 return RC;
705 }
706
707 /// Return a register class that can be used for a subregister copy from/into
708 /// \p SuperRC at \p SubRegIdx.
709 virtual const TargetRegisterClass *
710 getSubRegisterClass(const TargetRegisterClass *SuperRC,
711 unsigned SubRegIdx) const {
712 return nullptr;
713 }
714
715 /// Return the subregister index you get from composing
716 /// two subregister indices.
717 ///
718 /// The special null sub-register index composes as the identity.
719 ///
720 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
721 /// returns c. Note that composeSubRegIndices does not tell you about illegal
722 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
723 /// b, composeSubRegIndices doesn't tell you.
724 ///
725 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
726 /// ssub_0:S0 - ssub_3:S3 subregs.
727 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
728 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
729 if (!a) return b;
730 if (!b) return a;
731 return composeSubRegIndicesImpl(a, b);
732 }
733
734 /// Return a subregister index that will compose to give you the subregister
735 /// index.
736 ///
737 /// Finds a subregister index x such that composeSubRegIndices(a, x) ==
738 /// b. Note that this relationship does not hold if
739 /// reverseComposeSubRegIndices returns the null subregister.
740 ///
741 /// The special null sub-register index composes as the identity.
742 unsigned reverseComposeSubRegIndices(unsigned a, unsigned b) const {
743 if (!a)
744 return b;
745 if (!b)
746 return a;
747 return reverseComposeSubRegIndicesImpl(a, b);
748 }
749
750 /// Transforms a LaneMask computed for one subregister to the lanemask that
751 /// would have been computed when composing the subsubregisters with IdxA
752 /// first. @sa composeSubRegIndices()
753 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
754 LaneBitmask Mask) const {
755 if (!IdxA)
756 return Mask;
757 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
758 }
759
760 /// Transform a lanemask given for a virtual register to the corresponding
761 /// lanemask before using subregister with index \p IdxA.
762 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
763 /// valie lane mask (no invalid bits set) the following holds:
764 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
765 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
766 /// => X1 == Mask
767 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
768 LaneBitmask LaneMask) const {
769 if (!IdxA)
770 return LaneMask;
771 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
772 }
773
774 /// Debugging helper: dump register in human readable form to dbgs() stream.
775 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
776 const TargetRegisterInfo *TRI = nullptr);
777
778 /// Return target defined base register class for a physical register.
779 /// This is the register class with the lowest BaseClassOrder containing the
780 /// register.
781 /// Will be nullptr if the register is not in any base register class.
782 virtual const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const {
783 return nullptr;
784 }
785
786protected:
787 /// Overridden by TableGen in targets that have sub-registers.
788 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
789 llvm_unreachable("Target has no sub-registers");
790 }
791
792 /// Overridden by TableGen in targets that have sub-registers.
793 virtual unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const {
794 llvm_unreachable("Target has no sub-registers");
795 }
796
797 /// Overridden by TableGen in targets that have sub-registers.
798 virtual LaneBitmask
799 composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
800 llvm_unreachable("Target has no sub-registers");
801 }
802
803 virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
804 LaneBitmask) const {
805 llvm_unreachable("Target has no sub-registers");
806 }
807
808 /// Return the register cost table index. This implementation is sufficient
809 /// for most architectures and can be overriden by targets in case there are
810 /// multiple cost values associated with each register.
811 virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
812 return 0;
813 }
814
815public:
816 /// Find a common super-register class if it exists.
817 ///
818 /// Find a register class, SuperRC and two sub-register indices, PreA and
819 /// PreB, such that:
820 ///
821 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
822 ///
823 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
824 ///
825 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
826 ///
827 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
828 /// requirements, and there is no register class with a smaller spill size
829 /// that satisfies the requirements.
830 ///
831 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
832 ///
833 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
834 /// that case, the returned register class will be a sub-class of the
835 /// corresponding argument register class.
836 ///
837 /// The function returns NULL if no register class can be found.
838 const TargetRegisterClass*
839 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
840 const TargetRegisterClass *RCB, unsigned SubB,
841 unsigned &PreA, unsigned &PreB) const;
842
843 //===--------------------------------------------------------------------===//
844 // Register Class Information
845 //
846protected:
847 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
848 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
849 }
850
851public:
852 /// Register class iterators
853 regclass_iterator regclass_begin() const { return RegClassBegin; }
854 regclass_iterator regclass_end() const { return RegClassEnd; }
855 iterator_range<regclass_iterator> regclasses() const {
856 return make_range(x: regclass_begin(), y: regclass_end());
857 }
858
859 unsigned getNumRegClasses() const {
860 return (unsigned)(regclass_end()-regclass_begin());
861 }
862
863 /// Returns the register class associated with the enumeration value.
864 /// See class MCOperandInfo.
865 const TargetRegisterClass *getRegClass(unsigned i) const {
866 assert(i < getNumRegClasses() && "Register Class ID out of range");
867 return RegClassBegin[i];
868 }
869
870 /// Returns the name of the register class.
871 const char *getRegClassName(const TargetRegisterClass *Class) const {
872 return MCRegisterInfo::getRegClassName(Class: Class->MC);
873 }
874
875 /// Find the largest common subclass of A and B.
876 /// Return NULL if there is no common subclass.
877 const TargetRegisterClass *
878 getCommonSubClass(const TargetRegisterClass *A,
879 const TargetRegisterClass *B) const;
880
881 /// Returns a TargetRegisterClass used for pointer values.
882 /// If a target supports multiple different pointer register classes,
883 /// kind specifies which one is indicated.
884 virtual const TargetRegisterClass *
885 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
886 llvm_unreachable("Target didn't implement getPointerRegClass!");
887 }
888
889 /// Returns a legal register class to copy a register in the specified class
890 /// to or from. If it is possible to copy the register directly without using
891 /// a cross register class copy, return the specified RC. Returns NULL if it
892 /// is not possible to copy between two registers of the specified class.
893 virtual const TargetRegisterClass *
894 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
895 return RC;
896 }
897
898 /// Returns the largest super class of RC that is legal to use in the current
899 /// sub-target and has the same spill size.
900 /// The returned register class can be used to create virtual registers which
901 /// means that all its registers can be copied and spilled.
902 virtual const TargetRegisterClass *
903 getLargestLegalSuperClass(const TargetRegisterClass *RC,
904 const MachineFunction &) const {
905 /// The default implementation is very conservative and doesn't allow the
906 /// register allocator to inflate register classes.
907 return RC;
908 }
909
910 /// Return the register pressure "high water mark" for the specific register
911 /// class. The scheduler is in high register pressure mode (for the specific
912 /// register class) if it goes over the limit.
913 ///
914 /// Note: this is the old register pressure model that relies on a manually
915 /// specified representative register class per value type.
916 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
917 MachineFunction &MF) const {
918 return 0;
919 }
920
921 /// Return a heuristic for the machine scheduler to compare the profitability
922 /// of increasing one register pressure set versus another. The scheduler
923 /// will prefer increasing the register pressure of the set which returns
924 /// the largest value for this function.
925 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
926 unsigned PSetID) const {
927 return PSetID;
928 }
929
930 /// Get the weight in units of pressure for this register class.
931 virtual const RegClassWeight &getRegClassWeight(
932 const TargetRegisterClass *RC) const = 0;
933
934 /// Returns size in bits of a phys/virtual/generic register.
935 TypeSize getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
936
937 /// Get the weight in units of pressure for this register unit.
938 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
939
940 /// Get the number of dimensions of register pressure.
941 virtual unsigned getNumRegPressureSets() const = 0;
942
943 /// Get the name of this register unit pressure set.
944 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
945
946 /// Get the register unit pressure limit for this dimension.
947 /// This limit must be adjusted dynamically for reserved registers.
948 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
949 unsigned Idx) const = 0;
950
951 /// Get the dimensions of register pressure impacted by this register class.
952 /// Returns a -1 terminated array of pressure set IDs.
953 virtual const int *getRegClassPressureSets(
954 const TargetRegisterClass *RC) const = 0;
955
956 /// Get the dimensions of register pressure impacted by this register unit.
957 /// Returns a -1 terminated array of pressure set IDs.
958 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
959
960 /// Get the scale factor of spill weight for this register class.
961 virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const;
962
963 /// Get a list of 'hint' registers that the register allocator should try
964 /// first when allocating a physical register for the virtual register
965 /// VirtReg. These registers are effectively moved to the front of the
966 /// allocation order. If true is returned, regalloc will try to only use
967 /// hints to the greatest extent possible even if it means spilling.
968 ///
969 /// The Order argument is the allocation order for VirtReg's register class
970 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
971 /// come from Order, and they must not be reserved.
972 ///
973 /// The default implementation of this function will only add target
974 /// independent register allocation hints. Targets that override this
975 /// function should typically call this default implementation as well and
976 /// expect to see generic copy hints added.
977 virtual bool
978 getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
979 SmallVectorImpl<MCPhysReg> &Hints,
980 const MachineFunction &MF,
981 const VirtRegMap *VRM = nullptr,
982 const LiveRegMatrix *Matrix = nullptr) const;
983
984 /// A callback to allow target a chance to update register allocation hints
985 /// when a register is "changed" (e.g. coalesced) to another register.
986 /// e.g. On ARM, some virtual registers should target register pairs,
987 /// if one of pair is coalesced to another register, the allocation hint of
988 /// the other half of the pair should be changed to point to the new register.
989 virtual void updateRegAllocHint(Register Reg, Register NewReg,
990 MachineFunction &MF) const {
991 // Do nothing.
992 }
993
994 /// Allow the target to reverse allocation order of local live ranges. This
995 /// will generally allocate shorter local live ranges first. For targets with
996 /// many registers, this could reduce regalloc compile time by a large
997 /// factor. It is disabled by default for three reasons:
998 /// (1) Top-down allocation is simpler and easier to debug for targets that
999 /// don't benefit from reversing the order.
1000 /// (2) Bottom-up allocation could result in poor evicition decisions on some
1001 /// targets affecting the performance of compiled code.
1002 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
1003 virtual bool reverseLocalAssignment() const { return false; }
1004
1005 /// Allow the target to override the cost of using a callee-saved register for
1006 /// the first time. Default value of 0 means we will use a callee-saved
1007 /// register if it is available.
1008 virtual unsigned getCSRFirstUseCost() const { return 0; }
1009
1010 /// Returns true if the target requires (and can make use of) the register
1011 /// scavenger.
1012 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
1013 return false;
1014 }
1015
1016 /// Returns true if the target wants to use frame pointer based accesses to
1017 /// spill to the scavenger emergency spill slot.
1018 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
1019 return true;
1020 }
1021
1022 /// Returns true if the target requires post PEI scavenging of registers for
1023 /// materializing frame index constants.
1024 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
1025 return false;
1026 }
1027
1028 /// Returns true if the target requires using the RegScavenger directly for
1029 /// frame elimination despite using requiresFrameIndexScavenging.
1030 virtual bool requiresFrameIndexReplacementScavenging(
1031 const MachineFunction &MF) const {
1032 return false;
1033 }
1034
1035 /// Returns true if the target wants the LocalStackAllocation pass to be run
1036 /// and virtual base registers used for more efficient stack access.
1037 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1038 return false;
1039 }
1040
1041 /// Return true if target has reserved a spill slot in the stack frame of
1042 /// the given function for the specified register. e.g. On x86, if the frame
1043 /// register is required, the first fixed stack object is reserved as its
1044 /// spill slot. This tells PEI not to create a new stack frame
1045 /// object for the given register. It should be called only after
1046 /// determineCalleeSaves().
1047 virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
1048 int &FrameIdx) const {
1049 return false;
1050 }
1051
1052 /// Returns true if the live-ins should be tracked after register allocation.
1053 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
1054 return true;
1055 }
1056
1057 /// True if the stack can be realigned for the target.
1058 virtual bool canRealignStack(const MachineFunction &MF) const;
1059
1060 /// True if storage within the function requires the stack pointer to be
1061 /// aligned more than the normal calling convention calls for.
1062 virtual bool shouldRealignStack(const MachineFunction &MF) const;
1063
1064 /// True if stack realignment is required and still possible.
1065 bool hasStackRealignment(const MachineFunction &MF) const {
1066 return shouldRealignStack(MF) && canRealignStack(MF);
1067 }
1068
1069 /// Get the offset from the referenced frame index in the instruction,
1070 /// if there is one.
1071 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
1072 int Idx) const {
1073 return 0;
1074 }
1075
1076 /// Returns true if the instruction's frame index reference would be better
1077 /// served by a base register other than FP or SP.
1078 /// Used by LocalStackFrameAllocation to determine which frame index
1079 /// references it should create new base registers for.
1080 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1081 return false;
1082 }
1083
1084 /// Insert defining instruction(s) for a pointer to FrameIdx before
1085 /// insertion point I. Return materialized frame pointer.
1086 virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB,
1087 int FrameIdx,
1088 int64_t Offset) const {
1089 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1090 "target");
1091 }
1092
1093 /// Resolve a frame index operand of an instruction
1094 /// to reference the indicated base register plus offset instead.
1095 virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
1096 int64_t Offset) const {
1097 llvm_unreachable("resolveFrameIndex does not exist on this target");
1098 }
1099
1100 /// Determine whether a given base register plus offset immediate is
1101 /// encodable to resolve a frame index.
1102 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1103 int64_t Offset) const {
1104 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1105 }
1106
1107 /// Gets the DWARF expression opcodes for \p Offset.
1108 virtual void getOffsetOpcodes(const StackOffset &Offset,
1109 SmallVectorImpl<uint64_t> &Ops) const;
1110
1111 /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1112 DIExpression *
1113 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1114 const StackOffset &Offset) const;
1115
1116 virtual int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const {
1117 llvm_unreachable("getDwarfRegNumForVirtReg does not exist on this target");
1118 }
1119
1120 /// Spill the register so it can be used by the register scavenger.
1121 /// Return true if the register was spilled, false otherwise.
1122 /// If this function does not spill the register, the scavenger
1123 /// will instead spill it to the emergency spill slot.
1124 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
1125 MachineBasicBlock::iterator I,
1126 MachineBasicBlock::iterator &UseMI,
1127 const TargetRegisterClass *RC,
1128 Register Reg) const {
1129 return false;
1130 }
1131
1132 /// Process frame indices in reverse block order. This changes the behavior of
1133 /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
1134 /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
1135 /// should prefer reverse scavenging behavior.
1136 /// TODO: Remove this when all targets return true.
1137 virtual bool eliminateFrameIndicesBackwards() const { return true; }
1138
1139 /// This method must be overriden to eliminate abstract frame indices from
1140 /// instructions which may use them. The instruction referenced by the
1141 /// iterator contains an MO_FrameIndex operand which must be eliminated by
1142 /// this method. This method may modify or replace the specified instruction,
1143 /// as long as it keeps the iterator pointing at the finished product.
1144 /// SPAdj is the SP adjustment due to call frame setup instruction.
1145 /// FIOperandNum is the FI operand number.
1146 /// Returns true if the current instruction was removed and the iterator
1147 /// is not longer valid
1148 virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
1149 int SPAdj, unsigned FIOperandNum,
1150 RegScavenger *RS = nullptr) const = 0;
1151
1152 /// Return the assembly name for \p Reg.
1153 virtual StringRef getRegAsmName(MCRegister Reg) const {
1154 // FIXME: We are assuming that the assembly name is equal to the TableGen
1155 // name converted to lower case
1156 //
1157 // The TableGen name is the name of the definition for this register in the
1158 // target's tablegen files. For example, the TableGen name of
1159 // def EAX : Register <...>; is "EAX"
1160 return StringRef(getName(RegNo: Reg));
1161 }
1162
1163 //===--------------------------------------------------------------------===//
1164 /// Subtarget Hooks
1165
1166 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1167 virtual bool shouldCoalesce(MachineInstr *MI,
1168 const TargetRegisterClass *SrcRC,
1169 unsigned SubReg,
1170 const TargetRegisterClass *DstRC,
1171 unsigned DstSubReg,
1172 const TargetRegisterClass *NewRC,
1173 LiveIntervals &LIS) const
1174 { return true; }
1175
1176 /// Region split has a high compile time cost especially for large live range.
1177 /// This method is used to decide whether or not \p VirtReg should
1178 /// go through this expensive splitting heuristic.
1179 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1180 const LiveInterval &VirtReg) const;
1181
1182 /// Last chance recoloring has a high compile time cost especially for
1183 /// targets with a lot of registers.
1184 /// This method is used to decide whether or not \p VirtReg should
1185 /// go through this expensive heuristic.
1186 /// When this target hook is hit, by returning false, there is a high
1187 /// chance that the register allocation will fail altogether (usually with
1188 /// "ran out of registers").
1189 /// That said, this error usually points to another problem in the
1190 /// optimization pipeline.
1191 virtual bool
1192 shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF,
1193 const LiveInterval &VirtReg) const {
1194 return true;
1195 }
1196
1197 /// When prioritizing live ranges in register allocation, if this hook returns
1198 /// true then the AllocationPriority of the register class will be treated as
1199 /// more important than whether the range is local to a basic block or global.
1200 virtual bool
1201 regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const {
1202 return false;
1203 }
1204
1205 //===--------------------------------------------------------------------===//
1206 /// Debug information queries.
1207
1208 /// getFrameRegister - This method should return the register used as a base
1209 /// for values allocated in the current stack frame.
1210 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1211
1212 /// Mark a register and all its aliases as reserved in the given set.
1213 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1214
1215 /// Returns true if for every register in the set all super registers are part
1216 /// of the set as well.
1217 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1218 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1219
1220 virtual const TargetRegisterClass *
1221 getConstrainedRegClassForOperand(const MachineOperand &MO,
1222 const MachineRegisterInfo &MRI) const {
1223 return nullptr;
1224 }
1225
1226 /// Some targets have non-allocatable registers that aren't technically part
1227 /// of the explicit callee saved register list, but should be handled as such
1228 /// in certain cases.
1229 virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
1230 return false;
1231 }
1232
1233 /// Some targets delay assigning the frame until late and use a placeholder
1234 /// to represent it earlier. This method can be used to identify the frame
1235 /// register placeholder.
1236 virtual bool isVirtualFrameRegister(MCRegister Reg) const { return false; }
1237
1238 virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
1239 return {};
1240 }
1241
1242 virtual SmallVector<StringLiteral>
1243 getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
1244 return {};
1245 }
1246
1247 // Whether this register should be ignored when generating CodeView debug
1248 // info, because it's a known there is no mapping available.
1249 virtual bool isIgnoredCVReg(MCRegister LLVMReg) const { return false; }
1250};
1251
1252//===----------------------------------------------------------------------===//
1253// SuperRegClassIterator
1254//===----------------------------------------------------------------------===//
1255//
1256// Iterate over the possible super-registers for a given register class. The
1257// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1258// possible classes of super-registers.
1259//
1260// Each bit mask will have at least one set bit, and each set bit in Mask
1261// corresponds to a SuperRC such that:
1262//
1263// For all Reg in SuperRC: Reg:Idx is in RC.
1264//
1265// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1266// also satisfies the above requirement, assuming Reg:0 == Reg.
1267//
1268class SuperRegClassIterator {
1269 const unsigned RCMaskWords;
1270 unsigned SubReg = 0;
1271 const uint16_t *Idx;
1272 const uint32_t *Mask;
1273
1274public:
1275 /// Create a SuperRegClassIterator that visits all the super-register classes
1276 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1277 SuperRegClassIterator(const TargetRegisterClass *RC,
1278 const TargetRegisterInfo *TRI,
1279 bool IncludeSelf = false)
1280 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1281 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1282 if (!IncludeSelf)
1283 ++*this;
1284 }
1285
1286 /// Returns true if this iterator is still pointing at a valid entry.
1287 bool isValid() const { return Idx; }
1288
1289 /// Returns the current sub-register index.
1290 unsigned getSubReg() const { return SubReg; }
1291
1292 /// Returns the bit mask of register classes that getSubReg() projects into
1293 /// RC.
1294 /// See TargetRegisterClass::getSubClassMask() for how to use it.
1295 const uint32_t *getMask() const { return Mask; }
1296
1297 /// Advance iterator to the next entry.
1298 void operator++() {
1299 assert(isValid() && "Cannot move iterator past end.");
1300 Mask += RCMaskWords;
1301 SubReg = *Idx++;
1302 if (!SubReg)
1303 Idx = nullptr;
1304 }
1305};
1306
1307//===----------------------------------------------------------------------===//
1308// BitMaskClassIterator
1309//===----------------------------------------------------------------------===//
1310/// This class encapuslates the logic to iterate over bitmask returned by
1311/// the various RegClass related APIs.
1312/// E.g., this class can be used to iterate over the subclasses provided by
1313/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1314class BitMaskClassIterator {
1315 /// Total number of register classes.
1316 const unsigned NumRegClasses;
1317 /// Base index of CurrentChunk.
1318 /// In other words, the number of bit we read to get at the
1319 /// beginning of that chunck.
1320 unsigned Base = 0;
1321 /// Adjust base index of CurrentChunk.
1322 /// Base index + how many bit we read within CurrentChunk.
1323 unsigned Idx = 0;
1324 /// Current register class ID.
1325 unsigned ID = 0;
1326 /// Mask we are iterating over.
1327 const uint32_t *Mask;
1328 /// Current chunk of the Mask we are traversing.
1329 uint32_t CurrentChunk;
1330
1331 /// Move ID to the next set bit.
1332 void moveToNextID() {
1333 // If the current chunk of memory is empty, move to the next one,
1334 // while making sure we do not go pass the number of register
1335 // classes.
1336 while (!CurrentChunk) {
1337 // Move to the next chunk.
1338 Base += 32;
1339 if (Base >= NumRegClasses) {
1340 ID = NumRegClasses;
1341 return;
1342 }
1343 CurrentChunk = *++Mask;
1344 Idx = Base;
1345 }
1346 // Otherwise look for the first bit set from the right
1347 // (representation of the class ID is big endian).
1348 // See getSubClassMask for more details on the representation.
1349 unsigned Offset = llvm::countr_zero(Val: CurrentChunk);
1350 // Add the Offset to the adjusted base number of this chunk: Idx.
1351 // This is the ID of the register class.
1352 ID = Idx + Offset;
1353
1354 // Consume the zeros, if any, and the bit we just read
1355 // so that we are at the right spot for the next call.
1356 // Do not do Offset + 1 because Offset may be 31 and 32
1357 // will be UB for the shift, though in that case we could
1358 // have make the chunk being equal to 0, but that would
1359 // have introduced a if statement.
1360 moveNBits(NumBits: Offset);
1361 moveNBits(NumBits: 1);
1362 }
1363
1364 /// Move \p NumBits Bits forward in CurrentChunk.
1365 void moveNBits(unsigned NumBits) {
1366 assert(NumBits < 32 && "Undefined behavior spotted!");
1367 // Consume the bit we read for the next call.
1368 CurrentChunk >>= NumBits;
1369 // Adjust the base for the chunk.
1370 Idx += NumBits;
1371 }
1372
1373public:
1374 /// Create a BitMaskClassIterator that visits all the register classes
1375 /// represented by \p Mask.
1376 ///
1377 /// \pre \p Mask != nullptr
1378 BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1379 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1380 // Move to the first ID.
1381 moveToNextID();
1382 }
1383
1384 /// Returns true if this iterator is still pointing at a valid entry.
1385 bool isValid() const { return getID() != NumRegClasses; }
1386
1387 /// Returns the current register class ID.
1388 unsigned getID() const { return ID; }
1389
1390 /// Advance iterator to the next entry.
1391 void operator++() {
1392 assert(isValid() && "Cannot move iterator past end.");
1393 moveToNextID();
1394 }
1395};
1396
1397// This is useful when building IndexedMaps keyed on virtual registers
1398struct VirtReg2IndexFunctor {
1399 using argument_type = Register;
1400 unsigned operator()(Register Reg) const { return Reg.virtRegIndex(); }
1401};
1402
1403/// Prints virtual and physical registers with or without a TRI instance.
1404///
1405/// The format is:
1406/// %noreg - NoRegister
1407/// %5 - a virtual register.
1408/// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1409/// %eax - a physical register
1410/// %physreg17 - a physical register when no TRI instance given.
1411///
1412/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1413LLVM_ABI Printable printReg(Register Reg,
1414 const TargetRegisterInfo *TRI = nullptr,
1415 unsigned SubIdx = 0,
1416 const MachineRegisterInfo *MRI = nullptr);
1417
1418/// Create Printable object to print register units on a \ref raw_ostream.
1419///
1420/// Register units are named after their root registers:
1421///
1422/// al - Single root.
1423/// fp0~st7 - Dual roots.
1424///
1425/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1426LLVM_ABI Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1427
1428/// Create Printable object to print virtual registers and physical
1429/// registers on a \ref raw_ostream.
1430LLVM_ABI Printable printVRegOrUnit(unsigned VRegOrUnit,
1431 const TargetRegisterInfo *TRI);
1432
1433/// Create Printable object to print register classes or register banks
1434/// on a \ref raw_ostream.
1435LLVM_ABI Printable printRegClassOrBank(Register Reg,
1436 const MachineRegisterInfo &RegInfo,
1437 const TargetRegisterInfo *TRI);
1438
1439} // end namespace llvm
1440
1441#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
1442

source code of llvm/include/llvm/CodeGen/TargetRegisterInfo.h