1//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCREGISTERINFO_H
16#define LLVM_MC_MCREGISTERINFO_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/iterator.h"
20#include "llvm/ADT/iterator_range.h"
21#include "llvm/MC/LaneBitmask.h"
22#include "llvm/MC/MCRegister.h"
23#include "llvm/Support/Compiler.h"
24#include <cassert>
25#include <cstdint>
26#include <iterator>
27#include <utility>
28
29namespace llvm {
30
31class MCRegUnitIterator;
32class MCSubRegIterator;
33class MCSuperRegIterator;
34
35/// MCRegisterClass - Base class of TargetRegisterClass.
36class MCRegisterClass {
37public:
38 using iterator = const MCPhysReg*;
39 using const_iterator = const MCPhysReg*;
40
41 const iterator RegsBegin;
42 const uint8_t *const RegSet;
43 const uint32_t NameIdx;
44 const uint16_t RegsSize;
45 const uint16_t RegSetSize;
46 const uint16_t ID;
47 const uint16_t RegSizeInBits;
48 const int8_t CopyCost;
49 const bool Allocatable;
50 const bool BaseClass;
51
52 /// getID() - Return the register class ID number.
53 ///
54 unsigned getID() const { return ID; }
55
56 /// begin/end - Return all of the registers in this class.
57 ///
58 iterator begin() const { return RegsBegin; }
59 iterator end() const { return RegsBegin + RegsSize; }
60
61 /// getNumRegs - Return the number of registers in this class.
62 ///
63 unsigned getNumRegs() const { return RegsSize; }
64
65 /// getRegister - Return the specified register in the class.
66 ///
67 MCRegister getRegister(unsigned i) const {
68 assert(i < getNumRegs() && "Register number out of range!");
69 return RegsBegin[i];
70 }
71
72 /// contains - Return true if the specified register is included in this
73 /// register class. This does not include virtual registers.
74 bool contains(MCRegister Reg) const {
75 unsigned RegNo = Reg.id();
76 unsigned InByte = RegNo % 8;
77 unsigned Byte = RegNo / 8;
78 if (Byte >= RegSetSize)
79 return false;
80 return (RegSet[Byte] & (1 << InByte)) != 0;
81 }
82
83 /// contains - Return true if both registers are in this class.
84 bool contains(MCRegister Reg1, MCRegister Reg2) const {
85 return contains(Reg: Reg1) && contains(Reg: Reg2);
86 }
87
88 /// Return the size of the physical register in bits if we are able to
89 /// determine it. This always returns zero for registers of targets that use
90 /// HW modes, as we need more information to determine the size of registers
91 /// in such cases. Use TargetRegisterInfo to cover them.
92 unsigned getSizeInBits() const { return RegSizeInBits; }
93
94 /// getCopyCost - Return the cost of copying a value between two registers in
95 /// this class. A negative number means the register class is very expensive
96 /// to copy e.g. status flag register classes.
97 int getCopyCost() const { return CopyCost; }
98
99 /// isAllocatable - Return true if this register class may be used to create
100 /// virtual registers.
101 bool isAllocatable() const { return Allocatable; }
102
103 /// Return true if this register class has a defined BaseClassOrder.
104 bool isBaseClass() const { return BaseClass; }
105};
106
107/// MCRegisterDesc - This record contains information about a particular
108/// register. The SubRegs field is a zero terminated array of registers that
109/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
110/// of AX. The SuperRegs field is a zero terminated array of registers that are
111/// super-registers of the specific register, e.g. RAX, EAX, are
112/// super-registers of AX.
113///
114struct MCRegisterDesc {
115 uint32_t Name; // Printable name for the reg (for debugging)
116 uint32_t SubRegs; // Sub-register set, described above
117 uint32_t SuperRegs; // Super-register set, described above
118
119 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
120 // sub-register in SubRegs.
121 uint32_t SubRegIndices;
122
123 // Points to the list of register units. The low bits hold the first regunit
124 // number, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
125 uint32_t RegUnits;
126
127 /// Index into list with lane mask sequences. The sequence contains a lanemask
128 /// for every register unit.
129 uint16_t RegUnitLaneMasks;
130
131 // Is true for constant registers.
132 bool IsConstant;
133
134 // Is true for artificial registers.
135 bool IsArtificial;
136};
137
138/// MCRegisterInfo base class - We assume that the target defines a static
139/// array of MCRegisterDesc objects that represent all of the machine
140/// registers that the target has. As such, we simply have to track a pointer
141/// to this array so that we can turn register number into a register
142/// descriptor.
143///
144/// Note this class is designed to be a base class of TargetRegisterInfo, which
145/// is the interface used by codegen. However, specific targets *should never*
146/// specialize this class. MCRegisterInfo should only contain getters to access
147/// TableGen generated physical register data. It must not be extended with
148/// virtual methods.
149///
150class LLVM_ABI MCRegisterInfo {
151public:
152 using regclass_iterator = const MCRegisterClass *;
153
154 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
155 /// performed with a binary search.
156 struct DwarfLLVMRegPair {
157 unsigned FromReg;
158 unsigned ToReg;
159
160 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
161 };
162
163private:
164 const MCRegisterDesc *Desc; // Pointer to the descriptor array
165 unsigned NumRegs; // Number of entries in the array
166 MCRegister RAReg; // Return address register
167 MCRegister PCReg; // Program counter register
168 const MCRegisterClass *Classes; // Pointer to the regclass array
169 unsigned NumClasses; // Number of entries in the array
170 unsigned NumRegUnits; // Number of regunits.
171 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
172 const int16_t *DiffLists; // Pointer to the difflists array
173 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
174 // for register units.
175 const char *RegStrings; // Pointer to the string table.
176 const char *RegClassStrings; // Pointer to the class strings.
177 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
178 // array.
179 unsigned NumSubRegIndices; // Number of subreg indices.
180 const uint16_t *RegEncodingTable; // Pointer to array of register
181 // encodings.
182
183 unsigned L2DwarfRegsSize;
184 unsigned EHL2DwarfRegsSize;
185 unsigned Dwarf2LRegsSize;
186 unsigned EHDwarf2LRegsSize;
187 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
188 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
189 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
190 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
191 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
192 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
193
194 mutable std::vector<std::vector<MCPhysReg>> RegAliasesCache;
195 ArrayRef<MCPhysReg> getCachedAliasesOf(MCRegister R) const;
196
197 /// Iterator class that can traverse the differentially encoded values in
198 /// DiffLists. Don't use this class directly, use one of the adaptors below.
199 class DiffListIterator
200 : public iterator_facade_base<DiffListIterator, std::forward_iterator_tag,
201 unsigned> {
202 unsigned Val = 0;
203 const int16_t *List = nullptr;
204
205 public:
206 /// Constructs an invalid iterator, which is also the end iterator.
207 /// Call init() to point to something useful.
208 DiffListIterator() = default;
209
210 /// Point the iterator to InitVal, decoding subsequent values from DiffList.
211 void init(unsigned InitVal, const int16_t *DiffList) {
212 Val = InitVal;
213 List = DiffList;
214 }
215
216 /// Returns true if this iterator is not yet at the end.
217 bool isValid() const { return List; }
218
219 /// Dereference the iterator to get the value at the current position.
220 const unsigned &operator*() const { return Val; }
221
222 using DiffListIterator::iterator_facade_base::operator++;
223 /// Pre-increment to move to the next position.
224 DiffListIterator &operator++() {
225 assert(isValid() && "Cannot move off the end of the list.");
226 int16_t D = *List++;
227 Val += D;
228 // The end of the list is encoded as a 0 differential.
229 if (!D)
230 List = nullptr;
231 return *this;
232 }
233
234 bool operator==(const DiffListIterator &Other) const {
235 return List == Other.List;
236 }
237 };
238
239public:
240 /// Return an iterator range over all sub-registers of \p Reg, excluding \p
241 /// Reg.
242 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
243
244 /// Return an iterator range over all sub-registers of \p Reg, including \p
245 /// Reg.
246 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const;
247
248 /// Return an iterator range over all super-registers of \p Reg, excluding \p
249 /// Reg.
250 iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const;
251
252 /// Return an iterator range over all super-registers of \p Reg, including \p
253 /// Reg.
254 iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const;
255
256 /// Return an iterator range over all sub- and super-registers of \p Reg,
257 /// including \p Reg.
258 detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>,
259 iterator_range<MCSuperRegIterator>>
260 sub_and_superregs_inclusive(MCRegister Reg) const;
261
262 /// Returns an iterator range over all regunits for \p Reg.
263 iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const;
264
265 // These iterators are allowed to sub-class DiffListIterator and access
266 // internal list pointers.
267 friend class MCSubRegIterator;
268 friend class MCSubRegIndexIterator;
269 friend class MCSuperRegIterator;
270 friend class MCRegUnitIterator;
271 friend class MCRegUnitMaskIterator;
272 friend class MCRegUnitRootIterator;
273 friend class MCRegAliasIterator;
274
275 virtual ~MCRegisterInfo() {}
276
277 /// Initialize MCRegisterInfo, called by TableGen
278 /// auto-generated routines. *DO NOT USE*.
279 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
280 unsigned PC, const MCRegisterClass *C, unsigned NC,
281 const MCPhysReg (*RURoots)[2], unsigned NRU,
282 const int16_t *DL, const LaneBitmask *RUMS,
283 const char *Strings, const char *ClassStrings,
284 const uint16_t *SubIndices, unsigned NumIndices,
285 const uint16_t *RET) {
286 Desc = D;
287 NumRegs = NR;
288 RAReg = RA;
289 PCReg = PC;
290 Classes = C;
291 DiffLists = DL;
292 RegUnitMaskSequences = RUMS;
293 RegStrings = Strings;
294 RegClassStrings = ClassStrings;
295 NumClasses = NC;
296 RegUnitRoots = RURoots;
297 NumRegUnits = NRU;
298 SubRegIndices = SubIndices;
299 NumSubRegIndices = NumIndices;
300 RegEncodingTable = RET;
301
302 // Initialize DWARF register mapping variables
303 EHL2DwarfRegs = nullptr;
304 EHL2DwarfRegsSize = 0;
305 L2DwarfRegs = nullptr;
306 L2DwarfRegsSize = 0;
307 EHDwarf2LRegs = nullptr;
308 EHDwarf2LRegsSize = 0;
309 Dwarf2LRegs = nullptr;
310 Dwarf2LRegsSize = 0;
311
312 RegAliasesCache.resize(new_size: NumRegs);
313 }
314
315 /// Used to initialize LLVM register to Dwarf
316 /// register number mapping. Called by TableGen auto-generated routines.
317 /// *DO NOT USE*.
318 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
319 bool isEH) {
320 if (isEH) {
321 EHL2DwarfRegs = Map;
322 EHL2DwarfRegsSize = Size;
323 } else {
324 L2DwarfRegs = Map;
325 L2DwarfRegsSize = Size;
326 }
327 }
328
329 /// Used to initialize Dwarf register to LLVM
330 /// register number mapping. Called by TableGen auto-generated routines.
331 /// *DO NOT USE*.
332 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
333 bool isEH) {
334 if (isEH) {
335 EHDwarf2LRegs = Map;
336 EHDwarf2LRegsSize = Size;
337 } else {
338 Dwarf2LRegs = Map;
339 Dwarf2LRegsSize = Size;
340 }
341 }
342
343 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
344 /// number mapping. By default the SEH register number is just the same
345 /// as the LLVM register number.
346 /// FIXME: TableGen these numbers. Currently this requires target specific
347 /// initialization code.
348 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
349 L2SEHRegs[LLVMReg] = SEHReg;
350 }
351
352 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
353 L2CVRegs[LLVMReg] = CVReg;
354 }
355
356 /// This method should return the register where the return
357 /// address can be found.
358 MCRegister getRARegister() const {
359 return RAReg;
360 }
361
362 /// Return the register which is the program counter.
363 MCRegister getProgramCounter() const {
364 return PCReg;
365 }
366
367 const MCRegisterDesc &operator[](MCRegister Reg) const {
368 assert(Reg.id() < NumRegs &&
369 "Attempting to access record for invalid register number!");
370 return Desc[Reg.id()];
371 }
372
373 /// Provide a get method, equivalent to [], but more useful with a
374 /// pointer to this object.
375 const MCRegisterDesc &get(MCRegister Reg) const {
376 return operator[](Reg);
377 }
378
379 /// Returns the physical register number of sub-register "Index"
380 /// for physical register RegNo. Return zero if the sub-register does not
381 /// exist.
382 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
383
384 /// Return a super-register of the specified register
385 /// Reg so its sub-register of index SubIdx is Reg.
386 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
387 const MCRegisterClass *RC) const;
388
389 /// For a given register pair, return the sub-register index
390 /// if the second register is a sub-register of the first. Return zero
391 /// otherwise.
392 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
393
394 /// Return the human-readable symbolic target-specific name for the
395 /// specified physical register.
396 const char *getName(MCRegister RegNo) const {
397 return RegStrings + get(Reg: RegNo).Name;
398 }
399
400 /// Returns true if the given register is constant.
401 bool isConstant(MCRegister RegNo) const { return get(Reg: RegNo).IsConstant; }
402
403 /// Returns true if the given register is artificial, which means it
404 /// represents a regunit that is not separately addressable but still needs to
405 /// be modelled, such as the top 16-bits of a 32-bit GPR.
406 bool isArtificial(MCRegister RegNo) const { return get(Reg: RegNo).IsArtificial; }
407
408 /// Returns true when the given register unit is considered artificial.
409 /// Register units are considered artificial when at least one of the
410 /// root registers is artificial.
411 bool isArtificialRegUnit(MCRegUnit Unit) const;
412
413 /// Return the number of registers this target has (useful for
414 /// sizing arrays holding per register information)
415 unsigned getNumRegs() const {
416 return NumRegs;
417 }
418
419 /// Return the number of sub-register indices
420 /// understood by the target. Index 0 is reserved for the no-op sub-register,
421 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
422 unsigned getNumSubRegIndices() const {
423 return NumSubRegIndices;
424 }
425
426 /// Return the number of (native) register units in the
427 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
428 /// can be accessed through MCRegUnitIterator defined below.
429 unsigned getNumRegUnits() const {
430 return NumRegUnits;
431 }
432
433 /// Map a target register to an equivalent dwarf register
434 /// number. Returns -1 if there is no equivalent value. The second
435 /// parameter allows targets to use different numberings for EH info and
436 /// debugging info.
437 virtual int64_t getDwarfRegNum(MCRegister RegNum, bool isEH) const;
438
439 /// Map a dwarf register back to a target register. Returns std::nullopt if
440 /// there is no mapping.
441 std::optional<MCRegister> getLLVMRegNum(uint64_t RegNum, bool isEH) const;
442
443 /// Map a target EH register number to an equivalent DWARF register
444 /// number.
445 int64_t getDwarfRegNumFromDwarfEHRegNum(uint64_t RegNum) const;
446
447 /// Map a target register to an equivalent SEH register
448 /// number. Returns LLVM register number if there is no equivalent value.
449 int getSEHRegNum(MCRegister RegNum) const;
450
451 /// Map a target register to an equivalent CodeView register
452 /// number.
453 int getCodeViewRegNum(MCRegister RegNum) const;
454
455 regclass_iterator regclass_begin() const { return Classes; }
456 regclass_iterator regclass_end() const { return Classes+NumClasses; }
457 iterator_range<regclass_iterator> regclasses() const {
458 return make_range(x: regclass_begin(), y: regclass_end());
459 }
460
461 unsigned getNumRegClasses() const {
462 return (unsigned)(regclass_end()-regclass_begin());
463 }
464
465 /// Returns the register class associated with the enumeration
466 /// value. See class MCOperandInfo.
467 const MCRegisterClass& getRegClass(unsigned i) const {
468 assert(i < getNumRegClasses() && "Register Class ID out of range");
469 return Classes[i];
470 }
471
472 const char *getRegClassName(const MCRegisterClass *Class) const {
473 return RegClassStrings + Class->NameIdx;
474 }
475
476 /// Returns the encoding for Reg
477 uint16_t getEncodingValue(MCRegister Reg) const {
478 assert(Reg.id() < NumRegs &&
479 "Attempting to get encoding for invalid register number!");
480 return RegEncodingTable[Reg.id()];
481 }
482
483 /// Returns true if RegB is a sub-register of RegA.
484 bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
485 return isSuperRegister(RegA: RegB, RegB: RegA);
486 }
487
488 /// Returns true if RegB is a super-register of RegA.
489 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
490
491 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
492 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
493 return isSuperRegisterEq(RegA: RegB, RegB: RegA);
494 }
495
496 /// Returns true if RegB is a super-register of RegA or if
497 /// RegB == RegA.
498 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
499 return RegA == RegB || isSuperRegister(RegA, RegB);
500 }
501
502 /// Returns true if RegB is a super-register or sub-register of RegA
503 /// or if RegB == RegA.
504 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
505 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
506 }
507
508 /// Returns true if the two registers are equal or alias each other.
509 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
510};
511
512//===----------------------------------------------------------------------===//
513// Register List Iterators
514//===----------------------------------------------------------------------===//
515
516// MCRegisterInfo provides lists of super-registers, sub-registers, and
517// aliasing registers. Use these iterator classes to traverse the lists.
518
519/// MCSubRegIterator enumerates all sub-registers of Reg.
520/// If IncludeSelf is set, Reg itself is included in the list.
521class MCSubRegIterator
522 : public iterator_adaptor_base<MCSubRegIterator,
523 MCRegisterInfo::DiffListIterator,
524 std::forward_iterator_tag, const MCPhysReg> {
525 // Cache the current value, so that we can return a reference to it.
526 MCPhysReg Val;
527
528public:
529 /// Constructs an end iterator.
530 MCSubRegIterator() = default;
531
532 MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
533 bool IncludeSelf = false) {
534 assert(Reg.isPhysical());
535 I.init(InitVal: Reg.id(), DiffList: MCRI->DiffLists + MCRI->get(Reg).SubRegs);
536 // Initially, the iterator points to Reg itself.
537 Val = MCPhysReg(*I);
538 if (!IncludeSelf)
539 ++*this;
540 }
541
542 const MCPhysReg &operator*() const { return Val; }
543
544 using iterator_adaptor_base::operator++;
545 MCSubRegIterator &operator++() {
546 Val = MCPhysReg(*++I);
547 return *this;
548 }
549
550 /// Returns true if this iterator is not yet at the end.
551 bool isValid() const { return I.isValid(); }
552};
553
554/// Iterator that enumerates the sub-registers of a Reg and the associated
555/// sub-register indices.
556class MCSubRegIndexIterator {
557 MCSubRegIterator SRIter;
558 const uint16_t *SRIndex;
559
560public:
561 /// Constructs an iterator that traverses subregisters and their
562 /// associated subregister indices.
563 MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
564 : SRIter(Reg, MCRI) {
565 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
566 }
567
568 /// Returns current sub-register.
569 MCRegister getSubReg() const {
570 return *SRIter;
571 }
572
573 /// Returns sub-register index of the current sub-register.
574 unsigned getSubRegIndex() const {
575 return *SRIndex;
576 }
577
578 /// Returns true if this iterator is not yet at the end.
579 bool isValid() const { return SRIter.isValid(); }
580
581 /// Moves to the next position.
582 MCSubRegIndexIterator &operator++() {
583 ++SRIter;
584 ++SRIndex;
585 return *this;
586 }
587};
588
589/// MCSuperRegIterator enumerates all super-registers of Reg.
590/// If IncludeSelf is set, Reg itself is included in the list.
591class MCSuperRegIterator
592 : public iterator_adaptor_base<MCSuperRegIterator,
593 MCRegisterInfo::DiffListIterator,
594 std::forward_iterator_tag, const MCPhysReg> {
595 // Cache the current value, so that we can return a reference to it.
596 MCPhysReg Val;
597
598public:
599 /// Constructs an end iterator.
600 MCSuperRegIterator() = default;
601
602 MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
603 bool IncludeSelf = false) {
604 assert(Reg.isPhysical());
605 I.init(InitVal: Reg.id(), DiffList: MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
606 // Initially, the iterator points to Reg itself.
607 Val = MCPhysReg(*I);
608 if (!IncludeSelf)
609 ++*this;
610 }
611
612 const MCPhysReg &operator*() const { return Val; }
613
614 using iterator_adaptor_base::operator++;
615 MCSuperRegIterator &operator++() {
616 Val = MCPhysReg(*++I);
617 return *this;
618 }
619
620 /// Returns true if this iterator is not yet at the end.
621 bool isValid() const { return I.isValid(); }
622};
623
624// Definition for isSuperRegister. Put it down here since it needs the
625// iterator defined above in addition to the MCRegisterInfo class itself.
626inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{
627 return is_contained(Range: superregs(Reg: RegA), Element: RegB);
628}
629
630//===----------------------------------------------------------------------===//
631// Register Units
632//===----------------------------------------------------------------------===//
633
634// MCRegUnitIterator enumerates a list of register units for Reg. The list is
635// in ascending numerical order.
636class MCRegUnitIterator
637 : public iterator_adaptor_base<MCRegUnitIterator,
638 MCRegisterInfo::DiffListIterator,
639 std::forward_iterator_tag, const MCRegUnit> {
640 // The value must be kept in sync with RegisterInfoEmitter.cpp.
641 static constexpr unsigned RegUnitBits = 12;
642 // Cache the current value, so that we can return a reference to it.
643 MCRegUnit Val;
644
645public:
646 /// Constructs an end iterator.
647 MCRegUnitIterator() = default;
648
649 MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
650 assert(Reg.isPhysical());
651 // Decode the RegUnits MCRegisterDesc field.
652 unsigned RU = MCRI->get(Reg).RegUnits;
653 unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);
654 unsigned Offset = RU >> RegUnitBits;
655 I.init(InitVal: FirstRU, DiffList: MCRI->DiffLists + Offset);
656 Val = MCRegUnit(*I);
657 }
658
659 const MCRegUnit &operator*() const { return Val; }
660
661 using iterator_adaptor_base::operator++;
662 MCRegUnitIterator &operator++() {
663 Val = MCRegUnit(*++I);
664 return *this;
665 }
666
667 /// Returns true if this iterator is not yet at the end.
668 bool isValid() const { return I.isValid(); }
669};
670
671/// MCRegUnitMaskIterator enumerates a list of register units and their
672/// associated lane masks for Reg. The register units are in ascending
673/// numerical order.
674class MCRegUnitMaskIterator {
675 MCRegUnitIterator RUIter;
676 const LaneBitmask *MaskListIter;
677
678public:
679 MCRegUnitMaskIterator() = default;
680
681 /// Constructs an iterator that traverses the register units and their
682 /// associated LaneMasks in Reg.
683 MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
684 : RUIter(Reg, MCRI) {
685 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
686 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
687 }
688
689 /// Returns a (RegUnit, LaneMask) pair.
690 std::pair<unsigned,LaneBitmask> operator*() const {
691 return std::make_pair(x: *RUIter, y: *MaskListIter);
692 }
693
694 /// Returns true if this iterator is not yet at the end.
695 bool isValid() const { return RUIter.isValid(); }
696
697 /// Moves to the next position.
698 MCRegUnitMaskIterator &operator++() {
699 ++MaskListIter;
700 ++RUIter;
701 return *this;
702 }
703};
704
705// Each register unit has one or two root registers. The complete set of
706// registers containing a register unit is the union of the roots and their
707// super-registers. All registers aliasing Unit can be visited like this:
708//
709// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
710// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
711// visit(*SI);
712// }
713
714/// MCRegUnitRootIterator enumerates the root registers of a register unit.
715class MCRegUnitRootIterator {
716 uint16_t Reg0 = 0;
717 uint16_t Reg1 = 0;
718
719public:
720 MCRegUnitRootIterator() = default;
721
722 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
723 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
724 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
725 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
726 }
727
728 /// Dereference to get the current root register.
729 unsigned operator*() const {
730 return Reg0;
731 }
732
733 /// Check if the iterator is at the end of the list.
734 bool isValid() const {
735 return Reg0;
736 }
737
738 /// Preincrement to move to the next root register.
739 MCRegUnitRootIterator &operator++() {
740 assert(isValid() && "Cannot move off the end of the list.");
741 Reg0 = Reg1;
742 Reg1 = 0;
743 return *this;
744 }
745};
746
747/// MCRegAliasIterator enumerates all registers aliasing Reg.
748class MCRegAliasIterator {
749private:
750 const MCPhysReg *It = nullptr;
751 const MCPhysReg *End = nullptr;
752
753public:
754 MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
755 bool IncludeSelf) {
756 ArrayRef<MCPhysReg> Cache = MCRI->getCachedAliasesOf(R: Reg);
757 assert(Cache.back() == Reg);
758 It = Cache.begin();
759 End = Cache.end();
760 if (!IncludeSelf)
761 --End;
762 }
763
764 bool isValid() const { return It != End; }
765
766 MCRegister operator*() const { return *It; }
767
768 MCRegAliasIterator &operator++() {
769 assert(isValid() && "Cannot move off the end of the list.");
770 ++It;
771 return *this;
772 }
773};
774
775inline iterator_range<MCSubRegIterator>
776MCRegisterInfo::subregs(MCRegister Reg) const {
777 return make_range(x: {Reg, this, /*IncludeSelf=*/false}, y: MCSubRegIterator());
778}
779
780inline iterator_range<MCSubRegIterator>
781MCRegisterInfo::subregs_inclusive(MCRegister Reg) const {
782 return make_range(x: {Reg, this, /*IncludeSelf=*/true}, y: MCSubRegIterator());
783}
784
785inline iterator_range<MCSuperRegIterator>
786MCRegisterInfo::superregs(MCRegister Reg) const {
787 return make_range(x: {Reg, this, /*IncludeSelf=*/false}, y: MCSuperRegIterator());
788}
789
790inline iterator_range<MCSuperRegIterator>
791MCRegisterInfo::superregs_inclusive(MCRegister Reg) const {
792 return make_range(x: {Reg, this, /*IncludeSelf=*/true}, y: MCSuperRegIterator());
793}
794
795inline detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>,
796 iterator_range<MCSuperRegIterator>>
797MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const {
798 return concat<const MCPhysReg>(Ranges: subregs_inclusive(Reg), Ranges: superregs(Reg));
799}
800
801inline iterator_range<MCRegUnitIterator>
802MCRegisterInfo::regunits(MCRegister Reg) const {
803 return make_range(x: {Reg, this}, y: MCRegUnitIterator());
804}
805
806} // end namespace llvm
807
808#endif // LLVM_MC_MCREGISTERINFO_H
809

source code of llvm/include/llvm/MC/MCRegisterInfo.h