1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "SIDefines.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/IR/InstrTypes.h"
15#include "llvm/IR/Module.h"
16#include "llvm/Support/Alignment.h"
17#include <array>
18#include <functional>
19#include <utility>
20
21struct amd_kernel_code_t;
22
23namespace llvm {
24
25struct Align;
26class Argument;
27class Function;
28class GlobalValue;
29class MCInstrInfo;
30class MCRegisterClass;
31class MCRegisterInfo;
32class MCSubtargetInfo;
33class StringRef;
34class Triple;
35class raw_ostream;
36
37namespace amdhsa {
38struct kernel_descriptor_t;
39}
40
41namespace AMDGPU {
42
43struct IsaVersion;
44
45/// Generic target versions emitted by this version of LLVM.
46///
47/// These numbers are incremented every time a codegen breaking change occurs
48/// within a generic family.
49namespace GenericVersion {
50static constexpr unsigned GFX9 = 1;
51static constexpr unsigned GFX10_1 = 1;
52static constexpr unsigned GFX10_3 = 1;
53static constexpr unsigned GFX11 = 1;
54} // namespace GenericVersion
55
56enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };
57
58/// \returns True if \p STI is AMDHSA.
59bool isHsaAbi(const MCSubtargetInfo &STI);
60
61/// \returns Code object version from the IR module flag.
62unsigned getAMDHSACodeObjectVersion(const Module &M);
63
64/// \returns Code object version from ELF's e_ident[EI_ABIVERSION].
65unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion);
66
67/// \returns The default HSA code object version. This should only be used when
68/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module
69/// flag or a .amdhsa_code_object_version directive)
70unsigned getDefaultAMDHSACodeObjectVersion();
71
72/// \returns ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION]. \param
73/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().
74uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);
75
76/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
77unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
78
79/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
80unsigned getHostcallImplicitArgPosition(unsigned COV);
81
82unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
83unsigned getCompletionActionImplicitArgPosition(unsigned COV);
84
85struct GcnBufferFormatInfo {
86 unsigned Format;
87 unsigned BitsPerComp;
88 unsigned NumComponents;
89 unsigned NumFormat;
90 unsigned DataFormat;
91};
92
93struct MAIInstInfo {
94 uint16_t Opcode;
95 bool is_dgemm;
96 bool is_gfx940_xdl;
97};
98
99#define GET_MIMGBaseOpcode_DECL
100#define GET_MIMGDim_DECL
101#define GET_MIMGEncoding_DECL
102#define GET_MIMGLZMapping_DECL
103#define GET_MIMGMIPMapping_DECL
104#define GET_MIMGBiASMapping_DECL
105#define GET_MAIInstInfoTable_DECL
106#include "AMDGPUGenSearchableTables.inc"
107
108namespace IsaInfo {
109
110enum {
111 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
112 // doesn't spill SGPRs as much as when 80 is set.
113 FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
114 TRAP_NUM_SGPRS = 16
115};
116
117enum class TargetIDSetting {
118 Unsupported,
119 Any,
120 Off,
121 On
122};
123
124class AMDGPUTargetID {
125private:
126 const MCSubtargetInfo &STI;
127 TargetIDSetting XnackSetting;
128 TargetIDSetting SramEccSetting;
129
130public:
131 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
132 ~AMDGPUTargetID() = default;
133
134 /// \return True if the current xnack setting is not "Unsupported".
135 bool isXnackSupported() const {
136 return XnackSetting != TargetIDSetting::Unsupported;
137 }
138
139 /// \returns True if the current xnack setting is "On" or "Any".
140 bool isXnackOnOrAny() const {
141 return XnackSetting == TargetIDSetting::On ||
142 XnackSetting == TargetIDSetting::Any;
143 }
144
145 /// \returns True if current xnack setting is "On" or "Off",
146 /// false otherwise.
147 bool isXnackOnOrOff() const {
148 return getXnackSetting() == TargetIDSetting::On ||
149 getXnackSetting() == TargetIDSetting::Off;
150 }
151
152 /// \returns The current xnack TargetIDSetting, possible options are
153 /// "Unsupported", "Any", "Off", and "On".
154 TargetIDSetting getXnackSetting() const {
155 return XnackSetting;
156 }
157
158 /// Sets xnack setting to \p NewXnackSetting.
159 void setXnackSetting(TargetIDSetting NewXnackSetting) {
160 XnackSetting = NewXnackSetting;
161 }
162
163 /// \return True if the current sramecc setting is not "Unsupported".
164 bool isSramEccSupported() const {
165 return SramEccSetting != TargetIDSetting::Unsupported;
166 }
167
168 /// \returns True if the current sramecc setting is "On" or "Any".
169 bool isSramEccOnOrAny() const {
170 return SramEccSetting == TargetIDSetting::On ||
171 SramEccSetting == TargetIDSetting::Any;
172 }
173
174 /// \returns True if current sramecc setting is "On" or "Off",
175 /// false otherwise.
176 bool isSramEccOnOrOff() const {
177 return getSramEccSetting() == TargetIDSetting::On ||
178 getSramEccSetting() == TargetIDSetting::Off;
179 }
180
181 /// \returns The current sramecc TargetIDSetting, possible options are
182 /// "Unsupported", "Any", "Off", and "On".
183 TargetIDSetting getSramEccSetting() const {
184 return SramEccSetting;
185 }
186
187 /// Sets sramecc setting to \p NewSramEccSetting.
188 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
189 SramEccSetting = NewSramEccSetting;
190 }
191
192 void setTargetIDFromFeaturesString(StringRef FS);
193 void setTargetIDFromTargetIDStream(StringRef TargetID);
194
195 /// \returns String representation of an object.
196 std::string toString() const;
197};
198
199/// \returns Wavefront size for given subtarget \p STI.
200unsigned getWavefrontSize(const MCSubtargetInfo *STI);
201
202/// \returns Local memory size in bytes for given subtarget \p STI.
203unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
204
205/// \returns Maximum addressable local memory size in bytes for given subtarget
206/// \p STI.
207unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI);
208
209/// \returns Number of execution units per compute unit for given subtarget \p
210/// STI.
211unsigned getEUsPerCU(const MCSubtargetInfo *STI);
212
213/// \returns Maximum number of work groups per compute unit for given subtarget
214/// \p STI and limited by given \p FlatWorkGroupSize.
215unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
216 unsigned FlatWorkGroupSize);
217
218/// \returns Minimum number of waves per execution unit for given subtarget \p
219/// STI.
220unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
221
222/// \returns Maximum number of waves per execution unit for given subtarget \p
223/// STI without any kind of limitation.
224unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
225
226/// \returns Number of waves per execution unit required to support the given \p
227/// FlatWorkGroupSize.
228unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
229 unsigned FlatWorkGroupSize);
230
231/// \returns Minimum flat work group size for given subtarget \p STI.
232unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
233
234/// \returns Maximum flat work group size for given subtarget \p STI.
235unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
236
237/// \returns Number of waves per work group for given subtarget \p STI and
238/// \p FlatWorkGroupSize.
239unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
240 unsigned FlatWorkGroupSize);
241
242/// \returns SGPR allocation granularity for given subtarget \p STI.
243unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
244
245/// \returns SGPR encoding granularity for given subtarget \p STI.
246unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
247
248/// \returns Total number of SGPRs for given subtarget \p STI.
249unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
250
251/// \returns Addressable number of SGPRs for given subtarget \p STI.
252unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
253
254/// \returns Minimum number of SGPRs that meets the given number of waves per
255/// execution unit requirement for given subtarget \p STI.
256unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
257
258/// \returns Maximum number of SGPRs that meets the given number of waves per
259/// execution unit requirement for given subtarget \p STI.
260unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
261 bool Addressable);
262
263/// \returns Number of extra SGPRs implicitly required by given subtarget \p
264/// STI when the given special registers are used.
265unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
266 bool FlatScrUsed, bool XNACKUsed);
267
268/// \returns Number of extra SGPRs implicitly required by given subtarget \p
269/// STI when the given special registers are used. XNACK is inferred from
270/// \p STI.
271unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
272 bool FlatScrUsed);
273
274/// \returns Number of SGPR blocks needed for given subtarget \p STI when
275/// \p NumSGPRs are used. \p NumSGPRs should already include any special
276/// register counts.
277unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
278
279/// \returns VGPR allocation granularity for given subtarget \p STI.
280///
281/// For subtargets which support it, \p EnableWavefrontSize32 should match
282/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
283unsigned
284getVGPRAllocGranule(const MCSubtargetInfo *STI,
285 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
286
287/// \returns VGPR encoding granularity for given subtarget \p STI.
288///
289/// For subtargets which support it, \p EnableWavefrontSize32 should match
290/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
291unsigned getVGPREncodingGranule(
292 const MCSubtargetInfo *STI,
293 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
294
295/// \returns Total number of VGPRs for given subtarget \p STI.
296unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
297
298/// \returns Addressable number of VGPRs for given subtarget \p STI.
299unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
300
301/// \returns Minimum number of VGPRs that meets given number of waves per
302/// execution unit requirement for given subtarget \p STI.
303unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
304
305/// \returns Maximum number of VGPRs that meets given number of waves per
306/// execution unit requirement for given subtarget \p STI.
307unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
308
309/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
310/// subtarget \p STI.
311unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
312 unsigned NumVGPRs);
313
314/// \returns Number of VGPR blocks needed for given subtarget \p STI when
315/// \p NumVGPRs are used.
316///
317/// For subtargets which support it, \p EnableWavefrontSize32 should match the
318/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
319unsigned
320getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
321 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
322
323} // end namespace IsaInfo
324
325LLVM_READONLY
326int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
327
328LLVM_READONLY
329inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
330 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
331}
332
333LLVM_READONLY
334int getSOPPWithRelaxation(uint16_t Opcode);
335
336struct MIMGBaseOpcodeInfo {
337 MIMGBaseOpcode BaseOpcode;
338 bool Store;
339 bool Atomic;
340 bool AtomicX2;
341 bool Sampler;
342 bool Gather4;
343
344 uint8_t NumExtraArgs;
345 bool Gradients;
346 bool G16;
347 bool Coordinates;
348 bool LodOrClampOrMip;
349 bool HasD16;
350 bool MSAA;
351 bool BVH;
352 bool A16;
353};
354
355LLVM_READONLY
356const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
357
358LLVM_READONLY
359const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
360
361struct MIMGDimInfo {
362 MIMGDim Dim;
363 uint8_t NumCoords;
364 uint8_t NumGradients;
365 bool MSAA;
366 bool DA;
367 uint8_t Encoding;
368 const char *AsmSuffix;
369};
370
371LLVM_READONLY
372const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
373
374LLVM_READONLY
375const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
376
377LLVM_READONLY
378const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
379
380struct MIMGLZMappingInfo {
381 MIMGBaseOpcode L;
382 MIMGBaseOpcode LZ;
383};
384
385struct MIMGMIPMappingInfo {
386 MIMGBaseOpcode MIP;
387 MIMGBaseOpcode NONMIP;
388};
389
390struct MIMGBiasMappingInfo {
391 MIMGBaseOpcode Bias;
392 MIMGBaseOpcode NoBias;
393};
394
395struct MIMGOffsetMappingInfo {
396 MIMGBaseOpcode Offset;
397 MIMGBaseOpcode NoOffset;
398};
399
400struct MIMGG16MappingInfo {
401 MIMGBaseOpcode G;
402 MIMGBaseOpcode G16;
403};
404
405LLVM_READONLY
406const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
407
408struct WMMAOpcodeMappingInfo {
409 unsigned Opcode2Addr;
410 unsigned Opcode3Addr;
411};
412
413LLVM_READONLY
414const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
415
416LLVM_READONLY
417const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
418
419LLVM_READONLY
420const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
421
422LLVM_READONLY
423const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
424
425LLVM_READONLY
426int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
427 unsigned VDataDwords, unsigned VAddrDwords);
428
429LLVM_READONLY
430int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
431
432LLVM_READONLY
433unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
434 const MIMGDimInfo *Dim, bool IsA16,
435 bool IsG16Supported);
436
437struct MIMGInfo {
438 uint16_t Opcode;
439 uint16_t BaseOpcode;
440 uint8_t MIMGEncoding;
441 uint8_t VDataDwords;
442 uint8_t VAddrDwords;
443 uint8_t VAddrOperands;
444};
445
446LLVM_READONLY
447const MIMGInfo *getMIMGInfo(unsigned Opc);
448
449LLVM_READONLY
450int getMTBUFBaseOpcode(unsigned Opc);
451
452LLVM_READONLY
453int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
454
455LLVM_READONLY
456int getMTBUFElements(unsigned Opc);
457
458LLVM_READONLY
459bool getMTBUFHasVAddr(unsigned Opc);
460
461LLVM_READONLY
462bool getMTBUFHasSrsrc(unsigned Opc);
463
464LLVM_READONLY
465bool getMTBUFHasSoffset(unsigned Opc);
466
467LLVM_READONLY
468int getMUBUFBaseOpcode(unsigned Opc);
469
470LLVM_READONLY
471int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
472
473LLVM_READONLY
474int getMUBUFElements(unsigned Opc);
475
476LLVM_READONLY
477bool getMUBUFHasVAddr(unsigned Opc);
478
479LLVM_READONLY
480bool getMUBUFHasSrsrc(unsigned Opc);
481
482LLVM_READONLY
483bool getMUBUFHasSoffset(unsigned Opc);
484
485LLVM_READONLY
486bool getMUBUFIsBufferInv(unsigned Opc);
487
488LLVM_READONLY
489bool getSMEMIsBuffer(unsigned Opc);
490
491LLVM_READONLY
492bool getVOP1IsSingle(unsigned Opc);
493
494LLVM_READONLY
495bool getVOP2IsSingle(unsigned Opc);
496
497LLVM_READONLY
498bool getVOP3IsSingle(unsigned Opc);
499
500LLVM_READONLY
501bool isVOPC64DPP(unsigned Opc);
502
503LLVM_READONLY
504bool isVOPCAsmOnly(unsigned Opc);
505
506/// Returns true if MAI operation is a double precision GEMM.
507LLVM_READONLY
508bool getMAIIsDGEMM(unsigned Opc);
509
510LLVM_READONLY
511bool getMAIIsGFX940XDL(unsigned Opc);
512
513struct CanBeVOPD {
514 bool X;
515 bool Y;
516};
517
518/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.
519LLVM_READONLY
520unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
521
522LLVM_READONLY
523CanBeVOPD getCanBeVOPD(unsigned Opc);
524
525LLVM_READONLY
526const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
527 uint8_t NumComponents,
528 uint8_t NumFormat,
529 const MCSubtargetInfo &STI);
530LLVM_READONLY
531const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
532 const MCSubtargetInfo &STI);
533
534LLVM_READONLY
535int getMCOpcode(uint16_t Opcode, unsigned Gen);
536
537LLVM_READONLY
538unsigned getVOPDOpcode(unsigned Opc);
539
540LLVM_READONLY
541int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily);
542
543LLVM_READONLY
544bool isVOPD(unsigned Opc);
545
546LLVM_READNONE
547bool isMAC(unsigned Opc);
548
549LLVM_READNONE
550bool isPermlane16(unsigned Opc);
551
552LLVM_READNONE
553bool isGenericAtomic(unsigned Opc);
554
555LLVM_READNONE
556bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc);
557
558namespace VOPD {
559
560enum Component : unsigned {
561 DST = 0,
562 SRC0,
563 SRC1,
564 SRC2,
565
566 DST_NUM = 1,
567 MAX_SRC_NUM = 3,
568 MAX_OPR_NUM = DST_NUM + MAX_SRC_NUM
569};
570
571// LSB mask for VGPR banks per VOPD component operand.
572// 4 banks result in a mask 3, setting 2 lower bits.
573constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
574
575enum ComponentIndex : unsigned { X = 0, Y = 1 };
576constexpr unsigned COMPONENTS[] = {ComponentIndex::X, ComponentIndex::Y};
577constexpr unsigned COMPONENTS_NUM = 2;
578
579// Properties of VOPD components.
580class ComponentProps {
581private:
582 unsigned SrcOperandsNum = 0;
583 unsigned MandatoryLiteralIdx = ~0u;
584 bool HasSrc2Acc = false;
585
586public:
587 ComponentProps() = default;
588 ComponentProps(const MCInstrDesc &OpDesc);
589
590 // Return the total number of src operands this component has.
591 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
592
593 // Return the number of src operands of this component visible to the parser.
594 unsigned getCompParsedSrcOperandsNum() const {
595 return SrcOperandsNum - HasSrc2Acc;
596 }
597
598 // Return true iif this component has a mandatory literal.
599 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
600
601 // If this component has a mandatory literal, return component operand
602 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
603 unsigned getMandatoryLiteralCompOperandIndex() const {
604 assert(hasMandatoryLiteral());
605 return MandatoryLiteralIdx;
606 }
607
608 // Return true iif this component has operand
609 // with component index CompSrcIdx and this operand may be a register.
610 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
611 assert(CompSrcIdx < Component::MAX_SRC_NUM);
612 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
613 }
614
615 // Return true iif this component has tied src2.
616 bool hasSrc2Acc() const { return HasSrc2Acc; }
617
618private:
619 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
620 assert(CompSrcIdx < Component::MAX_SRC_NUM);
621 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
622 }
623};
624
625enum ComponentKind : unsigned {
626 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
627 COMPONENT_X, // A VOPD instruction, X component.
628 COMPONENT_Y, // A VOPD instruction, Y component.
629 MAX = COMPONENT_Y
630};
631
632// Interface functions of this class map VOPD component operand indices
633// to indices of operands in MachineInstr/MCInst or parsed operands array.
634//
635// Note that this class operates with 3 kinds of indices:
636// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
637// - MC operand indices (they refer operands in a MachineInstr/MCInst);
638// - parsed operand indices (they refer operands in parsed operands array).
639//
640// For SINGLE components mapping between these indices is trivial.
641// But things get more complicated for COMPONENT_X and
642// COMPONENT_Y because these components share the same
643// MachineInstr/MCInst and the same parsed operands array.
644// Below is an example of component operand to parsed operand
645// mapping for the following instruction:
646//
647// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
648//
649// PARSED COMPONENT PARSED
650// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
651// -------------------------------------------------------------------
652// "v_dual_add_f32" 0
653// v_dual_add_f32 v255 0 (DST) --> 1
654// v4 1 (SRC0) --> 2
655// v5 2 (SRC1) --> 3
656// "::" 4
657// "v_dual_mov_b32" 5
658// v_dual_mov_b32 v6 0 (DST) --> 6
659// v1 1 (SRC0) --> 7
660// -------------------------------------------------------------------
661//
662class ComponentLayout {
663private:
664 // Regular MachineInstr/MCInst operands are ordered as follows:
665 // dst, src0 [, other src operands]
666 // VOPD MachineInstr/MCInst operands are ordered as follows:
667 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
668 // Each ComponentKind has operand indices defined below.
669 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
670 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
671
672 // Parsed operands of regular instructions are ordered as follows:
673 // Mnemo dst src0 [vsrc1 ...]
674 // Parsed VOPD operands are ordered as follows:
675 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
676 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
677 // Each ComponentKind has operand indices defined below.
678 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
679 4 /* + OpX.ParsedSrcNum */};
680 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
681 2, 2, 5 /* + OpX.ParsedSrcNum */};
682
683private:
684 const ComponentKind Kind;
685 const ComponentProps PrevComp;
686
687public:
688 // Create layout for COMPONENT_X or SINGLE component.
689 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
690 assert(Kind == ComponentKind::SINGLE || Kind == ComponentKind::COMPONENT_X);
691 }
692
693 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
694 ComponentLayout(const ComponentProps &OpXProps)
695 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
696
697public:
698 // Return the index of dst operand in MCInst operands.
699 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
700
701 // Return the index of the specified src operand in MCInst operands.
702 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
703 assert(CompSrcIdx < Component::MAX_SRC_NUM);
704 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
705 }
706
707 // Return the index of dst operand in the parsed operands array.
708 unsigned getIndexOfDstInParsedOperands() const {
709 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
710 }
711
712 // Return the index of the specified src operand in the parsed operands array.
713 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
714 assert(CompSrcIdx < Component::MAX_SRC_NUM);
715 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
716 }
717
718private:
719 unsigned getPrevCompSrcNum() const {
720 return PrevComp.getCompSrcOperandsNum();
721 }
722 unsigned getPrevCompParsedSrcNum() const {
723 return PrevComp.getCompParsedSrcOperandsNum();
724 }
725};
726
727// Layout and properties of VOPD components.
728class ComponentInfo : public ComponentLayout, public ComponentProps {
729public:
730 // Create ComponentInfo for COMPONENT_X or SINGLE component.
731 ComponentInfo(const MCInstrDesc &OpDesc,
732 ComponentKind Kind = ComponentKind::SINGLE)
733 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
734
735 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
736 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
737 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
738
739 // Map component operand index to parsed operand index.
740 // Return 0 if the specified operand does not exist.
741 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
742};
743
744// Properties of VOPD instructions.
745class InstInfo {
746private:
747 const ComponentInfo CompInfo[COMPONENTS_NUM];
748
749public:
750 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
751
752 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
753 : CompInfo{OpX, OpY} {}
754
755 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
756 : CompInfo{OprInfoX, OprInfoY} {}
757
758 const ComponentInfo &operator[](size_t ComponentIdx) const {
759 assert(ComponentIdx < COMPONENTS_NUM);
760 return CompInfo[ComponentIdx];
761 }
762
763 // Check VOPD operands constraints.
764 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
765 // for the specified component and MC operand. The callback must return 0
766 // if the operand is not a register or not a VGPR.
767 // If \p SkipSrc is set to true then constraints for source operands are not
768 // checked.
769 bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
770 bool SkipSrc = false) const {
771 return getInvalidCompOperandIndex(GetRegIdx: GetRegIdx, SkipSrc).has_value();
772 }
773
774 // Check VOPD operands constraints.
775 // Return the index of an invalid component operand, if any.
776 // If \p SkipSrc is set to true then constraints for source operands are not
777 // checked.
778 std::optional<unsigned> getInvalidCompOperandIndex(
779 std::function<unsigned(unsigned, unsigned)> GetRegIdx,
780 bool SkipSrc = false) const;
781
782private:
783 RegIndices
784 getRegIndices(unsigned ComponentIdx,
785 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
786};
787
788} // namespace VOPD
789
790LLVM_READONLY
791std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
792
793LLVM_READONLY
794// Get properties of 2 single VOP1/VOP2 instructions
795// used as components to create a VOPD instruction.
796VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
797
798LLVM_READONLY
799// Get properties of VOPD X and Y components.
800VOPD::InstInfo
801getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
802
803LLVM_READONLY
804bool isTrue16Inst(unsigned Opc);
805
806LLVM_READONLY
807unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
808
809LLVM_READONLY
810unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
811
812void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
813 const MCSubtargetInfo *STI);
814
815amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
816 const MCSubtargetInfo *STI);
817
818bool isGroupSegment(const GlobalValue *GV);
819bool isGlobalSegment(const GlobalValue *GV);
820bool isReadOnlySegment(const GlobalValue *GV);
821
822/// \returns True if constants should be emitted to .text section for given
823/// target triple \p TT, false otherwise.
824bool shouldEmitConstantsToTextSection(const Triple &TT);
825
826/// \returns Integer value requested using \p F's \p Name attribute.
827///
828/// \returns \p Default if attribute is not present.
829///
830/// \returns \p Default and emits error if requested value cannot be converted
831/// to integer.
832int getIntegerAttribute(const Function &F, StringRef Name, int Default);
833
834/// \returns A pair of integer values requested using \p F's \p Name attribute
835/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
836/// is false).
837///
838/// \returns \p Default if attribute is not present.
839///
840/// \returns \p Default and emits error if one of the requested values cannot be
841/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
842/// not present.
843std::pair<unsigned, unsigned>
844getIntegerPairAttribute(const Function &F, StringRef Name,
845 std::pair<unsigned, unsigned> Default,
846 bool OnlyFirstRequired = false);
847
848/// Represents the counter values to wait for in an s_waitcnt instruction.
849///
850/// Large values (including the maximum possible integer) can be used to
851/// represent "don't care" waits.
852struct Waitcnt {
853 unsigned LoadCnt = ~0u; // Corresponds to Vmcnt prior to gfx12.
854 unsigned ExpCnt = ~0u;
855 unsigned DsCnt = ~0u; // Corresponds to LGKMcnt prior to gfx12.
856 unsigned StoreCnt = ~0u; // Corresponds to VScnt on gfx10/gfx11.
857 unsigned SampleCnt = ~0u; // gfx12+ only.
858 unsigned BvhCnt = ~0u; // gfx12+ only.
859 unsigned KmCnt = ~0u; // gfx12+ only.
860
861 Waitcnt() = default;
862 // Pre-gfx12 constructor.
863 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
864 : LoadCnt(VmCnt), ExpCnt(ExpCnt), DsCnt(LgkmCnt), StoreCnt(VsCnt),
865 SampleCnt(~0u), BvhCnt(~0u), KmCnt(~0u) {}
866
867 // gfx12+ constructor.
868 Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt,
869 unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
870 : LoadCnt(LoadCnt), ExpCnt(ExpCnt), DsCnt(DsCnt), StoreCnt(StoreCnt),
871 SampleCnt(SampleCnt), BvhCnt(BvhCnt), KmCnt(KmCnt) {}
872
873 static Waitcnt allZero(bool Extended, bool HasStorecnt) {
874 return Extended ? Waitcnt(0, 0, 0, 0, 0, 0, 0)
875 : Waitcnt(0, 0, 0, HasStorecnt ? 0 : ~0u);
876 }
877
878 static Waitcnt allZeroExceptVsCnt(bool Extended) {
879 return Extended ? Waitcnt(0, 0, 0, ~0u, 0, 0, 0) : Waitcnt(0, 0, 0, ~0u);
880 }
881
882 bool hasWait() const { return StoreCnt != ~0u || hasWaitExceptStoreCnt(); }
883
884 bool hasWaitExceptStoreCnt() const {
885 return LoadCnt != ~0u || ExpCnt != ~0u || DsCnt != ~0u ||
886 SampleCnt != ~0u || BvhCnt != ~0u || KmCnt != ~0u;
887 }
888
889 bool hasWaitStoreCnt() const { return StoreCnt != ~0u; }
890
891 Waitcnt combined(const Waitcnt &Other) const {
892 // Does the right thing provided self and Other are either both pre-gfx12
893 // or both gfx12+.
894 return Waitcnt(
895 std::min(LoadCnt, Other.LoadCnt), std::min(ExpCnt, Other.ExpCnt),
896 std::min(DsCnt, Other.DsCnt), std::min(StoreCnt, Other.StoreCnt),
897 std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt),
898 std::min(KmCnt, Other.KmCnt));
899 }
900};
901
902// The following methods are only meaningful on targets that support
903// S_WAITCNT.
904
905/// \returns Vmcnt bit mask for given isa \p Version.
906unsigned getVmcntBitMask(const IsaVersion &Version);
907
908/// \returns Expcnt bit mask for given isa \p Version.
909unsigned getExpcntBitMask(const IsaVersion &Version);
910
911/// \returns Lgkmcnt bit mask for given isa \p Version.
912unsigned getLgkmcntBitMask(const IsaVersion &Version);
913
914/// \returns Waitcnt bit mask for given isa \p Version.
915unsigned getWaitcntBitMask(const IsaVersion &Version);
916
917/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
918unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
919
920/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
921unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
922
923/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
924unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
925
926/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
927/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
928/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction
929/// which needs it is deprecated
930///
931/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
932/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
933/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
934/// \p Vmcnt = \p Waitcnt[15:10] (gfx11)
935/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
936/// \p Expcnt = \p Waitcnt[2:0] (gfx11)
937/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
938/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
939/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11)
940///
941void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
942 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
943
944Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
945
946/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
947unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
948 unsigned Vmcnt);
949
950/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
951unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
952 unsigned Expcnt);
953
954/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
955unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
956 unsigned Lgkmcnt);
957
958/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
959/// \p Version. Should not be used on gfx12+, the instruction which needs
960/// it is deprecated
961///
962/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
963/// Waitcnt[2:0] = \p Expcnt (gfx11+)
964/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
965/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
966/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
967/// Waitcnt[9:4] = \p Lgkmcnt (gfx11)
968/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
969/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
970/// Waitcnt[15:10] = \p Vmcnt (gfx11)
971/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
972///
973/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
974/// isa \p Version.
975///
976unsigned encodeWaitcnt(const IsaVersion &Version,
977 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
978
979unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
980
981// The following methods are only meaningful on targets that support
982// S_WAIT_*CNT, introduced with gfx12.
983
984/// \returns Loadcnt bit mask for given isa \p Version.
985/// Returns 0 for versions that do not support LOADcnt
986unsigned getLoadcntBitMask(const IsaVersion &Version);
987
988/// \returns Samplecnt bit mask for given isa \p Version.
989/// Returns 0 for versions that do not support SAMPLEcnt
990unsigned getSamplecntBitMask(const IsaVersion &Version);
991
992/// \returns Bvhcnt bit mask for given isa \p Version.
993/// Returns 0 for versions that do not support BVHcnt
994unsigned getBvhcntBitMask(const IsaVersion &Version);
995
996/// \returns Dscnt bit mask for given isa \p Version.
997/// Returns 0 for versions that do not support DScnt
998unsigned getDscntBitMask(const IsaVersion &Version);
999
1000/// \returns Dscnt bit mask for given isa \p Version.
1001/// Returns 0 for versions that do not support KMcnt
1002unsigned getKmcntBitMask(const IsaVersion &Version);
1003
1004/// \return STOREcnt or VScnt bit mask for given isa \p Version.
1005/// returns 0 for versions that do not support STOREcnt or VScnt.
1006/// STOREcnt and VScnt are the same counter, the name used
1007/// depends on the ISA version.
1008unsigned getStorecntBitMask(const IsaVersion &Version);
1009
1010// The following are only meaningful on targets that support
1011// S_WAIT_LOADCNT_DSCNT and S_WAIT_STORECNT_DSCNT.
1012
1013/// \returns Decoded Waitcnt structure from given \p LoadcntDscnt for given
1014/// isa \p Version.
1015Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt);
1016
1017/// \returns Decoded Waitcnt structure from given \p StorecntDscnt for given
1018/// isa \p Version.
1019Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt);
1020
1021/// \returns \p Loadcnt and \p Dscnt components of \p Decoded encoded as an
1022/// immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa
1023/// \p Version.
1024unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1025
1026/// \returns \p Storecnt and \p Dscnt components of \p Decoded encoded as an
1027/// immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa
1028/// \p Version.
1029unsigned encodeStorecntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1030
1031namespace Hwreg {
1032
1033LLVM_READONLY
1034int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
1035
1036LLVM_READNONE
1037bool isValidHwreg(int64_t Id);
1038
1039LLVM_READNONE
1040bool isValidHwregOffset(int64_t Offset);
1041
1042LLVM_READNONE
1043bool isValidHwregWidth(int64_t Width);
1044
1045LLVM_READNONE
1046uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
1047
1048LLVM_READNONE
1049StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
1050
1051void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
1052
1053} // namespace Hwreg
1054
1055namespace DepCtr {
1056
1057int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
1058int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1059 const MCSubtargetInfo &STI);
1060bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1061 const MCSubtargetInfo &STI);
1062bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1063 bool &IsDefault, const MCSubtargetInfo &STI);
1064
1065/// \returns Decoded VaVdst from given immediate \p Encoded.
1066unsigned decodeFieldVaVdst(unsigned Encoded);
1067
1068/// \returns Decoded VmVsrc from given immediate \p Encoded.
1069unsigned decodeFieldVmVsrc(unsigned Encoded);
1070
1071/// \returns Decoded SaSdst from given immediate \p Encoded.
1072unsigned decodeFieldSaSdst(unsigned Encoded);
1073
1074/// \returns \p VmVsrc as an encoded Depctr immediate.
1075unsigned encodeFieldVmVsrc(unsigned VmVsrc);
1076
1077/// \returns \p Encoded combined with encoded \p VmVsrc.
1078unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
1079
1080/// \returns \p VaVdst as an encoded Depctr immediate.
1081unsigned encodeFieldVaVdst(unsigned VaVdst);
1082
1083/// \returns \p Encoded combined with encoded \p VaVdst.
1084unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
1085
1086/// \returns \p SaSdst as an encoded Depctr immediate.
1087unsigned encodeFieldSaSdst(unsigned SaSdst);
1088
1089/// \returns \p Encoded combined with encoded \p SaSdst.
1090unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1091
1092} // namespace DepCtr
1093
1094namespace Exp {
1095
1096bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1097
1098LLVM_READONLY
1099unsigned getTgtId(const StringRef Name);
1100
1101LLVM_READNONE
1102bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1103
1104} // namespace Exp
1105
1106namespace MTBUFFormat {
1107
1108LLVM_READNONE
1109int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1110
1111void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1112
1113int64_t getDfmt(const StringRef Name);
1114
1115StringRef getDfmtName(unsigned Id);
1116
1117int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1118
1119StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1120
1121bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1122
1123bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1124
1125int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1126
1127StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1128
1129bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1130
1131int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1132 const MCSubtargetInfo &STI);
1133
1134bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1135
1136unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1137
1138} // namespace MTBUFFormat
1139
1140namespace SendMsg {
1141
1142LLVM_READONLY
1143int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1144
1145LLVM_READONLY
1146int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1147
1148LLVM_READNONE
1149StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1150
1151LLVM_READNONE
1152StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1153
1154LLVM_READNONE
1155bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1156
1157LLVM_READNONE
1158bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1159 bool Strict = true);
1160
1161LLVM_READNONE
1162bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1163 const MCSubtargetInfo &STI, bool Strict = true);
1164
1165LLVM_READNONE
1166bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1167
1168LLVM_READNONE
1169bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1170
1171void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1172 uint16_t &StreamId, const MCSubtargetInfo &STI);
1173
1174LLVM_READNONE
1175uint64_t encodeMsg(uint64_t MsgId,
1176 uint64_t OpId,
1177 uint64_t StreamId);
1178
1179} // namespace SendMsg
1180
1181
1182unsigned getInitialPSInputAddr(const Function &F);
1183
1184bool getHasColorExport(const Function &F);
1185
1186bool getHasDepthExport(const Function &F);
1187
1188LLVM_READNONE
1189bool isShader(CallingConv::ID CC);
1190
1191LLVM_READNONE
1192bool isGraphics(CallingConv::ID CC);
1193
1194LLVM_READNONE
1195bool isCompute(CallingConv::ID CC);
1196
1197LLVM_READNONE
1198bool isEntryFunctionCC(CallingConv::ID CC);
1199
1200// These functions are considered entrypoints into the current module, i.e. they
1201// are allowed to be called from outside the current module. This is different
1202// from isEntryFunctionCC, which is only true for functions that are entered by
1203// the hardware. Module entry points include all entry functions but also
1204// include functions that can be called from other functions inside or outside
1205// the current module. Module entry functions are allowed to allocate LDS.
1206LLVM_READNONE
1207bool isModuleEntryFunctionCC(CallingConv::ID CC);
1208
1209LLVM_READNONE
1210bool isChainCC(CallingConv::ID CC);
1211
1212bool isKernelCC(const Function *Func);
1213
1214// FIXME: Remove this when calling conventions cleaned up
1215LLVM_READNONE
1216inline bool isKernel(CallingConv::ID CC) {
1217 switch (CC) {
1218 case CallingConv::AMDGPU_KERNEL:
1219 case CallingConv::SPIR_KERNEL:
1220 return true;
1221 default:
1222 return false;
1223 }
1224}
1225
1226bool hasXNACK(const MCSubtargetInfo &STI);
1227bool hasSRAMECC(const MCSubtargetInfo &STI);
1228bool hasMIMG_R128(const MCSubtargetInfo &STI);
1229bool hasA16(const MCSubtargetInfo &STI);
1230bool hasG16(const MCSubtargetInfo &STI);
1231bool hasPackedD16(const MCSubtargetInfo &STI);
1232bool hasGDS(const MCSubtargetInfo &STI);
1233unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler = false);
1234unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1235
1236bool isSI(const MCSubtargetInfo &STI);
1237bool isCI(const MCSubtargetInfo &STI);
1238bool isVI(const MCSubtargetInfo &STI);
1239bool isGFX9(const MCSubtargetInfo &STI);
1240bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1241bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI);
1242bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1243bool isGFX8Plus(const MCSubtargetInfo &STI);
1244bool isGFX9Plus(const MCSubtargetInfo &STI);
1245bool isGFX10(const MCSubtargetInfo &STI);
1246bool isGFX10_GFX11(const MCSubtargetInfo &STI);
1247bool isGFX10Plus(const MCSubtargetInfo &STI);
1248bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1249bool isGFX10Before1030(const MCSubtargetInfo &STI);
1250bool isGFX11(const MCSubtargetInfo &STI);
1251bool isGFX11Plus(const MCSubtargetInfo &STI);
1252bool isGFX12(const MCSubtargetInfo &STI);
1253bool isGFX12Plus(const MCSubtargetInfo &STI);
1254bool isNotGFX12Plus(const MCSubtargetInfo &STI);
1255bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1256bool isGCN3Encoding(const MCSubtargetInfo &STI);
1257bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1258bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1259bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1260bool isGFX10_3_GFX11(const MCSubtargetInfo &STI);
1261bool isGFX90A(const MCSubtargetInfo &STI);
1262bool isGFX940(const MCSubtargetInfo &STI);
1263bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
1264bool hasMAIInsts(const MCSubtargetInfo &STI);
1265bool hasVOPD(const MCSubtargetInfo &STI);
1266bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
1267int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1268unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1269
1270/// Is Reg - scalar register
1271bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1272
1273/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
1274/// The bit indicating isHi is the LSB of the encoding.
1275bool isHi(unsigned Reg, const MCRegisterInfo &MRI);
1276
1277/// If \p Reg is a pseudo reg, return the correct hardware register given
1278/// \p STI otherwise return \p Reg.
1279unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1280
1281/// Convert hardware register \p Reg to a pseudo register
1282LLVM_READNONE
1283unsigned mc2PseudoReg(unsigned Reg);
1284
1285LLVM_READNONE
1286bool isInlineValue(unsigned Reg);
1287
1288/// Is this an AMDGPU specific source operand? These include registers,
1289/// inline constants, literals and mandatory literals (KImm).
1290bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1291
1292/// Is this a KImm operand?
1293bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1294
1295/// Is this floating-point operand?
1296bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1297
1298/// Does this operand support only inlinable literals?
1299bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1300
1301/// Get the size in bits of a register from the register class \p RC.
1302unsigned getRegBitWidth(unsigned RCID);
1303
1304/// Get the size in bits of a register from the register class \p RC.
1305unsigned getRegBitWidth(const MCRegisterClass &RC);
1306
1307/// Get size of register operand
1308unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1309 unsigned OpNo);
1310
1311LLVM_READNONE
1312inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1313 switch (OpInfo.OperandType) {
1314 case AMDGPU::OPERAND_REG_IMM_INT32:
1315 case AMDGPU::OPERAND_REG_IMM_FP32:
1316 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
1317 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
1318 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
1319 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
1320 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
1321 case AMDGPU::OPERAND_REG_IMM_V2INT32:
1322 case AMDGPU::OPERAND_REG_IMM_V2FP32:
1323 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
1324 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
1325 case AMDGPU::OPERAND_KIMM32:
1326 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1327 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
1328 return 4;
1329
1330 case AMDGPU::OPERAND_REG_IMM_INT64:
1331 case AMDGPU::OPERAND_REG_IMM_FP64:
1332 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
1333 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
1334 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
1335 return 8;
1336
1337 case AMDGPU::OPERAND_REG_IMM_INT16:
1338 case AMDGPU::OPERAND_REG_IMM_FP16:
1339 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
1340 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1341 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
1342 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1343 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
1344 case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
1345 case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
1346 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
1347 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
1348 case AMDGPU::OPERAND_REG_IMM_V2INT16:
1349 case AMDGPU::OPERAND_REG_IMM_V2FP16:
1350 return 2;
1351
1352 default:
1353 llvm_unreachable("unhandled operand type");
1354 }
1355}
1356
1357LLVM_READNONE
1358inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1359 return getOperandSize(Desc.operands()[OpNo]);
1360}
1361
1362/// Is this literal inlinable, and not one of the values intended for floating
1363/// point values.
1364LLVM_READNONE
1365inline bool isInlinableIntLiteral(int64_t Literal) {
1366 return Literal >= -16 && Literal <= 64;
1367}
1368
1369/// Is this literal inlinable
1370LLVM_READNONE
1371bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1372
1373LLVM_READNONE
1374bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1375
1376LLVM_READNONE
1377bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1378
1379LLVM_READNONE
1380std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal);
1381
1382LLVM_READNONE
1383std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal);
1384
1385LLVM_READNONE
1386bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType);
1387
1388LLVM_READNONE
1389bool isInlinableLiteralV2I16(uint32_t Literal);
1390
1391LLVM_READNONE
1392bool isInlinableLiteralV2F16(uint32_t Literal);
1393
1394LLVM_READNONE
1395bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
1396
1397bool isArgPassedInSGPR(const Argument *Arg);
1398
1399bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1400
1401LLVM_READONLY
1402bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
1403 int64_t EncodedOffset);
1404
1405LLVM_READONLY
1406bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
1407 int64_t EncodedOffset,
1408 bool IsBuffer);
1409
1410/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1411/// offsets.
1412uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
1413
1414/// \returns The encoding that will be used for \p ByteOffset in the
1415/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1416/// S_LOAD instructions have a signed offset, on other subtargets it is
1417/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1418std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1419 int64_t ByteOffset, bool IsBuffer);
1420
1421/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1422/// instruction. This is only useful on CI.s
1423std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1424 int64_t ByteOffset);
1425
1426/// For pre-GFX12 FLAT instructions the offset must be positive;
1427/// MSB is ignored and forced to zero.
1428///
1429/// \return The number of bits available for the signed offset field in flat
1430/// instructions. Note that some forms of the instruction disallow negative
1431/// offsets.
1432unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1433
1434/// \returns true if this offset is small enough to fit in the SMRD
1435/// offset field. \p ByteOffset should be the offset in bytes and
1436/// not the encoded offset.
1437bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1438
1439LLVM_READNONE
1440inline bool isLegalDPALU_DPPControl(unsigned DC) {
1441 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1442}
1443
1444/// \returns true if an instruction may have a 64-bit VGPR operand.
1445bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1446
1447/// \returns true if an instruction is a DP ALU DPP.
1448bool isDPALU_DPP(const MCInstrDesc &OpDesc);
1449
1450/// \returns true if the intrinsic is divergent
1451bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1452
1453/// \returns true if the intrinsic is uniform
1454bool isIntrinsicAlwaysUniform(unsigned IntrID);
1455
1456} // end namespace AMDGPU
1457
1458raw_ostream &operator<<(raw_ostream &OS,
1459 const AMDGPU::IsaInfo::TargetIDSetting S);
1460
1461} // end namespace llvm
1462
1463#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1464

source code of llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h