linux/linux/drivers/gpu/drm/amd/include/ Source Tree

../
aldebaran_ip_offset.h IP_BASE IP_BASE_INSTANCE
amd_acpi.h atcs_pref_req_input atcs_pref_req_output atcs_pwr_shift_input atcs_verify_interface atif_qbtc_arguments atif_qbtc_data_point atif_qbtc_output atif_sbios_requests atif_system_params atif_verify_interface
amd_cper.h cper_aca_reg cper_error_severity cper_hdr cper_sec_crashdump_body_boot cper_sec_crashdump_body_fatal cper_sec_crashdump_boot cper_sec_crashdump_fatal cper_sec_crashdump_hdr cper_sec_crashdump_reg_data cper_sec_desc cper_sec_nonstd_err cper_sec_nonstd_err_ctx cper_sec_nonstd_err_hdr cper_sec_nonstd_err_info cper_timestamp
amd_pcie.h
amd_shared.h DC_DEBUG_MASK DC_FEATURE_MASK PP_FEATURE_MASK amd_apu_flags amd_chip_flags amd_clockgating_state amd_harvest_ip_mask amd_ip_block_type amd_ip_funcs amd_powergating_state
amdgpu_reg_state.h amdgpu_reg_inst_header amdgpu_reg_inst_state amdgpu_reg_state amdgpu_reg_state_header amdgpu_reg_state_pcie_v1_0 amdgpu_reg_state_usr_v1_0 amdgpu_reg_state_wafl_v1_0 amdgpu_reg_state_xgmi_v1_0 amdgpu_regs_pcie_v1_0 amdgpu_regs_usr_v1_0 amdgpu_regs_wafl_v1_0 amdgpu_regs_xgmi_v1_0 amdgpu_smn_reg_data amdgpu_sysfs_reg_offset
arct_ip_offset.h IP_BASE IP_BASE_INSTANCE
[+] asic_reg/
atom-bits.h
atom-names.h
atom-types.h
atombios.h CORE_REF_CLK_SOURCE POWER_CONNECTOR_DETECTION_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 _ADJUST_DISPLAY_PLL_PARAMETERS _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 _ASIC_ENCODER_INFO _ASIC_INIT_CLOCK_PARAMETERS _ASIC_INIT_PARAMETERS _ASIC_INIT_PARAMETERS_V1_2 _ASIC_INIT_PS_ALLOCATION _ASIC_INIT_PS_ALLOCATION_V1_2 _ASIC_TRANSMITTER_INFO _ASIC_TRANSMITTER_INFO_V2 _ATOM_ADJUST_MEMORY_CLOCK_FREQ _ATOM_ANALOG_TV_INFO _ATOM_ASIC_INTERNAL_SS_INFO _ATOM_ASIC_INTERNAL_SS_INFO_V2 _ATOM_ASIC_INTERNAL_SS_INFO_V3 _ATOM_ASIC_MVDD_INFO _ATOM_ASIC_PROFILE_VOLTAGE _ATOM_ASIC_PROFILING_INFO _ATOM_ASIC_PROFILING_INFO_V2_1 _ATOM_ASIC_PROFILING_INFO_V3_1 _ATOM_ASIC_PROFILING_INFO_V3_2 _ATOM_ASIC_PROFILING_INFO_V3_3 _ATOM_ASIC_PROFILING_INFO_V3_4 _ATOM_ASIC_PROFILING_INFO_V3_5 _ATOM_ASIC_PROFILING_INFO_V3_6 _ATOM_ASIC_SS_ASSIGNMENT _ATOM_ASIC_SS_ASSIGNMENT_V2 _ATOM_ASIC_SS_ASSIGNMENT_V3 _ATOM_AVAILABLE_SCLK_LIST _ATOM_BIOS_INT_TVSTD_MODE _ATOM_BRACKET_LAYOUT_RECORD _ATOM_CLK_VOLT_CAPABILITY _ATOM_CLK_VOLT_CAPABILITY_V2 _ATOM_COMMON_RECORD_HEADER _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER _ATOM_COMMON_TABLE_HEADER _ATOM_COMPONENT_VIDEO_INFO _ATOM_COMPONENT_VIDEO_INFO_V21 _ATOM_COMPUTE_CLOCK_FREQ _ATOM_CONNECTOR_AUXDDC_LUT_RECORD _ATOM_CONNECTOR_CF_RECORD _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD _ATOM_CONNECTOR_DEVICE_TAG _ATOM_CONNECTOR_DEVICE_TAG_RECORD _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD _ATOM_CONNECTOR_HARDCODE_DTD_RECORD _ATOM_CONNECTOR_HPDPIN_LUT_RECORD _ATOM_CONNECTOR_INC_SRC_BITMAP _ATOM_CONNECTOR_INFO _ATOM_CONNECTOR_INFO_ACCESS _ATOM_CONNECTOR_INFO_I2C _ATOM_CONNECTOR_LAYOUT_INFO _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD _ATOM_CONNECTOR_REMOTE_CAP_RECORD _ATOM_DAC_INFO _ATOM_DIG_ENCODER_CONFIG_V2 _ATOM_DIG_ENCODER_CONFIG_V3 _ATOM_DIG_ENCODER_CONFIG_V4 _ATOM_DIG_TRANSMITTER_CONFIG_V2 _ATOM_DIG_TRANSMITTER_CONFIG_V3 _ATOM_DIG_TRANSMITTER_CONFIG_V4 _ATOM_DIG_TRANSMITTER_CONFIG_V5 _ATOM_DISPLAY_DEVICE_PRIORITY_INFO _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH _ATOM_DISPLAY_OBJECT_PATH _ATOM_DISPLAY_OBJECT_PATH_TABLE _ATOM_DISP_CLOCK_ID _ATOM_DISP_OUT_INFO _ATOM_DISP_OUT_INFO_V2 _ATOM_DISP_OUT_INFO_V3 _ATOM_DPCD_INFO _ATOM_DP_CONN_CHANNEL_MAPPING _ATOM_DP_VS_MODE _ATOM_DP_VS_MODE_V4 _ATOM_DRAM_DATA_REMAP _ATOM_DTD_FORMAT _ATOM_DVI_CONN_CHANNEL_MAPPING _ATOM_ENCODER_ANALOG_ATTRIBUTE _ATOM_ENCODER_ATTRIBUTE _ATOM_ENCODER_CAP_RECORD _ATOM_ENCODER_CAP_RECORD_V2 _ATOM_ENCODER_DIGITAL_ATTRIBUTE _ATOM_ENCODER_DVO_CF_RECORD _ATOM_ENCODER_FPGA_CONTROL_RECORD _ATOM_EVV_DPM_INFO _ATOM_EVV_VOLTAGE_OBJECT_V3 _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO _ATOM_FAKE_EDID_PATCH_RECORD _ATOM_FIRMWARE_CAPABILITY _ATOM_FIRMWARE_CAPABILITY_ACCESS _ATOM_FIRMWARE_INFO _ATOM_FIRMWARE_INFO_V1_2 _ATOM_FIRMWARE_INFO_V1_3 _ATOM_FIRMWARE_INFO_V1_4 _ATOM_FIRMWARE_INFO_V2_1 _ATOM_FIRMWARE_INFO_V2_2 _ATOM_FIRMWARE_VRAM_RESERVE_INFO _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 _ATOM_FUSION_SYSTEM_INFO_V1 _ATOM_FUSION_SYSTEM_INFO_V2 _ATOM_FUSION_SYSTEM_INFO_V3 _ATOM_GFX_INFO_V2_1 _ATOM_GFX_INFO_V2_3 _ATOM_GPIO_I2C_ASSIGMENT _ATOM_GPIO_I2C_INFO _ATOM_GPIO_INFO _ATOM_GPIO_PIN_ASSIGNMENT _ATOM_GPIO_PIN_CONTROL_PAIR _ATOM_GPIO_PIN_LUT _ATOM_GPIO_VOLTAGE_OBJECT_V3 _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 _ATOM_HOLE_INFO _ATOM_HPD_INT_RECORD _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 _ATOM_HW_MISC_OPERATION_PS_ALLOCATION _ATOM_I2C_DATA_RECORD _ATOM_I2C_DEVICE_SETUP_INFO _ATOM_I2C_ID_CONFIG _ATOM_I2C_ID_CONFIG_ACCESS _ATOM_I2C_RECORD _ATOM_I2C_REG_INFO _ATOM_I2C_VOLTAGE_OBJECT_V3 _ATOM_INIT_REG_BLOCK _ATOM_INIT_REG_INDEX_FORMAT _ATOM_INTEGRATED_SYSTEM_INFO _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 _ATOM_INTEGRATED_SYSTEM_INFO_V2 _ATOM_INTEGRATED_SYSTEM_INFO_V5 _ATOM_INTEGRATED_SYSTEM_INFO_V6 _ATOM_JTAG_RECORD _ATOM_LCD_INFO_V13 _ATOM_LCD_MODE_CONTROL_CAP _ATOM_LCD_REFRESH_RATE_SUPPORT _ATOM_LCD_RTS_RECORD _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 _ATOM_LEAKID_VOLTAGE _ATOM_LVDS_INFO _ATOM_LVDS_INFO_V12 _ATOM_MASTER_COMMAND_TABLE _ATOM_MASTER_DATA_TABLE _ATOM_MASTER_LIST_OF_COMMAND_TABLES _ATOM_MASTER_LIST_OF_DATA_TABLES _ATOM_MC_INIT_PARAM_TABLE _ATOM_MC_INIT_PARAM_TABLE_V2_1 _ATOM_MEMORY_FORMAT _ATOM_MEMORY_SETTING_DATA_BLOCK _ATOM_MEMORY_SETTING_ID_CONFIG _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS _ATOM_MEMORY_TIMING_FORMAT _ATOM_MEMORY_TIMING_FORMAT_V1 _ATOM_MEMORY_TIMING_FORMAT_V2 _ATOM_MEMORY_TRAINING_INFO _ATOM_MEMORY_TRAINING_INFO_V3_1 _ATOM_MEMORY_VENDOR_BLOCK _ATOM_MERGED_VOLTAGE_OBJECT_V3 _ATOM_MISC_CONTROL_INFO _ATOM_MODE_MISC_INFO _ATOM_MODE_MISC_INFO_ACCESS _ATOM_MODE_TIMING _ATOM_MULTIMEDIA_CAPABILITY_INFO _ATOM_MULTIMEDIA_CONFIG_INFO _ATOM_OBJECT _ATOM_OBJECT_GPIO_CNTL_RECORD _ATOM_OBJECT_HEADER _ATOM_OBJECT_HEADER_V3 _ATOM_OBJECT_LINK_RECORD _ATOM_OBJECT_TABLE _ATOM_OEM_INFO _ATOM_OUTPUT_PROTECTION_RECORD _ATOM_PANEL_RESOLUTION_PATCH_RECORD _ATOM_PATCH_RECORD_MODE _ATOM_POWERMODE_INFO _ATOM_POWERMODE_INFO_V2 _ATOM_POWERMODE_INFO_V3 _ATOM_POWERPLAY_INFO _ATOM_POWERPLAY_INFO_V2 _ATOM_POWERPLAY_INFO_V3 _ATOM_POWER_SOURCE_INFO _ATOM_POWER_SOURCE_OBJECT _ATOM_REG_INIT_SETTING _ATOM_ROM_HEADER _ATOM_ROM_HEADER_V2_1 _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD _ATOM_ROUTER_DDC_PATH_SELECT_RECORD _ATOM_SCLK_FCW_RANGE_ENTRY_V1 _ATOM_SERVICE_DESCRIPTION _ATOM_SERVICE_INFO _ATOM_SMU_INFO_V2_1 _ATOM_SPREAD_SPECTRUM_ASSIGNMENT _ATOM_SPREAD_SPECTRUM_INFO _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT _ATOM_STANDARD_VESA_TIMING _ATOM_STD_FORMAT _ATOM_SUPPORTED_DEVICES_INFO _ATOM_SUPPORTED_DEVICES_INFO_2 _ATOM_SUPPORTED_DEVICES_INFO_2d1 _ATOM_SVID2_VOLTAGE_OBJECT_V3 _ATOM_S_MPLL_FB_DIVIDER _ATOM_TABLE_ATTRIBUTE _ATOM_TDP_CONFIG _ATOM_TDP_CONFIG_BITS _ATOM_TMDS_INFO _ATOM_TV_MODE _ATOM_TV_MODE_SCALER_PTR _ATOM_VESA_TO_EXTENDED_MODE _ATOM_VESA_TO_INTENAL_MODE_LUT _ATOM_VOLTAGE_CONTROL _ATOM_VOLTAGE_FORMULA _ATOM_VOLTAGE_FORMULA_V2 _ATOM_VOLTAGE_INFO _ATOM_VOLTAGE_INFO_HEADER _ATOM_VOLTAGE_OBJECT _ATOM_VOLTAGE_OBJECT_HEADER_V3 _ATOM_VOLTAGE_OBJECT_INFO _ATOM_VOLTAGE_OBJECT_INFO_V2 _ATOM_VOLTAGE_OBJECT_INFO_V3_1 _ATOM_VOLTAGE_OBJECT_V2 _ATOM_VOLTAGE_OBJECT_V3 _ATOM_VRAM_GPIO_DETECTION_INFO _ATOM_VRAM_INFO_HEADER_V2_1 _ATOM_VRAM_INFO_HEADER_V2_2 _ATOM_VRAM_INFO_V2 _ATOM_VRAM_INFO_V3 _ATOM_VRAM_INFO_V4 _ATOM_VRAM_MODULE_V1 _ATOM_VRAM_MODULE_V2 _ATOM_VRAM_MODULE_V3 _ATOM_VRAM_MODULE_V4 _ATOM_VRAM_MODULE_V5 _ATOM_VRAM_MODULE_V6 _ATOM_VRAM_MODULE_V7 _ATOM_VRAM_MODULE_V8 _ATOM_VRAM_USAGE_BY_FIRMWARE _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 _ATOM_XTMDS_INFO _BLANK_CRTC_PARAMETERS _CAMERA_DATA _CAMERA_MODULE_INFO _CLOCK_CONDITION_REGESTER_INFO _CLOCK_CONDITION_SETTING_ENTRY _CLOCK_CONDITION_SETTING_INFO _COMPASSIONATE_DATA _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 _CRTC_PIXEL_CLOCK_FREQ _DAC_ENCODER_CONTROL_PARAMETERS _DAC_LOAD_DETECTION_PARAMETERS _DAC_LOAD_DETECTION_PS_ALLOCATION _DFP_DPMS_STATUS_CHANGE_PARAMETERS _DIG_ENCODER_CONTROL_PARAMETERS _DIG_ENCODER_CONTROL_PARAMETERS_V2 _DIG_ENCODER_CONTROL_PARAMETERS_V3 _DIG_ENCODER_CONTROL_PARAMETERS_V4 _DIG_ENCODER_CONTROL_PARAMETERS_V5 _DIG_TRANSMITTER_CONTROL_PARAMETERS _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 _DIG_TRANSMITTER_INFO_HEADER_V3_1 _DIG_TRANSMITTER_INFO_HEADER_V3_2 _DIG_TRANSMITTER_INFO_HEADER_V3_3 _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS _DPHY_ELEC_PARA _DPHY_TIMING_PARA _DP_ENCODER_SERVICE_PARAMETERS _DP_ENCODER_SERVICE_PARAMETERS_V2 _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 _DP_PANEL_MODE_SETUP_PARAMETERS_V5 _DVO_ENCODER_CONTROL_PARAMETERS _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 _DVO_ENCODER_CONTROL_PARAMETERS_V3 _DVO_ENCODER_CONTROL_PS_ALLOCATION _DYNAMICE_ENGINE_SETTINGS_PARAMETER _DYNAMICE_MC_DPM_SETTINGS_PARAMETER _DYNAMICE_MEMORY_SETTINGS_PARAMETER _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 _DYNAMIC_CLOCK_GATING_PARAMETERS _EFUSE_INPUT_PARAMETER _EFUSE_LINEAR_FUNC_PARAM _EFUSE_LOGISTIC_FUNC_PARAM _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS _ENABLE_CRTC_PARAMETERS _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 _ENABLE_DISP_POWER_GATING_PS_ALLOCATION _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 _ENABLE_GRAPH_SURFACE_PARAMETERS _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 _ENABLE_GRAPH_SURFACE_PS_ALLOCATION _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION _ENABLE_LVDS_SS_PARAMETERS _ENABLE_LVDS_SS_PARAMETERS_V2 _ENABLE_SCALER_PARAMETERS _ENABLE_SPREAD_SPECTRUM_ON_PPLL _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 _ENABLE_YUV_PARAMETERS _ENCODER_GENERIC_CMD_PARAMETERS_V5 _ENCODER_LINK_SETUP_PARAMETERS_V5 _ENCODER_STREAM_SETUP_PARAMETERS_V5 _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 _EXT_DISPLAY_PATH _FLASHLIGHT_INFO _GET_DISPLAY_SURFACE_SIZE_PARAMETERS _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 _GET_ENGINE_CLOCK_PARAMETERS _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 _GET_MEMORY_CLOCK_PARAMETERS _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1 _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 _GFX_HAVESTING_PARAMETERS _GPIO_PIN_CONTROL_PARAMETERS _INDIRECT_IO_ACCESS _INTERRUPT_SERVICE_PARAMETERS_V2 _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 _LVDS_ENCODER_CONTROL_PARAMETERS _LVDS_ENCODER_CONTROL_PARAMETERS_V2 _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 _MCuCodeHeader _MEMORY_CLEAN_UP_PARAMETERS _MEMORY_PLLINIT_PARAMETERS _MEMORY_TRAINING_PARAMETERS _MEMORY_TRAINING_PARAMETERS_V1_2 _PALETTE_DATA_CONTROL_PARAMETERS_V3 _PHY_ANALOG_SETTING_INFO _PHY_ANALOG_SETTING_INFO_V2 _PHY_CONDITION_REG_INFO _PHY_CONDITION_REG_INFO_V2 _PHY_CONDITION_REG_VAL _PHY_CONDITION_REG_VAL_V2 _PIXEL_CLOCK_PARAMETERS _PIXEL_CLOCK_PARAMETERS_V2 _PIXEL_CLOCK_PARAMETERS_V3 _PIXEL_CLOCK_PARAMETERS_V5 _PIXEL_CLOCK_PARAMETERS_V6 _PIXEL_CLOCK_PARAMETERS_V7 _POWER_CONNECTOR_DETECTION_PARAMETERS _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS _PRODUCT_BRANDING _PTR_32_BIT_STRUCTURE _PTR_32_BIT_UNION _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS _READ_EFUSE_VALUE_PARAMETER _SELECT_CRTC_SOURCE_PARAMETERS _SELECT_CRTC_SOURCE_PARAMETERS_V2 _SELECT_CRTC_SOURCE_PARAMETERS_V3 _SET_CRTC_OVERSCAN_PARAMETERS _SET_CRTC_REPLICATION_PARAMETERS _SET_CRTC_TIMING_PARAMETERS _SET_CRTC_USING_DTD_TIMING_PARAMETERS _SET_DCE_CLOCK_PARAMETERS_V1_1 _SET_DCE_CLOCK_PARAMETERS_V2_1 _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 _SET_ENGINE_CLOCK_PARAMETERS _SET_ENGINE_CLOCK_PS_ALLOCATION _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 _SET_HWBLOCK_INSTANCE_PARAMETER_V2 _SET_MEMORY_CLOCK_PARAMETERS _SET_MEMORY_CLOCK_PS_ALLOCATION _SET_PIXEL_CLOCK_PS_ALLOCATION _SET_UP_HW_I2C_DATA_PARAMETERS _SET_VOLTAGE_PARAMETERS _SET_VOLTAGE_PARAMETERS_V1_3 _SET_VOLTAGE_PARAMETERS_V2 _SET_VOLTAGE_PS_ALLOCATION _SW_I2C_IO_DATA_PARAMETERS _TV_ENCODER_CONTROL_PARAMETERS _TV_ENCODER_CONTROL_PS_ALLOCATION _VBE_1_2_INFO_BLOCK_UPDATABLE _VBE_2_0_INFO_BLOCK_UPDATABLE _VBE_FP_INFO _VBE_INFO_BLOCK _VBE_VERSION_UNION _VBIOS_ROM_HEADER _VESA_MODE_INFO_BLOCK _VOLTAGE_LUT_ENTRY _VOLTAGE_LUT_ENTRY_V2 _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
atomfirmware.h _flags amd_acpi_description_header asic_init_engine_parameters asic_init_mem_parameters asic_init_parameters_v2_1 asic_init_ps_allocation_v2_1 atom_14nm_combphy_tmds_vs_set atom_14nm_dig_transmitter_info_header_v4_0 atom_14nm_dpphy_dp_setting atom_14nm_dpphy_dp_tuningset atom_14nm_dpphy_dvihdmi_tuningset atom_DCN_dpphy_dp_setting atom_DCN_dpphy_dp_tuningset atom_DCN_dpphy_dvihdmi_tuningset atom_asic_init_engine_flag atom_asic_init_mem_flag atom_asic_profiling_info_v4_1 atom_asic_profiling_info_v4_2 atom_bios_header_version_def atom_blank_crtc_command atom_bracket_layout_record atom_bracket_layout_record_v2 atom_camera_data atom_camera_dphy_elec_param atom_camera_dphy_timing_param atom_camera_flashlight_info atom_camera_module_info atom_common_record_header atom_common_table_header atom_connector_auxddc_lut_record atom_connector_caps_def atom_connector_caps_record atom_connector_forced_tmds_cap_record atom_connector_hpdpin_lut_record atom_connector_layout_info atom_connector_layout_info_connector_type_def atom_connector_layout_info_mini_type_def atom_connector_speed_record atom_cooling_solution_id atom_crtc_def atom_dc_golden_table_v1 atom_dgpu_vram_type atom_dig_def atom_dig_encoder_control_action atom_dig_encoder_control_panelmode atom_dig_encoder_control_v5_digid atom_dig_transmitter_control_action atom_dig_transmitter_control_digfe_sel atom_dig_transmitter_control_dplaneset atom_dig_transmitter_control_hpd_sel atom_disp_connector_caps_record atom_display_controller_info_v4_1 atom_display_controller_info_v4_2 atom_display_controller_info_v4_3 atom_display_controller_info_v4_4 atom_display_controller_info_v4_5 atom_display_device_tag_def atom_display_object_path_v2 atom_display_object_path_v3 atom_display_phy_tuning_info atom_dmi_t17_mem_type_def atom_dp_vs_preemph_def atom_dtd_format atom_dtd_format_modemiscinfo atom_dynamic_memory_setting_command atom_embedded_display_op_def atom_encode_mode_def atom_encoder_caps_def atom_encoder_caps_record atom_encoder_refclk_src_def atom_ext_display_path atom_external_display_connection_info atom_firmware_info_v3_1 atom_firmware_info_v3_2 atom_firmware_info_v3_3 atom_firmware_info_v3_4 atom_firmware_info_v3_5 atom_function_attribute atom_fusion_system_info_v4 atom_gddr6_ac_timing_v2_5 atom_gddr6_bit_byte_remap atom_gddr6_dram_data_remap atom_get_smu_clock_info_command atom_get_smu_clock_info_output_parameters_v3_1 atom_get_smu_clock_info_parameters_v3_1 atom_gfx_info_v2_2 atom_gfx_info_v2_3 atom_gfx_info_v2_4 atom_gfx_info_v2_7 atom_gfx_info_v3_0 atom_glsync_record_gpio_index_def atom_gpio_pin_assignment atom_gpio_pin_assignment_gpio_id atom_gpio_pin_control_pair atom_gpio_pin_control_pinstate_def atom_gpio_pin_lut_v2_1 atom_gpio_voltage_object_v4 atom_gpu_clock_type atom_hdmi_retimer_redriver_set atom_hpd_int_record atom_i2c_data_entry atom_i2c_record atom_i2c_reg_info atom_i2c_voltage_control_flag atom_i2c_voltage_object_v4 atom_integrated_system_info_v1_11 atom_integrated_system_info_v1_12 atom_integrated_system_info_v2_1 atom_integrated_system_info_v2_2 atom_integrated_system_info_v2_3 atom_lcd_info_dptolvds_rx_id atom_lcd_info_panel_misc atom_master_command_function_v2_1 atom_master_data_table_v2_1 atom_master_list_of_command_functions_v2_1 atom_master_list_of_data_tables_v2_1 atom_merged_voltage_object_v4 atom_multimedia_info_v2_1 atom_n6_display_phy_tuning_set atom_object_gpio_cntl_record atom_object_record_type_id atom_operation_def atom_panel_bit_per_color atom_ppll_def atom_process_i2c_flag atom_process_i2c_status atom_rom_header_v2_2 atom_rom_hw_function_header atom_scaler_def atom_set_dce_clock_clock_type atom_set_dce_clock_dprefclk_flag atom_set_dce_clock_pixclk_flag atom_set_engine_mem_clock_flag atom_set_pixel_clock_v1_7_deepcolor_ratio atom_set_pixel_clock_v1_7_misc_info atom_set_voltage_command atom_smc_dpm_info_v4_1 atom_smc_dpm_info_v4_10 atom_smc_dpm_info_v4_3 atom_smc_dpm_info_v4_4 atom_smc_dpm_info_v4_5 atom_smc_dpm_info_v4_6 atom_smc_dpm_info_v4_7 atom_smc_dpm_info_v4_9 atom_smu11_syspll0_clock_id atom_smu11_syspll1_0_clock_id atom_smu11_syspll1_1_clock_id atom_smu11_syspll1_2_clock_id atom_smu11_syspll2_clock_id atom_smu11_syspll3_0_clock_id atom_smu11_syspll3_1_clock_id atom_smu11_syspll_id atom_smu12_syspll0_clock_id atom_smu12_syspll1_clock_id atom_smu12_syspll2_clock_id atom_smu12_syspll3_0_clock_id atom_smu12_syspll3_1_clock_id atom_smu12_syspll_id atom_smu9_syspll0_clock_id atom_smu_info_v3_1 atom_smu_info_v3_2 atom_smu_info_v3_3 atom_smu_info_v3_5 atom_smu_info_v3_6 atom_smu_info_v4_0 atom_spread_spectrum_mode atom_svid2_voltage_object_v4 atom_sys_info_lvds_misc_def atom_sysinfo_dpphy_override_def atom_system_gpucapinf_def atom_system_vbiosmisc_def atom_umc6_0_ucode_function_call_enum_id atom_umc_config1_def atom_umc_config_def atom_umc_info_v3_1 atom_umc_info_v3_2 atom_umc_info_v3_3 atom_umc_info_v4_0 atom_umc_init_reg_block atom_umc_reg_setting_data_block atom_umc_reg_setting_id_config atom_umc_reg_setting_id_config_access atom_umc_register_addr_info atom_umc_register_addr_info_access atom_umc_register_addr_info_flag atom_voltage_gpio_map_lut atom_voltage_object_header_v4 atom_voltage_object_mode atom_voltage_object_v4 atom_voltage_objects_info_v4_1 atom_voltage_type atom_vram_info_header_v2_3 atom_vram_info_header_v2_4 atom_vram_info_header_v2_5 atom_vram_info_header_v2_6 atom_vram_info_header_v3_0 atom_vram_module_v10 atom_vram_module_v11 atom_vram_module_v3_0 atom_vram_module_v9 atombios_firmware_capability atombios_image_offset blank_crtc_parameters compute_gpu_clock_input_parameter_v1_8 compute_gpu_clock_output_parameter_v1_8 dce_info_caps_def dig_encoder_control_parameters_v1_5 dig_encoder_generic_cmd_parameters_v1_5 dig_encoder_link_setup_parameters_v1_5 dig_encoder_stream_setup_parameters_v1_5 dig_transmitter_control_parameters_v1_6 dig_transmitter_control_ps_allocation_v1_6 display_object_info_table_v1_4 display_object_info_table_v1_5 dp_panel_mode_set_parameters_v1_5 dynamic_mclk_settings_parameters_v2_1 dynamic_memory_settings_parameters_v2_1 dynamic_sclk_settings_parameters_v2_1 edp_info_table enable_crtc_parameters enable_disp_power_gating_parameters_v2_1 enable_disp_power_gating_ps_allocation ext_display_path_cap_def external_encoder_control_action_def external_encoder_control_parameters_v2_4 external_encoder_control_ps_allocation_v2_4 external_encoder_control_v2_4_config_def get_engine_clock_parameter get_memory_clock_parameter gop_lib1_content gop_vbios_content lcd_info_v2_1 memory_training_parameters_v2_1 process_aux_channel_transaction_parameters_v1_2 process_i2c_channel_transaction_parameters read_efuse_input_parameters_v3_1 read_efuse_value_parameters_v3_1 scratch_acc_change_info_bits_def scratch_acc_change_info_bitshift_def scratch_active_info_bits_def scratch_bl_bri_level_info_bit_def scratch_device_connect_info_bit_def scratch_device_req_info_bits_def scratch_pre_os_mode_info_bits_def scratch_register_def select_crtc_source_parameters_v2_3 set_crtc_using_dtd_timing_parameters set_dce_clock_parameters_v2_1 set_dce_clock_ps_allocation_v2_1 set_engine_clock_parameters_v2_1 set_engine_clock_ps_allocation_v2_1 set_memory_clock_parameters_v2_1 set_memory_clock_ps_allocation_v2_1 set_pixel_clock_parameter_v1_7 set_voltage_parameters_v1_4 set_voltage_ps_allocation_v1_4 smudpm_i2c_controller_config_v2 smudpm_i2c_controller_config_v3 smudpm_i2ccontrollerconfig_t smudpm_v4_5_i2ccontrollername_e smudpm_v4_5_i2ccontrollerprotocol_e smudpm_v4_5_i2ccontrollerthrottler_e uefi_acpi_vfct uma_carveout_option vfct_image_header vram_usagebyfirmware_v2_1 vram_usagebyfirmware_v2_2
atomfirmwareid.h atom_master_command_table_id atom_master_data_table_id
cgs_common.h cgs_device cgs_firmware_info cgs_ind_reg cgs_ops cgs_ucode_id
cik_structs.h cik_mqd cik_sdma_rlc_registers
cyan_skillfish_ip_offset.h IP_BASE IP_BASE_INSTANCE
dimgrey_cavefish_ip_offset.h IP_BASE IP_BASE_INSTANCE
discovery.h _fuse_data binary_header die die_header die_info gc_info_v1_0 gc_info_v1_1 gc_info_v1_2 gc_info_v1_3 gc_info_v2_0 gc_info_v2_1 gpu_info_header harvest_info harvest_info_header harvest_table ip ip_discovery_header ip_structure ip_v3 ip_v4 mall_info_header mall_info_v1_0 mall_info_v2_0 nps_info_header nps_info_v1_0 nps_instance_info_v1_0 table_info vcn_info_header vcn_info_v1_0 vcn_instance_info_v1_0
dm_pp_interface.h PP_DAL_POWERLEVEL amd_pp_clock_info amd_pp_clock_type amd_pp_clocks amd_pp_display_config_type amd_pp_display_configuration amd_pp_simple_clock_info pp_clock_levels_with_latency pp_clock_levels_with_voltage pp_clock_with_latency pp_clock_with_voltage pp_display_clock_request single_display_configuration
[+] ivsrcid/
kgd_kfd_interface.h kfd2kgd_calls kfd_cu_occupancy kfd_local_mem_info kfd_preempt_type kfd_sched_policy kfd_vm_fault_info kgd2kfd_shared_resources kgd_memory_pool tile_config
kgd_pp_interface.h PP_HWMON_TEMP PP_OD_DPM_TABLE_COMMAND PP_SMC_POWER_PROFILE amd_dpm_forced_level amd_fan_ctrl_mode amd_pm_funcs amd_pm_state_type amd_pp_sensors amd_pp_task amd_vce_level amd_vce_state amdgpu_partition_metrics_v1_0 amdgpu_pm_metrics amdgpu_pmmetrics_header amdgpu_xcp_metrics amdgpu_xcp_metrics_v1_1 amdgpu_xcp_metrics_v1_2 gpu_metrics_v1_0 gpu_metrics_v1_1 gpu_metrics_v1_2 gpu_metrics_v1_3 gpu_metrics_v1_4 gpu_metrics_v1_5 gpu_metrics_v1_6 gpu_metrics_v1_7 gpu_metrics_v1_8 gpu_metrics_v2_0 gpu_metrics_v2_1 gpu_metrics_v2_2 gpu_metrics_v2_3 gpu_metrics_v2_4 gpu_metrics_v3_0 metrics_table_header pp_clock_type pp_df_cstate pp_mp1_state pp_pm_policy pp_policy_soc_pstate pp_power_limit_level pp_power_type pp_states_info pp_xgmi_plpd_mode smu_event_type
mes_v11_api_def.h CHANGE_CONFIG INV_GART MESAPI_AMD_LOG MESAPI_MISC_OPCODE MESAPI_MISC__CHANGE_CONFIG_OPTION MESAPI_SET_HW_RESOURCES MESAPI_SET_HW_RESOURCES_1 MESAPI__ADD_QUEUE MESAPI__CHANGE_GANG_PRIORITY_LEVEL MESAPI__MISC MESAPI__PERFORM_YIELD MESAPI__PROGRAM_GDS MESAPI__QUERY_MES_STATUS MESAPI__REMOVE_QUEUE MESAPI__RESET MESAPI__RESUME MESAPI__SET_DEBUG_VMID MESAPI__SET_LOGGING_BUFFER MESAPI__SET_SCHEDULING_CONFIG MESAPI__SUSPEND MESAPI__UPDATE_ROOT_PAGE_TABLE MES_AMD_PRIORITY_LEVEL MES_API_HEADER MES_API_STATUS MES_API_TYPE MES_LOG_BUFFER MES_LOG_CONTEXT_STATE MES_LOG_CONTEXT_STATE_CHANGE MES_LOG_ENTRY_DATA MES_LOG_ENTRY_HEADER MES_LOG_OPERATION MES_LOG_QUEUE_NEW_WORK MES_LOG_QUEUE_NO_MORE_WORK MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT MES_LOG_QUEUE_WAIT_SYNC_OBJECT MES_QUEUE_TYPE MES_SCH_API_OPCODE MES_SWIP_TO_HWIP_DEF QUERY_STATUS READ_REG SET_DEBUG_VMID_OPERATIONS SET_SHADER_DEBUGGER VM_HUB_TYPE WAIT_REG_MEM WRITE_REG WRM_OPERATION
mes_v12_api_def.h CHANGE_CONFIG INV_GART MESAPI_AMD_LOG MESAPI_MISC_OPCODE MESAPI_MISC__CHANGE_CONFIG_OPTION MESAPI_SET_HW_RESOURCES MESAPI_SET_HW_RESOURCES_1 MESAPI__ADD_QUEUE MESAPI__CHANGE_GANG_PRIORITY_LEVEL MESAPI__MISC MESAPI__PERFORM_YIELD MESAPI__QUERY_MES_STATUS MESAPI__REMOVE_QUEUE MESAPI__RESET MESAPI__RESUME MESAPI__SET_DEBUG_VMID MESAPI__SET_GANG_SUBMIT MESAPI__SET_LOGGING_BUFFER MESAPI__SET_SCHEDULING_CONFIG MESAPI__SET_SE_MODE MESAPI__SUSPEND MESAPI__UPDATE_ROOT_PAGE_TABLE MES_AMD_PRIORITY_LEVEL MES_API_HEADER MES_API_QUERY_MES_OPCODE MES_API_QUERY_MES__CTX_ARRAY_SIZE MES_API_QUERY_MES__HEALTHY_CHECK MES_API_STATUS MES_API_TYPE MES_ERROR_CATEGORY_CODE_12 MES_LOG_BUFFER MES_LOG_CONTEXT_STATE_CHANGE MES_LOG_ENTRY_DATA MES_LOG_ENTRY_HEADER MES_LOG_QUEUE_NEW_WORK MES_LOG_QUEUE_NO_MORE_WORK MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT MES_LOG_QUEUE_WAIT_SYNC_OBJECT MES_MS_LOG_CONTEXT_STATE MES_MS_LOG_OPERATION MES_QUEUE_TYPE MES_SCH_API_OPCODE MES_SE_MODE MES_SWIP_TO_HWIP_DEF QUERY_STATUS READ_REG SET_DEBUG_VMID_OPERATIONS SET_GANG_SUBMIT SET_SHADER_DEBUGGER VM_HUB_TYPE WAIT_REG_MEM WRITE_REG WRM_OPERATION
navi10_enum.h AFMT_AUDIO_CRC_CONTROL_CH_SEL AFMT_AUDIO_CRC_CONTROL_CONT AFMT_AUDIO_CRC_CONTROL_SOURCE AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS AFMT_AUDIO_SRC_CONTROL_SELECT AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE AFMT_INTERRUPT_STATUS_CHG_MASK AFMT_RAMP_CONTROL0_SIGN AFMT_VBI_GSP_INDEX ALLOW_SR_ON_TRANS_REQ ARRAY_MODE AUDIO_LAYOUT_SELECT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE AZALIA_SOFT_RESET_REFCLK_SOFT_RESET AZ_CORB_SIZE AZ_GLOBAL_CAPABILITIES AZ_LATENCY_COUNTER_CONTROL AZ_RIRB_SIZE AZ_RIRB_WRITE_POINTER_RESET AZ_STATE_CHANGE_STATUS ArrayMode BANK_HEIGHT BANK_WIDTH BUF_DATA_FORMAT BUF_FMT BUF_NUM_FORMAT BankHeight BankInterleaveSize BankSwapBytes BankTiling BankWidth BankWidthHeight BinEventCntl BinMapMode BinSizeExtend BinningMode BlendOp BlendOpt CBMode CBPerfClearFilterSel CBPerfOpFilterSel CBPerfSel CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY CHA_PERF_SEL CHCG_PERF_SEL CHC_PERF_SEL CHUNK_SIZE CLEAR_SMU_INTR CLKGATE_BASE_MODE CLKGATE_SM_MODE CLOCK_BRANCH_SOFT_RESET CLOCK_GATING_DISABLE_ENUM CLOCK_GATING_EN CMC_3DLUT_30BIT_ENUM CMC_3DLUT_RAM_SEL CMC_3DLUT_SIZE_ENUM CMC_LUT_2_CONFIG_ENUM CMC_LUT_2_MODE_ENUM CMC_LUT_NUM_SEG CMC_LUT_RAM_SEL CM_BYPASS CM_COEF_FORMAT_ENUM CM_DATA_SIGNED CM_EN CM_GAMUT_REMAP_MODE_ENUM CM_ICSC_MODE_ENUM CM_LUT_2_CONFIG_ENUM CM_LUT_2_MODE_ENUM CM_LUT_4_CONFIG_ENUM CM_LUT_4_MODE_ENUM CM_LUT_NUM_SEG CM_LUT_RAM_SEL CM_PENDING CM_WRITE_BASE_ONLY CNVC_BYPASS CNVC_ENABLE CNVC_PENDING CNV_CSC_BYPASS_ENUM CNV_EYE_SELECT CNV_FRAME_CAPTURE_EN_ENUM CNV_FRAME_CAPTURE_RATE_ENUM CNV_INTERLACED_FIELD_ORDER_ENUM CNV_INTERLACED_MODE_ENUM CNV_NEW_CONTENT_ENUM CNV_OUT_BPC_ENUM CNV_STEREO_POLARITY_ENUM CNV_STEREO_SPLIT_ENUM CNV_STEREO_TYPE_ENUM CNV_TEST_CRC_CONT_EN_ENUM CNV_TEST_CRC_EN_ENUM CNV_UPDATE_LOCK_ENUM CNV_UPDATE_PENDING_ENUM CNV_WINDOW_CROP_EN_ENUM COEF_RAM_SELECT_RD COLOR_KEYER_MODE CORB_READ_POINTER_RESET CPC_LATENCY_STATS_SEL CPC_PERFCOUNT_SEL CPF_LATENCY_STATS_SEL CPF_PERFCOUNTWINDOW_SEL CPF_PERFCOUNT_SEL CPG_LATENCY_STATS_SEL CPG_PERFCOUNTWINDOW_SEL CPG_PERFCOUNT_SEL CP_ALPHA_TAG_RAM_SEL CP_DDID_CNTL_MODE CP_DDID_CNTL_SIZE CP_DDID_CNTL_VMID_SEL CP_ME_ID CP_PERFMON_ENABLE_MODE CP_PERFMON_STATE CP_PIPE_ID CP_RING_ID CRC_CUR_BITS_SEL CRC_CUR_SEL CRC_INTERLACE_SEL CRC_IN_CUR_SEL CRC_IN_PIX_SEL CRC_SRC_SEL CRC_STEREO_SEL CROB_MEM_PWR_LIGHT_SLEEP_MODE CROSSBAR_FOR_ALPHA CROSSBAR_FOR_CB_B CROSSBAR_FOR_CR_R CROSSBAR_FOR_Y_G CSCNTL_TYPE CSDATA_TYPE CURSOR_2X_MAGNIFY CURSOR_ENABLE CURSOR_LINES_PER_CHUNK CURSOR_MODE CURSOR_PERFMON_LATENCY_MEASURE_EN CURSOR_PERFMON_LATENCY_MEASURE_SEL CURSOR_PITCH CURSOR_SNOOP CURSOR_STEREO_EN CURSOR_SURFACE_TMZ CURSOR_SYSTEM CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS CUR_ENABLE CUR_EXPAND_MODE CUR_INV_CLAMP CUR_MODE CUR_PENDING CUR_ROM_EN CmaskAddr CmaskCode CmaskMode ColorArray ColorFormat ColorTransform CombFunc CompareFrag CompareRef ConservativeZExport CovToShaderSel DAC_MUX_SELECT DCCG_AUDIO_DTO0_SOURCE_SEL DCCG_AUDIO_DTO2_SOURCE_SEL DCCG_AUDIO_DTO_SEL DCCG_AUDIO_DTO_USE_512FBR_DTO DCCG_DEEP_COLOR_CNTL DCCG_FIFO_ERRDET_OVR_EN DCCG_FIFO_ERRDET_RESET DCCG_FIFO_ERRDET_STATE DCCG_PERF_MODE_HSYNC DCCG_PERF_MODE_VSYNC DCCG_PERF_OTG_SELECT DCCG_PERF_RUN DCIOCHIP_AUXSLAVE_PAD_MODE DCIOCHIP_AUX_ALL_PWR_OK DCIOCHIP_AUX_CSEL0P9 DCIOCHIP_AUX_CSEL1P1 DCIOCHIP_AUX_FALLSLEWSEL DCIOCHIP_AUX_HYS_TUNE DCIOCHIP_AUX_RECEIVER_SEL DCIOCHIP_AUX_RSEL0P9 DCIOCHIP_AUX_RSEL1P1 DCIOCHIP_AUX_SPIKESEL DCIOCHIP_AUX_VOD_TUNE DCIOCHIP_DVO_VREFPON DCIOCHIP_DVO_VREFSEL DCIOCHIP_ENABLE_2BIT DCIOCHIP_ENABLE_4BIT DCIOCHIP_ENABLE_5BIT DCIOCHIP_GPIO_I2C_DRIVE DCIOCHIP_GPIO_I2C_EN DCIOCHIP_GPIO_I2C_MASK DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL DCIOCHIP_I2C_COMPSEL DCIOCHIP_I2C_FALLSLEWSEL DCIOCHIP_I2C_RECEIVER_SEL DCIOCHIP_I2C_VPH_1V2_EN DCIOCHIP_INVERT DCIOCHIP_MASK DCIOCHIP_MASK_2BIT DCIOCHIP_MASK_4BIT DCIOCHIP_MASK_5BIT DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL DCIOCHIP_SPDIF1_IMODE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN DCIO_BL_PWM_CNTL_BL_PWM_EN DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN DCIO_BL_PWM_GRP1_REG_LOCK DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_DACA_SOFT_RESET DCIO_DCRXPHY_SOFT_RESET DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN DCIO_DC_GENERICA_SEL DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL DCIO_DIO_EXT_VSYNC_MASK DCIO_DIO_OTG_EXT_VSYNC_MUX DCIO_DPCS_INTERRUPT_MASK DCIO_DPCS_INTERRUPT_TYPE DCIO_DPHY_LANE_SEL DCIO_DSYNC_SOFT_RESET DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK DCIO_GSL_SEL DCIO_IMPCAL_STEP_DELAY DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION DC_DMCUB_INT_TYPE DC_DMCUB_TIMER_WINDOW DC_MEM_GLOBAL_PWR_REQ_DIS DC_SMU_INTERRUPT_ENABLE DENORM_TRUNCATE DETILE_BUFFER_PACKER_ENABLE DET_MEM_PWR_LIGHT_SLEEP_MODE DFQ_MIN_FREE_ENTRIES DFQ_NUM_ENTRIES DFQ_SIZE DFSMFlushEvents DIG_BE_CNTL_HPD_SELECT DIG_BE_CNTL_MODE DIG_DIGITAL_BYPASS_SEL DIG_FE_CNTL_SOURCE_SELECT DIG_FE_CNTL_STEREOSYNC_SELECT DIG_FIFO_ERROR_ACK DIG_FIFO_READ_CLOCK_SRC DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL DIG_INPUT_PIXEL_SEL DIG_OUTPUT_CRC_CNTL_LINK_SEL DIG_OUTPUT_CRC_DATA_SEL DIG_RANDOM_PATTERN_SEED_RAN_PAT DIG_TEST_PATTERN_EXTERNAL_RESET_EN DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN DIG_TEST_PATTERN_RANDOM_PATTERN_RESET DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN DIM_TYPE DIOMEM_PWR_DIS_CTRL DIOMEM_PWR_FORCE_CTRL DIOMEM_PWR_FORCE_CTRL2 DIOMEM_PWR_SEL_CTRL DIOMEM_PWR_SEL_CTRL2 DIO_FIFO_ERROR DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE DISABLE_CLOCK_GATING DISABLE_CLOCK_GATING_IN_DCO DISPCLK_CHG_FWD_CORR_DISABLE DISPCLK_FREQ_RAMP_DONE DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE DMDATA_DONE DMDATA_MODE DMDATA_QOS_MODE DMDATA_REPEAT DMDATA_UNDERFLOW DMDATA_UNDERFLOW_CLEAR DMDATA_UPDATED DMU_CLOCK_GATING_DISABLE DMU_CLOCK_ON DMU_DC_GPU_TIMER_READ_SELECT DMU_DC_GPU_TIMER_START_POSITION DOLBY_VISION_ENABLE DOUT_I2C_ACK DOUT_I2C_ARBITRATION_ABORT_XFER DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO DOUT_I2C_ARBITRATION_SW_PRIORITY DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ DOUT_I2C_CONTROL_DDC_SELECT DOUT_I2C_CONTROL_GO DOUT_I2C_CONTROL_SEND_RESET DOUT_I2C_CONTROL_SEND_RESET_LENGTH DOUT_I2C_CONTROL_SOFT_RESET DOUT_I2C_CONTROL_SW_STATUS_RESET DOUT_I2C_CONTROL_TRANSACTION_COUNT DOUT_I2C_DATA_INDEX_WRITE DOUT_I2C_DDC_EDID_DETECT_STATUS DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE DOUT_I2C_DDC_SPEED_THRESHOLD DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE DOUT_I2C_TRANSACTION_STOP_ON_NACK DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL DPCSTX_DVI_LINK_MODE DPHY_8B10B_CUR_DISP DPHY_8B10B_RESET DPHY_ATEST_SEL_LANE0 DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3 DPHY_BYPASS DPHY_CRC_CONT_EN DPHY_CRC_EN DPHY_CRC_FIELD DPHY_CRC_MST_PHASE_ERROR_ACK DPHY_CRC_SEL DPHY_FEC_ENABLE DPHY_FEC_READY DPHY_LOAD_BS_COUNT_START DPHY_PRBS_EN DPHY_PRBS_SEL DPHY_RX_FAST_TRAINING_CAPABLE DPHY_SKEW_BYPASS DPHY_SW_FAST_TRAINING_START DPHY_TRAINING_PATTERN_SEL DPREFCLK_SRC_SEL DPTE_GROUP_SIZE DP_AUX_ARB_CONTROL_ARB_PRIORITY DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ DP_AUX_CONTROL_HPD_SEL DP_AUX_CONTROL_TEST_MODE DP_AUX_DEFINITE_ERR_REACHED_ACK DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW DP_AUX_DPHY_RX_CONTROL_START_WINDOW DP_AUX_DPHY_RX_DETECTION_THRESHOLD DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL DP_AUX_ERR_OCCURRED_ACK DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN DP_AUX_INT_ACK DP_AUX_LS_UPDATE_ACK DP_AUX_PHY_WAKE_PRIORITY DP_AUX_POTENTIAL_ERR_REACHED_ACK DP_AUX_RESET DP_AUX_RESET_DONE DP_AUX_RX_TIMEOUT_LEN_MUL DP_AUX_SW_CONTROL_LS_READ_TRIG DP_AUX_SW_CONTROL_SW_GO DP_AUX_TX_PRECHARGE_LEN_MUL DP_COMBINE_PIXEL_NUM DP_COMPONENT_DEPTH DP_DPHY_8B10B_EXT_DISP DP_DPHY_FAST_TRAINING_COMPLETE_ACK DP_DPHY_FAST_TRAINING_COMPLETE_MASK DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN DP_DPHY_HBR2_PATTERN_CONTROL_MODE DP_DSC_MODE DP_DTO_DS_DISABLE DP_EMBEDDED_PANEL_MODE DP_LINK_TRAINING_COMPLETE DP_LINK_TRAINING_SWITCH_MODE DP_ML_PHY_SEQ_MODE DP_MSA_V_TIMING_OVERRIDE_EN DP_MSE_BLANK_CODE DP_MSE_LINK_LINE DP_MSE_SAT_UPDATE_ACT DP_MSE_TIMESTAMP_MODE DP_MSE_ZERO_ENCODER DP_MSO_NUM_OF_SST_LINKS DP_PIXEL_ENCODING DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE DP_SEC_ASP_PRIORITY DP_SEC_AUDIO_MUTE DP_SEC_COLLISION_ACK DP_SEC_GSP0_PRIORITY DP_SEC_GSP_SEND DP_SEC_GSP_SEND_ANY_LINE DP_SEC_GSP_SEND_PPS DP_SEC_LINE_REFERENCE DP_SEC_TIMESTAMP_MODE DP_STEER_OVERFLOW_ACK DP_STEER_OVERFLOW_MASK DP_SYNC_POLARITY DP_TU_OVERFLOW_ACK DP_UDI_LANES DP_VID_ENHANCED_FRAME_MODE DP_VID_M_N_DOUBLE_BUFFER_MODE DP_VID_M_N_GEN_EN DP_VID_N_MUL DP_VID_STREAM_DISABLE_ACK DP_VID_STREAM_DISABLE_MASK DP_VID_STREAM_DIS_DEFER DP_VID_VBID_FIELD_POL DRR_UPDATE_LOCK_SEL DSCCIF_BITS_PER_COMPONENT_ENUM DSCCIF_ENABLE_ENUM DSCCIF_INPUT_PIXEL_FORMAT_ENUM DSCC_BITS_PER_COMPONENT_ENUM DSCC_DSC_VERSION_MAJOR_ENUM DSCC_DSC_VERSION_MINOR_ENUM DSCC_ENABLE_ENUM DSCC_ICH_RESET_ENUM DSCC_LINEBUF_DEPTH_ENUM DSCC_MEM_PWR_DIS_ENUM DSCC_MEM_PWR_FORCE_ENUM DSCL_MODE_SEL DSM_DATA_SEL DSM_ENABLE_ERROR_INJECT DSM_SELECT_INJECT_DELAY DSM_SINGLE_WRITE DS_HW_CAL_ENABLE DS_JITTER_COUNT_SRC_SEL DS_REF_SRC DVOACLKC_IN_PHASE DVOACLKC_MVP_IN_PHASE DVOACLKC_MVP_SKEW_PHASE_OVERRIDE DVOACLKD_IN_PHASE DVOACLK_COARSE_SKEW_CNTL DVOACLK_FINE_SKEW_CNTL DVO_ENABLE_RST DWB_DATA_DEPTH_WARMUP_ENUM DWB_GMC_WARM_UP_ENABLE_ENUM DWB_MODE_WARMUP_ENUM DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE DbMemArbWatermarks DbPRTFaultBehavior DbPSLControl DepthArray DepthFormat EFC_SURFACE_PIXEL_FORMAT ENABLE ENABLE_CLOCK ENABLE_ENUM ENUM_DPG_BIT_DEPTH ENUM_DPG_DYNAMIC_RANGE ENUM_DPG_EN ENUM_DPG_FIELD_POLARITY ENUM_DPG_MODE ENUM_FMT_PTI_FIELD_POLARITY ENUM_NUM_SIMD_PER_CU FEC_ACTIVE_STATUS FLIP_RATE FMTMEM_PWR_DIS_CTRL FMTMEM_PWR_FORCE_CTRL FMT_BIT_DEPTH_CONTROL_25FRC_SEL FMT_BIT_DEPTH_CONTROL_50FRC_SEL FMT_BIT_DEPTH_CONTROL_75FRC_SEL FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE FMT_CLAMP_CNTL_COLOR_FORMAT FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS FMT_CONTROL_PIXEL_ENCODING FMT_CONTROL_SUBSAMPLING_MODE FMT_CONTROL_SUBSAMPLING_ORDER FMT_DYNAMIC_EXP_MODE FMT_FRAME_RANDOM_ENABLE_CONTROL FMT_POWER_STATE_ENUM FMT_RGB_RANDOM_ENABLE_CONTROL FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL FMT_SPATIAL_DITHER_MODE FMT_STEREOSYNC_OVERRIDE_CONTROL FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 ForceControl FullTileWaveBreak GATCL1RequestType GB_EDC_DED_MODE GCRPerfSel GDS_PERFCOUNT_SELECT GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED GENERIC_AZ_CONTROLLER_REGISTER_STATUS GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED GENERIC_STEREOSYNC_SEL GE_PERFCOUNT_SELECT GL0V_CACHE_POLICIES GL1A_PERF_SEL GL1CG_PERF_SEL GL1C_PERF_SEL GL1_CACHE_POLICIES GL1_CACHE_STORE_POLICIES GL2A_PERF_SEL GL2C_PERF_SEL GL2_CACHE_POLICIES GL2_EA_CID GL2_NACKS GL2_OP GL2_OP_MASKS GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE GLOBAL_CONTROL_CONTROLLER_RESET GLOBAL_CONTROL_FLUSH_CONTROL GLOBAL_STATUS_FLUSH_STATUS GRBM_PERF_SEL GRBM_SE0_PERF_SEL GRBM_SE1_PERF_SEL GRBM_SE2_PERF_SEL GRBM_SE3_PERF_SEL GroupInterleave HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CONT HDMI_ACR_N_MULTIPLE HDMI_ACR_SELECT HDMI_ACR_SEND HDMI_ACR_SOURCE HDMI_AUDIO_DELAY_EN HDMI_AUDIO_INFO_CONT HDMI_AUDIO_INFO_SEND HDMI_AUDIO_SEND_MAX_PACKETS HDMI_CLOCK_CHANNEL_RATE HDMI_DEEP_COLOR_DEPTH HDMI_DEFAULT_PAHSE HDMI_ERROR_ACK HDMI_ERROR_MASK HDMI_GC_AVMUTE HDMI_GC_AVMUTE_CONT HDMI_GC_CONT HDMI_GC_SEND HDMI_GENERIC_CONT HDMI_GENERIC_SEND HDMI_ISRC_CONT HDMI_ISRC_SEND HDMI_KEEPOUT_MODE HDMI_METADATA_ENABLE HDMI_MPEG_INFO_CONT HDMI_MPEG_INFO_SEND HDMI_NO_EXTRA_NULL_PACKET_FILLED HDMI_NULL_SEND HDMI_PACKET_GEN_VERSION HDMI_PACKET_LINE_REFERENCE HDMI_PACKING_PHASE_OVERRIDE HPD_INT_CONTROL_ACK HPD_INT_CONTROL_POLARITY HPD_INT_CONTROL_RX_INT_ACK HUBP_BLANK_EN HUBP_DISABLE HUBP_IN_BLANK HUBP_MEASURE_WIN_MODE_DCFCLK HUBP_NO_OUTSTANDING_REQ HUBP_TTU_DISABLE HUBP_VREADY_AT_OR_AFTER_VSYNC HUBP_VTG_SEL HUBP_XFC_CHUNK_SIZE_ENUM HUBP_XFC_FRAME_MODE_ENUM HUBP_XFC_PIXEL_FORMAT_ENUM H_MIRROR_EN Hdp_SurfaceEndian IHC_INTERRUPT_LINE_STATUS IH_CLIENT_TYPE IH_INTERFACE_TYPE IH_PERF_SEL IH_RING_ID IH_VF_RB_SELECT IMG_DATA_FORMAT IMG_FMT IMG_NUM_FORMAT IMG_NUM_FORMAT_FMASK IMG_NUM_FORMAT_N_IN_16 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID INT_MASK INVALID_REG_ACCESS_TYPE JITTER_REMOVE_DISABLE LB_ALPHA_EN LB_INTERLEAVE_EN LEGACY_NUM_BANKS LEGACY_PIPE_INTERLEAVE LVTMA_RANDOM_PATTERN_SEED_RAN_PAT MACRO_TILE_ASPECT MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_SEL MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE MAX_COMPRESSED_FRAGS MEM_PWR_DIS_CTRL MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2 MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2 METADATA_HUBP_SEL METADATA_STREAM_TYPE_SEL META_CHUNK_SIZE META_LINEAR MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL MICRO_TILE_MODE_NEW MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL MIN_CHUNK_SIZE MIN_META_CHUNK_SIZE MMHUBBUB_XFC_FRAME_MODE_ENUM MMHUBBUB_XFC_PIXEL_FORMAT_ENUM MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM MMHUBBUB_XFC_XFCMON_MODE_ENUM MPCC_BG_COLOR_BPC MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY MPCC_CONTROL_MPCC_ALPHA_BLND_MODE MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE MPCC_CONTROL_MPCC_BOT_GAIN_MODE MPCC_CONTROL_MPCC_MODE MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_MODE_MPCC_OGAM_MODE MPCC_SM_CONTROL_MPCC_SM_EN MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT MPCC_SM_CONTROL_MPCC_SM_MODE MPCC_STALL_STATUS_MPCC_STALL_INT_ACK MPCC_STALL_STATUS_MPCC_STALL_INT_MASK MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET MPC_CFG_ADR_VUPDATE_LOCK_SET MPC_CFG_CFG_VUPDATE_LOCK_SET MPC_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_MPC_TEST_CLK_SEL MPC_CRC_CALC_INTERLACE_MODE MPC_CRC_CALC_MODE MPC_CRC_CALC_STEREO_MODE MPC_CRC_SOURCE_SELECT MPC_OCSC_COEF_FORMAT MPC_OUT_CSC_MODE MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE MPC_OUT_RATE_CONTROL_DISABLE_SET MPTE_GROUP_SIZE MTYPE MacroTileAspect MemArbMode MicroTileMode MultiGPUTileSize NUM_BANKS NUM_BANKS_BC_ENUM NUM_PIPES NUM_PIPES_BC_ENUM NUM_RB_PER_SE NUM_SE NonDispTilingOrder NumBanks NumBanksConfig NumGPUs NumLowerPipes NumMaxCompressedFragments NumPipes NumRbPerShaderEngine NumShaderEngines OBUF_BYPASS_SEL OBUF_IS_HALF_RECOUT_WIDTH_SEL OBUF_USE_FULL_BUFFER_SEL OPP_PIPE_CLOCK_ENABLE_CONTROL OPP_PIPE_CRC_CONT_EN OPP_PIPE_CRC_EN OPP_PIPE_CRC_INTERLACE_EN OPP_PIPE_CRC_INTERLACE_MODE OPP_PIPE_CRC_ONE_SHOT_PENDING OPP_PIPE_CRC_PIXEL_SELECT OPP_PIPE_CRC_SOURCE_SELECT OPP_PIPE_CRC_STEREO_EN OPP_PIPE_CRC_STEREO_MODE OPP_PIPE_DIGTIAL_BYPASS_CONTROL OPP_TEST_CLK_SEL_CONTROL OPP_TOP_CLOCK_ENABLE_STATUS OPP_TOP_CLOCK_GATING_CONTROL OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE OTG_ADD_PIXEL OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE OTG_CONTROL_OTG_DISABLE_POINT_CNTL OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE OTG_CONTROL_OTG_FIELD_NUMBER_CNTL OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY OTG_CONTROL_OTG_MASTER_EN OTG_CONTROL_OTG_SOF_PULL_EN OTG_CONTROL_OTG_START_POINT_CNTL OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE OTG_CRC_CNTL2_OTG_CRC_DSC_MODE OTG_CRC_CNTL_OTG_CRC_CONT_EN OTG_CRC_CNTL_OTG_CRC_EN OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE OTG_CRC_CNTL_OTG_CRC_STEREO_MODE OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY OTG_DROP_PIXEL OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL OTG_GSL_MASTER_MODE OTG_HORZ_REPETITION_COUNT OTG_H_SYNC_A_POL OTG_H_TIMING_DIV_BY2 OTG_H_TIMING_DIV_BY2_UPDATE_MODE OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE OTG_MASTER_UPDATE_LOCK_GSL_EN OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR OTG_PIPE_ABORT OTG_PTI_CONTROL_OTG_PIT_EN OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN OTG_START_LINE_CONTROL_OTG_PREFETCH_EN OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE OTG_STEREO_CONTROL_OTG_STEREO_EN OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT OTG_TRIGA_FALLING_EDGE_DETECT_CNTL OTG_TRIGA_FREQUENCY_SELECT OTG_TRIGA_RISING_EDGE_DETECT_CNTL OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT OTG_TRIGB_FALLING_EDGE_DETECT_CNTL OTG_TRIGB_FREQUENCY_SELECT OTG_TRIGB_RISING_EDGE_DETECT_CNTL OTG_UPDATE_LOCK_OTG_UPDATE_LOCK OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR OTG_V_SYNC_A_POL OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE PERFCOUNTER_ACTIVE PERFCOUNTER_CNT0_STATE PERFCOUNTER_CNT1_STATE PERFCOUNTER_CNT2_STATE PERFCOUNTER_CNT3_STATE PERFCOUNTER_CNT4_STATE PERFCOUNTER_CNT5_STATE PERFCOUNTER_CNT6_STATE PERFCOUNTER_CNT7_STATE PERFCOUNTER_CNTL_SEL PERFCOUNTER_CNTOFF_START_DIS PERFCOUNTER_COUNTED_VALUE_TYPE PERFCOUNTER_CVALUE_SEL PERFCOUNTER_HW_CNTL_SEL PERFCOUNTER_HW_STOP1_SEL PERFCOUNTER_HW_STOP2_SEL PERFCOUNTER_INC_MODE PERFCOUNTER_INT_EN PERFCOUNTER_INT_TYPE PERFCOUNTER_OFF_MASK PERFCOUNTER_RESTART_EN PERFCOUNTER_RUNEN_MODE PERFCOUNTER_STATE_SEL0 PERFCOUNTER_STATE_SEL1 PERFCOUNTER_STATE_SEL2 PERFCOUNTER_STATE_SEL3 PERFCOUNTER_STATE_SEL4 PERFCOUNTER_STATE_SEL5 PERFCOUNTER_STATE_SEL6 PERFCOUNTER_STATE_SEL7 PERFMON_CNTOFF_AND_OR PERFMON_CNTOFF_INT_EN PERFMON_CNTOFF_INT_TYPE PERFMON_COUNTER_MODE PERFMON_SPM_MODE PERFMON_STATE PH_PERFCNT_SEL PIPE_ALIGNED PIPE_CONFIG PIPE_INTERLEAVE PIPE_PHYPLL_PIXEL_RATE_SOURCE PIPE_PIXEL_RATE_PLL_SOURCE PIPE_PIXEL_RATE_SOURCE PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE PIX_EXPAND_MODE PLL_CFG_IF_SOFT_RESET PM_ASSERT_RESET POWER_STATE_ENUM PTE_ROW_HEIGHT_LINEAR PerfCounter_Vals PipeConfig PipeInterleaveSize PipeTiling PixelPipeCounterId PixelPipeStride PkrMap PkrXsel PkrXsel2 PkrYsel QuadExportFormat QuadExportFormatOld RB_ALIGNED RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET RDPCSTX_CNTL_RDPCS_TX_FIFO_EN RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE RDPCS_TEST_CLK_SEL RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE REFCLK_CLOCK_EN REFCLK_SRC_SEL RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL RMIPerfSel RMI_CID ROTATION_ANGLE RbMap RbXsel RbXsel2 RbYsel ReadPolicy ReadSize RingCounterControl RoundMode RowSize RowTiling SCL_2TAP_HARDCODE SCL_ALPHA_COEF SCL_AUTOCAL_MODE SCL_BOUNDARY SCL_CHROMA_COEF SCL_COEF_FILTER_TYPE_SEL SCL_COEF_RAM_SEL SCL_SHARP_EN SC_PERFCNT_SEL SDMA_PERF_SEL SEM_PERF_SEL SH_MEM_ADDRESS_MODE SH_MEM_ALIGNMENT_MODE SH_MEM_RETRY_MODE SOFT_RESET SPI_FOG_MODE SPI_LB_WAVES_SELECT SPI_PERFCNT_SEL SPI_PNT_SPRITE_OVERRIDE SPI_SAMPLE_CNTL SPI_SHADER_EX_FORMAT SPI_SHADER_FORMAT SPM_PERFMON_STATE SQ_CAC_POWER_SEL SQ_EDC_INFO_SOURCE SQ_IBUF_ST SQ_IMG_FILTER_TYPE SQ_IND_CMD_CMD SQ_IND_CMD_MODE SQ_INST_STR_ST SQ_INTERRUPT_WORD_ENCODING SQ_OOB_SELECT SQ_PERF_SEL SQ_ROUND_MODE SQ_RSRC_BUF_TYPE SQ_RSRC_FLAT_TYPE SQ_RSRC_IMG_TYPE SQ_SEL_XYZW01 SQ_TEX_ANISO_RATIO SQ_TEX_BORDER_COLOR SQ_TEX_CLAMP SQ_TEX_DEPTH_COMPARE SQ_TEX_MIP_FILTER SQ_TEX_XY_FILTER SQ_TEX_Z_FILTER SQ_TT_MODE SQ_TT_RT_FREQ SQ_TT_TOKEN_MASK_INST_EXCLUDE SQ_TT_TOKEN_MASK_REG_INCLUDE SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT SQ_TT_UTIL_TIMER SQ_TT_WAVESTART_MODE SQ_TT_WTYPE_INCLUDE SQ_TT_WTYPE_INCLUDE_SHIFT SQ_WATCH_MODES SQ_WAVE_IB_ECC_ST SQ_WAVE_SCHED_MODES SQ_WAVE_TYPE STATIC_SCREEN_SMU_INTR STREAM_0_SYNCHRONIZATION STREAM_10_SYNCHRONIZATION STREAM_11_SYNCHRONIZATION STREAM_12_SYNCHRONIZATION STREAM_13_SYNCHRONIZATION STREAM_14_SYNCHRONIZATION STREAM_15_SYNCHRONIZATION STREAM_1_SYNCHRONIZATION STREAM_2_SYNCHRONIZATION STREAM_3_SYNCHRONIZATION STREAM_4_SYNCHRONIZATION STREAM_5_SYNCHRONIZATION STREAM_6_SYNCHRONIZATION STREAM_7_SYNCHRONIZATION STREAM_8_SYNCHRONIZATION STREAM_9_SYNCHRONIZATION SURFACE_DCC SURFACE_DCC_IND_64B SURFACE_FLIP_AWAY_INT_TYPE SURFACE_FLIP_INT_TYPE SURFACE_FLIP_IN_STEREOSYNC SURFACE_FLIP_MODE_FOR_STEREOSYNC SURFACE_FLIP_STEREO_SELECT_DISABLE SURFACE_FLIP_STEREO_SELECT_POLARITY SURFACE_FLIP_TYPE SURFACE_FLIP_VUPDATE_SKIP_NUM SURFACE_INUSE_RAED_NO_LATCH SURFACE_PIXEL_FORMAT SURFACE_TMZ SURFACE_UPDATE_LOCK SU_PERFCNT_SEL SWATH_HEIGHT SWIZZLE_MODE_ENUM SWIZZLE_TYPE_ENUM SW_MODE SX_BLEND_OPT SX_DOWNCONVERT_FORMAT SX_OPT_COMB_FCN SX_PERFCOUNTER_VALS SYMCLK_FE_FORCE_EN SYMCLK_FE_FORCE_SRC SampleSplit SampleSplitBytes ScMap ScUncertaintyRegionMode ScXsel ScYsel SeEnable SeMap SePairMap SePairXsel SePairYsel SeXsel SeYsel ShaderEngineTileSize SourceFormat StencilFormat StencilOp SurfaceArray SurfaceEndian SurfaceFormat SurfaceNumber SurfaceSwap SurfaceTiling TA_PERFCOUNT_SEL TA_TC_ADDR_MODES TA_TC_REQ_MODES TCC_CACHE_POLICIES TCC_MTYPE TCP_CACHE_POLICIES TCP_CACHE_STORE_POLICIES TCP_DSM_DATA_SEL TCP_DSM_INJECT_SEL TCP_DSM_SINGLE_WRITE TCP_OPCODE_TYPE TCP_PERFCOUNT_SELECT TCP_WATCH_MODES TC_EA_CID TC_MICRO_TILE_MODE TC_NACKS TC_OP TC_OP_MASKS TD_PERFCOUNT_SEL TEST_CLK_DIV_SEL TEST_CLK_SEL TEST_CLOCK_MUX_SELECT_ENUM TEX_BC_SWIZZLE TEX_BORDER_COLOR_TYPE TEX_CHROMA_KEY TEX_CLAMP TEX_COORD_TYPE TEX_DEPTH_COMPARE_FUNCTION TEX_DIM TEX_FORMAT_COMP TEX_MAX_ANISO_RATIO TEX_MIP_FILTER TEX_REQUEST_SIZE TEX_SAMPLER_TYPE TEX_XY_FILTER TEX_Z_FILTER TILE_SPLIT TMDS_COLOR_FORMAT TMDS_CTL0_DATA_INVERT TMDS_CTL0_DATA_MODULATION TMDS_CTL0_DATA_SEL TMDS_CTL0_PATTERN_OUT_EN TMDS_CTL1_DATA_INVERT TMDS_CTL1_DATA_MODULATION TMDS_CTL1_DATA_SEL TMDS_CTL1_PATTERN_OUT_EN TMDS_CTL2_DATA_INVERT TMDS_CTL2_DATA_MODULATION TMDS_CTL2_DATA_SEL TMDS_CTL2_PATTERN_OUT_EN TMDS_CTL3_DATA_INVERT TMDS_CTL3_DATA_MODULATION TMDS_CTL3_DATA_SEL TMDS_CTL3_PATTERN_OUT_EN TMDS_DATA_SYNCHRONIZATION_DSINTSEL TMDS_MUX_SELECT TMDS_PIXEL_ENCODING TMDS_REG_TEST_OUTPUTA_CNTLA TMDS_REG_TEST_OUTPUTB_CNTLB TMDS_STEREOSYNC_CTL_SEL_REG TMDS_SYNC_PHASE TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB TMDS_TRANSMITTER_CONTROL_IDSCKSELA TMDS_TRANSMITTER_CONTROL_IDSCKSELB TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS TMDS_TRANSMITTER_ENABLE_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK TVX_DATA_FORMAT TVX_DST_SEL TVX_ENDIAN_SWAP TVX_INST TVX_NUM_FORMAT_ALL TVX_SRC_SEL TVX_SRF_MODE_ALL TVX_TYPE TileSplit TileType UTCL0FaultType UTCL0RequestType UTCL1FaultType UTCL1PerfSel UTCL1RequestType UVDFirmwareCommand VGT_CACHE_INVALID_MODE VGT_DETECT_ONE VGT_DETECT_ZERO VGT_DIST_MODE VGT_DI_INDEX_SIZE VGT_DI_MAJOR_MODE_SELECT VGT_DI_PRIM_TYPE VGT_DI_SOURCE_SELECT VGT_DMA_BUF_TYPE VGT_DMA_SWAP_MODE VGT_EVENT_TYPE VGT_GROUP_CONV_SEL VGT_GRP_PRIM_ORDER VGT_GRP_PRIM_TYPE VGT_GS_CUT_MODE VGT_GS_MODE_TYPE VGT_GS_OUTPRIM_TYPE VGT_INDEX_TYPE_MODE VGT_OUTPATH_SELECT VGT_OUT_PRIM_TYPE VGT_RDREQ_POLICY VGT_STAGES_ES_EN VGT_STAGES_GS_EN VGT_STAGES_HS_EN VGT_STAGES_LS_EN VGT_STAGES_VS_EN VGT_TESS_PARTITION VGT_TESS_TOPOLOGY VGT_TESS_TYPE VMEMCMD_RETURN_ORDER VMPG_SIZE VSYNC_CNT_LATCH_MASK VSYNC_CNT_REFCLK_SEL VSYNC_CNT_RESET_SEL VTX_CLAMP VTX_FETCH_TYPE VTX_FORMAT_COMP_ALL VTX_MEM_REQUEST_SIZE WBSCL_BACKPRESSURE_CNT_EN_ENUM WBSCL_COEF_FILTER_TYPE_SEL WBSCL_COEF_RAM_FILTER_TYPE_ENUM WBSCL_COEF_RAM_PHASE_ENUM WBSCL_COEF_RAM_RD_SEL_ENUM WBSCL_COEF_RAM_SEL_ENUM WBSCL_COEF_RAM_TAP_COEF_EN_ENUM WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM WBSCL_HOST_CONFLICT_INT_TYPE_ENUM WBSCL_LB_MEM_PWR_FORCE_ENUM WBSCL_LB_MEM_PWR_MODE_SEL_ENUM WBSCL_LUT_MEM_PWR_STATE_ENUM WBSCL_MEM_PWR_STATE_ENUM WBSCL_MODE_SEL WBSCL_NUM_OF_TAPS_ENUM WBSCL_OUTSIDE_PIX_STRATEGY_ENUM WBSCL_PIXEL_DEPTH WBSCL_STATUS_ACK_ENUM WBSCL_STATUS_MASK_ENUM WBSCL_TEST_CRC_CONT_EN_ENUM WBSCL_TEST_CRC_EN_ENUM WBSCL_TEST_CRC_MASK_ENUM WB_CLK_GATE_DIS_ENUM WB_ENABLE_ENUM WB_MEM_PWR_DIS_ENUM WB_RAM_PW_SAVE_MODE_ENUM WB_SOFT_RESET_ENUM WB_TEST_CLK_SEL_ENUM WD_IA_DRAW_REG_XFER WD_IA_DRAW_SOURCE WD_IA_DRAW_TYPE WritePolicy XNORM XTAL_REF_CLOCK_SOURCE_SEL XTAL_REF_SEL ZFormat ZLimitSumm ZModeForce ZOrder ZSamplePosition ZpassControl
navi10_ip_offset.h IP_BASE IP_BASE_INSTANCE
pptable.h ATOM_PPLIB_VQ_Budgeting_Record ATOM_PPLIB_VQ_Budgeting_Table _ATOM_PPLIB_ACPClk_Voltage_Limit_Record _ATOM_PPLIB_ACPClk_Voltage_Limit_Table _ATOM_PPLIB_ACP_Table _ATOM_PPLIB_CAC_Leakage_Record _ATOM_PPLIB_CAC_Leakage_Table _ATOM_PPLIB_CI_CLOCK_INFO _ATOM_PPLIB_CZ_CLOCK_INFO _ATOM_PPLIB_Clock_Voltage_Dependency_Record _ATOM_PPLIB_Clock_Voltage_Dependency_Table _ATOM_PPLIB_Clock_Voltage_Limit_Record _ATOM_PPLIB_Clock_Voltage_Limit_Table _ATOM_PPLIB_EVERGREEN_CLOCK_INFO _ATOM_PPLIB_EXTENDEDHEADER _ATOM_PPLIB_FANTABLE _ATOM_PPLIB_FANTABLE2 _ATOM_PPLIB_FANTABLE3 _ATOM_PPLIB_FANTABLE4 _ATOM_PPLIB_FANTABLE5 _ATOM_PPLIB_KV_CLOCK_INFO _ATOM_PPLIB_NONCLOCK_INFO _ATOM_PPLIB_POWERPLAYTABLE _ATOM_PPLIB_POWERPLAYTABLE2 _ATOM_PPLIB_POWERPLAYTABLE3 _ATOM_PPLIB_POWERPLAYTABLE4 _ATOM_PPLIB_POWERPLAYTABLE5 _ATOM_PPLIB_POWERTUNE_Table _ATOM_PPLIB_POWERTUNE_Table_V1 _ATOM_PPLIB_PPM_Table _ATOM_PPLIB_PhaseSheddingLimits_Record _ATOM_PPLIB_PhaseSheddingLimits_Table _ATOM_PPLIB_R600_CLOCK_INFO _ATOM_PPLIB_RS780_CLOCK_INFO _ATOM_PPLIB_SAMClk_Voltage_Limit_Record _ATOM_PPLIB_SAMClk_Voltage_Limit_Table _ATOM_PPLIB_SAMU_Table _ATOM_PPLIB_SI_CLOCK_INFO _ATOM_PPLIB_STATE _ATOM_PPLIB_STATE_V2 _ATOM_PPLIB_SUMO_CLOCK_INFO _ATOM_PPLIB_THERMALCONTROLLER _ATOM_PPLIB_THERMAL_STATE _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table _ATOM_PPLIB_UVD_Table _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table _ATOM_PPLIB_VCE_State_Record _ATOM_PPLIB_VCE_State_Table _ATOM_PPLIB_VCE_Table _ATOM_PowerTune_Table _ClockInfoArray _NonClockInfoArray _StateArray _UVDClockInfo _UVDClockInfoArray _VCEClockInfo _VCEClockInfoArray
renoir_ip_offset.h IP_BASE IP_BASE_INSTANCE
sienna_cichlid_ip_offset.h IP_BASE IP_BASE_INSTANCE
soc15_hw_ip.h
soc15_ih_clientid.h soc15_ih_clientid soc21_ih_clientid
soc21_enum.h AFMT_ACP_TYPE AFMT_AUDIO_CRC_CONTROL_CH_SEL AFMT_AUDIO_CRC_CONTROL_CONT AFMT_AUDIO_CRC_CONTROL_SOURCE AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS AFMT_AUDIO_SRC_CONTROL_SELECT AFMT_HDMI_AUDIO_SEND_MAX_PACKETS AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE AFMT_INTERRUPT_STATUS_CHG_MASK AFMT_MEM_PWR_DIS_CTRL AFMT_MEM_PWR_FORCE_CTRL AFMT_RAMP_CONTROL0_SIGN AFMT_VBI_PACKET_CONTROL_ACP_SOURCE ALLOW_SR_ON_TRANS_REQ AMCLOCK_ENABLE APG_AUDIO_CRC_CONTROL_CH_SEL APG_AUDIO_CRC_CONTROL_CONT APG_DBG_ACP_TYPE APG_DBG_AUDIO_DTO_BASE APG_DBG_AUDIO_DTO_DIV APG_DBG_AUDIO_DTO_MULTI APG_DBG_MUX_SEL APG_DP_ASP_CHANNEL_COUNT_OVERRIDE APG_MEM_POWER_STATE APG_MEM_PWR_DIS_CTRL APG_MEM_PWR_FORCE_CTRL APG_PACKET_CONTROL_ACP_SOURCE APG_PACKET_CONTROL_AUDIO_INFO_SOURCE APG_RAMP_CONTROL_SIGN AUDIO_LAYOUT_SELECT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE AZALIA_SOFT_RESET_REFCLK_SOFT_RESET AZ_CORB_SIZE AZ_GLOBAL_CAPABILITIES AZ_LATENCY_COUNTER_CONTROL AZ_RIRB_SIZE AZ_RIRB_WRITE_POINTER_RESET AZ_STATE_CHANGE_STATUS BIGK_FRAGMENT_SIZE BORROWBUFFER_MEM_POWER_STATE_ENUM BinEventCntl BinMapMode BinSizeExtend BinningMode BlendOp BlendOpt CBMode CBPerfClearFilterSel CBPerfOpFilterSel CBPerfSel CBRamList CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY CHA_PERF_SEL CHCG_PERF_SEL CHC_PERF_SEL CHUNK_SIZE CLEAR_SMU_INTR CLKGATE_BASE_MODE CLKGATE_SM_MODE CLOCK_BRANCH_SOFT_RESET CLOCK_GATING_DISABLE_ENUM CLOCK_GATING_EN CMC_3DLUT_30BIT_ENUM CMC_3DLUT_RAM_SEL CMC_3DLUT_SIZE_ENUM CMC_LUT_2_CONFIG_ENUM CMC_LUT_2_MODE_ENUM CMC_LUT_NUM_SEG CMC_LUT_RAM_SEL CM_BYPASS CM_COEF_FORMAT_ENUM CM_DATA_SIGNED CM_EN CM_GAMMA_LUT_MODE_ENUM CM_GAMMA_LUT_PWL_DISABLE_ENUM CM_GAMMA_LUT_SEL_ENUM CM_GAMUT_REMAP_MODE_ENUM CM_LUT_2_CONFIG_ENUM CM_LUT_2_MODE_ENUM CM_LUT_4_CONFIG_ENUM CM_LUT_4_MODE_ENUM CM_LUT_CONFIG_MODE CM_LUT_NUM_SEG CM_LUT_RAM_SEL CM_LUT_READ_COLOR_SEL CM_LUT_READ_DBG CM_PENDING CM_POST_CSC_MODE_ENUM CM_WRITE_BASE_ONLY CNVC_BYPASS CNVC_COEF_FORMAT_ENUM CNVC_ENABLE CNVC_PENDING COEF_RAM_SELECT_RD COLOR_KEYER_MODE COMPAT_LEVEL CORB_READ_POINTER_RESET CPC_LATENCY_STATS_SEL CPC_PERFCOUNT_SEL CPF_LATENCY_STATS_SEL CPF_PERFCOUNTWINDOW_SEL CPF_PERFCOUNT_SEL CPF_SCRATCH_REG_ATOMIC_OP CPG_LATENCY_STATS_SEL CPG_PERFCOUNTWINDOW_SEL CPG_PERFCOUNT_SEL CP_ALPHA_TAG_RAM_SEL CP_DDID_CNTL_MODE CP_DDID_CNTL_SIZE CP_DDID_CNTL_VMID_SEL CP_ME_ID CP_PERFMON_ENABLE_MODE CP_PERFMON_STATE CP_PIPE_ID CP_RING_ID CRC_CUR_SEL CRC_INTERLACE_SEL CRC_IN_CUR_SEL CRC_IN_PIX_SEL CRC_SRC_SEL CRC_STEREO_SEL CROB_MEM_PWR_LIGHT_SLEEP_MODE CROSSBAR_FOR_ALPHA CROSSBAR_FOR_CB_B CROSSBAR_FOR_CR_R CROSSBAR_FOR_Y_G CSCNTL_TYPE CSDATA_TYPE CURSOR_2X_MAGNIFY CURSOR_ENABLE CURSOR_LINES_PER_CHUNK CURSOR_MODE CURSOR_PERFMON_LATENCY_MEASURE_EN CURSOR_PERFMON_LATENCY_MEASURE_SEL CURSOR_PITCH CURSOR_REQ_MODE CURSOR_SNOOP CURSOR_STEREO_EN CURSOR_SURFACE_TMZ CURSOR_SYSTEM CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS CUR_ENABLE CUR_EXPAND_MODE CUR_INV_CLAMP CUR_MODE CUR_PENDING CUR_ROM_EN CmaskCode CombFunc CompareFrag ConservativeZExport CovToShaderSel DAC_MUX_SELECT DCCG_AUDIO_DTO0_SOURCE_SEL DCCG_AUDIO_DTO2_SOURCE_SEL DCCG_AUDIO_DTO_SEL DCCG_AUDIO_DTO_USE_512FBR_DTO DCCG_DBG_BLOCK_SEL DCCG_DBG_EN DCCG_DEEP_COLOR_CNTL DCCG_FIFO_ERRDET_OVR_EN DCCG_FIFO_ERRDET_RESET DCCG_FIFO_ERRDET_STATE DCCG_PERF_MODE_HSYNC DCCG_PERF_MODE_VSYNC DCCG_PERF_OTG_SELECT DCCG_PERF_RUN DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE DCHUBBUB_MEM_PWR_DIS_MODE DCHUBBUB_MEM_PWR_MODE DCIOCHIP_AUX_ALL_PWR_OK DCIOCHIP_AUX_CSEL0P9 DCIOCHIP_AUX_CSEL1P1 DCIOCHIP_AUX_FALLSLEWSEL DCIOCHIP_AUX_HYS_TUNE DCIOCHIP_AUX_RECEIVER_SEL DCIOCHIP_AUX_RSEL0P9 DCIOCHIP_AUX_RSEL1P1 DCIOCHIP_AUX_SPIKESEL DCIOCHIP_AUX_VOD_TUNE DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL DCIOCHIP_I2C_COMPSEL DCIOCHIP_I2C_FALLSLEWSEL DCIOCHIP_I2C_RECEIVER_SEL DCIOCHIP_I2C_VPH_1V2_EN DCIOCHIP_INVERT DCIOCHIP_MASK DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_DBG_ASYNC_4BIT_SEL DCIO_DBG_ASYNC_BLOCK_SEL DCIO_DCRXPHY_SOFT_RESET DCIO_DC_GENERICA_SEL DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL DCIO_DIO_EXT_VSYNC_MASK DCIO_DIO_OTG_EXT_VSYNC_MUX DCIO_DPCS_INTERRUPT_MASK DCIO_DPCS_INTERRUPT_TYPE DCIO_DSYNC_SOFT_RESET DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK DCIO_GSL_SEL DCIO_PHY_HPO_ENC_SRC_SEL DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK DC_DMCUB_INT_TYPE DC_DMCUB_TIMER_WINDOW DC_MEM_GLOBAL_PWR_REQ_DIS DC_SMU_INTERRUPT_ENABLE DENORM_TRUNCATE DETILE_BUFFER_PACKER_ENABLE DFQ_MIN_FREE_ENTRIES DFQ_NUM_ENTRIES DFQ_SIZE DFSMFlushEvents DIG_BE_CNTL_HPD_SELECT DIG_BE_CNTL_MODE DIG_DIGITAL_BYPASS_ENABLE DIG_DIGITAL_BYPASS_SEL DIG_FE_CNTL_SOURCE_SELECT DIG_FE_CNTL_STEREOSYNC_SELECT DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL DIG_FIFO_FORCE_RECAL_AVERAGE DIG_FIFO_OUTPUT_PROCESSING_MODE DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR DIG_FIFO_READ_CLOCK_SRC DIG_INPUT_PIXEL_SEL DIG_OUTPUT_CRC_CNTL_LINK_SEL DIG_OUTPUT_CRC_DATA_SEL DIG_RANDOM_PATTERN_SEED_RAN_PAT DIG_SL_PIXEL_GROUPING DIG_TEST_PATTERN_EXTERNAL_RESET_EN DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN DIG_TEST_PATTERN_RANDOM_PATTERN_RESET DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN DIOMEM_PWR_DIS_CTRL DIOMEM_PWR_FORCE_CTRL DIOMEM_PWR_FORCE_CTRL2 DIOMEM_PWR_SEL_CTRL DIOMEM_PWR_SEL_CTRL2 DIO_DBG_BLOCK_SEL DIO_FIFO_ERROR DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE DISABLE_CLOCK_GATING DISABLE_CLOCK_GATING_IN_DCO DISPCLK_CHG_FWD_CORR_DISABLE DISPCLK_FREQ_RAMP_DONE DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE DMDATA_DONE DMDATA_MODE DMDATA_QOS_MODE DMDATA_REPEAT DMDATA_UNDERFLOW DMDATA_UNDERFLOW_CLEAR DMDATA_UPDATED DMDATA_VM_DONE DME_MEM_POWER_STATE_ENUM DME_MEM_PWR_DIS_CTRL DME_MEM_PWR_FORCE_CTRL DMU_CLOCK_ON DMU_DC_GPU_TIMER_READ_SELECT DMU_DC_GPU_TIMER_START_POSITION DOLBY_VISION_ENABLE DOUT_I2C_ACK DOUT_I2C_ARBITRATION_ABORT_XFER DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO DOUT_I2C_ARBITRATION_SW_PRIORITY DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ DOUT_I2C_CONTROL_DBG_REF_SEL DOUT_I2C_CONTROL_DDC_SELECT DOUT_I2C_CONTROL_GO DOUT_I2C_CONTROL_SEND_RESET DOUT_I2C_CONTROL_SEND_RESET_LENGTH DOUT_I2C_CONTROL_SOFT_RESET DOUT_I2C_CONTROL_SW_STATUS_RESET DOUT_I2C_CONTROL_TRANSACTION_COUNT DOUT_I2C_DATA_INDEX_WRITE DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE DOUT_I2C_DDC_SPEED_THRESHOLD DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE DOUT_I2C_TRANSACTION_STOP_ON_NACK DPHY_8B10B_CUR_DISP DPHY_8B10B_RESET DPHY_ALT_SCRAMBLER_RESET_EN DPHY_ALT_SCRAMBLER_RESET_SEL DPHY_ATEST_SEL_LANE0 DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3 DPHY_BYPASS DPHY_CRC_CONT_EN DPHY_CRC_EN DPHY_CRC_FIELD DPHY_CRC_MST_PHASE_ERROR_ACK DPHY_CRC_SEL DPHY_FEC_ENABLE DPHY_FEC_READY DPHY_LOAD_BS_COUNT_START DPHY_PRBS_EN DPHY_PRBS_SEL DPHY_RX_FAST_TRAINING_CAPABLE DPHY_SCRAMBLER_ADVANCE DPHY_SCRAMBLER_DIS DPHY_SCRAMBLER_KCODE DPHY_SCRAMBLER_SEL DPHY_SKEW_BYPASS DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM DPHY_SW_FAST_TRAINING_START DPHY_TRAINING_PATTERN_SEL DPREFCLK_SRC_SEL DPTE_GROUP_SIZE DP_AUX_ARB_CONTROL_ARB_PRIORITY DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ DP_AUX_ARB_STATUS DP_AUX_CONTROL_HPD_SEL DP_AUX_CONTROL_TEST_MODE DP_AUX_DEFINITE_ERR_REACHED_ACK DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW DP_AUX_DPHY_RX_CONTROL_START_WINDOW DP_AUX_DPHY_RX_DETECTION_THRESHOLD DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL DP_AUX_ERR_OCCURRED_ACK DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN DP_AUX_INT_ACK DP_AUX_LS_UPDATE_ACK DP_AUX_PHY_WAKE_PRIORITY DP_AUX_POTENTIAL_ERR_REACHED_ACK DP_AUX_RESET DP_AUX_RESET_DONE DP_AUX_RX_TIMEOUT_LEN_MUL DP_AUX_SW_CONTROL_LS_READ_TRIG DP_AUX_SW_CONTROL_SW_GO DP_AUX_TX_PRECHARGE_LEN_MUL DP_COMPONENT_DEPTH DP_CP_ENCRYPTION_TYPE DP_DPHY_8B10B_EXT_DISP DP_DPHY_FAST_TRAINING_COMPLETE_ACK DP_DPHY_FAST_TRAINING_COMPLETE_MASK DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN DP_DPHY_HBR2_PATTERN_CONTROL_MODE DP_DSC_MODE DP_DTO_DS_DISABLE DP_EMBEDDED_PANEL_MODE DP_LINK_TRAINING_COMPLETE DP_LINK_TRAINING_SWITCH_MODE DP_ML_PHY_SEQ_MODE DP_MSA_V_TIMING_OVERRIDE_EN DP_MSE_BLANK_CODE DP_MSE_LINK_LINE DP_MSE_SAT_ENCRYPT0 DP_MSE_SAT_ENCRYPT1 DP_MSE_SAT_ENCRYPT2 DP_MSE_SAT_ENCRYPT3 DP_MSE_SAT_ENCRYPT4 DP_MSE_SAT_ENCRYPT5 DP_MSE_SAT_UPDATE_ACT DP_MSE_TIMESTAMP_MODE DP_MSE_ZERO_ENCODER DP_MSO_NUM_OF_SST_LINKS DP_PIXEL_ENCODING DP_PIXEL_PER_CYCLE_PROCESSING_NUM DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE DP_SEC_ASP_PRIORITY DP_SEC_AUDIO_MUTE DP_SEC_COLLISION_ACK DP_SEC_GSP0_PRIORITY DP_SEC_GSP_SEND DP_SEC_GSP_SEND_ANY_LINE DP_SEC_GSP_SEND_PPS DP_SEC_LINE_REFERENCE DP_SEC_TIMESTAMP_MODE DP_STEER_OVERFLOW_ACK DP_STEER_OVERFLOW_MASK DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT DP_STREAM_ENC_READ_CLOCK_CONTROL DP_STREAM_ENC_RESET_CONTROL DP_STREAM_ENC_STREAM_ACTIVE DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET DP_SYNC_POLARITY DP_TU_OVERFLOW_ACK DP_UDI_LANES DP_VID_ENHANCED_FRAME_MODE DP_VID_M_N_DOUBLE_BUFFER_MODE DP_VID_M_N_GEN_EN DP_VID_N_MUL DP_VID_STREAM_DISABLE_ACK DP_VID_STREAM_DISABLE_MASK DP_VID_STREAM_DIS_DEFER DP_VID_VBID_FIELD_POL DSCCIF_BITS_PER_COMPONENT_ENUM DSCCIF_ENABLE_ENUM DSCCIF_INPUT_PIXEL_FORMAT_ENUM DSCC_BITS_PER_COMPONENT_ENUM DSCC_DSC_VERSION_MAJOR_ENUM DSCC_DSC_VERSION_MINOR_ENUM DSCC_ENABLE_ENUM DSCC_ICH_RESET_ENUM DSCC_LINEBUF_DEPTH_ENUM DSCC_MEM_PWR_DIS_ENUM DSCC_MEM_PWR_FORCE_ENUM DSCL_MODE_SEL DSM_DATA_SEL DSM_ENABLE_ERROR_INJECT DSM_SELECT_INJECT_DELAY DSM_SINGLE_WRITE DS_HW_CAL_ENABLE DS_JITTER_COUNT_SRC_SEL DS_REF_SRC DVOACLKC_IN_PHASE DVOACLKC_MVP_IN_PHASE DVOACLKC_MVP_SKEW_PHASE_OVERRIDE DVOACLKD_IN_PHASE DVOACLK_COARSE_SKEW_CNTL DVOACLK_FINE_SKEW_CNTL DVO_ENABLE_RST DWB_CRC_CONT_EN_ENUM DWB_CRC_SRC_SEL_ENUM DWB_DATA_OVERFLOW_INT_TYPE_ENUM DWB_DATA_OVERFLOW_TYPE_ENUM DWB_DEBUG_SEL_ENUM DWB_GAMUT_REMAP_COEF_FORMAT_ENUM DWB_GAMUT_REMAP_MODE_ENUM DWB_LUT_NUM_SEG DWB_MEM_PWR_FORCE_ENUM DWB_MEM_PWR_STATE_ENUM DWB_OGAM_LUT_CONFIG_MODE_ENUM DWB_OGAM_LUT_HOST_SEL_ENUM DWB_OGAM_LUT_READ_COLOR_SEL_ENUM DWB_OGAM_LUT_READ_DBG_ENUM DWB_OGAM_MODE_ENUM DWB_OGAM_PWL_DISABLE_ENUM DWB_OGAM_SELECT_ENUM DWB_TEST_CLK_SEL_ENUM DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE DbMemArbWatermarks DbPRTFaultBehavior DbPSLControl EFC_SURFACE_PIXEL_FORMAT ENABLE ENABLE_CLOCK ENABLE_ENUM ENUM_DIO_DCN_ACTIVE_STATUS ENUM_DPG_BIT_DEPTH ENUM_DPG_DYNAMIC_RANGE ENUM_DPG_EN ENUM_DPG_FIELD_POLARITY ENUM_DPG_MODE ENUM_DP_DPHY_SYM32_CRC_END_EVENT ENUM_DP_DPHY_SYM32_CRC_START_EVENT ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS ENUM_DP_DPHY_SYM32_ENABLE ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE ENUM_DP_DPHY_SYM32_MODE ENUM_DP_DPHY_SYM32_NUM_LANES ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING ENUM_DP_DPHY_SYM32_RESET ENUM_DP_DPHY_SYM32_RESET_STATUS ENUM_DP_DPHY_SYM32_SAT_UPDATE ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING ENUM_DP_DPHY_SYM32_STATUS ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE ENUM_DP_DPHY_SYM32_TP_PRBS_SEL ENUM_DP_DPHY_SYM32_TP_SELECT ENUM_DP_SYM32_ENC_AUDIO_MUTE ENUM_DP_SYM32_ENC_CONTINUOUS_MODE ENUM_DP_SYM32_ENC_CRC_VALID ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH ENUM_DP_SYM32_ENC_ENABLE ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM ENUM_DP_SYM32_ENC_OVERFLOW_STATUS ENUM_DP_SYM32_ENC_PENDING ENUM_DP_SYM32_ENC_PIXEL_ENCODING ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE ENUM_DP_SYM32_ENC_POWER_STATE_ENUM ENUM_DP_SYM32_ENC_RESET ENUM_DP_SYM32_ENC_SDP_PRIORITY ENUM_DP_SYM32_ENC_SOF_REFERENCE ENUM_DP_SYM32_ENC_VID_STREAM_DEFER ENUM_DSCRM_EN ENUM_NUM_SIMD_PER_CU EXPANSION_MODE FC_EYE_SELECTION_ENUM FC_FRAME_CAPTURE_RATE_ENUM FC_STEREO_EYE_POLARITY_ENUM FEC_ACTIVE_STATUS FLIP_RATE FMTMEM_PWR_DIS_CTRL FMTMEM_PWR_FORCE_CTRL FMT_BIT_DEPTH_CONTROL_25FRC_SEL FMT_BIT_DEPTH_CONTROL_50FRC_SEL FMT_BIT_DEPTH_CONTROL_75FRC_SEL FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE FMT_CLAMP_CNTL_COLOR_FORMAT FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS FMT_CONTROL_PIXEL_ENCODING FMT_CONTROL_SUBSAMPLING_MODE FMT_CONTROL_SUBSAMPLING_ORDER FMT_DEBUG_CNTL_COLOR_SELECT FMT_DYNAMIC_EXP_MODE FMT_FRAME_RANDOM_ENABLE_CONTROL FMT_POWER_STATE_ENUM FMT_RGB_RANDOM_ENABLE_CONTROL FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL FMT_SPATIAL_DITHER_MODE FMT_STEREOSYNC_OVERRIDE_CONTROL FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 FORCE_DISABLE_CLOCK FORCE_ONE_ROW_FOR_FRAME FORMAT_CROSSBAR ForceControl GATCL1RequestType GB_EDC_DED_MODE GCRPerfSel GDS_PERFCOUNT_SELECT GE1_PERFCOUNT_SELECT GE2_DIST_PERFCOUNT_SELECT GE2_SE_PERFCOUNT_SELECT GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED GENERIC_AZ_CONTROLLER_REGISTER_STATUS GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED GENERIC_STEREOSYNC_SEL GL0V_CACHE_POLICIES GL1A_PERF_SEL GL1C_PERF_SEL GL1H_REQ_PERF_SEL GL1_CACHE_POLICIES GL1_CACHE_STORE_POLICIES GL2A_PERF_SEL GL2C_PERF_SEL GL2_CACHE_POLICIES GL2_EA_CID GL2_NACKS GL2_OP GL2_OP_MASKS GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE GLOBAL_CONTROL_CONTROLLER_RESET GLOBAL_CONTROL_FLUSH_CONTROL GLOBAL_STATUS_FLUSH_STATUS GRBM_PERF_SEL GRBM_SE0_PERF_SEL GRBM_SE1_PERF_SEL GRBM_SE2_PERF_SEL GRBM_SE3_PERF_SEL GRBM_SE4_PERF_SEL GRBM_SE5_PERF_SEL GRBM_SE6_PERF_SEL GRBM_SE7_PERF_SEL HDMICHARCLK_SRC_SEL HDMISTREAMCLK_DTO_FORCE_DIS HDMISTREAMCLK_SRC_SEL HDMI_ACP_SEND HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CONT HDMI_ACR_N_MULTIPLE HDMI_ACR_SELECT HDMI_ACR_SEND HDMI_ACR_SOURCE HDMI_AUDIO_DELAY_EN HDMI_AUDIO_INFO_CONT HDMI_AUDIO_INFO_SEND HDMI_BORROW_MODE HDMI_CLOCK_CHANNEL_RATE HDMI_DATA_SCRAMBLE_EN HDMI_DEEP_COLOR_DEPTH HDMI_DEFAULT_PAHSE HDMI_ERROR_ACK HDMI_ERROR_MASK HDMI_GC_AVMUTE HDMI_GC_AVMUTE_CONT HDMI_GC_CONT HDMI_GC_SEND HDMI_GENERIC_CONT HDMI_GENERIC_SEND HDMI_ISRC_CONT HDMI_ISRC_SEND HDMI_KEEPOUT_MODE HDMI_METADATA_ENABLE HDMI_MPEG_INFO_CONT HDMI_MPEG_INFO_SEND HDMI_NO_EXTRA_NULL_PACKET_FILLED HDMI_NULL_SEND HDMI_PACKET_GEN_VERSION HDMI_PACKET_LINE_REFERENCE HDMI_PACKING_PHASE_OVERRIDE HDMI_STREAM_ENC_DB_DISABLE_CONTROL HDMI_STREAM_ENC_DSC_MODE HDMI_STREAM_ENC_ENABLE_CONTROL HDMI_STREAM_ENC_ODM_COMBINE_MODE HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT HDMI_STREAM_ENC_PIXEL_ENCODING HDMI_STREAM_ENC_READ_CLOCK_CONTROL HDMI_STREAM_ENC_RESET_CONTROL HDMI_STREAM_ENC_STREAM_ACTIVE HDMI_TB_ENC_ACP_SEND HDMI_TB_ENC_ACR_AUDIO_PRIORITY HDMI_TB_ENC_ACR_CONT HDMI_TB_ENC_ACR_N_MULTIPLE HDMI_TB_ENC_ACR_SELECT HDMI_TB_ENC_ACR_SEND HDMI_TB_ENC_ACR_SOURCE HDMI_TB_ENC_AUDIO_INFO_CONT HDMI_TB_ENC_AUDIO_INFO_SEND HDMI_TB_ENC_CRC_SRC_SEL HDMI_TB_ENC_CRC_TYPE HDMI_TB_ENC_DEEP_COLOR_DEPTH HDMI_TB_ENC_DEFAULT_PAHSE HDMI_TB_ENC_DSC_MODE HDMI_TB_ENC_ENABLE HDMI_TB_ENC_GC_AVMUTE HDMI_TB_ENC_GC_AVMUTE_CONT HDMI_TB_ENC_GC_CONT HDMI_TB_ENC_GC_SEND HDMI_TB_ENC_GENERIC_CONT HDMI_TB_ENC_GENERIC_LOCK_EN HDMI_TB_ENC_GENERIC_SEND HDMI_TB_ENC_ISRC_CONT HDMI_TB_ENC_ISRC_SEND HDMI_TB_ENC_METADATA_ENABLE HDMI_TB_ENC_PACKET_LINE_REFERENCE HDMI_TB_ENC_PIXEL_ENCODING HDMI_TB_ENC_RESET HDMI_TB_ENC_SYNC_PHASE HPD_INT_CONTROL_ACK HPD_INT_CONTROL_POLARITY HPD_INT_CONTROL_RX_INT_ACK HPO_TOP_CLOCK_GATING_DISABLE HPO_TOP_TEST_CLK_SEL HUBP_BLANK_EN HUBP_IN_BLANK HUBP_MEASURE_WIN_MODE_DCFCLK HUBP_NO_OUTSTANDING_REQ HUBP_SOFT_RESET HUBP_TTU_DISABLE HUBP_VREADY_AT_OR_AFTER_VSYNC HUBP_VTG_SEL H_MIRROR_EN Hdp_SurfaceEndian IHC_INTERRUPT_DEST IHC_INTERRUPT_LINE_STATUS IH_CLIENT_TYPE IH_INTERFACE_TYPE IH_PERF_SEL IH_RING_ID IH_VF_RB_SELECT IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID INPUT_FIFO_ERROR_TYPE INT_MASK INVALID_REG_ACCESS_TYPE JITTER_REMOVE_DISABLE LB_ALPHA_EN LB_INTERLEAVE_EN LB_MEMORY_CONFIG LEGACY_PIPE_INTERLEAVE LSDMA_PERF_SEL LVTMA_RANDOM_PATTERN_SEED_RAN_PAT MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_SEL MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE MEM_PWR_DIS_CTRL MEM_PWR_DIS_MODE MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2 MEM_PWR_FORCE_MODE MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2 MEM_PWR_STATUS METADATA_HUBP_SEL METADATA_STREAM_TYPE_SEL META_CHUNK_SIZE META_LINEAR MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL MIN_CHUNK_SIZE MIN_META_CHUNK_SIZE MPCC_BG_COLOR_BPC MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY MPCC_CONTROL_MPCC_ALPHA_BLND_MODE MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE MPCC_CONTROL_MPCC_BOT_GAIN_MODE MPCC_CONTROL_MPCC_MODE MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM MPCC_GAMUT_REMAP_MODE_ENUM MPCC_MCM_3DLUT_30BIT_ENUM MPCC_MCM_3DLUT_RAM_SEL MPCC_MCM_3DLUT_SIZE_ENUM MPCC_MCM_GAMMA_LUT_MODE_ENUM MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM MPCC_MCM_GAMMA_LUT_SEL_ENUM MPCC_MCM_LUT_2_MODE_ENUM MPCC_MCM_LUT_CONFIG_MODE MPCC_MCM_LUT_NUM_SEG MPCC_MCM_LUT_RAM_SEL MPCC_MCM_LUT_READ_COLOR_SEL MPCC_MCM_LUT_READ_DBG MPCC_MCM_MEM_PWR_FORCE_ENUM MPCC_MCM_MEM_PWR_STATE_ENUM MPCC_OGAM_LUT_2_CONFIG_ENUM MPCC_OGAM_LUT_CONFIG_MODE MPCC_OGAM_LUT_PWL_DISABLE_ENUM MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_LUT_READ_COLOR_SEL MPCC_OGAM_LUT_READ_DBG MPCC_OGAM_LUT_SEL_ENUM MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM MPCC_OGAM_NUM_SEG MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN MPCC_SM_CONTROL_MPCC_SM_EN MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT MPCC_SM_CONTROL_MPCC_SM_MODE MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET MPC_CFG_ADR_VUPDATE_LOCK_SET MPC_CFG_CFG_VUPDATE_LOCK_SET MPC_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_MPC_TEST_CLK_SEL MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN MPC_CRC_CALC_INTERLACE_MODE MPC_CRC_CALC_MODE MPC_CRC_CALC_STEREO_MODE MPC_CRC_SOURCE_SELECT MPC_DEBUG_BUS1_DATA_SELECT MPC_DEBUG_BUS2_DATA_SELECT MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT MPC_DEBUG_BUS_MPCC_BYTE_SELECT MPC_OCSC_COEF_FORMAT MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN MPC_OUT_CSC_MODE MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE MPC_OUT_RATE_CONTROL_DISABLE_SET MTYPE MemArbMode OBUF_BYPASS_SEL OBUF_IS_HALF_RECOUT_WIDTH_SEL OBUF_USE_FULL_BUFFER_SEL OPPBUF_DISPLAY_SEGMENTATION OPP_ABM_DEBUG_BUS_SELECT_CONTROL OPP_DPG_DEBUG_BUS_SELECT_CONTROL OPP_FMT_DEBUG_BUS_SELECT_CONTROL OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL OPP_PIPE_CLOCK_ENABLE_CONTROL OPP_PIPE_CRC_CONT_EN OPP_PIPE_CRC_EN OPP_PIPE_CRC_INTERLACE_EN OPP_PIPE_CRC_INTERLACE_MODE OPP_PIPE_CRC_ONE_SHOT_PENDING OPP_PIPE_CRC_PIXEL_SELECT OPP_PIPE_CRC_SOURCE_SELECT OPP_PIPE_CRC_STEREO_EN OPP_PIPE_CRC_STEREO_MODE OPP_PIPE_DIGTIAL_BYPASS_CONTROL OPP_TEST_CLK_SEL_CONTROL OPP_TOP_CLOCK_ENABLE_STATUS OPP_TOP_CLOCK_GATING_CONTROL OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE OTG_ADD_PIXEL OTG_CONTROL_OTG_DISABLE_POINT_CNTL OTG_CONTROL_OTG_FIELD_NUMBER_CNTL OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY OTG_CONTROL_OTG_MASTER_EN OTG_CONTROL_OTG_OUT_MUX OTG_CONTROL_OTG_START_POINT_CNTL OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN OTG_CRC_CNTL_OTG_CRC1_EN OTG_CRC_CNTL_OTG_CRC_CONT_EN OTG_CRC_CNTL_OTG_CRC_CONT_MODE OTG_CRC_CNTL_OTG_CRC_EN OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE OTG_CRC_CNTL_OTG_CRC_STEREO_MODE OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT OTG_DIG_UPDATE_VCOUNT_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY OTG_DROP_PIXEL OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL OTG_GLOBAL_UPDATE_LOCK_EN OTG_GSL_MASTER_MODE OTG_HORZ_REPETITION_COUNT OTG_H_SYNC_A_POL OTG_H_TIMING_DIV_MODE OTG_H_TIMING_DIV_MODE_MANUAL OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE OTG_MASTER_UPDATE_LOCK_DB_EN OTG_MASTER_UPDATE_LOCK_GSL_EN OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL OTG_STEREO_CONTROL_OTG_STEREO_EN OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT OTG_TRIGA_FALLING_EDGE_DETECT_CNTL OTG_TRIGA_FREQUENCY_SELECT OTG_TRIGA_RISING_EDGE_DETECT_CNTL OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT OTG_TRIGB_FALLING_EDGE_DETECT_CNTL OTG_TRIGB_FREQUENCY_SELECT OTG_TRIGB_RISING_EDGE_DETECT_CNTL OTG_UPDATE_LOCK_OTG_UPDATE_LOCK OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR OTG_VUPDATE_BLOCK_DISABLE OTG_V_SYNC_A_POL OTG_V_SYNC_MODE OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE OreoMode PERFCOUNTER_ACTIVE PERFCOUNTER_CNT0_STATE PERFCOUNTER_CNT1_STATE PERFCOUNTER_CNT2_STATE PERFCOUNTER_CNT3_STATE PERFCOUNTER_CNT4_STATE PERFCOUNTER_CNT5_STATE PERFCOUNTER_CNT6_STATE PERFCOUNTER_CNT7_STATE PERFCOUNTER_CNTL_SEL PERFCOUNTER_CNTOFF_START_DIS PERFCOUNTER_COUNTED_VALUE_TYPE PERFCOUNTER_CVALUE_SEL PERFCOUNTER_HW_CNTL_SEL PERFCOUNTER_HW_STOP1_SEL PERFCOUNTER_HW_STOP2_SEL PERFCOUNTER_INC_MODE PERFCOUNTER_INT_EN PERFCOUNTER_INT_TYPE PERFCOUNTER_OFF_MASK PERFCOUNTER_RESTART_EN PERFCOUNTER_RUNEN_MODE PERFCOUNTER_STATE_SEL0 PERFCOUNTER_STATE_SEL1 PERFCOUNTER_STATE_SEL2 PERFCOUNTER_STATE_SEL3 PERFCOUNTER_STATE_SEL4 PERFCOUNTER_STATE_SEL5 PERFCOUNTER_STATE_SEL6 PERFCOUNTER_STATE_SEL7 PERFMON_CNTOFF_AND_OR PERFMON_CNTOFF_INT_EN PERFMON_CNTOFF_INT_TYPE PERFMON_COUNTER_MODE PERFMON_SPM_MODE PERFMON_STATE PHYSYMCLK_FORCE_EN PHYSYMCLK_FORCE_SRC_SEL PH_PERFCNT_SEL PIPE_ALIGNED PIPE_COMPAT_LEVEL PIPE_INT_MASK_MODE PIPE_INT_TYPE_MODE PIPE_IN_FLUSH_URGENT PIPE_PHYPLL_PIXEL_RATE_SOURCE PIPE_PIXEL_RATE_PLL_SOURCE PIPE_PIXEL_RATE_SOURCE PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE PIX_EXPAND_MODE PLL_CFG_IF_SOFT_RESET PM_ASSERT_RESET POWER_STATE_ENUM PRE_CSC_MODE_ENUM PRE_DEGAM_MODE PRE_DEGAM_SELECT PRQ_MRQ_FLUSH_URGENT PTE_BUFFER_MODE PTE_ROW_HEIGHT_LINEAR PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT PWRSEQ_BL_PWM_CNTL_BL_PWM_EN PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN PWRSEQ_BL_PWM_GRP1_REG_LOCK PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START PWRSEQ_GPIO_MASK_EN PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN PerfCounter_Vals PhSPIstatusMode PixelPipeCounterId PixelPipeStride PkrMap PkrXsel PkrXsel2 PkrYsel RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK RDPCSPIPE_DBG_OCLA_SEL RDPCSPIPE_ENC_TYPE RDPCSPIPE_FIFO_EMPTY RDPCSPIPE_FIFO_FULL RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK RDPCSPIPE_PACK_MODE RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE RDPCSPIPE_PHY_IF_WIDTH RDPCSPIPE_PHY_RATE RDPCSPIPE_PHY_REF_ALT_CLK_EN RDPCSPIPE_TEST_CLK_SEL RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE RESPONSE_STATUS RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL RLC_DOORBELL_MODE RLC_PERFCOUNTER_SEL RLC_PERFMON_STATE RMIPerfSel RMI_CID ROTATION_ANGLE ROW_TTU_MODE RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK RSPM_CMD RbMap RbXsel RbXsel2 RbYsel ReadPolicy RingCounterControl SCL_2TAP_HARDCODE SCL_ALPHA_COEF SCL_AUTOCAL_MODE SCL_BOUNDARY SCL_CHROMA_COEF SCL_COEF_FILTER_TYPE_SEL SCL_COEF_RAM_SEL SCL_SHARP_EN SC_PERFCNT_SEL SDMA_PERFMON_SEL SDMA_PERF_SEL SEM_PERF_SEL SH_MEM_ADDRESS_MODE SH_MEM_ALIGNMENT_MODE SMU_INTR SOFT_RESET SPI_FOG_MODE SPI_LB_WAVES_SELECT SPI_PERFCNT_SEL SPI_PNT_SPRITE_OVERRIDE SPI_PS_LDS_GROUP_SIZE SPI_SAMPLE_CNTL SPI_SHADER_EX_FORMAT SPI_SHADER_FORMAT SPM_PERFMON_STATE SQG_PERF_SEL SQ_CAC_POWER_SEL SQ_EDC_INFO_SOURCE SQ_IBUF_ST SQ_IMG_FILTER_TYPE SQ_IND_CMD_CMD SQ_IND_CMD_MODE SQ_INST_STR_ST SQ_INST_TYPE SQ_LLC_CTL SQ_NO_INST_ISSUE SQ_OOB_SELECT SQ_PERF_SEL SQ_ROUND_MODE SQ_RSRC_BUF_TYPE SQ_RSRC_FLAT_TYPE SQ_RSRC_IMG_TYPE SQ_SEL_XYZW01 SQ_TEX_ANISO_RATIO SQ_TEX_BORDER_COLOR SQ_TEX_CLAMP SQ_TEX_DEPTH_COMPARE SQ_TEX_MIP_FILTER SQ_TEX_XY_FILTER SQ_TEX_Z_FILTER SQ_TT_MODE SQ_TT_RT_FREQ SQ_TT_TOKEN_MASK_INST_EXCLUDE SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT SQ_TT_TOKEN_MASK_REG_EXCLUDE SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT SQ_TT_TOKEN_MASK_REG_INCLUDE SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT SQ_TT_UTIL_TIMER SQ_TT_WAVESTART_MODE SQ_TT_WTYPE_INCLUDE SQ_TT_WTYPE_INCLUDE_SHIFT SQ_WATCH_MODES SQ_WAVE_FWD_PROG_INTERVAL SQ_WAVE_IB_ECC_ST SQ_WAVE_SCHED_MODES SQ_WAVE_TYPE STREAM_0_SYNCHRONIZATION STREAM_10_SYNCHRONIZATION STREAM_11_SYNCHRONIZATION STREAM_12_SYNCHRONIZATION STREAM_13_SYNCHRONIZATION STREAM_14_SYNCHRONIZATION STREAM_15_SYNCHRONIZATION STREAM_1_SYNCHRONIZATION STREAM_2_SYNCHRONIZATION STREAM_3_SYNCHRONIZATION STREAM_4_SYNCHRONIZATION STREAM_5_SYNCHRONIZATION STREAM_6_SYNCHRONIZATION STREAM_7_SYNCHRONIZATION STREAM_8_SYNCHRONIZATION STREAM_9_SYNCHRONIZATION SURFACE_DCC SURFACE_DCC_IND_128B SURFACE_DCC_IND_64B SURFACE_DCC_IND_BLK SURFACE_FLIP_AWAY_INT_TYPE SURFACE_FLIP_EXEC_DEBUG_MODE SURFACE_FLIP_INT_TYPE SURFACE_FLIP_IN_STEREOSYNC SURFACE_FLIP_MODE_FOR_STEREOSYNC SURFACE_FLIP_STEREO_SELECT_DISABLE SURFACE_FLIP_STEREO_SELECT_POLARITY SURFACE_FLIP_TYPE SURFACE_FLIP_VUPDATE_SKIP_NUM SURFACE_INUSE_RAED_NO_LATCH SURFACE_PIXEL_FORMAT SURFACE_TMZ SURFACE_UPDATE_LOCK SU_PERFCNT_SEL SWATH_HEIGHT SX_BLEND_OPT SX_DOWNCONVERT_FORMAT SX_OPT_COMB_FCN SX_PERFCOUNTER_VALS SYMCLK_FE_FORCE_EN SYMCLK_FE_FORCE_SRC ScMap ScUncertaintyRegionMode ScUncertaintyRegionMult ScXsel ScYsel SeMap SePairMap SePairXsel SePairYsel SeXsel SeYsel SourceFormat StencilOp TA_PERFCOUNT_SEL TA_TC_ADDR_MODES TA_TC_REQ_MODES TCC_CACHE_POLICIES TCC_MTYPE TCP_CACHE_POLICIES TCP_CACHE_STORE_POLICIES TCP_DSM_DATA_SEL TCP_DSM_INJECT_SEL TCP_DSM_SINGLE_WRITE TCP_OPCODE_TYPE TCP_PERFCOUNT_SELECT TCP_WATCH_MODES TC_EA_CID TC_NACKS TC_OP TC_OP_MASKS TD_PERFCOUNT_SEL TEST_CLK_DIV_SEL TEST_CLK_SEL TEST_CLOCK_MUX_SELECT_ENUM TEX_BC_SWIZZLE TEX_BORDER_COLOR_TYPE TEX_CHROMA_KEY TEX_CLAMP TEX_COORD_TYPE TEX_DEPTH_COMPARE_FUNCTION TEX_FORMAT_COMP TEX_MAX_ANISO_RATIO TEX_MIP_FILTER TEX_REQUEST_SIZE TEX_SAMPLER_TYPE TEX_XY_FILTER TEX_Z_FILTER TMDS_COLOR_FORMAT TMDS_CTL0_DATA_INVERT TMDS_CTL0_DATA_MODULATION TMDS_CTL0_DATA_SEL TMDS_CTL0_PATTERN_OUT_EN TMDS_CTL1_DATA_INVERT TMDS_CTL1_DATA_MODULATION TMDS_CTL1_DATA_SEL TMDS_CTL1_PATTERN_OUT_EN TMDS_CTL2_DATA_INVERT TMDS_CTL2_DATA_MODULATION TMDS_CTL2_DATA_SEL TMDS_CTL2_PATTERN_OUT_EN TMDS_CTL3_DATA_INVERT TMDS_CTL3_DATA_MODULATION TMDS_CTL3_DATA_SEL TMDS_CTL3_PATTERN_OUT_EN TMDS_DATA_SYNCHRONIZATION_DSINTSEL TMDS_MUX_SELECT TMDS_PIXEL_ENCODING TMDS_REG_TEST_OUTPUTA_CNTLA TMDS_REG_TEST_OUTPUTB_CNTLB TMDS_STEREOSYNC_CTL_SEL_REG TMDS_SYNC_PHASE TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB TMDS_TRANSMITTER_CONTROL_IDSCKSELA TMDS_TRANSMITTER_CONTROL_IDSCKSELB TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS TMDS_TRANSMITTER_ENABLE_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK TVX_TYPE USE_MALL_FOR_CURSOR USE_MALL_FOR_PSTATE_CHANGE USE_MALL_FOR_STATIC_SCREEN UTCL0FaultType UTCL0RequestType UTCL1FaultType UTCL1PerfSel UTCL1RequestType VGT_DETECT_ONE VGT_DETECT_ZERO VGT_DIST_MODE VGT_DI_INDEX_SIZE VGT_DI_MAJOR_MODE_SELECT VGT_DI_PRIM_TYPE VGT_DI_SOURCE_SELECT VGT_DMA_BUF_TYPE VGT_DMA_SWAP_MODE VGT_EVENT_TYPE VGT_GROUP_CONV_SEL VGT_GS_MODE_TYPE VGT_GS_OUTPRIM_TYPE VGT_INDEX_TYPE_MODE VGT_OUTPATH_SELECT VGT_OUT_PRIM_TYPE VGT_RDREQ_POLICY VGT_STAGES_ES_EN VGT_STAGES_GS_EN VGT_STAGES_HS_EN VGT_STAGES_LS_EN VGT_STAGES_VS_EN VGT_TESS_PARTITION VGT_TESS_TOPOLOGY VGT_TESS_TYPE VMEMCMD_RETURN_ORDER VMPG_SIZE VM_GROUP_SIZE VPG_MEM_PWR_DIS_CTRL VPG_MEM_PWR_FORCE_CTRL VRSCombinerModeSC VRSrate VSYNC_CNT_LATCH_MASK VSYNC_CNT_RESET_SEL WD_IA_DRAW_REG_XFER WD_IA_DRAW_SOURCE WD_IA_DRAW_TYPE WritePolicy XNORM XTAL_REF_CLOCK_SOURCE_SEL XTAL_REF_SEL ZLimitSumm ZModeForce ZOrder ZSamplePosition ZpassControl
soc24_enum.h AFMT_ACP_TYPE AFMT_AUDIO_CRC_CONTROL_CH_SEL AFMT_AUDIO_CRC_CONTROL_CONT AFMT_AUDIO_CRC_CONTROL_SOURCE AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS AFMT_AUDIO_SRC_CONTROL_SELECT AFMT_HDMI_AUDIO_SEND_MAX_PACKETS AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE AFMT_INTERRUPT_STATUS_CHG_MASK AFMT_MEM_PWR_DIS_CTRL AFMT_MEM_PWR_FORCE_CTRL AFMT_RAMP_CONTROL0_SIGN AFMT_VBI_PACKET_CONTROL_ACP_SOURCE ALLOW_SR_ON_TRANS_REQ AMCLOCK_ENABLE APG_AUDIO_CRC_CONTROL_CH_SEL APG_AUDIO_CRC_CONTROL_CONT APG_DBG_ACP_TYPE APG_DBG_AUDIO_DTO_BASE APG_DBG_AUDIO_DTO_DIV APG_DBG_AUDIO_DTO_MULTI APG_DBG_MUX_SEL APG_DP_ASP_CHANNEL_COUNT_OVERRIDE APG_MEM_POWER_STATE APG_MEM_PWR_DIS_CTRL APG_MEM_PWR_FORCE_CTRL APG_PACKET_CONTROL_ACP_SOURCE APG_PACKET_CONTROL_AUDIO_INFO_SOURCE APG_RAMP_CONTROL_SIGN AUDIO_LAYOUT_SELECT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE AZALIA_SOFT_RESET_REFCLK_SOFT_RESET AZ_CORB_SIZE AZ_GLOBAL_CAPABILITIES AZ_LATENCY_COUNTER_CONTROL AZ_RIRB_SIZE AZ_RIRB_WRITE_POINTER_RESET AZ_STATE_CHANGE_STATUS BIGK_FRAGMENT_SIZE BinEventCntl BinMapMode BinSizeExtend BinningMode BlendOp BlendOpt CBMode CBPerfClearFilterSel CBPerfOpFilterSel CBPerfSel CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY CHA_PERF_SEL CHC_PERF_SEL CHUNK_SIZE CLEAR_SMU_INTR CLKGATE_BASE_MODE CLKGATE_SM_MODE CLOCK_BRANCH_SOFT_RESET CLOCK_GATING_DISABLE_ENUM CLOCK_GATING_EN CMC_3DLUT_30BIT_ENUM CMC_3DLUT_RAM_SEL CMC_3DLUT_SIZE_ENUM CMC_LUT_2_CONFIG_ENUM CMC_LUT_2_MODE_ENUM CMC_LUT_NUM_SEG CMC_LUT_RAM_SEL CM_BYPASS CM_COEF_FORMAT_ENUM CM_DATA_SIGNED CM_EN CM_GAMMA_LUT_MODE_ENUM CM_GAMMA_LUT_PWL_DISABLE_ENUM CM_GAMMA_LUT_SEL_ENUM CM_LUT_2_CONFIG_ENUM CM_LUT_2_MODE_ENUM CM_LUT_4_CONFIG_ENUM CM_LUT_4_MODE_ENUM CM_LUT_CONFIG_MODE CM_LUT_NUM_SEG CM_LUT_RAM_SEL CM_LUT_READ_COLOR_SEL CM_LUT_READ_DBG CM_PENDING CM_POST_CSC_MODE_ENUM CM_WRITE_BASE_ONLY COEF_RAM_SELECT_RD COLOR_KEYER_ENABLE COLOR_KEYER_MODE CORB_READ_POINTER_RESET CPC_LATENCY_STATS_SEL CPC_PERFCOUNT_SEL CPF_LATENCY_STATS_SEL CPF_PERFCOUNTWINDOW_SEL CPF_PERFCOUNT_SEL CPF_SCRATCH_REG_ATOMIC_OP CPG_LATENCY_STATS_SEL CPG_PERFCOUNTWINDOW_SEL CPG_PERFCOUNT_SEL CP_ALPHA_TAG_RAM_SEL CP_DDID_CNTL_MODE CP_DDID_CNTL_SIZE CP_DDID_CNTL_VMID_SEL CP_ME_ID CP_PERFMON_ENABLE_MODE CP_PERFMON_STATE CP_PIPE_ID CP_RING_ID CRC_CUR_SEL CRC_INTERLACE_SEL CRC_IN_PIX_SEL CRC_SRC_SEL CRC_STEREO_SEL CROB_MEM_PWR_LIGHT_SLEEP_MODE CROSSBAR_FOR_ALPHA CROSSBAR_FOR_CB_B CROSSBAR_FOR_CR_R CROSSBAR_FOR_Y_G CSCNTL_TYPE CSDATA_TYPE CURSOR_2X_MAGNIFY CURSOR_ENABLE CURSOR_LINES_PER_CHUNK CURSOR_MODE CURSOR_PERFMON_LATENCY_MEASURE_EN CURSOR_PERFMON_LATENCY_MEASURE_SEL CURSOR_PITCH CURSOR_REQ_MODE CURSOR_SNOOP CURSOR_STEREO_EN CURSOR_SURFACE_TMZ CURSOR_SYSTEM CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS CUR_ENABLE CUR_EXPAND_MODE CUR_INV_CLAMP CUR_MATRIX_COEF_FORMAT_ENUM CUR_MODE CUR_PENDING CUR_ROM_EN CombFunc CompareFrag ConservativeZExport CovToShaderSel DAC_MUX_SELECT DCCG_AUDIO_DTO0_SOURCE_SEL DCCG_AUDIO_DTO2_SOURCE_SEL DCCG_AUDIO_DTO_SEL DCCG_AUDIO_DTO_USE_512FBR_DTO DCCG_DBG_BLOCK_SEL DCCG_DBG_EN DCCG_DEEP_COLOR_CNTL DCCG_FIFO_ERRDET_OVR_EN DCCG_FIFO_ERRDET_RESET DCCG_FIFO_ERRDET_STATE DCCG_PERF_MODE_HSYNC DCCG_PERF_MODE_VSYNC DCCG_PERF_OTG_SELECT DCCG_PERF_RUN DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE DCHUBBUB_MEM_PWR_DIS_MODE DCHUBBUB_MEM_PWR_MODE DCIOCHIP_AUX_ALL_PWR_OK DCIOCHIP_AUX_CSEL0P9 DCIOCHIP_AUX_CSEL1P1 DCIOCHIP_AUX_FALLSLEWSEL DCIOCHIP_AUX_HYS_TUNE DCIOCHIP_AUX_RECEIVER_SEL DCIOCHIP_AUX_RSEL0P9 DCIOCHIP_AUX_RSEL1P1 DCIOCHIP_AUX_SPIKESEL DCIOCHIP_AUX_VOD_TUNE DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL DCIOCHIP_I2C_COMPSEL DCIOCHIP_I2C_FALLSLEWSEL DCIOCHIP_I2C_RECEIVER_SEL DCIOCHIP_I2C_VPH_1V2_EN DCIOCHIP_INVERT DCIOCHIP_MASK DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_DBG_ASYNC_4BIT_SEL DCIO_DBG_ASYNC_BLOCK_SEL DCIO_DCRXPHY_SOFT_RESET DCIO_DC_GENERICA_SEL DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL DCIO_DIO_EXT_VSYNC_MASK DCIO_DIO_OTG_EXT_VSYNC_MUX DCIO_DPCS_INTERRUPT_MASK DCIO_DPCS_INTERRUPT_TYPE DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK DCIO_GSL_SEL DCIO_PHY_HPO_ENC_SRC_SEL DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK DCOH_TEST_CLOCK_MUX_SELECT_ENUM DCOH_TOP_CLOCK_GATING_DISABLE_ENUM DCOH_TOP_ENABLE_ENUM DC_DMCUB_INT_TYPE DC_DMCUB_TIMER_WINDOW DC_MEM_GLOBAL_PWR_REQ_DIS DC_SMU_INTERRUPT_ENABLE DENORM_TRUNCATE DETILE_BUFFER_PACKER_ENABLE DFQ_MIN_FREE_ENTRIES DFQ_NUM_ENTRIES DFQ_SIZE DIG_BE_CNTL_HPD_SELECT DIG_BE_CNTL_MODE DIG_DIGITAL_BYPASS_ENABLE DIG_DIGITAL_BYPASS_SEL DIG_FE_CNTL_SOURCE_SELECT DIG_FE_CNTL_STEREOSYNC_SELECT DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL DIG_FIFO_FORCE_RECAL_AVERAGE DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR DIG_FIFO_READ_CLOCK_SRC DIG_MODE DIG_OUTPUT_CRC_CNTL_LINK_SEL DIG_OUTPUT_CRC_DATA_SEL DIG_RANDOM_PATTERN_SEED_RAN_PAT DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET DIG_TEST_PATTERN_EXTERNAL_RESET_EN DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN DIG_TEST_PATTERN_RANDOM_PATTERN_RESET DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN DIOMEM_PWR_DIS_CTRL DIOMEM_PWR_FORCE_CTRL DIOMEM_PWR_FORCE_CTRL2 DIOMEM_PWR_SEL_CTRL DIOMEM_PWR_SEL_CTRL2 DIO_CLOCK_GATING_DISABLE DIO_DBG_BLOCK_SEL DIO_FIFO_ERROR DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE DISABLE_CLOCK_GATING DISABLE_CLOCK_GATING_IN_DCO DISPCLK_CHG_FWD_CORR_DISABLE DISPCLK_FREQ_RAMP_DONE DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE DMDATA_DONE DMDATA_MODE DMDATA_QOS_MODE DMDATA_REPEAT DMDATA_UNDERFLOW DMDATA_UNDERFLOW_CLEAR DMDATA_UPDATED DMDATA_VM_DONE DME_MEM_POWER_STATE_ENUM DME_MEM_PWR_DIS_CTRL DME_MEM_PWR_FORCE_CTRL DMU_CLOCK_ON DMU_DC_GPU_TIMER_READ_SELECT DMU_DC_GPU_TIMER_START_POSITION DOUT_I2C_ACK DOUT_I2C_ARBITRATION_ABORT_XFER DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO DOUT_I2C_ARBITRATION_SW_PRIORITY DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ DOUT_I2C_CONTROL_DBG_REF_SEL DOUT_I2C_CONTROL_DDC_SELECT DOUT_I2C_CONTROL_GO DOUT_I2C_CONTROL_SEND_RESET DOUT_I2C_CONTROL_SEND_RESET_LENGTH DOUT_I2C_CONTROL_SOFT_RESET DOUT_I2C_CONTROL_SW_STATUS_RESET DOUT_I2C_CONTROL_TRANSACTION_COUNT DOUT_I2C_DATA_INDEX_WRITE DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE DOUT_I2C_DDC_SPEED_THRESHOLD DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE DOUT_I2C_TRANSACTION_STOP_ON_NACK DPHY_8B10B_CUR_DISP DPHY_8B10B_RESET DPHY_ATEST_SEL_LANE0 DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3 DPHY_BYPASS DPHY_CRC_CONT_EN DPHY_CRC_EN DPHY_CRC_FIELD DPHY_CRC_MST_PHASE_ERROR_ACK DPHY_CRC_SEL DPHY_FEC_ENABLE DPHY_FEC_READY DPHY_LOAD_BS_COUNT_START DPHY_PRBS_EN DPHY_PRBS_SEL DPHY_RX_FAST_TRAINING_CAPABLE DPHY_SKEW_BYPASS DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM DPHY_SW_FAST_TRAINING_START DPHY_TRAINING_PATTERN_SEL DPREFCLK_SRC_SEL DPTE_GROUP_SIZE DP_AUX_ARB_CONTROL_ARB_PRIORITY DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ DP_AUX_ARB_STATUS DP_AUX_CONTROL_HPD_SEL DP_AUX_CONTROL_TEST_MODE DP_AUX_DEFINITE_ERR_REACHED_ACK DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW DP_AUX_DPHY_RX_CONTROL_START_WINDOW DP_AUX_DPHY_RX_DETECTION_THRESHOLD DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL DP_AUX_ERR_OCCURRED_ACK DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN DP_AUX_INT_ACK DP_AUX_LS_UPDATE_ACK DP_AUX_PHY_WAKE_PRIORITY DP_AUX_POTENTIAL_ERR_REACHED_ACK DP_AUX_RESET DP_AUX_RESET_DONE DP_AUX_RX_TIMEOUT_LEN_MUL DP_AUX_SW_CONTROL_LS_READ_TRIG DP_AUX_SW_CONTROL_SW_GO DP_AUX_TX_PRECHARGE_LEN_MUL DP_COMPONENT_DEPTH DP_COMPRESSED_PIXEL_FORMAT DP_DPHY_8B10B_EXT_DISP DP_DPHY_FAST_TRAINING_COMPLETE_ACK DP_DPHY_FAST_TRAINING_COMPLETE_MASK DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN DP_DPHY_HBR2_PATTERN_CONTROL_MODE DP_DTO_DS_DISABLE DP_LINK_TRAINING_COMPLETE DP_LINK_TRAINING_SWITCH_MODE DP_ML_PHY_SEQ_MODE DP_MSA_V_TIMING_OVERRIDE_EN DP_MSE_BLANK_CODE DP_MSE_LINK_LINE DP_MSE_TIMESTAMP_MODE DP_MSE_ZERO_ENCODER DP_MSO_NUM_OF_SST_LINKS DP_PIXEL_ENCODING DP_PIXEL_ENCODING_TYPE DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE DP_SEC_ASP_PRIORITY DP_SEC_AUDIO_MUTE DP_SEC_COLLISION_ACK DP_SEC_GSP0_PRIORITY DP_SEC_GSP_SEND DP_SEC_GSP_SEND_ANY_LINE DP_SEC_GSP_SEND_PPS DP_SEC_LINE_REFERENCE DP_SEC_TIMESTAMP_MODE DP_STEER_OUTPUT_PIXEL_PER_CYCLE DP_STEER_OVERFLOW_ACK DP_STEER_OVERFLOW_MASK DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT DP_STREAM_ENC_READ_CLOCK_CONTROL DP_STREAM_ENC_RESET_CONTROL DP_STREAM_ENC_STREAM_ACTIVE DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET DP_SYNC_POLARITY DP_TU_OVERFLOW_ACK DP_UDI_LANES DP_VID_ENHANCED_FRAME_MODE DP_VID_M_N_DOUBLE_BUFFER_MODE DP_VID_M_N_GEN_EN DP_VID_N_INTERVAL DP_VID_STREAM_DISABLE_ACK DP_VID_STREAM_DISABLE_MASK DP_VID_STREAM_DIS_DEFER DP_VID_VBID_FIELD_POL DSCCIF_BITS_PER_COMPONENT_ENUM DSCCIF_ENABLE_ENUM DSCCIF_INPUT_PIXEL_FORMAT_ENUM DSCC_BITS_PER_COMPONENT_ENUM DSCC_DSC_VERSION_MAJOR_ENUM DSCC_DSC_VERSION_MINOR_ENUM DSCC_ENABLE_ENUM DSCC_ICH_RESET_ENUM DSCC_LINEBUF_DEPTH_ENUM DSCC_MEM_PWR_DIS_ENUM DSCC_MEM_PWR_FORCE_ENUM DSCL_MODE_SEL DS_HW_CAL_ENABLE DS_REF_SRC DVO_ENABLE_RST DWB_CRC_CONT_EN_ENUM DWB_CRC_SRC_SEL_ENUM DWB_DATA_OVERFLOW_INT_TYPE_ENUM DWB_DATA_OVERFLOW_TYPE_ENUM DWB_DEBUG_SEL_ENUM DWB_GAMUT_REMAP_COEF_FORMAT_ENUM DWB_GAMUT_REMAP_MODE_ENUM DWB_LUT_NUM_SEG DWB_MEM_PWR_FORCE_ENUM DWB_MEM_PWR_STATE_ENUM DWB_OGAM_LUT_CONFIG_MODE_ENUM DWB_OGAM_LUT_HOST_SEL_ENUM DWB_OGAM_LUT_READ_COLOR_SEL_ENUM DWB_OGAM_LUT_READ_DBG_ENUM DWB_OGAM_MODE_ENUM DWB_OGAM_PWL_DISABLE_ENUM DWB_OGAM_SELECT_ENUM DWB_TEST_CLK_SEL_ENUM DbMemArbWatermarks DbPRTFaultBehavior DbPSLControl EFC_SURFACE_PIXEL_FORMAT ENABLE ENABLE_CLOCK ENABLE_ENUM ENUM_DIO_DCN_ACTIVE_STATUS ENUM_DPG_BIT_DEPTH ENUM_DPG_DYNAMIC_RANGE ENUM_DPG_EN ENUM_DPG_FIELD_POLARITY ENUM_DPG_MODE ENUM_DP_DPHY_SYM32_CRC_END_EVENT ENUM_DP_DPHY_SYM32_CRC_START_EVENT ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS ENUM_DP_DPHY_SYM32_ENABLE ENUM_DP_DPHY_SYM32_MODE ENUM_DP_DPHY_SYM32_NUM_LANES ENUM_DP_DPHY_SYM32_OUTPUT_MODE ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING ENUM_DP_DPHY_SYM32_RESET ENUM_DP_DPHY_SYM32_RESET_STATUS ENUM_DP_DPHY_SYM32_SAT_UPDATE ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS ENUM_DP_DPHY_SYM32_STATUS ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE ENUM_DP_DPHY_SYM32_TP_PRBS_SEL ENUM_DP_DPHY_SYM32_TP_SELECT ENUM_DP_SYM32_ENC_AUDIO_MUTE ENUM_DP_SYM32_ENC_CONTINUOUS_MODE ENUM_DP_SYM32_ENC_CRC_VALID ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH ENUM_DP_SYM32_ENC_ENABLE ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM ENUM_DP_SYM32_ENC_OVERFLOW_STATUS ENUM_DP_SYM32_ENC_PENDING ENUM_DP_SYM32_ENC_PIXEL_ENCODING ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE ENUM_DP_SYM32_ENC_POWER_STATE_ENUM ENUM_DP_SYM32_ENC_RESET ENUM_DP_SYM32_ENC_SDP_PRIORITY ENUM_DP_SYM32_ENC_SOF_REFERENCE ENUM_DP_SYM32_ENC_VID_STREAM_DEFER ENUM_NUM_SIMD_PER_CU EXPANSION_MODE FC_EYE_SELECTION_ENUM FC_FRAME_CAPTURE_RATE_ENUM FC_STEREO_EYE_POLARITY_ENUM FEC_ACTIVE_STATUS FLIP_RATE FMTMEM_PWR_DIS_CTRL FMTMEM_PWR_FORCE_CTRL FMT_BIT_DEPTH_CONTROL_25FRC_SEL FMT_BIT_DEPTH_CONTROL_50FRC_SEL FMT_BIT_DEPTH_CONTROL_75FRC_SEL FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE FMT_CLAMP_CNTL_COLOR_FORMAT FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS FMT_CONTROL_PIXEL_ENCODING FMT_CONTROL_SUBSAMPLING_MODE FMT_CONTROL_SUBSAMPLING_ORDER FMT_DEBUG_CNTL_COLOR_SELECT FMT_DYNAMIC_EXP_MODE FMT_FRAME_RANDOM_ENABLE_CONTROL FMT_POWER_STATE_ENUM FMT_RGB_RANDOM_ENABLE_CONTROL FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL FMT_SPATIAL_DITHER_MODE FMT_STEREOSYNC_OVERRIDE_CONTROL FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 FORCE_DISABLE_CLOCK FORCE_ONE_ROW_FOR_FRAME FORMAT_CROSSBAR ForceControl GATCL1RequestType GCRPerfSel GCUTCL2_PERF_SEL GCVML2_PERF_SEL GCVML2_SPM_PERF_SEL GC_EA_CPWD_PERFCOUNT_SEL GC_EA_SE_PERFCOUNT_SEL GE1_PERFCOUNT_SELECT GE2_DIST_PERFCOUNT_SELECT GE2_SE_PERFCOUNT_SELECT GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED GENERIC_AZ_CONTROLLER_REGISTER_STATUS GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED GENERIC_STEREOSYNC_SEL GL0V_CACHE_POLICIES GL1A_PERF_SEL GL1C_PERF_SEL GL1XA_PERF_SEL GL1XC_PERF_SEL GL1_CACHE_POLICIES GL1_CACHE_STORE_POLICIES GL2A_PERF_SEL GL2C_PERF_SEL GL2_CACHE_POLICIES GL2_NACKS GL2_OP GL2_OP_MASKS GLCompressionMode GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE GLOBAL_CONTROL_CONTROLLER_RESET GLOBAL_CONTROL_FLUSH_CONTROL GLOBAL_STATUS_FLUSH_STATUS GRBMH_PERF_SEL GRBM_PERF_SEL HDMICHARCLK_SRC_SEL HDMISTREAMCLK_SRC_SEL HDMI_ACP_SEND HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CONT HDMI_ACR_N_MULTIPLE HDMI_ACR_SELECT HDMI_ACR_SEND HDMI_ACR_SOURCE HDMI_AUDIO_DELAY_EN HDMI_AUDIO_INFO_CONT HDMI_AUDIO_INFO_SEND HDMI_CLOCK_CHANNEL_RATE HDMI_DATA_SCRAMBLE_EN HDMI_DEEP_COLOR_DEPTH HDMI_DEFAULT_PAHSE HDMI_ERROR_ACK HDMI_ERROR_MASK HDMI_GC_AVMUTE HDMI_GC_AVMUTE_CONT HDMI_GC_CONT HDMI_GC_SEND HDMI_GENERIC_CONT HDMI_GENERIC_SEND HDMI_ISRC_CONT HDMI_ISRC_SEND HDMI_KEEPOUT_MODE HDMI_METADATA_ENABLE HDMI_MPEG_INFO_CONT HDMI_MPEG_INFO_SEND HDMI_NO_EXTRA_NULL_PACKET_FILLED HDMI_NULL_SEND HDMI_PACKET_GEN_VERSION HDMI_PACKET_LINE_REFERENCE HDMI_PACKING_PHASE_OVERRIDE HPD_INT_CONTROL_ACK HPD_INT_CONTROL_POLARITY HPD_INT_CONTROL_RX_INT_ACK HPO_TOP_CLOCK_GATING_DISABLE HPO_TOP_TEST_CLK_SEL HUBP_3DLUT_ADDRESSING_MODE HUBP_BLANK_EN HUBP_IN_BLANK HUBP_MEASURE_WIN_MODE_DCFCLK HUBP_NO_OUTSTANDING_REQ HUBP_SOFT_RESET HUBP_TTU_DISABLE HUBP_VREADY_AT_OR_AFTER_VSYNC HUBP_VTG_SEL H_MIRROR_EN Hdp_SurfaceEndian IHC_INTERRUPT_DEST IHC_INTERRUPT_LINE_STATUS IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID INT_MASK INVALID_REG_ACCESS_TYPE ISHARP_FMT_MODE_ENUM ISHARP_LBA_MODE_ENUM ISHARP_NOISEDET_MODE_ENUM JITTER_REMOVE_DISABLE LB_ALPHA_EN LB_INTERLEAVE_EN LB_MEMORY_CONFIG LEGACY_PIPE_INTERLEAVE LSDMA_PERF_SEL LUMA_KEYER_ENABLE LVTMA_RANDOM_PATTERN_SEED_RAN_PAT MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_SEL MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE MATRIX_MODE_ENUM MEM_PWR_DIS_CTRL MEM_PWR_DIS_MODE MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2 MEM_PWR_FORCE_MODE MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2 MEM_PWR_STATUS METADATA_HUBP_SEL METADATA_STREAM_TYPE_SEL META_CHUNK_SIZE META_LINEAR MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL MIN_CHUNK_SIZE MIN_META_CHUNK_SIZE MPCC_BG_COLOR_BPC MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY MPCC_CONTROL_MPCC_ALPHA_BLND_MODE MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE MPCC_CONTROL_MPCC_BOT_GAIN_MODE MPCC_CONTROL_MPCC_MODE MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM MPCC_GAMUT_REMAP_MODE_ENUM MPCC_MCM_3DLUT_30BIT_ENUM MPCC_MCM_3DLUT_RAM_SEL MPCC_MCM_3DLUT_SIZE_ENUM MPCC_MCM_GAMMA_LUT_MODE_ENUM MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM MPCC_MCM_GAMMA_LUT_SEL_ENUM MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM MPCC_MCM_GAMUT_REMAP_MODE_ENUM MPCC_MCM_LUT_2_MODE_ENUM MPCC_MCM_LUT_CONFIG_MODE MPCC_MCM_LUT_NUM_SEG MPCC_MCM_LUT_RAM_SEL MPCC_MCM_LUT_READ_COLOR_SEL MPCC_MCM_LUT_READ_DBG MPCC_MCM_MEM_PWR_FORCE_ENUM MPCC_MCM_MEM_PWR_STATE_ENUM MPCC_OGAM_LUT_2_CONFIG_ENUM MPCC_OGAM_LUT_CONFIG_MODE MPCC_OGAM_LUT_PWL_DISABLE_ENUM MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_LUT_READ_COLOR_SEL MPCC_OGAM_LUT_READ_DBG MPCC_OGAM_LUT_SEL_ENUM MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM MPCC_OGAM_NUM_SEG MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN MPCC_SM_CONTROL_MPCC_SM_EN MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT MPCC_SM_CONTROL_MPCC_SM_MODE MPC_CFG_3DLUT_FL_FORMAT MPC_CFG_3DLUT_FL_MODE MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET MPC_CFG_ADR_VUPDATE_LOCK_SET MPC_CFG_CFG_VUPDATE_LOCK_SET MPC_CFG_CUR_VUPDATE_LOCK_SET MPC_CFG_MPC_TEST_CLK_SEL MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN MPC_CRC_CALC_INTERLACE_MODE MPC_CRC_CALC_MODE MPC_CRC_CALC_STEREO_MODE MPC_CRC_SOURCE_SELECT MPC_OCSC_COEF_FORMAT MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN MPC_OUT_CSC_MODE MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE MPC_OUT_RATE_CONTROL_DISABLE_SET MTYPE MemArbMode OBUF_BYPASS_SEL OBUF_IS_HALF_RECOUT_WIDTH_SEL OBUF_USE_FULL_BUFFER_SEL OPPBUF_DISPLAY_SEGMENTATION OPP_PIPE_CLOCK_ENABLE_CONTROL OPP_PIPE_CRC_CONT_EN OPP_PIPE_CRC_EN OPP_PIPE_CRC_INTERLACE_EN OPP_PIPE_CRC_INTERLACE_MODE OPP_PIPE_CRC_ONE_SHOT_PENDING OPP_PIPE_CRC_PIXEL_SELECT OPP_PIPE_CRC_SOURCE_SELECT OPP_PIPE_CRC_STEREO_EN OPP_PIPE_CRC_STEREO_MODE OPP_PIPE_DIGTIAL_BYPASS_CONTROL OPP_TEST_CLK_SEL_CONTROL OPP_TOP_CLOCK_ENABLE_STATUS OPP_TOP_CLOCK_GATING_CONTROL OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE OTG_ADD_PIXEL OTG_CONTROL_OTG_DISABLE_POINT_CNTL OTG_CONTROL_OTG_FIELD_NUMBER_CNTL OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY OTG_CONTROL_OTG_MASTER_EN OTG_CONTROL_OTG_OUT_MUX OTG_CONTROL_OTG_START_POINT_CNTL OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN OTG_CRC_CNTL_OTG_CRC1_EN OTG_CRC_CNTL_OTG_CRC_CONT_EN OTG_CRC_CNTL_OTG_CRC_CONT_MODE OTG_CRC_CNTL_OTG_CRC_EN OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE OTG_CRC_CNTL_OTG_CRC_STEREO_MODE OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT OTG_DIG_UPDATE_VCOUNT_MODE OTG_DLPC_CONTROL_OTG_RESYNC_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY OTG_DROP_PIXEL OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL OTG_GLOBAL_UPDATE_LOCK_EN OTG_GSL_MASTER_MODE OTG_HORZ_REPETITION_COUNT OTG_H_SYNC_A_POL OTG_H_TIMING_DIV_MODE OTG_H_TIMING_DIV_MODE_MANUAL OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE OTG_MASTER_UPDATE_LOCK_DB_EN OTG_MASTER_UPDATE_LOCK_GSL_EN OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL OTG_STEREO_CONTROL_OTG_STEREO_EN OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT OTG_TRIGA_FALLING_EDGE_DETECT_CNTL OTG_TRIGA_FREQUENCY_SELECT OTG_TRIGA_RISING_EDGE_DETECT_CNTL OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT OTG_TRIGB_FALLING_EDGE_DETECT_CNTL OTG_TRIGB_FREQUENCY_SELECT OTG_TRIGB_RISING_EDGE_DETECT_CNTL OTG_UPDATE_LOCK_OTG_UPDATE_LOCK OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR OTG_VUPDATE_BLOCK_DISABLE OTG_V_SYNC_A_POL OTG_V_SYNC_MODE OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE OreoMode PC_PERFCNT_SEL PERFCOUNTER_ACTIVE PERFCOUNTER_CNT0_STATE PERFCOUNTER_CNT1_STATE PERFCOUNTER_CNT2_STATE PERFCOUNTER_CNT3_STATE PERFCOUNTER_CNT4_STATE PERFCOUNTER_CNT5_STATE PERFCOUNTER_CNT6_STATE PERFCOUNTER_CNT7_STATE PERFCOUNTER_CNTL_SEL PERFCOUNTER_CNTOFF_START_DIS PERFCOUNTER_COUNTED_VALUE_TYPE PERFCOUNTER_CVALUE_SEL PERFCOUNTER_HW_CNTL_SEL PERFCOUNTER_HW_STOP1_SEL PERFCOUNTER_HW_STOP2_SEL PERFCOUNTER_INC_MODE PERFCOUNTER_INT_EN PERFCOUNTER_INT_TYPE PERFCOUNTER_OFF_MASK PERFCOUNTER_RESTART_EN PERFCOUNTER_RUNEN_MODE PERFCOUNTER_STATE_SEL0 PERFCOUNTER_STATE_SEL1 PERFCOUNTER_STATE_SEL2 PERFCOUNTER_STATE_SEL3 PERFCOUNTER_STATE_SEL4 PERFCOUNTER_STATE_SEL5 PERFCOUNTER_STATE_SEL6 PERFCOUNTER_STATE_SEL7 PERFMON_CNTOFF_AND_OR PERFMON_CNTOFF_INT_EN PERFMON_CNTOFF_INT_TYPE PERFMON_COUNTER_MODE PERFMON_SPM_MODE PERFMON_STATE PHYSYMCLK_FORCE_EN PHYSYMCLK_FORCE_SRC_SEL PHY_MUX_ENABLE_ENUM PH_PERFCNT_SEL PIPE_ALIGNED PIPE_INT_MASK_MODE PIPE_INT_TYPE_MODE PIPE_IN_FLUSH_URGENT PIPE_PHYPLL_PIXEL_RATE_SOURCE PIPE_PIXEL_RATE_PLL_SOURCE PIPE_PIXEL_RATE_SOURCE PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE PIX_EXPAND_MODE PLL_CFG_IF_SOFT_RESET PM_ASSERT_RESET POWER_STATE_ENUM PRE_CSC_MODE_ENUM PRE_DEGAM_MODE PRE_DEGAM_SELECT PRQ_MRQ_FLUSH_URGENT PTE_BUFFER_MODE PTE_ROW_HEIGHT_LINEAR PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT PWRSEQ_BL_PWM_CNTL_BL_PWM_EN PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN PWRSEQ_BL_PWM_GRP1_REG_LOCK PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START PWRSEQ_GPIO_MASK_EN PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN PerfCounter_Vals PhSPIstatusMode PixelPipeCounterId PixelPipeStride PkrMap PkrXsel PkrXsel2 PkrYsel RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS RDPCSTX_CLOCK_CNTL_TX_CLK_EN RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET RDPCSTX_CNTL_RDPCS_TX_FIFO_EN RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET RDPCSTX_FIFO_EMPTY RDPCSTX_FIFO_FULL RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE RDPCSTX_PHY_REF_ALT_CLK_EN RDPCSTX_TX_FIFO_DISABLED_MASK RDPCS_DBG_OCLA_SEL RDPCS_TEST_CLK_SEL RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE READ_COMPRESSION_MODE RESPONSE_STATUS RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL RLC_DOORBELL_MODE RLC_PERFCOUNTER_SEL RLC_PERFMON_STATE RMIPerfSel ROTATION_ANGLE ROW_TTU_MODE RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK RSPM_CMD RbMap RbXsel RbXsel2 RbYsel ReadPolicy RingCounterControl SCL_2TAP_HARDCODE SCL_ALPHA_COEF SCL_AUTOCAL_MODE SCL_BOUNDARY SCL_CHROMA_COEF SCL_COEF_FILTER_TYPE_SEL SCL_COEF_RAM_SEL SCL_SHARP_EN SCOPE SC_PERFCNT_SEL SDMA_PERFMON_SEL SDMA_PERF_SEL SH_MEM_ADDRESS_MODE SH_MEM_ALIGNMENT_MODE SMU_INTR SOFT_RESET SPI_FOG_MODE SPI_LB_WAVES_SELECT SPI_PERFCNT_SEL SPI_PNT_SPRITE_OVERRIDE SPI_PS_LDS_GROUP_SIZE SPI_SAMPLE_CNTL SPI_SHADER_EX_FORMAT SPI_SHADER_FORMAT SPM_PERFMON_STATE SQG_PERF_SEL SQ_CAC_POWER_SEL SQ_EDC_INFO_SOURCE SQ_IBUF_ST SQ_IMG_FILTER_TYPE SQ_IND_CMD_CMD SQ_IND_CMD_MODE SQ_INST_STR_ST SQ_INST_TYPE SQ_LLC_CTL SQ_NO_INST_ISSUE SQ_OOB_SELECT SQ_PERF_SEL SQ_ROUND_MODE SQ_RSRC_BUF_TYPE SQ_RSRC_FLAT_TYPE SQ_RSRC_IMG_TYPE SQ_SEL_XYZW01 SQ_TEX_ANISO_RATIO SQ_TEX_BORDER_COLOR SQ_TEX_CLAMP SQ_TEX_DEPTH_COMPARE SQ_TEX_MIP_FILTER SQ_TEX_XY_FILTER SQ_TEX_Z_FILTER SQ_WATCH_MODES SQ_WAVE_FWD_PROG_INTERVAL SQ_WAVE_SCHED_MODES SQ_WAVE_TYPE STREAM_0_SYNCHRONIZATION STREAM_10_SYNCHRONIZATION STREAM_11_SYNCHRONIZATION STREAM_12_SYNCHRONIZATION STREAM_13_SYNCHRONIZATION STREAM_14_SYNCHRONIZATION STREAM_15_SYNCHRONIZATION STREAM_1_SYNCHRONIZATION STREAM_2_SYNCHRONIZATION STREAM_3_SYNCHRONIZATION STREAM_4_SYNCHRONIZATION STREAM_5_SYNCHRONIZATION STREAM_6_SYNCHRONIZATION STREAM_7_SYNCHRONIZATION STREAM_8_SYNCHRONIZATION STREAM_9_SYNCHRONIZATION SURFACE_DCC SURFACE_DCC_IND_128B SURFACE_DCC_IND_64B SURFACE_DCC_IND_BLK SURFACE_FLIP_AWAY_INT_TYPE SURFACE_FLIP_EXEC_DEBUG_MODE SURFACE_FLIP_INT_TYPE SURFACE_FLIP_IN_STEREOSYNC SURFACE_FLIP_MODE_FOR_STEREOSYNC SURFACE_FLIP_STEREO_SELECT_DISABLE SURFACE_FLIP_STEREO_SELECT_POLARITY SURFACE_FLIP_TYPE SURFACE_FLIP_VUPDATE_SKIP_NUM SURFACE_INUSE_RAED_NO_LATCH SURFACE_PIXEL_FORMAT SURFACE_TMZ SURFACE_UPDATE_LOCK SU_PERFCNT_SEL SWATH_HEIGHT SX_BLEND_OPT SX_DOWNCONVERT_FORMAT SX_OPT_COMB_FCN SX_PERFCOUNTER_VALS SYMCLK_FE_SRC ScMap ScUncertaintyRegionMode ScUncertaintyRegionMult ScXsel ScYsel SeMap SePairMap SePairXsel SePairYsel SeXsel SeYsel StencilOp TA_PERFCOUNT_SEL TA_TC_ADDR_MODES TA_TC_REQ_MODES TCC_MTYPE TCP_CACHE_POLICIES TCP_CACHE_STORE_POLICIES TCP_COMPRESSION_BYPASS TCP_COMPRESSION_OVERRIDE TCP_OPCODE_TYPE TCP_PERFCOUNT_SELECT TCP_WATCH_MODES TCP_WRITE_COMPRESSION_DISABLE TC_EA_CID TC_NACKS TC_OP TC_OP_MASKS TD_PERFCOUNT_SEL TEST_CLK_DIV_SEL TEST_CLK_SEL TEST_CLOCK_MUX_SELECT_ENUM TEX_BC_SWIZZLE TEX_BORDER_COLOR_TYPE TEX_CHROMA_KEY TEX_CLAMP TEX_COORD_TYPE TEX_DEPTH_COMPARE_FUNCTION TEX_FORMAT_COMP TEX_MAX_ANISO_RATIO TEX_MIP_FILTER TEX_REQUEST_SIZE TEX_SAMPLER_TYPE TEX_XY_FILTER TEX_Z_FILTER TMDS_COLOR_FORMAT TMDS_CTL0_DATA_INVERT TMDS_CTL0_DATA_MODULATION TMDS_CTL0_DATA_SEL TMDS_CTL0_PATTERN_OUT_EN TMDS_CTL1_DATA_INVERT TMDS_CTL1_DATA_MODULATION TMDS_CTL1_DATA_SEL TMDS_CTL1_PATTERN_OUT_EN TMDS_CTL2_DATA_INVERT TMDS_CTL2_DATA_MODULATION TMDS_CTL2_DATA_SEL TMDS_CTL2_PATTERN_OUT_EN TMDS_CTL3_DATA_INVERT TMDS_CTL3_DATA_MODULATION TMDS_CTL3_DATA_SEL TMDS_CTL3_PATTERN_OUT_EN TMDS_DATA_SYNCHRONIZATION_DSINTSEL TMDS_MUX_SELECT TMDS_PIXEL_ENCODING TMDS_REG_TEST_OUTPUTA_CNTLA TMDS_REG_TEST_OUTPUTB_CNTLB TMDS_STEREOSYNC_CTL_SEL_REG TMDS_SYNC_PHASE TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB TMDS_TRANSMITTER_CONTROL_IDSCKSELA TMDS_TRANSMITTER_CONTROL_IDSCKSELB TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS TMDS_TRANSMITTER_ENABLE_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK TVX_TYPE UTCL0FaultType UTCL0RequestType UTCL1FaultType UTCL1PerfSel UTCL1RequestType VGT_DETECT_ONE VGT_DETECT_ZERO VGT_DIST_MODE VGT_DI_INDEX_SIZE VGT_DI_PRIM_TYPE VGT_DI_SOURCE_SELECT VGT_DMA_BUF_TYPE VGT_DMA_SWAP_MODE VGT_EVENT_TYPE VGT_GROUP_CONV_SEL VGT_GS_MODE_TYPE VGT_GS_OUTPRIM_TYPE VGT_INDEX_TYPE_MODE VGT_OUTPATH_SELECT VGT_OUT_PRIM_TYPE VGT_RDREQ_POLICY VGT_SPEC_DATA_READ VGT_STAGES_GS_EN VGT_STAGES_HS_EN VGT_TEMPORAL VGT_TESS_PARTITION VGT_TESS_TOPOLOGY VGT_TESS_TYPE VMPG_SIZE VM_GROUP_SIZE VPG_MEM_PWR_DIS_CTRL VPG_MEM_PWR_FORCE_CTRL VRSCombinerModeSC VRSrate VSYNC_CNT_LATCH_MASK VSYNC_CNT_RESET_SEL WD_IA_DRAW_REG_XFER WD_IA_DRAW_SOURCE WD_IA_DRAW_TYPE WRITE_COMPRESSION_MODE WritePolicy XNORM XTAL_REF_CLOCK_SOURCE_SEL XTAL_REF_SEL ZLimitSumm ZModeForce ZOrder ZSamplePosition
umsch_mm_4_0_api_def.h UMSCHAPI__ADD_QUEUE UMSCHAPI__CHANGE_CONTEXT_PRIORITY_LEVEL UMSCHAPI__PERFORM_YIELD UMSCHAPI__QUERY_UMSCH_STATUS UMSCHAPI__REMOVE_QUEUE UMSCHAPI__RESET UMSCHAPI__RESUME UMSCHAPI__SET_HW_RESOURCES UMSCHAPI__SET_LOGGING_BUFFER UMSCHAPI__SET_SCHEDULING_CONFIG UMSCHAPI__SUSPEND UMSCHAPI__UPDATE_AFFINITY UMSCH_AFFINITY UMSCH_AMD_PRIORITY_LEVEL UMSCH_API_HEADER UMSCH_API_OPCODE UMSCH_API_STATUS UMSCH_API_TYPE UMSCH_ENGINE_TYPE UMSCH_INSTANCE_DB_OFFSET UMSCH_LOG_BUFFER UMSCH_LOG_CONTEXT_STATE_CHANGE UMSCH_LOG_ENTRY_DATA UMSCH_LOG_ENTRY_HEADER UMSCH_LOG_QUEUE_NEW_WORK UMSCH_LOG_QUEUE_NO_MORE_WORK UMSCH_LOG_QUEUE_UNWAIT_SYNC_OBJECT UMSCH_LOG_QUEUE_WAIT_SYNC_OBJECT UMSCH_MS_LOG_CONTEXT_STATE UMSCH_MS_LOG_OPERATION UMSCH_RESET_OPTION UMSCH_RESUME_OPTION VM_HUB_TYPE
v10_structs.h v10_ce_ib_state v10_compute_mqd v10_de_ib_state v10_gfx_meta_data v10_gfx_mqd v10_sdma_mqd
v11_structs.h v11_compute_mqd v11_gfx_mqd v11_sdma_mqd
v12_structs.h v12_compute_mqd v12_gfx_mqd v12_sdma_mqd
v9_structs.h v9_ce_ib_state v9_de_ib_state v9_gfx_meta_data v9_mqd v9_mqd_allocation v9_sdma_mqd
vangogh_ip_offset.h IP_BASE IP_BASE_INSTANCE
vega10_enum.h ABM_SOFT_RESET AFMT_AUDIO_CRC_CONTROL_CH_SEL AFMT_AUDIO_CRC_CONTROL_CONT AFMT_AUDIO_CRC_CONTROL_SOURCE AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS AFMT_AUDIO_SRC_CONTROL_SELECT AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE AFMT_INTERRUPT_STATUS_CHG_MASK AFMT_RAMP_CONTROL0_SIGN ALLOW_SR_ON_TRANS_REQ AOUT_CRC_CONT_EN AOUT_CRC_SOFT_RESET AOUT_CRC_TEST_EN AOUT_EN AOUT_FIFO_START_ADDR AUDIO_LAYOUT_SELECT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE AZALIA_SOFT_RESET_REFCLK_SOFT_RESET AZ_CORB_SIZE AZ_GLOBAL_CAPABILITIES AZ_LATENCY_COUNTER_CONTROL AZ_RIRB_SIZE AZ_RIRB_WRITE_POINTER_RESET AZ_STATE_CHANGE_STATUS ArrayMode BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN BLNDV_CONTROL2_PTI_ENABLE BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY BLNDV_CONTROL_BLND_ALPHA_MODE BLNDV_CONTROL_BLND_FEEDTHROUGH_EN BLNDV_CONTROL_BLND_MODE BLNDV_CONTROL_BLND_MULTIPLIED_MODE BLNDV_CONTROL_BLND_STEREO_POLARITY BLNDV_CONTROL_BLND_STEREO_TYPE BLNDV_DEBUG_BLND_CNV_MUX_SELECT BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE BLNDV_SM_CONTROL2_SM_MODE BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN BLND_CONTROL2_PTI_ENABLE BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY BLND_CONTROL_BLND_ALPHA_MODE BLND_CONTROL_BLND_FEEDTHROUGH_EN BLND_CONTROL_BLND_MODE BLND_CONTROL_BLND_MULTIPLIED_MODE BLND_CONTROL_BLND_STEREO_POLARITY BLND_CONTROL_BLND_STEREO_TYPE BLND_DEBUG_BLND_CNV_MUX_SELECT BLND_SM_CONTROL2_SM_FIELD_ALTERNATE BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL BLND_SM_CONTROL2_SM_FRAME_ALTERNATE BLND_SM_CONTROL2_SM_MODE BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE BUF_DATA_FORMAT BUF_NUM_FORMAT BankHeight BankInterleaveSize BankSwapBytes BankTiling BankWidth BankWidthHeight BinEventCntl BinningMode BlendOp BlendOpt CBMode CBPerfClearFilterSel CBPerfOpFilterSel CBPerfSel CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY CHUB_TC_RET_CREDITS_ENUM CLEAR_SMU_INTR CLKGATE_BASE_MODE CLKGATE_SM_MODE CLOCK_BRANCH_SOFT_RESET COL_MAN_DEGAMMA_MODE COL_MAN_DENORM_CLAMP_CONTROL COL_MAN_DISABLE_MULTIPLE_UPDATE COL_MAN_GAMUT_REMAP_MODE COL_MAN_GLOBAL_PASSTHROUGH_ENABLE COL_MAN_INPUTCSC_CONVERT COL_MAN_INPUTCSC_MODE COL_MAN_INPUTCSC_TYPE COL_MAN_INPUT_GAMMA_MODE COL_MAN_OUTPUT_CSC_MODE COL_MAN_PRESCALE_MODE COL_MAN_REGAMMA_MODE_CONTROL COL_MAN_UPDATE_LOCK CORB_READ_POINTER_RESET CPC_PERFCOUNT_SEL CPF_PERFCOUNT_SEL CPG_PERFCOUNT_SEL CP_ALPHA_TAG_RAM_SEL CP_ME_ID CP_PERFMON_ENABLE_MODE CP_PERFMON_STATE CP_PIPE_ID CP_RING_ID CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE CRTC_ADD_PIXEL CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY CRTC_CONTROL_CRTC_MASTER_EN CRTC_CONTROL_CRTC_SOF_PULL_EN CRTC_CONTROL_CRTC_START_POINT_CNTL CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN CRTC_CRC_CNTL_CRTC_CRC_CONT_EN CRTC_CRC_CNTL_CRTC_CRC_EN CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY CRTC_DROP_PIXEL CRTC_DRR_MODE_DBUF_UPDATE_MODE CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL CRTC_HORZ_REPETITION_COUNT CRTC_H_SYNC_A_POL CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE CRTC_STEREO_CONTROL_CRTC_STEREO_EN CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR CRTC_V_SYNC_A_POL CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR CSDATA_TYPE CmaskAddr CmaskCode CmaskMode ColorArray ColorFormat ColorTransform CombFunc CompareFrag CompareRef ConservativeZExport CovToShaderSel DACA_SOFT_RESET DAC_MUX_SELECT DB_CLK_SOFT_RESET DCCG_AUDIO_DTO0_SOURCE_SEL DCCG_AUDIO_DTO2_SOURCE_SEL DCCG_AUDIO_DTO_SEL DCCG_AUDIO_DTO_USE_512FBR_DTO DCCG_DBG_BLOCK_SEL DCCG_DBG_EN DCCG_DEEP_COLOR_CNTL DCCG_FIFO_ERRDET_OVR_EN DCCG_FIFO_ERRDET_RESET DCCG_FIFO_ERRDET_STATE DCCG_PERF_CRTC_SELECT DCCG_PERF_MODE_HSYNC DCCG_PERF_MODE_VSYNC DCCG_PERF_RUN DCIOCHIP_AUXSLAVE_PAD_MODE DCIOCHIP_AUX_CSEL0P9 DCIOCHIP_AUX_CSEL1P1 DCIOCHIP_AUX_FALLSLEWSEL DCIOCHIP_AUX_RSEL0P9 DCIOCHIP_AUX_RSEL1P1 DCIOCHIP_AUX_SPIKESEL DCIOCHIP_DVO_VREFPON DCIOCHIP_DVO_VREFSEL DCIOCHIP_ENABLE_2BIT DCIOCHIP_ENABLE_4BIT DCIOCHIP_ENABLE_5BIT DCIOCHIP_GPIO_I2C_DRIVE DCIOCHIP_GPIO_I2C_EN DCIOCHIP_GPIO_I2C_MASK DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL DCIOCHIP_INVERT DCIOCHIP_MASK DCIOCHIP_MASK_2BIT DCIOCHIP_MASK_4BIT DCIOCHIP_MASK_5BIT DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL DCIOCHIP_SPDIF1_IMODE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT DCIO_BL_PWM_CNTL_BL_PWM_EN DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN DCIO_BL_PWM_GRP1_REG_LOCK DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_DACA_SOFT_RESET DCIO_DBG_ASYNC_4BIT_SEL DCIO_DBG_ASYNC_BLOCK_SEL DCIO_DCO_DCFE_EXT_VSYNC_MUX DCIO_DCO_EXT_VSYNC_MASK DCIO_DCRXPHY_SOFT_RESET DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN DCIO_DC_GENERICA_SEL DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE DCIO_DC_GPIO_MACRO_DEBUG DCIO_DC_GPIO_VIP_DEBUG DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS DCIO_DC_PAD_EXTERN_SIG_SEL DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL DCIO_DPCS_INTERRUPT_MASK DCIO_DPCS_INTERRUPT_TYPE DCIO_DPHY_LANE_SEL DCIO_DSYNC_SOFT_RESET DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK DCIO_GSL0_GLOBAL_UNLOCK_SEL DCIO_GSL0_TIMING_SYNC_SEL DCIO_GSL1_GLOBAL_UNLOCK_SEL DCIO_GSL1_TIMING_SYNC_SEL DCIO_GSL2_GLOBAL_UNLOCK_SEL DCIO_GSL2_TIMING_SYNC_SEL DCIO_GSL_SEL DCIO_GSL_VSYNC_SEL DCIO_IMPCAL_STEP_DELAY DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION DCO_DBG_BLOCK_SEL DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE DCP_ALPHA_ROUND_TRUNC_MODE DCP_CRC_ENABLE DCP_CRC_LINE_SEL DCP_CRC_SOURCE_SEL DCP_CUR2_INV_TRANS_CLAMP DCP_CURSOR_2X_MAGNIFY DCP_CURSOR_ALPHA_BLND_ENA DCP_CURSOR_DEGAMMA_MODE DCP_CURSOR_DISABLE_MULTIPLE_UPDATE DCP_CURSOR_EN DCP_CURSOR_FORCE_MC_ON DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM DCP_CURSOR_MODE DCP_CURSOR_STEREO_EN DCP_CURSOR_STEREO_OFFSET_YNX DCP_CURSOR_UPDATE_LOCK DCP_CURSOR_UPDATE_PENDING DCP_CURSOR_UPDATE_STEREO_MODE DCP_CURSOR_UPDATE_TAKEN DCP_CURSOR_URGENT_CONTROL DCP_CUR_INV_TRANS_CLAMP DCP_CUR_REQUEST_FILTER_DIS DCP_DC_LUT_AUTOFILL DCP_DC_LUT_AUTOFILL_DONE DCP_DC_LUT_DATA_B_FLOAT_POINT_EN DCP_DC_LUT_DATA_B_FORMAT DCP_DC_LUT_DATA_B_SIGNED_EN DCP_DC_LUT_DATA_G_FLOAT_POINT_EN DCP_DC_LUT_DATA_G_FORMAT DCP_DC_LUT_DATA_G_SIGNED_EN DCP_DC_LUT_DATA_R_FLOAT_POINT_EN DCP_DC_LUT_DATA_R_FORMAT DCP_DC_LUT_DATA_R_SIGNED_EN DCP_DC_LUT_INC_B DCP_DC_LUT_INC_G DCP_DC_LUT_INC_R DCP_DC_LUT_RW_MODE DCP_DC_LUT_VGA_ACCESS_ENABLE DCP_DENORM_14BIT_OUT DCP_DENORM_MODE DCP_FRAME_RANDOM_ENABLE DCP_GRPH_ADDRESS_TRANSLATION_ENABLE DCP_GRPH_ALPHA_CROSSBAR DCP_GRPH_BLUE_CROSSBAR DCP_GRPH_COLOR_EXPANSION_MODE DCP_GRPH_DEGAMMA_MODE DCP_GRPH_DEPTH DCP_GRPH_DFQ_MIN_FREE_ENTRIES DCP_GRPH_DFQ_RESET DCP_GRPH_DFQ_RESET_ACK DCP_GRPH_DFQ_SIZE DCP_GRPH_ENABLE DCP_GRPH_ENDIAN_SWAP DCP_GRPH_FLIP_RATE DCP_GRPH_FLIP_RATE_ENABLE DCP_GRPH_FORMAT DCP_GRPH_GAMUT_REMAP_MODE DCP_GRPH_GREEN_CROSSBAR DCP_GRPH_INPUT_GAMMA_MODE DCP_GRPH_KEYER_ALPHA_SEL DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN DCP_GRPH_LUT_10BIT_BYPASS_EN DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE DCP_GRPH_MODE_UPDATE_PENDING DCP_GRPH_MODE_UPDATE_TAKEN DCP_GRPH_NUM_BANKS DCP_GRPH_NUM_PIPES DCP_GRPH_PFLIP_INT_CLEAR DCP_GRPH_PFLIP_INT_MASK DCP_GRPH_PFLIP_INT_TYPE DCP_GRPH_PRESCALE_BYPASS DCP_GRPH_PRESCALE_B_SIGN DCP_GRPH_PRESCALE_G_SIGN DCP_GRPH_PRESCALE_R_SIGN DCP_GRPH_PRESCALE_SELECT DCP_GRPH_PRIMARY_DFQ_ENABLE DCP_GRPH_RED_CROSSBAR DCP_GRPH_REGAMMA_MODE DCP_GRPH_ROTATION_ANGLE DCP_GRPH_SECONDARY_DFQ_ENABLE DCP_GRPH_STEREOSYNC_FLIP_EN DCP_GRPH_STEREOSYNC_FLIP_MODE DCP_GRPH_STEREOSYNC_SELECT_DISABLE DCP_GRPH_SURFACE_COUNTER_EN DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN DCP_GRPH_SURFACE_UPDATE_PENDING DCP_GRPH_SURFACE_UPDATE_TAKEN DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE DCP_GRPH_SW_MODE DCP_GRPH_UPDATE_LOCK DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK DCP_GRPH_XDMA_DRR_MODE_ENABLE DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK DCP_GRPH_XDMA_FLIP_TYPE_CLEAR DCP_GRPH_XDMA_MULTIFLIP_ENABLE DCP_GRPH_XDMA_SUPER_AA_EN DCP_GSL0_EN DCP_GSL1_EN DCP_GSL2_EN DCP_GSL_DELAY_SURFACE_UPDATE_PENDING DCP_GSL_MASTER_EN DCP_GSL_SYNC_SOURCE DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC DCP_GSL_XDMA_GROUP DCP_GSL_XDMA_GROUP_UNDERFLOW_EN DCP_HIGHPASS_RANDOM_ENABLE DCP_INPUT_CSC_GRPH_MODE DCP_KEY_MODE DCP_OUTPUT_CSC_GRPH_MODE DCP_OUT_ROUND_TRUNC_MODE DCP_RGB_RANDOM_ENABLE DCP_SPATIAL_DITHER_DEPTH DCP_SPATIAL_DITHER_EN DCP_SPATIAL_DITHER_MODE DCP_TEST_DEBUG_WRITE_EN DC_MEM_GLOBAL_PWR_REQ_DIS DFSMFlushEvents DIGA_BE_SOFT_RESET DIGA_FE_SOFT_RESET DIGB_BE_SOFT_RESET DIGB_FE_SOFT_RESET DIGC_BE_SOFT_RESET DIGC_FE_SOFT_RESET DIGD_BE_SOFT_RESET DIGD_FE_SOFT_RESET DIGE_BE_SOFT_RESET DIGE_FE_SOFT_RESET DIGF_BE_SOFT_RESET DIGF_FE_SOFT_RESET DIGG_BE_SOFT_RESET DIGG_FE_SOFT_RESET DIGLPA_BE_SOFT_RESET DIGLPA_FE_SOFT_RESET DIGLPB_BE_SOFT_RESET DIGLPB_FE_SOFT_RESET DIG_BE_CNTL_HPD_SELECT DIG_BE_CNTL_MODE DIG_FE_CNTL_SOURCE_SELECT DIG_FE_CNTL_STEREOSYNC_SELECT DIG_FIFO_ERROR_ACK DIG_FIFO_READ_CLOCK_SRC DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL DIG_OUTPUT_CRC_CNTL_LINK_SEL DIG_OUTPUT_CRC_DATA_SEL DIG_RANDOM_PATTERN_SEED_RAN_PAT DIG_TEST_PATTERN_EXTERNAL_RESET_EN DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN DIG_TEST_PATTERN_RANDOM_PATTERN_RESET DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN DISABLE_CLOCK_GATING DISABLE_CLOCK_GATING_IN_DCO DISPCLK_CHG_FWD_CORR_DISABLE DISPCLK_FREQ_RAMP_DONE DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE DOUT_I2C_ACK DOUT_I2C_ARBITRATION_ABORT_XFER DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO DOUT_I2C_ARBITRATION_SW_PRIORITY DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ DOUT_I2C_CONTROL_DBG_REF_SEL DOUT_I2C_CONTROL_DDC_SELECT DOUT_I2C_CONTROL_GO DOUT_I2C_CONTROL_SEND_RESET DOUT_I2C_CONTROL_SOFT_RESET DOUT_I2C_CONTROL_SW_STATUS_RESET DOUT_I2C_CONTROL_TRANSACTION_COUNT DOUT_I2C_DATA_INDEX_WRITE DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE DOUT_I2C_DDC_SPEED_THRESHOLD DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE DOUT_I2C_TRANSACTION_STOP_ON_NACK DPCSRX_DBG_CFGCLK_SEL DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL DPCSRX_RX_SYMCLK_SEL DPCSTX_DBG_CFGCLK_SEL DPCSTX_TX_SYMCLK_DIV2_SEL DPCSTX_TX_SYMCLK_SEL DPDBG_CLK_FORCE_EN DPDBG_EN DPDBG_ERROR_DETECTION_MODE DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE DPDBG_INPUT_EN DPDBG_SOFT_RESET DPHY_8B10B_CUR_DISP DPHY_8B10B_RESET DPHY_ALT_SCRAMBLER_RESET_EN DPHY_ALT_SCRAMBLER_RESET_SEL DPHY_ATEST_SEL_LANE0 DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3 DPHY_BYPASS DPHY_CRC_CONT_EN DPHY_CRC_EN DPHY_CRC_FIELD DPHY_CRC_MST_PHASE_ERROR_ACK DPHY_CRC_SEL DPHY_LOAD_BS_COUNT_START DPHY_PRBS_EN DPHY_PRBS_SEL DPHY_RX_FAST_TRAINING_CAPABLE DPHY_SCRAMBLER_ADVANCE DPHY_SCRAMBLER_DIS DPHY_SCRAMBLER_KCODE DPHY_SCRAMBLER_SEL DPHY_SKEW_BYPASS DPHY_SW_FAST_TRAINING_START DPHY_TRAINING_PATTERN_SEL DPREFCLK_SRC_SEL DPRX_SD_COMPONENT_DEPTH DPRX_SD_PIXEL_ENCODING DP_AUX_ARB_CONTROL_ARB_PRIORITY DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ DP_AUX_CONTROL_HPD_SEL DP_AUX_CONTROL_TEST_MODE DP_AUX_DEFINITE_ERR_REACHED_ACK DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW DP_AUX_DPHY_RX_CONTROL_START_WINDOW DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN DP_AUX_DPHY_RX_DETECTION_THRESHOLD DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL DP_AUX_ERR_OCCURRED_ACK DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN DP_AUX_INT_ACK DP_AUX_LS_UPDATE_ACK DP_AUX_POTENTIAL_ERR_REACHED_ACK DP_AUX_RESET DP_AUX_RESET_DONE DP_AUX_SW_CONTROL_LS_READ_TRIG DP_AUX_SW_CONTROL_SW_GO DP_COMPONENT_DEPTH DP_DPHY_8B10B_EXT_DISP DP_DPHY_FAST_TRAINING_COMPLETE_ACK DP_DPHY_FAST_TRAINING_COMPLETE_MASK DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN DP_DPHY_HBR2_PATTERN_CONTROL_MODE DP_DTO_DS_DISABLE DP_DYN_RANGE DP_EMBEDDED_PANEL_MODE DP_LINK_TRAINING_COMPLETE DP_MSA_MISC0_OVERRIDE_ENABLE DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE DP_MSA_V_TIMING_OVERRIDE_EN DP_MSE_BLANK_CODE DP_MSE_LINK_LINE DP_MSE_OUTPUT_DPDBG_DATA DP_MSE_SAT_UPDATE_ACT DP_MSE_TIMESTAMP_MODE DP_MSE_ZERO_ENCODER DP_PIXEL_ENCODING DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE DP_SEC_ASP_PRIORITY DP_SEC_AUDIO_MUTE DP_SEC_COLLISION_ACK DP_SEC_GSP0_PRIORITY DP_SEC_GSP0_SEND DP_SEC_TIMESTAMP_MODE DP_STEER_OVERFLOW_ACK DP_STEER_OVERFLOW_MASK DP_TU_OVERFLOW_ACK DP_UDI_LANES DP_VID_ENHANCED_FRAME_MODE DP_VID_MSA_TOP_FIELD_MODE DP_VID_M_DOUBLE_VALUE_EN DP_VID_M_N_DOUBLE_BUFFER_MODE DP_VID_M_N_GEN_EN DP_VID_STREAM_DISABLE_ACK DP_VID_STREAM_DISABLE_MASK DP_VID_STREAM_DIS_DEFER DP_VID_TIMING_MODE DP_VID_VBID_FIELD_POL DP_YCBCR_RANGE DSI_BIT_SWAP DSI_CLK_GATING DSI_CLOCK_LANE_EN DSI_CLOCK_LANE_HS_FORCE_REQUEST DSI_CMD_EMBEDDED_MODE DSI_CMD_MODE_EN DSI_CMD_ORDER DSI_CMD_PACKET_TYPE DSI_CMD_PWR_MODE DSI_COMMAND_MODE_DST_FORMAT DSI_COMMAND_MODE_SRC_FORMAT DSI_COMMAND_TRIGGER_MODE DSI_COMMAND_TRIGGER_ORDER DSI_COMMAND_TRIGGER_SEL DSI_CONTROLLER_EN DSI_CRC_ENABLE DSI_CRTC_FREEZE_TRIG DSI_CRTC_SEL DSI_DATA_BUFFER_ID DSI_DATA_LANE0_EN DSI_DATA_LANE1_EN DSI_DATA_LANE2_EN DSI_DATA_LANE3_EN DSI_DBG_CLK_SEL DSI_DEBUG_BYTECLK_SEL DSI_DEBUG_DSICLK_SEL DSI_DENG_FIFO_FORCE_RECAL_AVERAGE DSI_DENG_FIFO_FORCE_RECOMP_MINMAX DSI_DENG_FIFO_START DSI_DENG_FIFO_USE_OVERWRITE_LEVEL DSI_DMAFIFO_READ_WATERMARK DSI_DMAFIFO_WRITE_WATERMARK DSI_DWORD_BYTE_SWAP DSI_EXT_RESET_POL DSI_EXT_TE_MODE DSI_EXT_TE_MUX DSI_EXT_TE_POL DSI_FLAG_CLR DSI_HW_SOURCE_SEL DSI_INSERT_DCS_COMMAND DSI_LANE_FORCE_TX_STOP DSI_LANE_ULPS_EXIT DSI_LANE_ULPS_REQUEST DSI_MIPI_BIST_RESET DSI_MIPI_BIST_START DSI_MIPI_BIST_VIDEO_FRMT DSI_PACKET_BYTE_MSB_LSB_FLIP DSI_PERF_LATENCY_SEL DSI_PHY_DATA_LANE0_EN DSI_PHY_DATA_LANE1_EN DSI_PHY_DATA_LANE2_EN DSI_PHY_DATA_LANE3_EN DSI_RESET_BYTECLK DSI_RESET_DISPCLK DSI_RESET_DSICLK DSI_RESET_ESCCLK DSI_RESET_PANEL DSI_RGB_SWAP DSI_RX_EOT_IGNORE DSI_TE_SRC_SEL DSI_TX_EOT_APPEND DSI_USE_CMDFIFO DSI_USE_DENG_LENGTH DSI_VIDEO_BLLP_PWR_MODE DSI_VIDEO_EOF_BLLP_PWR_MODE DSI_VIDEO_MODE_DST_FORMAT DSI_VIDEO_MODE_EN DSI_VIDEO_PULSE_MODE_OPT DSI_VIDEO_PWR_MODE DSI_VIDEO_TRAFFIC_MODE DSM_ENABLE_ERROR_INJECT DSM_SELECT_INJECT_DELAY DS_REF_SRC DVOACLKC_IN_PHASE DVOACLKC_MVP_IN_PHASE DVOACLKC_MVP_SKEW_PHASE_OVERRIDE DVOACLKD_IN_PHASE DVOACLK_COARSE_SKEW_CNTL DVOACLK_FINE_SKEW_CNTL DVO_ENABLE_RST DVO_SOFT_RESET DbMemArbWatermarks DbPRTFaultBehavior DbPSLControl DepthArray DepthFormat ENABLE ENABLE_CLOCK ENUM_NUM_SIMD_PER_CU ENUM_SQ_EXPORT_RAT_INST ENUM_XDMA_LOCAL_SW_MODE ENUM_XDMA_MSTR_ALPHA_POSITION ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL ENUM_XDMA_SLV_ALPHA_POSITION FBC_IDLE_MASK_MASK_BITS FMT0_SOFT_RESET FMT1_SOFT_RESET FMT2_SOFT_RESET FMT3_SOFT_RESET FMT420_MEMORY_SOURCE_SEL FMT4_SOFT_RESET FMT5_SOFT_RESET FMT_BIT_DEPTH_CONTROL_25FRC_SEL FMT_BIT_DEPTH_CONTROL_50FRC_SEL FMT_BIT_DEPTH_CONTROL_75FRC_SEL FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE FMT_CLAMP_CNTL_COLOR_FORMAT FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS FMT_CONTROL_PIXEL_ENCODING FMT_CONTROL_SUBSAMPLING_MODE FMT_CONTROL_SUBSAMPLING_ORDER FMT_CRC_CNTL_CONT_EN FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT FMT_CRC_CNTL_INCLUDE_OVERSCAN FMT_CRC_CNTL_INTERLACE_MODE FMT_CRC_CNTL_ONLY_BLANKB FMT_CRC_CNTL_PSR_MODE_ENABLE FMT_DEBUG_CNTL_COLOR_SELECT FMT_DYNAMIC_EXP_MODE FMT_SPATIAL_DITHER_MODE FMT_STEREOSYNC_OVR_POL FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT FORCE_VBI ForceControl GATCL1RequestType GB_EDC_DED_MODE GDS_PERFCOUNT_SELECT GENERICA_STEREOSYNC_SEL GENERICB_STEREOSYNC_SEL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED GENERIC_AZ_CONTROLLER_REGISTER_STATUS GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE GLOBAL_CONTROL_CONTROLLER_RESET GLOBAL_CONTROL_FLUSH_CONTROL GLOBAL_STATUS_FLUSH_STATUS GRBM_PERF_SEL GRBM_SE0_PERF_SEL GRBM_SE1_PERF_SEL GRBM_SE2_PERF_SEL GRBM_SE3_PERF_SEL GroupInterleave HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CONT HDMI_ACR_N_MULTIPLE HDMI_ACR_SELECT HDMI_ACR_SEND HDMI_ACR_SOURCE HDMI_AUDIO_DELAY_EN HDMI_AUDIO_INFO_CONT HDMI_AUDIO_INFO_SEND HDMI_AUDIO_SEND_MAX_PACKETS HDMI_AVI_INFO_CONT HDMI_AVI_INFO_SEND HDMI_CLOCK_CHANNEL_RATE HDMI_DATA_SCRAMBLE_EN HDMI_DEEP_COLOR_DEPTH HDMI_DEFAULT_PAHSE HDMI_ERROR_ACK HDMI_ERROR_MASK HDMI_GC_AVMUTE HDMI_GC_AVMUTE_CONT HDMI_GC_CONT HDMI_GC_SEND HDMI_GENERIC0_CONT HDMI_GENERIC0_SEND HDMI_GENERIC1_CONT HDMI_GENERIC1_SEND HDMI_GENERIC2_CONT HDMI_GENERIC2_SEND HDMI_GENERIC3_CONT HDMI_GENERIC3_SEND HDMI_ISRC_CONT HDMI_ISRC_SEND HDMI_KEEPOUT_MODE HDMI_MPEG_INFO_CONT HDMI_MPEG_INFO_SEND HDMI_NO_EXTRA_NULL_PACKET_FILLED HDMI_NULL_SEND HDMI_PACKET_GEN_VERSION HDMI_PACKING_PHASE_OVERRIDE HPD_INT_CONTROL_ACK HPD_INT_CONTROL_POLARITY HPD_INT_CONTROL_RX_INT_ACK I2S0_SPDIF0_SOFT_RESET I2S1_SOFT_RESET I2S_LRCLK_POLARITY I2S_SAMPLE_ALIGNMENT I2S_SAMPLE_BIT_ORDER I2S_WORD_ALIGNMENT I2S_WORD_SIZE IA_PERFCOUNT_SELECT IH_PERF_SEL IMG_DATA_FORMAT IMG_NUM_FORMAT IMG_NUM_FORMAT_ASTC_2D IMG_NUM_FORMAT_ASTC_3D IMG_NUM_FORMAT_FMASK IMG_NUM_FORMAT_N_IN_16 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID JITTER_REMOVE_DISABLE LBV_DITHER_EN LBV_DOWNSCALE_PREFETCH_EN LBV_DYNAMIC_PIXEL_DEPTH LBV_INTERLEAVE_EN LBV_MEMORY_CONFIG LBV_PIXEL_DEPTH LBV_PIXEL_EXPAN_MODE LBV_PIXEL_REDUCE_MODE LBV_SYNC_DURATION LBV_SYNC_RESET_SEL2 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK LB_DATA_FORMAT_ALPHA_EN LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH LB_DATA_FORMAT_INTERLEAVE_EN LB_DATA_FORMAT_PIXEL_DEPTH LB_DATA_FORMAT_PIXEL_EXPAN_MODE LB_DATA_FORMAT_PIXEL_REDUCE_MODE LB_DATA_FORMAT_REQUEST_MODE LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE LB_SYNC_RESET_SEL_LB_SYNC_DURATION LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN LB_VBLANK_STATUS_VBLANK_ACK LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE LB_VLINE2_START_END_VLINE2_INV LB_VLINE2_STATUS_VLINE2_ACK LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE LB_VLINE_START_END_VLINE_INV LB_VLINE_STATUS_VLINE_ACK LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE LVTMA_RANDOM_PATTERN_SEED_RAN_PAT LptNumBanks LptNumPipes MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE MASTER_UPDATE_MODE_MASTER_UPDATE_MODE MEM_PWR_DIS_CTRL MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2 MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2 MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL MTYPE MVP_CLK_SRC_SEL MVP_SOFT_RESET MacroTileAspect MemArbMode MicroTileMode MultiGPUTileSize NonDispTilingOrder NumBanks NumBanksConfig NumGPUs NumLowerPipes NumMaxCompressedFragments NumPipes NumRbPerShaderEngine NumShaderEngines OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE OVERRIDE_CGTT_DCEFCLK OVERRIDE_CGTT_SCLK PERFCOUNTER_ACTIVE PERFCOUNTER_CNT0_STATE PERFCOUNTER_CNT1_STATE PERFCOUNTER_CNT2_STATE PERFCOUNTER_CNT3_STATE PERFCOUNTER_CNT4_STATE PERFCOUNTER_CNT5_STATE PERFCOUNTER_CNT6_STATE PERFCOUNTER_CNT7_STATE PERFCOUNTER_CNTL_SEL PERFCOUNTER_CNTOFF_START_DIS PERFCOUNTER_COUNTED_VALUE_TYPE PERFCOUNTER_CVALUE_SEL PERFCOUNTER_HW_CNTL_SEL PERFCOUNTER_INC_MODE PERFCOUNTER_INT_EN PERFCOUNTER_INT_TYPE PERFCOUNTER_OFF_MASK PERFCOUNTER_RESTART_EN PERFCOUNTER_RUNEN_MODE PERFCOUNTER_STATE_SEL0 PERFCOUNTER_STATE_SEL1 PERFCOUNTER_STATE_SEL2 PERFCOUNTER_STATE_SEL3 PERFCOUNTER_STATE_SEL4 PERFCOUNTER_STATE_SEL5 PERFCOUNTER_STATE_SEL6 PERFCOUNTER_STATE_SEL7 PERFMON_CNTOFF_AND_OR PERFMON_CNTOFF_INT_EN PERFMON_CNTOFF_INT_TYPE PERFMON_COUNTER_MODE PERFMON_SPM_MODE PERFMON_STATE PIPE_PHYPLL_PIXEL_RATE_SOURCE PIPE_PIXEL_RATE_PLL_SOURCE PIPE_PIXEL_RATE_SOURCE PLL_CFG_IF_SOFT_RESET PM_ASSERT_RESET PerfCounter_Vals PipeConfig PipeInterleaveSize PipeTiling PixelPipeCounterId PixelPipeStride PkrMap PkrXsel PkrXsel2 PkrYsel QuadExportFormat QuadExportFormatOld REFCLK_CLOCK_EN REFCLK_SRC_SEL RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL RMIPerfSel RMI_CID RbMap RbXsel RbXsel2 RbYsel ReadSize RingCounterControl RoundMode RowSize RowTiling SCLV_COEF_UPDATE_COMPLETE SCLV_INTERLACE_SOURCE SCLV_MODE_SEL SCLV_UPDATE_LOCK SCL_ALU_DISABLE SCL_BOUNDARY_MODE SCL_BYPASS_MODE SCL_COEF_UPDATE_COMPLETE SCL_C_RAM_FILTER_TYPE SCL_C_RAM_PHASE SCL_C_RAM_TAP_PAIR_IDX SCL_EARLY_EOL_MOD SCL_HF_SHARP_EN SCL_HF_SHARP_SCALE_FACTOR SCL_HOST_CONFLICT_MASK SCL_H_2TAP_HARDCODE_COEF_EN SCL_H_CALC_AUTO_RATIO_EN SCL_H_FILTER_PICK_NEAREST SCL_H_MANUAL_REPLICATE_FACTOR SCL_H_NUM_OF_TAPS SCL_MODE_SEL SCL_PSCL_EN SCL_SCL_MODE_CHANGE_MASK SCL_UPDATE_LOCK SCL_UPDATE_TAKEN SCL_VF_SHARP_EN SCL_VF_SHARP_SCALE_FACTOR SCL_V_2TAP_HARDCODE_COEF_EN SCL_V_CALC_AUTO_RATIO_EN SCL_V_FILTER_PICK_NEAREST SCL_V_MANUAL_REPLICATE_FACTOR SCL_V_NUM_OF_TAPS SC_PERFCNT_SEL SDMA_PERF_SEL SEM_PERF_SEL SH_MEM_ADDRESS_MODE SH_MEM_ALIGNMENT_MODE SPDIF1_SOFT_RESET SPDIF_INVERT_EN SPI_FOG_MODE SPI_PERFCNT_SEL SPI_PNT_SPRITE_OVERRIDE SPI_SAMPLE_CNTL SPI_SHADER_EX_FORMAT SPI_SHADER_FORMAT SPM_PERFMON_STATE SQ_CAC_POWER_SEL SQ_EDC_INFO_SOURCE SQ_IBUF_ST SQ_IMG_FILTER_TYPE SQ_IND_CMD_CMD SQ_IND_CMD_MODE SQ_INST_STR_ST SQ_INTERRUPT_WORD_ENCODING SQ_LB_CTR_SEL_VALUES SQ_PERF_SEL SQ_ROUND_MODE SQ_RSRC_BUF_TYPE SQ_RSRC_FLAT_TYPE SQ_RSRC_IMG_TYPE SQ_SEL_XYZW01 SQ_TEX_ANISO_RATIO SQ_TEX_BORDER_COLOR SQ_TEX_CLAMP SQ_TEX_DEPTH_COMPARE SQ_TEX_MIP_FILTER SQ_TEX_XY_FILTER SQ_TEX_Z_FILTER SQ_THREAD_TRACE_CAPTURE_MODE SQ_THREAD_TRACE_INST_TYPE SQ_THREAD_TRACE_ISSUE SQ_THREAD_TRACE_ISSUE_MASK SQ_THREAD_TRACE_MISC_TOKEN_TYPE SQ_THREAD_TRACE_MODE_SEL SQ_THREAD_TRACE_REG_OP SQ_THREAD_TRACE_REG_TYPE SQ_THREAD_TRACE_TOKEN_TYPE SQ_THREAD_TRACE_VM_ID_MASK SQ_THREAD_TRACE_WAVE_MASK SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX SQ_WAVE_IB_ECC_ST SQ_WAVE_TYPE STATIC_SCREEN_SMU_INTR STREAM_0_SYNCHRONIZATION STREAM_10_SYNCHRONIZATION STREAM_11_SYNCHRONIZATION STREAM_12_SYNCHRONIZATION STREAM_13_SYNCHRONIZATION STREAM_14_SYNCHRONIZATION STREAM_15_SYNCHRONIZATION STREAM_1_SYNCHRONIZATION STREAM_2_SYNCHRONIZATION STREAM_3_SYNCHRONIZATION STREAM_4_SYNCHRONIZATION STREAM_5_SYNCHRONIZATION STREAM_6_SYNCHRONIZATION STREAM_7_SYNCHRONIZATION STREAM_8_SYNCHRONIZATION STREAM_9_SYNCHRONIZATION SU_PERFCNT_SEL SWIZZLE_MODE_ENUM SWIZZLE_TYPE_ENUM SX_BLEND_OPT SX_DOWNCONVERT_FORMAT SX_OPT_COMB_FCN SX_PERFCOUNTER_VALS SYMCLK_FE_FORCE_EN SYMCLK_FE_FORCE_SRC SampleSplit SampleSplitBytes ScMap ScXsel ScYsel SeEnable SeMap SePairMap SePairXsel SePairYsel SeXsel SeYsel ShaderEngineTileSize SourceFormat StencilFormat StencilOp SurfaceArray SurfaceEndian SurfaceFormat SurfaceNumber SurfaceSwap SurfaceTiling TA_PERFCOUNT_SEL TA_TC_ADDR_MODES TCA_PERF_SEL TCC_CACHE_POLICIES TCC_PERF_SEL TCP_CACHE_POLICIES TCP_CACHE_STORE_POLICIES TCP_DSM_DATA_SEL TCP_DSM_INJECT_SEL TCP_DSM_SINGLE_WRITE TCP_PERFCOUNT_SELECT TCP_WATCH_MODES TC_CHUB_REQ_CREDITS_ENUM TC_EA_CID TC_MICRO_TILE_MODE TC_NACKS TC_OP TC_OP_MASKS TD_PERFCOUNT_SEL TEX_BORDER_COLOR_TYPE TEX_CHROMA_KEY TEX_CLAMP TEX_COORD_TYPE TEX_DEPTH_COMPARE_FUNCTION TEX_DIM TEX_FORMAT_COMP TEX_MAX_ANISO_RATIO TEX_MIP_FILTER TEX_REQUEST_SIZE TEX_SAMPLER_TYPE TEX_XY_FILTER TEX_Z_FILTER TMDS_COLOR_FORMAT TMDS_CTL0_DATA_INVERT TMDS_CTL0_DATA_MODULATION TMDS_CTL0_DATA_SEL TMDS_CTL0_PATTERN_OUT_EN TMDS_CTL1_DATA_INVERT TMDS_CTL1_DATA_MODULATION TMDS_CTL1_DATA_SEL TMDS_CTL1_PATTERN_OUT_EN TMDS_CTL2_DATA_INVERT TMDS_CTL2_DATA_MODULATION TMDS_CTL2_DATA_SEL TMDS_CTL2_PATTERN_OUT_EN TMDS_CTL3_DATA_INVERT TMDS_CTL3_DATA_MODULATION TMDS_CTL3_DATA_SEL TMDS_CTL3_PATTERN_OUT_EN TMDS_DATA_SYNCHRONIZATION_DSINTSEL TMDS_DVO_MUX_SELECT TMDS_PIXEL_ENCODING TMDS_REG_TEST_OUTPUTA_CNTLA TMDS_REG_TEST_OUTPUTB_CNTLB TMDS_STEREOSYNC_CTL_SEL_REG TMDS_SYNC_PHASE TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB TMDS_TRANSMITTER_CONTROL_IDSCKSELA TMDS_TRANSMITTER_CONTROL_IDSCKSELB TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS TMDS_TRANSMITTER_ENABLE_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK TVX_DATA_FORMAT TVX_DST_SEL TVX_ENDIAN_SWAP TVX_INST TVX_NUM_FORMAT_ALL TVX_SRC_SEL TVX_SRF_MODE_ALL TVX_TYPE TileSplit TileType UNP_BUFFER_MODE UNP_CRC_LINE_SEL UNP_CRC_SOURCE_SEL UNP_GRPH_ADDRESS_TRANSLATION_ENABLE UNP_GRPH_BANK_HEIGHT UNP_GRPH_BANK_WIDTH UNP_GRPH_BLUE_CROSSBAR UNP_GRPH_COLOR_EXPANSION_MODE UNP_GRPH_DEPTH UNP_GRPH_EN UNP_GRPH_ENDIAN_SWAP UNP_GRPH_GREEN_CROSSBAR UNP_GRPH_MACRO_TILE_ASPECT UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE UNP_GRPH_MODE_UPDATE_LOCKG UNP_GRPH_NUM_BANKS UNP_GRPH_RED_CROSSBAR UNP_GRPH_STACK_INTERLACE_FLIP_EN UNP_GRPH_STACK_INTERLACE_FLIP_MODE UNP_GRPH_STEREOSYNC_FLIP_EN UNP_GRPH_STEREOSYNC_FLIP_MODE UNP_GRPH_STEREOSYNC_SELECT_DISABLE UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK UNP_GRPH_TILE_SPLIT UNP_PIXEL_DROP UNP_ROTATION_ANGLE UNP_VIDEO_FORMAT UTCL1FaultType UTCL1RequestType VGT_CACHE_INVALID_MODE VGT_DIST_MODE VGT_DI_INDEX_SIZE VGT_DI_MAJOR_MODE_SELECT VGT_DI_PRIM_TYPE VGT_DI_SOURCE_SELECT VGT_DMA_BUF_TYPE VGT_DMA_SWAP_MODE VGT_EVENT_TYPE VGT_GROUP_CONV_SEL VGT_GRP_PRIM_ORDER VGT_GRP_PRIM_TYPE VGT_GS_CUT_MODE VGT_GS_MODE_TYPE VGT_GS_OUTPRIM_TYPE VGT_INDEX_TYPE_MODE VGT_OUTPATH_SELECT VGT_OUT_PRIM_TYPE VGT_PERFCOUNT_SELECT VGT_RDREQ_POLICY VGT_STAGES_ES_EN VGT_STAGES_GS_EN VGT_STAGES_HS_EN VGT_STAGES_LS_EN VGT_STAGES_VS_EN VGT_TESS_PARTITION VGT_TESS_TOPOLOGY VGT_TESS_TYPE VTX_CLAMP VTX_FETCH_TYPE VTX_FORMAT_COMP_ALL VTX_MEM_REQUEST_SIZE WD_IA_DRAW_REG_XFER WD_IA_DRAW_SOURCE WD_IA_DRAW_TYPE WD_PERFCOUNT_SELECT XTAL_REF_CLOCK_SOURCE_SEL XTAL_REF_SEL ZFormat ZLimitSumm ZModeForce ZOrder ZSamplePosition ZpassControl
vega10_ip_offset.h IP_BASE IP_BASE_INSTANCE
vega20_ip_offset.h IP_BASE IP_BASE_INSTANCE
vi_structs.h vi_ce_ib_state vi_ce_ib_state_chained_ib vi_de_ib_state vi_de_ib_state_chained_ib vi_gfx_meta_data vi_gfx_meta_data_chained_ib vi_mqd vi_mqd_allocation vi_sdma_mqd
yellow_carp_offset.h IP_BASE IP_BASE_INSTANCE

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