linux/linux/include/uapi/drm/ Source Tree

../
amdgpu_drm.h drm_amdgpu_bo_list drm_amdgpu_bo_list_entry drm_amdgpu_bo_list_in drm_amdgpu_bo_list_out drm_amdgpu_cs drm_amdgpu_cs_chunk drm_amdgpu_cs_chunk_cp_gfx_shadow drm_amdgpu_cs_chunk_data drm_amdgpu_cs_chunk_dep drm_amdgpu_cs_chunk_fence drm_amdgpu_cs_chunk_ib drm_amdgpu_cs_chunk_sem drm_amdgpu_cs_chunk_syncobj drm_amdgpu_cs_in drm_amdgpu_cs_out drm_amdgpu_ctx drm_amdgpu_ctx_in drm_amdgpu_ctx_out drm_amdgpu_fence drm_amdgpu_fence_to_handle drm_amdgpu_gem_create drm_amdgpu_gem_create_in drm_amdgpu_gem_create_out drm_amdgpu_gem_metadata drm_amdgpu_gem_mmap drm_amdgpu_gem_mmap_in drm_amdgpu_gem_mmap_out drm_amdgpu_gem_op drm_amdgpu_gem_userptr drm_amdgpu_gem_va drm_amdgpu_gem_wait_idle drm_amdgpu_gem_wait_idle_in drm_amdgpu_gem_wait_idle_out drm_amdgpu_heap_info drm_amdgpu_info drm_amdgpu_info_device drm_amdgpu_info_firmware drm_amdgpu_info_gds drm_amdgpu_info_gpuvm_fault drm_amdgpu_info_hw_ip drm_amdgpu_info_num_handles drm_amdgpu_info_vbios drm_amdgpu_info_vce_clock_table drm_amdgpu_info_vce_clock_table_entry drm_amdgpu_info_video_caps drm_amdgpu_info_video_codec_info drm_amdgpu_info_vram_gtt drm_amdgpu_memory_info drm_amdgpu_query_fw drm_amdgpu_sched drm_amdgpu_sched_in drm_amdgpu_vm drm_amdgpu_vm_in drm_amdgpu_vm_out drm_amdgpu_wait_cs drm_amdgpu_wait_cs_in drm_amdgpu_wait_cs_out drm_amdgpu_wait_fences drm_amdgpu_wait_fences_in drm_amdgpu_wait_fences_out
armada_drm.h drm_armada_gem_create drm_armada_gem_mmap drm_armada_gem_pwrite
drm.h drm_agp_binding drm_agp_buffer drm_agp_info drm_agp_mode drm_auth drm_block drm_buf_desc drm_buf_free drm_buf_info drm_buf_map drm_buf_pub drm_client drm_clip_rect drm_control drm_crtc_get_sequence drm_crtc_queue_sequence drm_ctx drm_ctx_flags drm_ctx_priv_map drm_ctx_res drm_dma drm_dma_flags drm_draw drm_drawable_info drm_event drm_event_crtc_sequence drm_event_vblank drm_gem_close drm_gem_flink drm_gem_open drm_get_cap drm_hw_lock drm_irq_busid drm_list drm_lock drm_lock_flags drm_map drm_map_flags drm_map_type drm_modeset_ctl drm_prime_handle drm_scatter_gather drm_set_client_cap drm_set_version drm_stat_type drm_stats drm_syncobj_array drm_syncobj_create drm_syncobj_destroy drm_syncobj_eventfd drm_syncobj_handle drm_syncobj_timeline_array drm_syncobj_timeline_wait drm_syncobj_transfer drm_syncobj_wait drm_tex_region drm_unique drm_update_draw drm_vblank_seq_type drm_version drm_wait_vblank drm_wait_vblank_reply drm_wait_vblank_request
drm_fourcc.h
drm_mode.h drm_color_ctm drm_color_ctm_3x4 drm_color_lut drm_format_modifier drm_format_modifier_blob drm_mode_atomic drm_mode_card_res drm_mode_closefb drm_mode_connector_set_property drm_mode_create_blob drm_mode_create_dumb drm_mode_create_lease drm_mode_crtc drm_mode_crtc_lut drm_mode_crtc_page_flip drm_mode_crtc_page_flip_target drm_mode_cursor drm_mode_cursor2 drm_mode_destroy_blob drm_mode_destroy_dumb drm_mode_fb_cmd drm_mode_fb_cmd2 drm_mode_fb_dirty_cmd drm_mode_get_blob drm_mode_get_connector drm_mode_get_encoder drm_mode_get_lease drm_mode_get_plane drm_mode_get_plane_res drm_mode_get_property drm_mode_list_lessees drm_mode_map_dumb drm_mode_mode_cmd drm_mode_modeinfo drm_mode_obj_get_properties drm_mode_obj_set_property drm_mode_property_enum drm_mode_rect drm_mode_revoke_lease drm_mode_set_plane drm_mode_subconnector hdr_metadata_infoframe hdr_output_metadata
etnaviv_drm.h drm_etnaviv_gem_cpu_fini drm_etnaviv_gem_cpu_prep drm_etnaviv_gem_info drm_etnaviv_gem_new drm_etnaviv_gem_submit drm_etnaviv_gem_submit_bo drm_etnaviv_gem_submit_pmr drm_etnaviv_gem_submit_reloc drm_etnaviv_gem_userptr drm_etnaviv_gem_wait drm_etnaviv_param drm_etnaviv_pm_domain drm_etnaviv_pm_signal drm_etnaviv_timespec drm_etnaviv_wait_fence
exynos_drm.h drm_exynos_g2d_buf_type drm_exynos_g2d_cmd drm_exynos_g2d_event drm_exynos_g2d_event_type drm_exynos_g2d_exec drm_exynos_g2d_get_ver drm_exynos_g2d_set_cmdlist drm_exynos_g2d_userptr drm_exynos_gem_create drm_exynos_gem_info drm_exynos_gem_map drm_exynos_ioctl_ipp_commit drm_exynos_ioctl_ipp_get_caps drm_exynos_ioctl_ipp_get_limits drm_exynos_ioctl_ipp_get_res drm_exynos_ipp_capability drm_exynos_ipp_event drm_exynos_ipp_flag drm_exynos_ipp_format drm_exynos_ipp_format_type drm_exynos_ipp_limit drm_exynos_ipp_limit_type drm_exynos_ipp_limit_val drm_exynos_ipp_task_alpha drm_exynos_ipp_task_buffer drm_exynos_ipp_task_id drm_exynos_ipp_task_rect drm_exynos_ipp_task_transform drm_exynos_vidi_connection e_drm_exynos_gem_mem_type
habanalabs_accel.h gaudi2_engine_id gaudi2_queue_id gaudi_dcores gaudi_engine_id gaudi_queue_id goya_engine_id goya_queue_id hl_cb_args hl_cb_in hl_cb_out hl_clk_throttling_type hl_cs_args hl_cs_chunk hl_cs_in hl_cs_out hl_debug_args hl_debug_params_bmon hl_debug_params_etf hl_debug_params_etr hl_debug_params_spmu hl_debug_params_stm hl_device_status hl_engine_command hl_gaudi2_pll_index hl_gaudi_pll_index hl_goya_dma_direction hl_goya_pll_index hl_info_args hl_info_clk_rate hl_info_clk_throttle hl_info_cs_counters hl_info_cs_timeout_event hl_info_dev_memalloc_page_sizes hl_info_device_status hl_info_device_utilization hl_info_dram_usage hl_info_energy hl_info_engine_err_event hl_info_fw_err_event hl_info_fw_err_type hl_info_hw_err_event hl_info_hw_idle hl_info_hw_ip_info hl_info_last_err_open_dev_time hl_info_pci_counters hl_info_razwi_event hl_info_reset_count hl_info_sec_attest hl_info_signed hl_info_sync_manager hl_info_time_sync hl_info_undefined_opcode_event hl_mem_args hl_mem_in hl_mem_out hl_open_stats_info hl_page_fault_info hl_pll_frequency_info hl_power_info hl_server_type hl_user_mapping hl_wait_cs_args hl_wait_cs_in hl_wait_cs_out
i915_drm.h _drm_i915_cmdbuffer _drm_i915_init _drm_i915_sarea drm_i915_batchbuffer drm_i915_engine_info drm_i915_gem_busy drm_i915_gem_caching drm_i915_gem_context_create drm_i915_gem_context_create_ext drm_i915_gem_context_create_ext_setparam drm_i915_gem_context_destroy drm_i915_gem_context_param drm_i915_gem_context_param_sseu drm_i915_gem_create drm_i915_gem_create_ext drm_i915_gem_create_ext_memory_regions drm_i915_gem_create_ext_protected_content drm_i915_gem_create_ext_set_pat drm_i915_gem_engine_class drm_i915_gem_exec_fence drm_i915_gem_exec_object drm_i915_gem_exec_object2 drm_i915_gem_execbuffer drm_i915_gem_execbuffer2 drm_i915_gem_execbuffer_ext_timeline_fences drm_i915_gem_get_aperture drm_i915_gem_get_tiling drm_i915_gem_init drm_i915_gem_madvise drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_gem_mmap drm_i915_gem_mmap_gtt drm_i915_gem_mmap_offset drm_i915_gem_pin drm_i915_gem_pread drm_i915_gem_pwrite drm_i915_gem_relocation_entry drm_i915_gem_set_domain drm_i915_gem_set_tiling drm_i915_gem_sw_finish drm_i915_gem_unpin drm_i915_gem_userptr drm_i915_gem_vm_control drm_i915_gem_wait drm_i915_get_pipe_from_crtc_id drm_i915_getparam drm_i915_hws_addr drm_i915_irq_emit drm_i915_irq_wait drm_i915_mem_alloc drm_i915_mem_destroy_heap drm_i915_mem_free drm_i915_mem_init_heap drm_i915_memory_region_info drm_i915_oa_format drm_i915_perf_oa_config drm_i915_perf_open_param drm_i915_perf_property_id drm_i915_perf_record_header drm_i915_perf_record_type drm_i915_pmu_engine_sample drm_i915_query drm_i915_query_engine_info drm_i915_query_guc_submission_version drm_i915_query_item drm_i915_query_memory_regions drm_i915_query_perf_config drm_i915_query_topology_info drm_i915_reg_read drm_i915_reset_stats drm_i915_setparam drm_i915_vblank_pipe drm_i915_vblank_swap drm_intel_overlay_attrs drm_intel_overlay_put_image drm_intel_sprite_colorkey i915_context_engines_bond i915_context_engines_load_balance i915_context_engines_parallel_submit i915_context_param_engines i915_engine_class_instance i915_mocs_table_index i915_user_extension
ivpu_accel.h drm_ivpu_bo_create drm_ivpu_bo_info drm_ivpu_bo_wait drm_ivpu_param drm_ivpu_submit
lima_drm.h drm_lima_ctx_create drm_lima_ctx_free drm_lima_gem_create drm_lima_gem_info drm_lima_gem_submit drm_lima_gem_submit_bo drm_lima_gem_wait drm_lima_get_param drm_lima_gp_frame drm_lima_m400_pp_frame drm_lima_m450_pp_frame drm_lima_param drm_lima_param_gpu_id
msm_drm.h drm_msm_gem_cpu_fini drm_msm_gem_cpu_prep drm_msm_gem_info drm_msm_gem_madvise drm_msm_gem_new drm_msm_gem_submit drm_msm_gem_submit_bo drm_msm_gem_submit_cmd drm_msm_gem_submit_reloc drm_msm_gem_submit_syncobj drm_msm_param drm_msm_submitqueue drm_msm_submitqueue_query drm_msm_timespec drm_msm_wait_fence
nouveau_drm.h drm_nouveau_channel_alloc drm_nouveau_channel_free drm_nouveau_exec drm_nouveau_exec_push drm_nouveau_gem_cpu_fini drm_nouveau_gem_cpu_prep drm_nouveau_gem_info drm_nouveau_gem_new drm_nouveau_gem_pushbuf drm_nouveau_gem_pushbuf_bo drm_nouveau_gem_pushbuf_bo_presumed drm_nouveau_gem_pushbuf_push drm_nouveau_gem_pushbuf_reloc drm_nouveau_getparam drm_nouveau_svm_bind drm_nouveau_svm_init drm_nouveau_sync drm_nouveau_vm_bind drm_nouveau_vm_bind_op drm_nouveau_vm_init
omap_drm.h drm_omap_gem_cpu_fini drm_omap_gem_cpu_prep drm_omap_gem_info drm_omap_gem_new drm_omap_param omap_gem_op omap_gem_size
panfrost_drm.h drm_panfrost_create_bo drm_panfrost_get_bo_offset drm_panfrost_get_param drm_panfrost_madvise drm_panfrost_mmap_bo drm_panfrost_param drm_panfrost_perfcnt_dump drm_panfrost_perfcnt_enable drm_panfrost_submit drm_panfrost_wait_bo panfrost_dump_object_header panfrost_dump_registers
pvr_drm.h drm_pvr_create_hwrt_geom_data_args drm_pvr_create_hwrt_rt_data_args drm_pvr_ctx_priority drm_pvr_ctx_type drm_pvr_dev_query drm_pvr_dev_query_enhancements drm_pvr_dev_query_gpu_info drm_pvr_dev_query_heap_info drm_pvr_dev_query_quirks drm_pvr_dev_query_runtime_info drm_pvr_dev_query_static_data_areas drm_pvr_heap drm_pvr_heap_id drm_pvr_hwrt_data_ref drm_pvr_ioctl_create_bo_args drm_pvr_ioctl_create_context_args drm_pvr_ioctl_create_free_list_args drm_pvr_ioctl_create_hwrt_dataset_args drm_pvr_ioctl_create_vm_context_args drm_pvr_ioctl_destroy_context_args drm_pvr_ioctl_destroy_free_list_args drm_pvr_ioctl_destroy_hwrt_dataset_args drm_pvr_ioctl_destroy_vm_context_args drm_pvr_ioctl_dev_query_args drm_pvr_ioctl_get_bo_mmap_offset_args drm_pvr_ioctl_submit_jobs_args drm_pvr_ioctl_vm_map_args drm_pvr_ioctl_vm_unmap_args drm_pvr_job drm_pvr_job_type drm_pvr_obj_array drm_pvr_static_data_area drm_pvr_static_data_area_usage drm_pvr_sync_op
qaic_accel.h qaic_attach_slice qaic_attach_slice_entry qaic_attach_slice_hdr qaic_create_bo qaic_detach_slice qaic_execute qaic_execute_entry qaic_execute_hdr qaic_manage_msg qaic_manage_trans_activate_from_dev qaic_manage_trans_activate_to_dev qaic_manage_trans_deactivate qaic_manage_trans_dma_xfer qaic_manage_trans_hdr qaic_manage_trans_passthrough qaic_manage_trans_status_from_dev qaic_manage_trans_status_to_dev qaic_mmap_bo qaic_partial_execute_entry qaic_perf_stats qaic_perf_stats_entry qaic_perf_stats_hdr qaic_sem qaic_wait
qxl_drm.h drm_qxl_alloc drm_qxl_alloc_surf drm_qxl_clientcap drm_qxl_command drm_qxl_execbuffer drm_qxl_getparam drm_qxl_map drm_qxl_reloc drm_qxl_update_area
radeon_drm.h drm_radeon_clear drm_radeon_clear_rect drm_radeon_cmd_buffer drm_radeon_cp_stop drm_radeon_cs drm_radeon_cs_chunk drm_radeon_cs_reloc drm_radeon_fullscreen drm_radeon_gem_busy drm_radeon_gem_create drm_radeon_gem_get_tiling drm_radeon_gem_info drm_radeon_gem_mmap drm_radeon_gem_op drm_radeon_gem_pread drm_radeon_gem_pwrite drm_radeon_gem_set_domain drm_radeon_gem_set_tiling drm_radeon_gem_userptr drm_radeon_gem_va drm_radeon_gem_wait_idle drm_radeon_getparam drm_radeon_indices drm_radeon_indirect drm_radeon_info drm_radeon_init drm_radeon_irq_emit drm_radeon_irq_wait drm_radeon_mem_alloc drm_radeon_mem_free drm_radeon_mem_init_heap drm_radeon_setparam drm_radeon_stipple drm_radeon_surface_alloc drm_radeon_surface_free drm_radeon_tex_image drm_radeon_texture drm_radeon_vertex drm_radeon_vertex2
tegra_drm.h drm_tegra_channel_close drm_tegra_channel_map drm_tegra_channel_open drm_tegra_channel_submit drm_tegra_channel_unmap drm_tegra_close_channel drm_tegra_cmdbuf drm_tegra_gem_create drm_tegra_gem_get_flags drm_tegra_gem_get_tiling drm_tegra_gem_mmap drm_tegra_gem_set_flags drm_tegra_gem_set_tiling drm_tegra_get_syncpt drm_tegra_get_syncpt_base drm_tegra_open_channel drm_tegra_reloc drm_tegra_submit drm_tegra_submit_buf drm_tegra_submit_cmd drm_tegra_submit_cmd_gather_uptr drm_tegra_submit_cmd_wait_syncpt drm_tegra_submit_syncpt drm_tegra_syncpoint_allocate drm_tegra_syncpoint_free drm_tegra_syncpoint_wait drm_tegra_syncpt drm_tegra_syncpt_incr drm_tegra_syncpt_read drm_tegra_syncpt_wait drm_tegra_waitchk
v3d_drm.h drm_v3d_copy_performance_query drm_v3d_copy_timestamp_query drm_v3d_create_bo drm_v3d_extension drm_v3d_get_bo_offset drm_v3d_get_param drm_v3d_indirect_csd drm_v3d_mmap_bo drm_v3d_multi_sync drm_v3d_param drm_v3d_perfmon_create drm_v3d_perfmon_destroy drm_v3d_perfmon_get_values drm_v3d_reset_performance_query drm_v3d_reset_timestamp_query drm_v3d_sem drm_v3d_submit_cl drm_v3d_submit_cpu drm_v3d_submit_csd drm_v3d_submit_tfu drm_v3d_timestamp_query drm_v3d_wait_bo v3d_queue
vc4_drm.h drm_vc4_create_bo drm_vc4_create_shader_bo drm_vc4_gem_madvise drm_vc4_get_hang_state drm_vc4_get_hang_state_bo drm_vc4_get_param drm_vc4_get_tiling drm_vc4_label_bo drm_vc4_mmap_bo drm_vc4_perfmon_create drm_vc4_perfmon_destroy drm_vc4_perfmon_get_values drm_vc4_set_tiling drm_vc4_submit_cl drm_vc4_submit_rcl_surface drm_vc4_wait_bo drm_vc4_wait_seqno
vgem_drm.h drm_vgem_fence_attach drm_vgem_fence_signal
virtgpu_drm.h drm_virtgpu_3d_box drm_virtgpu_3d_transfer_from_host drm_virtgpu_3d_transfer_to_host drm_virtgpu_3d_wait drm_virtgpu_context_init drm_virtgpu_context_set_param drm_virtgpu_execbuffer drm_virtgpu_execbuffer_syncobj drm_virtgpu_get_caps drm_virtgpu_getparam drm_virtgpu_map drm_virtgpu_resource_create drm_virtgpu_resource_create_blob drm_virtgpu_resource_info
vmwgfx_drm.h drm_vmw_alloc_bo_arg drm_vmw_alloc_bo_req drm_vmw_bo_rep drm_vmw_context_arg drm_vmw_control_stream_arg drm_vmw_cursor_bypass_arg drm_vmw_event_fence drm_vmw_execbuf_arg drm_vmw_extended_context drm_vmw_extended_context_arg drm_vmw_fence_arg drm_vmw_fence_event_arg drm_vmw_fence_rep drm_vmw_fence_signaled_arg drm_vmw_fence_wait_arg drm_vmw_gb_surface_create_arg drm_vmw_gb_surface_create_ext_arg drm_vmw_gb_surface_create_ext_req drm_vmw_gb_surface_create_rep drm_vmw_gb_surface_create_req drm_vmw_gb_surface_ref_ext_rep drm_vmw_gb_surface_ref_rep drm_vmw_gb_surface_reference_arg drm_vmw_gb_surface_reference_ext_arg drm_vmw_get_3d_cap_arg drm_vmw_getparam_arg drm_vmw_handle_close_arg drm_vmw_handle_type drm_vmw_mksstat_add_arg drm_vmw_mksstat_remove_arg drm_vmw_msg_arg drm_vmw_present_arg drm_vmw_present_readback_arg drm_vmw_rect drm_vmw_shader_arg drm_vmw_shader_create_arg drm_vmw_shader_type drm_vmw_size drm_vmw_stream_arg drm_vmw_surface_arg drm_vmw_surface_create_arg drm_vmw_surface_create_req drm_vmw_surface_flags drm_vmw_surface_reference_arg drm_vmw_surface_version drm_vmw_synccpu_arg drm_vmw_synccpu_flags drm_vmw_synccpu_op drm_vmw_update_layout_arg
xe_drm.h drm_xe_device_query drm_xe_engine drm_xe_engine_class_instance drm_xe_exec drm_xe_exec_queue_create drm_xe_exec_queue_destroy drm_xe_exec_queue_get_property drm_xe_ext_set_property drm_xe_gem_create drm_xe_gem_mmap_offset drm_xe_gt drm_xe_mem_region drm_xe_memory_class drm_xe_query_config drm_xe_query_engine_cycles drm_xe_query_engines drm_xe_query_gt_list drm_xe_query_mem_regions drm_xe_query_topology_mask drm_xe_query_uc_fw_version drm_xe_sync drm_xe_user_extension drm_xe_vm_bind drm_xe_vm_bind_op drm_xe_vm_create drm_xe_vm_destroy drm_xe_wait_user_fence

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