1//! `x86` and `x86_64` intrinsics.
2
3#[allow(unused_imports)]
4use crate::marker::Sized;
5use crate::{intrinsics, mem::transmute};
6
7#[macro_use]
8mod macros;
9
10types! {
11 /// 128-bit wide integer vector type, x86-specific
12 ///
13 /// This type is the same as the `__m128i` type defined by Intel,
14 /// representing a 128-bit SIMD register. Usage of this type typically
15 /// corresponds to the `sse` and up target features for x86/x86_64.
16 ///
17 /// Internally this type may be viewed as:
18 ///
19 /// * `i8x16` - sixteen `i8` variables packed together
20 /// * `i16x8` - eight `i16` variables packed together
21 /// * `i32x4` - four `i32` variables packed together
22 /// * `i64x2` - two `i64` variables packed together
23 ///
24 /// (as well as unsigned versions). Each intrinsic may interpret the
25 /// internal bits differently, check the documentation of the intrinsic
26 /// to see how it's being used.
27 ///
28 /// Note that this means that an instance of `__m128i` typically just means
29 /// a "bag of bits" which is left up to interpretation at the point of use.
30 ///
31 /// Most intrinsics using `__m128i` are prefixed with `_mm_` and the
32 /// integer types tend to correspond to suffixes like "epi8" or "epi32".
33 ///
34 /// # Examples
35 ///
36 /// ```
37 /// #[cfg(target_arch = "x86")]
38 /// use std::arch::x86::*;
39 /// #[cfg(target_arch = "x86_64")]
40 /// use std::arch::x86_64::*;
41 ///
42 /// # fn main() {
43 /// # #[target_feature(enable = "sse2")]
44 /// # unsafe fn foo() {
45 /// let all_bytes_zero = _mm_setzero_si128();
46 /// let all_bytes_one = _mm_set1_epi8(1);
47 /// let four_i32 = _mm_set_epi32(1, 2, 3, 4);
48 /// # }
49 /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } }
50 /// # }
51 /// ```
52 #[stable(feature = "simd_x86", since = "1.27.0")]
53 pub struct __m128i(i64, i64);
54
55 /// 128-bit wide set of four `f32` types, x86-specific
56 ///
57 /// This type is the same as the `__m128` type defined by Intel,
58 /// representing a 128-bit SIMD register which internally is consisted of
59 /// four packed `f32` instances. Usage of this type typically corresponds
60 /// to the `sse` and up target features for x86/x86_64.
61 ///
62 /// Note that unlike `__m128i`, the integer version of the 128-bit
63 /// registers, this `__m128` type has *one* interpretation. Each instance
64 /// of `__m128` always corresponds to `f32x4`, or four `f32` types packed
65 /// together.
66 ///
67 /// Most intrinsics using `__m128` are prefixed with `_mm_` and are
68 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
69 /// "pd" which is used for `__m128d`.
70 ///
71 /// # Examples
72 ///
73 /// ```
74 /// #[cfg(target_arch = "x86")]
75 /// use std::arch::x86::*;
76 /// #[cfg(target_arch = "x86_64")]
77 /// use std::arch::x86_64::*;
78 ///
79 /// # fn main() {
80 /// # #[target_feature(enable = "sse")]
81 /// # unsafe fn foo() {
82 /// let four_zeros = _mm_setzero_ps();
83 /// let four_ones = _mm_set1_ps(1.0);
84 /// let four_floats = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
85 /// # }
86 /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
87 /// # }
88 /// ```
89 #[stable(feature = "simd_x86", since = "1.27.0")]
90 pub struct __m128(f32, f32, f32, f32);
91
92 /// 128-bit wide set of two `f64` types, x86-specific
93 ///
94 /// This type is the same as the `__m128d` type defined by Intel,
95 /// representing a 128-bit SIMD register which internally is consisted of
96 /// two packed `f64` instances. Usage of this type typically corresponds
97 /// to the `sse` and up target features for x86/x86_64.
98 ///
99 /// Note that unlike `__m128i`, the integer version of the 128-bit
100 /// registers, this `__m128d` type has *one* interpretation. Each instance
101 /// of `__m128d` always corresponds to `f64x2`, or two `f64` types packed
102 /// together.
103 ///
104 /// Most intrinsics using `__m128d` are prefixed with `_mm_` and are
105 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
106 /// "ps" which is used for `__m128`.
107 ///
108 /// # Examples
109 ///
110 /// ```
111 /// #[cfg(target_arch = "x86")]
112 /// use std::arch::x86::*;
113 /// #[cfg(target_arch = "x86_64")]
114 /// use std::arch::x86_64::*;
115 ///
116 /// # fn main() {
117 /// # #[target_feature(enable = "sse")]
118 /// # unsafe fn foo() {
119 /// let two_zeros = _mm_setzero_pd();
120 /// let two_ones = _mm_set1_pd(1.0);
121 /// let two_floats = _mm_set_pd(1.0, 2.0);
122 /// # }
123 /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
124 /// # }
125 /// ```
126 #[stable(feature = "simd_x86", since = "1.27.0")]
127 pub struct __m128d(f64, f64);
128
129 /// 256-bit wide integer vector type, x86-specific
130 ///
131 /// This type is the same as the `__m256i` type defined by Intel,
132 /// representing a 256-bit SIMD register. Usage of this type typically
133 /// corresponds to the `avx` and up target features for x86/x86_64.
134 ///
135 /// Internally this type may be viewed as:
136 ///
137 /// * `i8x32` - thirty two `i8` variables packed together
138 /// * `i16x16` - sixteen `i16` variables packed together
139 /// * `i32x8` - eight `i32` variables packed together
140 /// * `i64x4` - four `i64` variables packed together
141 ///
142 /// (as well as unsigned versions). Each intrinsic may interpret the
143 /// internal bits differently, check the documentation of the intrinsic
144 /// to see how it's being used.
145 ///
146 /// Note that this means that an instance of `__m256i` typically just means
147 /// a "bag of bits" which is left up to interpretation at the point of use.
148 ///
149 /// # Examples
150 ///
151 /// ```
152 /// #[cfg(target_arch = "x86")]
153 /// use std::arch::x86::*;
154 /// #[cfg(target_arch = "x86_64")]
155 /// use std::arch::x86_64::*;
156 ///
157 /// # fn main() {
158 /// # #[target_feature(enable = "avx")]
159 /// # unsafe fn foo() {
160 /// let all_bytes_zero = _mm256_setzero_si256();
161 /// let all_bytes_one = _mm256_set1_epi8(1);
162 /// let eight_i32 = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
163 /// # }
164 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
165 /// # }
166 /// ```
167 #[stable(feature = "simd_x86", since = "1.27.0")]
168 pub struct __m256i(i64, i64, i64, i64);
169
170 /// 256-bit wide set of eight `f32` types, x86-specific
171 ///
172 /// This type is the same as the `__m256` type defined by Intel,
173 /// representing a 256-bit SIMD register which internally is consisted of
174 /// eight packed `f32` instances. Usage of this type typically corresponds
175 /// to the `avx` and up target features for x86/x86_64.
176 ///
177 /// Note that unlike `__m256i`, the integer version of the 256-bit
178 /// registers, this `__m256` type has *one* interpretation. Each instance
179 /// of `__m256` always corresponds to `f32x8`, or eight `f32` types packed
180 /// together.
181 ///
182 /// Most intrinsics using `__m256` are prefixed with `_mm256_` and are
183 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
184 /// "pd" which is used for `__m256d`.
185 ///
186 /// # Examples
187 ///
188 /// ```
189 /// #[cfg(target_arch = "x86")]
190 /// use std::arch::x86::*;
191 /// #[cfg(target_arch = "x86_64")]
192 /// use std::arch::x86_64::*;
193 ///
194 /// # fn main() {
195 /// # #[target_feature(enable = "avx")]
196 /// # unsafe fn foo() {
197 /// let eight_zeros = _mm256_setzero_ps();
198 /// let eight_ones = _mm256_set1_ps(1.0);
199 /// let eight_floats = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
200 /// # }
201 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
202 /// # }
203 /// ```
204 #[stable(feature = "simd_x86", since = "1.27.0")]
205 pub struct __m256(f32, f32, f32, f32, f32, f32, f32, f32);
206
207 /// 256-bit wide set of four `f64` types, x86-specific
208 ///
209 /// This type is the same as the `__m256d` type defined by Intel,
210 /// representing a 256-bit SIMD register which internally is consisted of
211 /// four packed `f64` instances. Usage of this type typically corresponds
212 /// to the `avx` and up target features for x86/x86_64.
213 ///
214 /// Note that unlike `__m256i`, the integer version of the 256-bit
215 /// registers, this `__m256d` type has *one* interpretation. Each instance
216 /// of `__m256d` always corresponds to `f64x4`, or four `f64` types packed
217 /// together.
218 ///
219 /// Most intrinsics using `__m256d` are prefixed with `_mm256_` and are
220 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
221 /// "ps" which is used for `__m256`.
222 ///
223 /// # Examples
224 ///
225 /// ```
226 /// #[cfg(target_arch = "x86")]
227 /// use std::arch::x86::*;
228 /// #[cfg(target_arch = "x86_64")]
229 /// use std::arch::x86_64::*;
230 ///
231 /// # fn main() {
232 /// # #[target_feature(enable = "avx")]
233 /// # unsafe fn foo() {
234 /// let four_zeros = _mm256_setzero_pd();
235 /// let four_ones = _mm256_set1_pd(1.0);
236 /// let four_floats = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
237 /// # }
238 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
239 /// # }
240 /// ```
241 #[stable(feature = "simd_x86", since = "1.27.0")]
242 pub struct __m256d(f64, f64, f64, f64);
243
244 /// 512-bit wide integer vector type, x86-specific
245 ///
246 /// This type is the same as the `__m512i` type defined by Intel,
247 /// representing a 512-bit SIMD register. Usage of this type typically
248 /// corresponds to the `avx512*` and up target features for x86/x86_64.
249 ///
250 /// Internally this type may be viewed as:
251 ///
252 /// * `i8x64` - sixty-four `i8` variables packed together
253 /// * `i16x32` - thirty-two `i16` variables packed together
254 /// * `i32x16` - sixteen `i32` variables packed together
255 /// * `i64x8` - eight `i64` variables packed together
256 ///
257 /// (as well as unsigned versions). Each intrinsic may interpret the
258 /// internal bits differently, check the documentation of the intrinsic
259 /// to see how it's being used.
260 ///
261 /// Note that this means that an instance of `__m512i` typically just means
262 /// a "bag of bits" which is left up to interpretation at the point of use.
263 #[stable(feature = "simd_avx512_types", since = "1.72.0")]
264 pub struct __m512i(i64, i64, i64, i64, i64, i64, i64, i64);
265
266 /// 512-bit wide set of sixteen `f32` types, x86-specific
267 ///
268 /// This type is the same as the `__m512` type defined by Intel,
269 /// representing a 512-bit SIMD register which internally is consisted of
270 /// eight packed `f32` instances. Usage of this type typically corresponds
271 /// to the `avx512*` and up target features for x86/x86_64.
272 ///
273 /// Note that unlike `__m512i`, the integer version of the 512-bit
274 /// registers, this `__m512` type has *one* interpretation. Each instance
275 /// of `__m512` always corresponds to `f32x16`, or sixteen `f32` types
276 /// packed together.
277 ///
278 /// Most intrinsics using `__m512` are prefixed with `_mm512_` and are
279 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
280 /// "pd" which is used for `__m512d`.
281 #[stable(feature = "simd_avx512_types", since = "1.72.0")]
282 pub struct __m512(
283 f32, f32, f32, f32, f32, f32, f32, f32,
284 f32, f32, f32, f32, f32, f32, f32, f32,
285 );
286
287 /// 512-bit wide set of eight `f64` types, x86-specific
288 ///
289 /// This type is the same as the `__m512d` type defined by Intel,
290 /// representing a 512-bit SIMD register which internally is consisted of
291 /// eight packed `f64` instances. Usage of this type typically corresponds
292 /// to the `avx` and up target features for x86/x86_64.
293 ///
294 /// Note that unlike `__m512i`, the integer version of the 512-bit
295 /// registers, this `__m512d` type has *one* interpretation. Each instance
296 /// of `__m512d` always corresponds to `f64x4`, or eight `f64` types packed
297 /// together.
298 ///
299 /// Most intrinsics using `__m512d` are prefixed with `_mm512_` and are
300 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
301 /// "ps" which is used for `__m512`.
302 #[stable(feature = "simd_avx512_types", since = "1.72.0")]
303 pub struct __m512d(f64, f64, f64, f64, f64, f64, f64, f64);
304
305 /// 128-bit wide set of eight `u16` types, x86-specific
306 ///
307 /// This type is representing a 128-bit SIMD register which internally is consisted of
308 /// eight packed `u16` instances. Its purpose is for bf16 related intrinsic
309 /// implementations.
310 #[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
311 pub struct __m128bh(u16, u16, u16, u16, u16, u16, u16, u16);
312
313 /// 256-bit wide set of 16 `u16` types, x86-specific
314 ///
315 /// This type is the same as the `__m256bh` type defined by Intel,
316 /// representing a 256-bit SIMD register which internally is consisted of
317 /// 16 packed `u16` instances. Its purpose is for bf16 related intrinsic
318 /// implementations.
319 #[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
320 pub struct __m256bh(
321 u16, u16, u16, u16, u16, u16, u16, u16,
322 u16, u16, u16, u16, u16, u16, u16, u16
323 );
324
325 /// 512-bit wide set of 32 `u16` types, x86-specific
326 ///
327 /// This type is the same as the `__m512bh` type defined by Intel,
328 /// representing a 512-bit SIMD register which internally is consisted of
329 /// 32 packed `u16` instances. Its purpose is for bf16 related intrinsic
330 /// implementations.
331 #[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
332 pub struct __m512bh(
333 u16, u16, u16, u16, u16, u16, u16, u16,
334 u16, u16, u16, u16, u16, u16, u16, u16,
335 u16, u16, u16, u16, u16, u16, u16, u16,
336 u16, u16, u16, u16, u16, u16, u16, u16
337 );
338}
339
340/// The `__mmask64` type used in AVX-512 intrinsics, a 64-bit integer
341#[allow(non_camel_case_types)]
342#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
343pub type __mmask64 = u64;
344
345/// The `__mmask32` type used in AVX-512 intrinsics, a 32-bit integer
346#[allow(non_camel_case_types)]
347#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
348pub type __mmask32 = u32;
349
350/// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer
351#[allow(non_camel_case_types)]
352#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
353pub type __mmask16 = u16;
354
355/// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer
356#[allow(non_camel_case_types)]
357#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
358pub type __mmask8 = u8;
359
360/// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics.
361#[allow(non_camel_case_types)]
362#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
363pub type _MM_CMPINT_ENUM = i32;
364
365/// The `MM_MANTISSA_NORM_ENUM` type used to specify mantissa normalized operations in AVX-512 intrinsics.
366#[allow(non_camel_case_types)]
367#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
368pub type _MM_MANTISSA_NORM_ENUM = i32;
369
370/// The `MM_MANTISSA_SIGN_ENUM` type used to specify mantissa signed operations in AVX-512 intrinsics.
371#[allow(non_camel_case_types)]
372#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
373pub type _MM_MANTISSA_SIGN_ENUM = i32;
374
375/// The `MM_PERM_ENUM` type used to specify shuffle operations in AVX-512 intrinsics.
376#[allow(non_camel_case_types)]
377#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
378pub type _MM_PERM_ENUM = i32;
379
380#[cfg(test)]
381mod test;
382#[cfg(test)]
383pub use self::test::*;
384
385#[allow(non_camel_case_types)]
386pub(crate) trait m128iExt: Sized {
387 fn as_m128i(self) -> __m128i;
388
389 #[inline]
390 fn as_u8x16(self) -> crate::core_arch::simd::u8x16 {
391 unsafe { transmute(self.as_m128i()) }
392 }
393
394 #[inline]
395 fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
396 unsafe { transmute(self.as_m128i()) }
397 }
398
399 #[inline]
400 fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
401 unsafe { transmute(self.as_m128i()) }
402 }
403
404 #[inline]
405 fn as_u64x2(self) -> crate::core_arch::simd::u64x2 {
406 unsafe { transmute(self.as_m128i()) }
407 }
408
409 #[inline]
410 fn as_i8x16(self) -> crate::core_arch::simd::i8x16 {
411 unsafe { transmute(self.as_m128i()) }
412 }
413
414 #[inline]
415 fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
416 unsafe { transmute(self.as_m128i()) }
417 }
418
419 #[inline]
420 fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
421 unsafe { transmute(self.as_m128i()) }
422 }
423
424 #[inline]
425 fn as_i64x2(self) -> crate::core_arch::simd::i64x2 {
426 unsafe { transmute(self.as_m128i()) }
427 }
428}
429
430impl m128iExt for __m128i {
431 #[inline]
432 fn as_m128i(self) -> Self {
433 self
434 }
435}
436
437#[allow(non_camel_case_types)]
438pub(crate) trait m256iExt: Sized {
439 fn as_m256i(self) -> __m256i;
440
441 #[inline]
442 fn as_u8x32(self) -> crate::core_arch::simd::u8x32 {
443 unsafe { transmute(self.as_m256i()) }
444 }
445
446 #[inline]
447 fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
448 unsafe { transmute(self.as_m256i()) }
449 }
450
451 #[inline]
452 fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
453 unsafe { transmute(self.as_m256i()) }
454 }
455
456 #[inline]
457 fn as_u64x4(self) -> crate::core_arch::simd::u64x4 {
458 unsafe { transmute(self.as_m256i()) }
459 }
460
461 #[inline]
462 fn as_i8x32(self) -> crate::core_arch::simd::i8x32 {
463 unsafe { transmute(self.as_m256i()) }
464 }
465
466 #[inline]
467 fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
468 unsafe { transmute(self.as_m256i()) }
469 }
470
471 #[inline]
472 fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
473 unsafe { transmute(self.as_m256i()) }
474 }
475
476 #[inline]
477 fn as_i64x4(self) -> crate::core_arch::simd::i64x4 {
478 unsafe { transmute(self.as_m256i()) }
479 }
480}
481
482impl m256iExt for __m256i {
483 #[inline]
484 fn as_m256i(self) -> Self {
485 self
486 }
487}
488
489#[allow(non_camel_case_types)]
490pub(crate) trait m128Ext: Sized {
491 fn as_m128(self) -> __m128;
492
493 #[inline]
494 fn as_f32x4(self) -> crate::core_arch::simd::f32x4 {
495 unsafe { transmute(self.as_m128()) }
496 }
497}
498
499impl m128Ext for __m128 {
500 #[inline]
501 fn as_m128(self) -> Self {
502 self
503 }
504}
505
506#[allow(non_camel_case_types)]
507pub(crate) trait m128dExt: Sized {
508 fn as_m128d(self) -> __m128d;
509
510 #[inline]
511 fn as_f64x2(self) -> crate::core_arch::simd::f64x2 {
512 unsafe { transmute(self.as_m128d()) }
513 }
514}
515
516impl m128dExt for __m128d {
517 #[inline]
518 fn as_m128d(self) -> Self {
519 self
520 }
521}
522
523#[allow(non_camel_case_types)]
524pub(crate) trait m256Ext: Sized {
525 fn as_m256(self) -> __m256;
526
527 #[inline]
528 fn as_f32x8(self) -> crate::core_arch::simd::f32x8 {
529 unsafe { transmute(self.as_m256()) }
530 }
531}
532
533impl m256Ext for __m256 {
534 #[inline]
535 fn as_m256(self) -> Self {
536 self
537 }
538}
539
540#[allow(non_camel_case_types)]
541pub(crate) trait m256dExt: Sized {
542 fn as_m256d(self) -> __m256d;
543
544 #[inline]
545 fn as_f64x4(self) -> crate::core_arch::simd::f64x4 {
546 unsafe { transmute(self.as_m256d()) }
547 }
548}
549
550impl m256dExt for __m256d {
551 #[inline]
552 fn as_m256d(self) -> Self {
553 self
554 }
555}
556
557#[allow(non_camel_case_types)]
558pub(crate) trait m512iExt: Sized {
559 fn as_m512i(self) -> __m512i;
560
561 #[inline]
562 fn as_u8x64(self) -> crate::core_arch::simd::u8x64 {
563 unsafe { transmute(self.as_m512i()) }
564 }
565
566 #[inline]
567 fn as_i8x64(self) -> crate::core_arch::simd::i8x64 {
568 unsafe { transmute(self.as_m512i()) }
569 }
570
571 #[inline]
572 fn as_u16x32(self) -> crate::core_arch::simd::u16x32 {
573 unsafe { transmute(self.as_m512i()) }
574 }
575
576 #[inline]
577 fn as_i16x32(self) -> crate::core_arch::simd::i16x32 {
578 unsafe { transmute(self.as_m512i()) }
579 }
580
581 #[inline]
582 fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
583 unsafe { transmute(self.as_m512i()) }
584 }
585
586 #[inline]
587 fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
588 unsafe { transmute(self.as_m512i()) }
589 }
590
591 #[inline]
592 fn as_u64x8(self) -> crate::core_arch::simd::u64x8 {
593 unsafe { transmute(self.as_m512i()) }
594 }
595
596 #[inline]
597 fn as_i64x8(self) -> crate::core_arch::simd::i64x8 {
598 unsafe { transmute(self.as_m512i()) }
599 }
600}
601
602impl m512iExt for __m512i {
603 #[inline]
604 fn as_m512i(self) -> Self {
605 self
606 }
607}
608
609#[allow(non_camel_case_types)]
610pub(crate) trait m512Ext: Sized {
611 fn as_m512(self) -> __m512;
612
613 #[inline]
614 fn as_f32x16(self) -> crate::core_arch::simd::f32x16 {
615 unsafe { transmute(self.as_m512()) }
616 }
617}
618
619impl m512Ext for __m512 {
620 #[inline]
621 fn as_m512(self) -> Self {
622 self
623 }
624}
625
626#[allow(non_camel_case_types)]
627pub(crate) trait m512dExt: Sized {
628 fn as_m512d(self) -> __m512d;
629
630 #[inline]
631 fn as_f64x8(self) -> crate::core_arch::simd::f64x8 {
632 unsafe { transmute(self.as_m512d()) }
633 }
634}
635
636impl m512dExt for __m512d {
637 #[inline]
638 fn as_m512d(self) -> Self {
639 self
640 }
641}
642
643#[allow(non_camel_case_types)]
644pub(crate) trait m128bhExt: Sized {
645 fn as_m128bh(self) -> __m128bh;
646
647 #[inline]
648 fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
649 unsafe { transmute(self.as_m128bh()) }
650 }
651
652 #[inline]
653 fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
654 unsafe { transmute(self.as_m128bh()) }
655 }
656
657 #[inline]
658 fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
659 unsafe { transmute(self.as_m128bh()) }
660 }
661
662 #[inline]
663 fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
664 unsafe { transmute(self.as_m128bh()) }
665 }
666}
667
668impl m128bhExt for __m128bh {
669 #[inline]
670 fn as_m128bh(self) -> Self {
671 self
672 }
673}
674
675#[allow(non_camel_case_types)]
676pub(crate) trait m256bhExt: Sized {
677 fn as_m256bh(self) -> __m256bh;
678
679 #[inline]
680 fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
681 unsafe { transmute(self.as_m256bh()) }
682 }
683
684 #[inline]
685 fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
686 unsafe { transmute(self.as_m256bh()) }
687 }
688
689 #[inline]
690 fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
691 unsafe { transmute(self.as_m256bh()) }
692 }
693
694 #[inline]
695 fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
696 unsafe { transmute(self.as_m256bh()) }
697 }
698}
699
700impl m256bhExt for __m256bh {
701 #[inline]
702 fn as_m256bh(self) -> Self {
703 self
704 }
705}
706
707#[allow(non_camel_case_types)]
708pub(crate) trait m512bhExt: Sized {
709 fn as_m512bh(self) -> __m512bh;
710
711 #[inline]
712 fn as_u16x32(self) -> crate::core_arch::simd::u16x32 {
713 unsafe { transmute(self.as_m512bh()) }
714 }
715
716 #[inline]
717 fn as_i16x32(self) -> crate::core_arch::simd::i16x32 {
718 unsafe { transmute(self.as_m512bh()) }
719 }
720
721 #[inline]
722 fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
723 unsafe { transmute(self.as_m512bh()) }
724 }
725
726 #[inline]
727 fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
728 unsafe { transmute(self.as_m512bh()) }
729 }
730}
731
732impl m512bhExt for __m512bh {
733 #[inline]
734 fn as_m512bh(self) -> Self {
735 self
736 }
737}
738
739mod eflags;
740#[stable(feature = "simd_x86", since = "1.27.0")]
741pub use self::eflags::*;
742
743mod fxsr;
744#[stable(feature = "simd_x86", since = "1.27.0")]
745pub use self::fxsr::*;
746
747mod bswap;
748#[stable(feature = "simd_x86", since = "1.27.0")]
749pub use self::bswap::*;
750
751mod rdtsc;
752#[stable(feature = "simd_x86", since = "1.27.0")]
753pub use self::rdtsc::*;
754
755mod cpuid;
756#[stable(feature = "simd_x86", since = "1.27.0")]
757pub use self::cpuid::*;
758mod xsave;
759#[stable(feature = "simd_x86", since = "1.27.0")]
760pub use self::xsave::*;
761
762mod sse;
763#[stable(feature = "simd_x86", since = "1.27.0")]
764pub use self::sse::*;
765mod sse2;
766#[stable(feature = "simd_x86", since = "1.27.0")]
767pub use self::sse2::*;
768mod sse3;
769#[stable(feature = "simd_x86", since = "1.27.0")]
770pub use self::sse3::*;
771mod ssse3;
772#[stable(feature = "simd_x86", since = "1.27.0")]
773pub use self::ssse3::*;
774mod sse41;
775#[stable(feature = "simd_x86", since = "1.27.0")]
776pub use self::sse41::*;
777mod sse42;
778#[stable(feature = "simd_x86", since = "1.27.0")]
779pub use self::sse42::*;
780mod avx;
781#[stable(feature = "simd_x86", since = "1.27.0")]
782pub use self::avx::*;
783mod avx2;
784#[stable(feature = "simd_x86", since = "1.27.0")]
785pub use self::avx2::*;
786mod fma;
787#[stable(feature = "simd_x86", since = "1.27.0")]
788pub use self::fma::*;
789
790mod abm;
791#[stable(feature = "simd_x86", since = "1.27.0")]
792pub use self::abm::*;
793mod bmi1;
794#[stable(feature = "simd_x86", since = "1.27.0")]
795pub use self::bmi1::*;
796
797mod bmi2;
798#[stable(feature = "simd_x86", since = "1.27.0")]
799pub use self::bmi2::*;
800
801#[cfg(not(stdarch_intel_sde))]
802mod sse4a;
803#[cfg(not(stdarch_intel_sde))]
804#[stable(feature = "simd_x86", since = "1.27.0")]
805pub use self::sse4a::*;
806
807#[cfg(not(stdarch_intel_sde))]
808mod tbm;
809#[cfg(not(stdarch_intel_sde))]
810#[stable(feature = "simd_x86", since = "1.27.0")]
811pub use self::tbm::*;
812
813mod pclmulqdq;
814#[stable(feature = "simd_x86", since = "1.27.0")]
815pub use self::pclmulqdq::*;
816
817mod aes;
818#[stable(feature = "simd_x86", since = "1.27.0")]
819pub use self::aes::*;
820
821mod rdrand;
822#[stable(feature = "simd_x86", since = "1.27.0")]
823pub use self::rdrand::*;
824
825mod sha;
826#[stable(feature = "simd_x86", since = "1.27.0")]
827pub use self::sha::*;
828
829mod adx;
830#[stable(feature = "simd_x86_adx", since = "1.33.0")]
831pub use self::adx::*;
832
833#[cfg(test)]
834use stdarch_test::assert_instr;
835
836mod avx512f;
837#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
838pub use self::avx512f::*;
839
840mod avx512bw;
841#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
842pub use self::avx512bw::*;
843
844mod avx512cd;
845#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
846pub use self::avx512cd::*;
847
848mod avx512ifma;
849#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
850pub use self::avx512ifma::*;
851
852mod avx512vbmi;
853#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
854pub use self::avx512vbmi::*;
855
856mod avx512vbmi2;
857#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
858pub use self::avx512vbmi2::*;
859
860mod avx512vnni;
861#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
862pub use self::avx512vnni::*;
863
864mod avx512bitalg;
865#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
866pub use self::avx512bitalg::*;
867
868mod gfni;
869#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
870pub use self::gfni::*;
871
872mod avx512vpopcntdq;
873#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
874pub use self::avx512vpopcntdq::*;
875
876mod vaes;
877#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
878pub use self::vaes::*;
879
880mod vpclmulqdq;
881#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
882pub use self::vpclmulqdq::*;
883
884mod bt;
885#[stable(feature = "simd_x86_bittest", since = "1.55.0")]
886pub use self::bt::*;
887
888mod rtm;
889#[unstable(feature = "stdarch_x86_rtm", issue = "111138")]
890pub use self::rtm::*;
891
892mod f16c;
893#[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")]
894pub use self::f16c::*;
895
896mod avx512bf16;
897#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
898pub use self::avx512bf16::*;
899