| 1 | //! FXSR floating-point context fast save and restore. | 
| 2 |  | 
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| 3 | #[ cfg(test)] | 
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| 4 | use stdarch_test::assert_instr; | 
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| 5 |  | 
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| 6 | #[ allow(improper_ctypes)] | 
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| 7 | unsafe extern "C"{ | 
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| 8 | #[ link_name= "llvm.x86.fxsave64"] | 
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| 9 | unsafefn fxsave64(p: *mut u8); | 
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| 10 | #[ link_name= "llvm.x86.fxrstor64"] | 
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| 11 | unsafefn fxrstor64(p: *const u8); | 
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| 12 | } | 
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| 13 |  | 
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| 14 | /// Saves the `x87` FPU, `MMX` technology, `XMM`, and `MXCSR` registers to the | 
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| 15 | /// 512-byte-long 16-byte-aligned memory region `mem_addr`. | 
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| 16 | /// | 
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| 17 | /// A misaligned destination operand raises a general-protection (#GP) or an | 
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| 18 | /// alignment check exception (#AC). | 
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| 19 | /// | 
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| 20 | /// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor]. | 
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| 21 | /// | 
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| 22 | /// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html | 
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| 23 | /// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html | 
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| 24 | /// | 
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| 25 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_fxsave64) | 
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| 26 | #[ inline] | 
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| 27 | #[ target_feature(enable = "fxsr")] | 
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| 28 | #[ cfg_attr(test, assert_instr(fxsave64))] | 
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| 29 | #[ stable(feature = "simd_x86", since = "1.27.0")] | 
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| 30 | pub unsafe fn _fxsave64(mem_addr: *mut u8) { | 
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| 31 | fxsave64(mem_addr) | 
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| 32 | } | 
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| 33 |  | 
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| 34 | /// Restores the `XMM`, `MMX`, `MXCSR`, and `x87` FPU registers from the | 
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| 35 | /// 512-byte-long 16-byte-aligned memory region `mem_addr`. | 
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| 36 | /// | 
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| 37 | /// The contents of this memory region should have been written to by a | 
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| 38 | /// previous | 
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| 39 | /// `_fxsave` or `_fxsave64` intrinsic. | 
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| 40 | /// | 
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| 41 | /// A misaligned destination operand raises a general-protection (#GP) or an | 
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| 42 | /// alignment check exception (#AC). | 
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| 43 | /// | 
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| 44 | /// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor]. | 
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| 45 | /// | 
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| 46 | /// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html | 
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| 47 | /// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html | 
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| 48 | /// | 
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| 49 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_fxrstor64) | 
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| 50 | #[ inline] | 
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| 51 | #[ target_feature(enable = "fxsr")] | 
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| 52 | #[ cfg_attr(test, assert_instr(fxrstor64))] | 
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| 53 | #[ stable(feature = "simd_x86", since = "1.27.0")] | 
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| 54 | pub unsafe fn _fxrstor64(mem_addr: *const u8) { | 
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| 55 | fxrstor64(mem_addr) | 
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| 56 | } | 
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| 57 |  | 
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| 58 | #[ cfg(test)] | 
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| 59 | mod tests { | 
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| 60 | use crate::core_arch::x86_64::*; | 
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| 61 | use std::{cmp::PartialEq, fmt}; | 
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| 62 | use stdarch_test::simd_test; | 
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| 63 |  | 
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| 64 | #[ repr(align(16))] | 
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| 65 | struct FxsaveArea { | 
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| 66 | data: [u8; 512], // 512 bytes | 
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| 67 | } | 
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| 68 |  | 
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| 69 | impl FxsaveArea { | 
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| 70 | fn new() -> FxsaveArea { | 
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| 71 | FxsaveArea { data: [0; 512] } | 
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| 72 | } | 
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| 73 | fn ptr(&mut self) -> *mut u8 { | 
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| 74 | self.data.as_mut_ptr() | 
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| 75 | } | 
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| 76 | } | 
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| 77 |  | 
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| 78 | #[simd_test(enable = "fxsr")] | 
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| 79 | #[ cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri | 
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| 80 | unsafe fn test_fxsave64() { | 
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| 81 | let mut a = FxsaveArea::new(); | 
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| 82 | let mut b = FxsaveArea::new(); | 
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| 83 |  | 
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| 84 | fxsr::_fxsave64(a.ptr()); | 
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| 85 | fxsr::_fxrstor64(a.ptr()); | 
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| 86 | fxsr::_fxsave64(b.ptr()); | 
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| 87 | } | 
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| 88 | } | 
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| 89 |  | 
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