1//! Run-time feature detection on RISC-V.
2
3features! {
4 @TARGET: riscv;
5 @CFG: any(target_arch = "riscv32", target_arch = "riscv64");
6 @MACRO_NAME: is_riscv_feature_detected;
7 @MACRO_ATTRS:
8 /// A macro to test at *runtime* whether instruction sets are available on
9 /// RISC-V platforms.
10 ///
11 /// RISC-V standard defined the base sets and the extension sets.
12 /// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
13 /// must support one base set and/or multiple extension sets.
14 ///
15 /// Any RISC-V standard instruction sets can be in state of either ratified,
16 /// frozen or draft. The version and status of current standard instruction
17 /// sets can be checked out from preface section of the [ISA manual].
18 ///
19 /// Platform may define and support their own custom instruction sets with
20 /// ISA prefix X. These sets are highly platform specific and should be
21 /// detected with their own platform support crates.
22 ///
23 /// # Unprivileged Specification
24 ///
25 /// The supported ratified RISC-V instruction sets are as follows:
26 ///
27 /// * RV32E: `"rv32e"`
28 /// * RV32I: `"rv32i"`
29 /// * RV64I: `"rv64i"`
30 /// * A: `"a"`
31 /// * B: `"b"`
32 /// * Zba: `"zba"`
33 /// * Zbb: `"zbb"`
34 /// * Zbc: `"zbc"`
35 /// * Zbs: `"zbs"`
36 /// * C: `"c"`
37 /// * D: `"d"`
38 /// * F: `"f"`
39 /// * M: `"m"`
40 /// * Q: `"q"`
41 /// * V: `"v"`
42 /// * Zicntr: `"zicntr"`
43 /// * Zicsr: `"zicsr"`
44 /// * Zifencei: `"zifencei"`
45 /// * Zihintpause: `"zihintpause"`
46 /// * Zihpm: `"zihpm"`
47 /// * Zk: `"zk"`
48 /// * Zbkb: `"zbkb"`
49 /// * Zbkc: `"zbkc"`
50 /// * Zbkx: `"zbkx"`
51 /// * Zkn: `"zkn"`
52 /// * Zknd: `"zknd"`
53 /// * Zkne: `"zkne"`
54 /// * Zknh: `"zknh"`
55 /// * Zkr: `"zkr"`
56 /// * Zks: `"zks"`
57 /// * Zksed: `"zksed"`
58 /// * Zksh: `"zksh"`
59 /// * Zkt: `"zkt"`
60 ///
61 /// There's also bases and extensions marked as standard instruction set,
62 /// but they are in frozen or draft state. These instruction sets are also
63 /// reserved by this macro and can be detected in the future platforms.
64 ///
65 /// Frozen RISC-V instruction sets:
66 ///
67 /// * Zfh: `"zfh"`
68 /// * Zfhmin: `"zfhmin"`
69 /// * Zfinx: `"zfinx"`
70 /// * Zdinx: `"zdinx"`
71 /// * Zhinx: `"zhinx"`
72 /// * Zhinxmin: `"zhinxmin"`
73 /// * Ztso: `"ztso"`
74 ///
75 /// Draft RISC-V instruction sets:
76 ///
77 /// * RV128I: `"rv128i"`
78 /// * J: `"j"`
79 /// * P: `"p"`
80 /// * Zam: `"zam"`
81 ///
82 /// Defined by Privileged Specification:
83 ///
84 /// * Supervisor: `"s"`
85 /// * Svnapot: `"svnapot"`
86 /// * Svpbmt: `"svpbmt"`
87 /// * Svinval: `"svinval"`
88 /// * Hypervisor: `"h"`
89 ///
90 /// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
91 #[stable(feature = "riscv_ratified", since = "1.76.0")]
92 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
93 /// RV32I Base Integer Instruction Set
94 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
95 /// "Zifencei" Instruction-Fetch Fence
96 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
97 /// "Zihintpause" Pause Hint
98 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
99 /// RV64I Base Integer Instruction Set
100 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] m: "m";
101 /// "M" Standard Extension for Integer Multiplication and Division
102 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] a: "a";
103 /// "A" Standard Extension for Atomic Instructions
104 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
105 /// "Zicsr", Control and Status Register (CSR) Instructions
106 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
107 /// "Zicntr", Standard Extension for Base Counters and Timers
108 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
109 /// "Zihpm", Standard Extension for Hardware Performance Counters
110 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
111 /// "F" Standard Extension for Single-Precision Floating-Point
112 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
113 /// "D" Standard Extension for Double-Precision Floating-Point
114 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
115 /// "Q" Standard Extension for Quad-Precision Floating-Point
116 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] c: "c";
117 /// "C" Standard Extension for Compressed Instructions
118
119 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
120 /// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
121 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
122 /// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
123 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
124 /// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
125 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
126 /// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
127 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
128 /// "Ztso" Standard Extension for Total Store Ordering
129
130 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
131 /// RV32E Base Integer Instruction Set
132 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
133 /// RV128I Base Integer Instruction Set
134 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
135 /// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
136 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
137 /// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
138 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
139 /// "J" Standard Extension for Dynamically Translated Languages
140 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
141 /// "P" Standard Extension for Packed-SIMD Instructions
142 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
143 /// "V" Standard Extension for Vector Operations
144 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
145 /// "Zam" Standard Extension for Misaligned Atomics
146
147 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
148 /// Supervisor-Level ISA
149 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
150 /// "Svnapot" Standard Extension for NAPOT Translation Contiguity
151 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
152 /// "Svpbmt" Standard Extension for Page-Based Memory Types
153 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
154 /// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
155 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
156 /// Hypervisor Extension
157
158 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zba: "zba";
159 /// "Zba" Standard Extension for Address Generation Instructions
160 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbb: "zbb";
161 /// "Zbb" Standard Extension for Basic Bit-Manipulation
162 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbc: "zbc";
163 /// "Zbc" Standard Extension for Carry-less Multiplication
164 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbs: "zbs";
165 /// "Zbs" Standard Extension for Single-Bit instructions
166
167 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkb: "zbkb";
168 /// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
169 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkc: "zbkc";
170 /// "Zbkc" Standard Extension for Carry-less multiply instructions
171 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkx: "zbkx";
172 /// "Zbkx" Standard Extension for Crossbar permutation instructions
173 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zknd: "zknd";
174 /// "Zknd" Standard Extension for NIST Suite: AES Decryption
175 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkne: "zkne";
176 /// "Zkne" Standard Extension for NIST Suite: AES Encryption
177 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zknh: "zknh";
178 /// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
179 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zksed: "zksed";
180 /// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
181 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zksh: "zksh";
182 /// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
183 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkr: "zkr";
184 /// "Zkr" Standard Extension for Entropy Source Extension
185 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkn: "zkn";
186 /// "Zkn" Standard Extension for NIST Algorithm Suite
187 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zks: "zks";
188 /// "Zks" Standard Extension for ShangMi Algorithm Suite
189 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zk: "zk";
190 /// "Zk" Standard Extension for Standard scalar cryptography extension
191 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkt: "zkt";
192 /// "Zkt" Standard Extension for Data Independent Execution Latency
193}
194