1//! Run-time feature detection on RISC-V.
2
3features! {
4 @TARGET: riscv;
5 @CFG: any(target_arch = "riscv32", target_arch = "riscv64");
6 @MACRO_NAME: is_riscv_feature_detected;
7 @MACRO_ATTRS:
8 /// A macro to test at *runtime* whether instruction sets are available on
9 /// RISC-V platforms.
10 ///
11 /// RISC-V standard defined the base sets and the extension sets.
12 /// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
13 /// must support one base set and/or multiple extension sets.
14 ///
15 /// Any RISC-V standard instruction sets can be in state of either ratified,
16 /// frozen or draft. The version and status of current standard instruction
17 /// sets can be checked out from preface section of the [ISA manual].
18 ///
19 /// Platform may define and support their own custom instruction sets with
20 /// ISA prefix X. These sets are highly platform specific and should be
21 /// detected with their own platform support crates.
22 ///
23 /// [ISA manual]: https://riscv.org/specifications/ratified/
24 ///
25 /// # Platform-specific/agnostic Behavior and Availability
26 ///
27 /// Runtime detection depends on the platform-specific feature detection
28 /// facility and its availability per feature is
29 /// highly platform/version-specific.
30 ///
31 /// Still, a best-effort attempt is performed to enable subset/dependent
32 /// features if a superset feature is enabled regardless of the platform.
33 /// For instance, if the A extension (`"a"`) is enabled, its subsets (the
34 /// Zalrsc and Zaamo extensions; `"zalrsc"` and `"zaamo"`) are also enabled.
35 /// Likewise, if the F extension (`"f"`) is enabled, one of its dependencies
36 /// (the Zicsr extension `"zicsr"`) is also enabled.
37 ///
38 /// # Unprivileged Specification
39 ///
40 /// The supported ratified RISC-V instruction sets are as follows:
41 ///
42 /// * RV32E: `"rv32e"`
43 /// * RV32I: `"rv32i"`
44 /// * RV64I: `"rv64i"`
45 /// * A: `"a"`
46 /// * Zaamo: `"zaamo"`
47 /// * Zalrsc: `"zalrsc"`
48 /// * B: `"b"`
49 /// * Zba: `"zba"`
50 /// * Zbb: `"zbb"`
51 /// * Zbs: `"zbs"`
52 /// * C: `"c"`
53 /// * Zca: `"zca"`
54 /// * Zcd: `"zcd"` (if D is enabled)
55 /// * Zcf: `"zcf"` (if F is enabled on RV32)
56 /// * D: `"d"`
57 /// * F: `"f"`
58 /// * M: `"m"`
59 /// * Q: `"q"`
60 /// * V: `"v"`
61 /// * Zve32x: `"zve32x"`
62 /// * Zve32f: `"zve32f"`
63 /// * Zve64x: `"zve64x"`
64 /// * Zve64f: `"zve64f"`
65 /// * Zve64d: `"zve64d"`
66 /// * Zicbom: `"zicbom"`
67 /// * Zicboz: `"zicboz"`
68 /// * Zicntr: `"zicntr"`
69 /// * Zicond: `"zicond"`
70 /// * Zicsr: `"zicsr"`
71 /// * Zifencei: `"zifencei"`
72 /// * Zihintntl: `"zihintntl"`
73 /// * Zihintpause: `"zihintpause"`
74 /// * Zihpm: `"zihpm"`
75 /// * Zimop: `"zimop"`
76 /// * Zacas: `"zacas"`
77 /// * Zawrs: `"zawrs"`
78 /// * Zfa: `"zfa"`
79 /// * Zfbfmin: `"zfbfmin"`
80 /// * Zfh: `"zfh"`
81 /// * Zfhmin: `"zfhmin"`
82 /// * Zfinx: `"zfinx"`
83 /// * Zdinx: `"zdinx"`
84 /// * Zhinx: `"zhinx"`
85 /// * Zhinxmin: `"zhinxmin"`
86 /// * Zcb: `"zcb"`
87 /// * Zcmop: `"zcmop"`
88 /// * Zbc: `"zbc"`
89 /// * Zbkb: `"zbkb"`
90 /// * Zbkc: `"zbkc"`
91 /// * Zbkx: `"zbkx"`
92 /// * Zk: `"zk"`
93 /// * Zkn: `"zkn"`
94 /// * Zknd: `"zknd"`
95 /// * Zkne: `"zkne"`
96 /// * Zknh: `"zknh"`
97 /// * Zkr: `"zkr"`
98 /// * Zks: `"zks"`
99 /// * Zksed: `"zksed"`
100 /// * Zksh: `"zksh"`
101 /// * Zkt: `"zkt"`
102 /// * Zvbb: `"zvbb"`
103 /// * Zvbc: `"zvbc"`
104 /// * Zvfbfmin: `"zvfbfmin"`
105 /// * Zvfbfwma: `"zvfbfwma"`
106 /// * Zvfh: `"zvfh"`
107 /// * Zvfhmin: `"zvfhmin"`
108 /// * Zvkb: `"zvkb"`
109 /// * Zvkg: `"zvkg"`
110 /// * Zvkn: `"zvkn"`
111 /// * Zvkned: `"zvkned"`
112 /// * Zvknha: `"zvknha"`
113 /// * Zvknhb: `"zvknhb"`
114 /// * Zvknc: `"zvknc"`
115 /// * Zvkng: `"zvkng"`
116 /// * Zvks: `"zvks"`
117 /// * Zvksed: `"zvksed"`
118 /// * Zvksh: `"zvksh"`
119 /// * Zvksc: `"zvksc"`
120 /// * Zvksg: `"zvksg"`
121 /// * Zvkt: `"zvkt"`
122 /// * Ztso: `"ztso"`
123 ///
124 /// There's also bases and extensions marked as standard instruction set,
125 /// but they are in frozen or draft state. These instruction sets are also
126 /// reserved by this macro and can be detected in the future platforms.
127 ///
128 /// Draft RISC-V instruction sets:
129 ///
130 /// * RV128I: `"rv128i"`
131 /// * J: `"j"`
132 /// * P: `"p"`
133 /// * Zam: `"zam"`
134 ///
135 /// # Performance Hints
136 ///
137 /// The two features below define performance hints for unaligned
138 /// scalar/vector memory accesses, respectively. If enabled, it denotes that
139 /// corresponding unaligned memory access is reasonably fast.
140 ///
141 /// * `"unaligned-scalar-mem"`
142 /// * Runtime detection requires Linux kernel version 6.4 or later.
143 /// * `"unaligned-vector-mem"`
144 /// * Runtime detection requires Linux kernel version 6.13 or later.
145 #[stable(feature = "riscv_ratified", since = "1.78.0")]
146
147 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
148 without cfg check: true;
149 /// RV32I Base Integer Instruction Set
150 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
151 without cfg check: true;
152 /// RV32E Base Integer Instruction Set
153 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
154 without cfg check: true;
155 /// RV64I Base Integer Instruction Set
156 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
157 without cfg check: true;
158 /// RV128I Base Integer Instruction Set
159
160 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
161 /// Has reasonably performant unaligned scalar
162 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
163 /// Has reasonably performant unaligned vector
164
165 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
166 /// "Zicsr" Extension for Control and Status Register (CSR) Instructions
167 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
168 /// "Zicntr" Extension for Base Counters and Timers
169 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
170 /// "Zihpm" Extension for Hardware Performance Counters
171 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
172 /// "Zifencei" Extension for Instruction-Fetch Fence
173
174 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintntl: "zihintntl";
175 /// "Zihintntl" Extension for Non-Temporal Locality Hints
176 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
177 /// "Zihintpause" Extension for Pause Hint
178 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zimop: "zimop";
179 /// "Zimop" Extension for May-Be-Operations
180 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicbom: "zicbom";
181 /// "Zicbom" Extension for Cache-Block Management Instructions
182 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicboz: "zicboz";
183 /// "Zicboz" Extension for Cache-Block Zero Instruction
184 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicond: "zicond";
185 /// "Zicond" Extension for Integer Conditional Operations
186
187 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
188 /// "M" Extension for Integer Multiplication and Division
189
190 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
191 /// "A" Extension for Atomic Instructions
192 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zalrsc: "zalrsc";
193 /// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
194 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zaamo: "zaamo";
195 /// "Zaamo" Extension for Atomic Memory Operations
196 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
197 /// "Zawrs" Extension for Wait-on-Reservation-Set Instructions
198 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
199 /// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
200 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
201 without cfg check: true;
202 /// "Zam" Extension for Misaligned Atomics
203 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
204 /// "Ztso" Extension for Total Store Ordering
205
206 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
207 /// "F" Extension for Single-Precision Floating-Point
208 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
209 /// "D" Extension for Double-Precision Floating-Point
210 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
211 without cfg check: true;
212 /// "Q" Extension for Quad-Precision Floating-Point
213 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
214 /// "Zfh" Extension for Half-Precision Floating-Point
215 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
216 /// "Zfhmin" Extension for Minimal Half-Precision Floating-Point
217 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfa: "zfa";
218 /// "Zfa" Extension for Additional Floating-Point Instructions
219 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfbfmin: "zfbfmin";
220 /// "Zfbfmin" Extension for Scalar BF16 Converts
221
222 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
223 /// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
224 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
225 /// "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
226 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
227 /// "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
228 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
229 /// "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers
230
231 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
232 /// "C" Extension for Compressed Instructions
233 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zca: "zca";
234 /// "Zca" Compressed Instructions excluding Floating-Point Loads/Stores
235 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcf: "zcf";
236 without cfg check: true;
237 /// "Zcf" Compressed Instructions for Single-Precision Floating-Point Loads/Stores on RV32
238 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcd: "zcd";
239 without cfg check: true;
240 /// "Zcd" Compressed Instructions for Double-Precision Floating-Point Loads/Stores
241 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcb: "zcb";
242 /// "Zcb" Simple Code-size Saving Compressed Instructions
243 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcmop: "zcmop";
244 /// "Zcmop" Extension for Compressed May-Be-Operations
245
246 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
247 /// "B" Extension for Bit Manipulation
248 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba";
249 /// "Zba" Extension for Address Generation
250 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbb: "zbb";
251 /// "Zbb" Extension for Basic Bit-Manipulation
252 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbc: "zbc";
253 /// "Zbc" Extension for Carry-less Multiplication
254 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbs: "zbs";
255 /// "Zbs" Extension for Single-Bit Instructions
256
257 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkb: "zbkb";
258 /// "Zbkb" Extension for Bit-Manipulation for Cryptography
259 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkc: "zbkc";
260 /// "Zbkc" Extension for Carry-less Multiplication for Cryptography
261 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkx: "zbkx";
262 /// "Zbkx" Extension for Crossbar Permutations
263 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknd: "zknd";
264 /// "Zknd" Cryptography Extension for NIST Suite: AES Decryption
265 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkne: "zkne";
266 /// "Zkne" Cryptography Extension for NIST Suite: AES Encryption
267 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknh: "zknh";
268 /// "Zknh" Cryptography Extension for NIST Suite: Hash Function Instructions
269 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksed: "zksed";
270 /// "Zksed" Cryptography Extension for ShangMi Suite: SM4 Block Cipher Instructions
271 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksh: "zksh";
272 /// "Zksh" Cryptography Extension for ShangMi Suite: SM3 Hash Function Instructions
273 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkr: "zkr";
274 /// "Zkr" Entropy Source Extension
275 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkn: "zkn";
276 /// "Zkn" Cryptography Extension for NIST Algorithm Suite
277 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zks: "zks";
278 /// "Zks" Cryptography Extension for ShangMi Algorithm Suite
279 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zk: "zk";
280 /// "Zk" Cryptography Extension for Standard Scalar Cryptography
281 @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt";
282 /// "Zkt" Cryptography Extension for Data Independent Execution Latency
283
284 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
285 /// "V" Extension for Vector Operations
286 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
287 /// "Zve32x" Vector Extension for Embedded Processors (32-bit+; Integer)
288 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
289 /// "Zve32f" Vector Extension for Embedded Processors (32-bit+; with Single-Precision Floating-Point)
290 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
291 /// "Zve64x" Vector Extension for Embedded Processors (64-bit+; Integer)
292 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
293 /// "Zve64f" Vector Extension for Embedded Processors (64-bit+; with Single-Precision Floating-Point)
294 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
295 /// "Zve64d" Vector Extension for Embedded Processors (64-bit+; with Double-Precision Floating-Point)
296 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
297 /// "Zvfh" Vector Extension for Half-Precision Floating-Point
298 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
299 /// "Zvfhmin" Vector Extension for Minimal Half-Precision Floating-Point
300 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfbfmin: "zvfbfmin";
301 /// "Zvfbfmin" Vector Extension for BF16 Converts
302 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfbfwma: "zvfbfwma";
303 /// "Zvfbfwma" Vector Extension for BF16 Widening Multiply-Add
304
305 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
306 /// "Zvbb" Extension for Vector Basic Bit-Manipulation
307 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
308 /// "Zvbc" Extension for Vector Carryless Multiplication
309 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
310 /// "Zvkb" Extension for Vector Cryptography Bit-Manipulation
311 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
312 /// "Zvkg" Cryptography Extension for Vector GCM/GMAC
313 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
314 /// "Zvkned" Cryptography Extension for NIST Suite: Vector AES Block Cipher
315 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
316 /// "Zvknha" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256)
317 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
318 /// "Zvknhb" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256/512)
319 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
320 /// "Zvksed" Cryptography Extension for ShangMi Suite: Vector SM4 Block Cipher
321 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
322 /// "Zvksh" Cryptography Extension for ShangMi Suite: Vector SM3 Secure Hash
323 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
324 /// "Zvkn" Cryptography Extension for NIST Algorithm Suite
325 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
326 /// "Zvknc" Cryptography Extension for NIST Algorithm Suite with Carryless Multiply
327 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
328 /// "Zvkng" Cryptography Extension for NIST Algorithm Suite with GCM
329 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
330 /// "Zvks" Cryptography Extension for ShangMi Algorithm Suite
331 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
332 /// "Zvksc" Cryptography Extension for ShangMi Algorithm Suite with Carryless Multiply
333 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
334 /// "Zvksg" Cryptography Extension for ShangMi Algorithm Suite with GCM
335 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
336 /// "Zvkt" Extension for Vector Data-Independent Execution Latency
337
338 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
339 without cfg check: true;
340 /// "J" Extension for Dynamically Translated Languages
341 @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
342 without cfg check: true;
343 /// "P" Extension for Packed-SIMD Instructions
344}
345