1//! `x86` and `x86_64` intrinsics.
2
3use crate::{intrinsics, marker::Sized, mem::transmute};
4
5#[macro_use]
6mod macros;
7
8types! {
9 /// 128-bit wide integer vector type, x86-specific
10 ///
11 /// This type is the same as the `__m128i` type defined by Intel,
12 /// representing a 128-bit SIMD register. Usage of this type typically
13 /// corresponds to the `sse` and up target features for x86/x86_64.
14 ///
15 /// Internally this type may be viewed as:
16 ///
17 /// * `i8x16` - sixteen `i8` variables packed together
18 /// * `i16x8` - eight `i16` variables packed together
19 /// * `i32x4` - four `i32` variables packed together
20 /// * `i64x2` - two `i64` variables packed together
21 ///
22 /// (as well as unsigned versions). Each intrinsic may interpret the
23 /// internal bits differently, check the documentation of the intrinsic
24 /// to see how it's being used.
25 ///
26 /// Note that this means that an instance of `__m128i` typically just means
27 /// a "bag of bits" which is left up to interpretation at the point of use.
28 ///
29 /// Most intrinsics using `__m128i` are prefixed with `_mm_` and the
30 /// integer types tend to correspond to suffixes like "epi8" or "epi32".
31 ///
32 /// # Examples
33 ///
34 /// ```
35 /// #[cfg(target_arch = "x86")]
36 /// use std::arch::x86::*;
37 /// #[cfg(target_arch = "x86_64")]
38 /// use std::arch::x86_64::*;
39 ///
40 /// # fn main() {
41 /// # #[target_feature(enable = "sse2")]
42 /// # unsafe fn foo() {
43 /// let all_bytes_zero = _mm_setzero_si128();
44 /// let all_bytes_one = _mm_set1_epi8(1);
45 /// let four_i32 = _mm_set_epi32(1, 2, 3, 4);
46 /// # }
47 /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } }
48 /// # }
49 /// ```
50 #[stable(feature = "simd_x86", since = "1.27.0")]
51 pub struct __m128i(i64, i64);
52
53 /// 128-bit wide set of four `f32` types, x86-specific
54 ///
55 /// This type is the same as the `__m128` type defined by Intel,
56 /// representing a 128-bit SIMD register which internally is consisted of
57 /// four packed `f32` instances. Usage of this type typically corresponds
58 /// to the `sse` and up target features for x86/x86_64.
59 ///
60 /// Note that unlike `__m128i`, the integer version of the 128-bit
61 /// registers, this `__m128` type has *one* interpretation. Each instance
62 /// of `__m128` always corresponds to `f32x4`, or four `f32` types packed
63 /// together.
64 ///
65 /// Most intrinsics using `__m128` are prefixed with `_mm_` and are
66 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
67 /// "pd" which is used for `__m128d`.
68 ///
69 /// # Examples
70 ///
71 /// ```
72 /// #[cfg(target_arch = "x86")]
73 /// use std::arch::x86::*;
74 /// #[cfg(target_arch = "x86_64")]
75 /// use std::arch::x86_64::*;
76 ///
77 /// # fn main() {
78 /// # #[target_feature(enable = "sse")]
79 /// # unsafe fn foo() {
80 /// let four_zeros = _mm_setzero_ps();
81 /// let four_ones = _mm_set1_ps(1.0);
82 /// let four_floats = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
83 /// # }
84 /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
85 /// # }
86 /// ```
87 #[stable(feature = "simd_x86", since = "1.27.0")]
88 pub struct __m128(f32, f32, f32, f32);
89
90 /// 128-bit wide set of two `f64` types, x86-specific
91 ///
92 /// This type is the same as the `__m128d` type defined by Intel,
93 /// representing a 128-bit SIMD register which internally is consisted of
94 /// two packed `f64` instances. Usage of this type typically corresponds
95 /// to the `sse` and up target features for x86/x86_64.
96 ///
97 /// Note that unlike `__m128i`, the integer version of the 128-bit
98 /// registers, this `__m128d` type has *one* interpretation. Each instance
99 /// of `__m128d` always corresponds to `f64x2`, or two `f64` types packed
100 /// together.
101 ///
102 /// Most intrinsics using `__m128d` are prefixed with `_mm_` and are
103 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
104 /// "ps" which is used for `__m128`.
105 ///
106 /// # Examples
107 ///
108 /// ```
109 /// #[cfg(target_arch = "x86")]
110 /// use std::arch::x86::*;
111 /// #[cfg(target_arch = "x86_64")]
112 /// use std::arch::x86_64::*;
113 ///
114 /// # fn main() {
115 /// # #[target_feature(enable = "sse")]
116 /// # unsafe fn foo() {
117 /// let two_zeros = _mm_setzero_pd();
118 /// let two_ones = _mm_set1_pd(1.0);
119 /// let two_floats = _mm_set_pd(1.0, 2.0);
120 /// # }
121 /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
122 /// # }
123 /// ```
124 #[stable(feature = "simd_x86", since = "1.27.0")]
125 pub struct __m128d(f64, f64);
126
127 /// 256-bit wide integer vector type, x86-specific
128 ///
129 /// This type is the same as the `__m256i` type defined by Intel,
130 /// representing a 256-bit SIMD register. Usage of this type typically
131 /// corresponds to the `avx` and up target features for x86/x86_64.
132 ///
133 /// Internally this type may be viewed as:
134 ///
135 /// * `i8x32` - thirty two `i8` variables packed together
136 /// * `i16x16` - sixteen `i16` variables packed together
137 /// * `i32x8` - eight `i32` variables packed together
138 /// * `i64x4` - four `i64` variables packed together
139 ///
140 /// (as well as unsigned versions). Each intrinsic may interpret the
141 /// internal bits differently, check the documentation of the intrinsic
142 /// to see how it's being used.
143 ///
144 /// Note that this means that an instance of `__m256i` typically just means
145 /// a "bag of bits" which is left up to interpretation at the point of use.
146 ///
147 /// # Examples
148 ///
149 /// ```
150 /// #[cfg(target_arch = "x86")]
151 /// use std::arch::x86::*;
152 /// #[cfg(target_arch = "x86_64")]
153 /// use std::arch::x86_64::*;
154 ///
155 /// # fn main() {
156 /// # #[target_feature(enable = "avx")]
157 /// # unsafe fn foo() {
158 /// let all_bytes_zero = _mm256_setzero_si256();
159 /// let all_bytes_one = _mm256_set1_epi8(1);
160 /// let eight_i32 = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
161 /// # }
162 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
163 /// # }
164 /// ```
165 #[stable(feature = "simd_x86", since = "1.27.0")]
166 pub struct __m256i(i64, i64, i64, i64);
167
168 /// 256-bit wide set of eight `f32` types, x86-specific
169 ///
170 /// This type is the same as the `__m256` type defined by Intel,
171 /// representing a 256-bit SIMD register which internally is consisted of
172 /// eight packed `f32` instances. Usage of this type typically corresponds
173 /// to the `avx` and up target features for x86/x86_64.
174 ///
175 /// Note that unlike `__m256i`, the integer version of the 256-bit
176 /// registers, this `__m256` type has *one* interpretation. Each instance
177 /// of `__m256` always corresponds to `f32x8`, or eight `f32` types packed
178 /// together.
179 ///
180 /// Most intrinsics using `__m256` are prefixed with `_mm256_` and are
181 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
182 /// "pd" which is used for `__m256d`.
183 ///
184 /// # Examples
185 ///
186 /// ```
187 /// #[cfg(target_arch = "x86")]
188 /// use std::arch::x86::*;
189 /// #[cfg(target_arch = "x86_64")]
190 /// use std::arch::x86_64::*;
191 ///
192 /// # fn main() {
193 /// # #[target_feature(enable = "avx")]
194 /// # unsafe fn foo() {
195 /// let eight_zeros = _mm256_setzero_ps();
196 /// let eight_ones = _mm256_set1_ps(1.0);
197 /// let eight_floats = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
198 /// # }
199 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
200 /// # }
201 /// ```
202 #[stable(feature = "simd_x86", since = "1.27.0")]
203 pub struct __m256(f32, f32, f32, f32, f32, f32, f32, f32);
204
205 /// 256-bit wide set of four `f64` types, x86-specific
206 ///
207 /// This type is the same as the `__m256d` type defined by Intel,
208 /// representing a 256-bit SIMD register which internally is consisted of
209 /// four packed `f64` instances. Usage of this type typically corresponds
210 /// to the `avx` and up target features for x86/x86_64.
211 ///
212 /// Note that unlike `__m256i`, the integer version of the 256-bit
213 /// registers, this `__m256d` type has *one* interpretation. Each instance
214 /// of `__m256d` always corresponds to `f64x4`, or four `f64` types packed
215 /// together.
216 ///
217 /// Most intrinsics using `__m256d` are prefixed with `_mm256_` and are
218 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
219 /// "ps" which is used for `__m256`.
220 ///
221 /// # Examples
222 ///
223 /// ```
224 /// #[cfg(target_arch = "x86")]
225 /// use std::arch::x86::*;
226 /// #[cfg(target_arch = "x86_64")]
227 /// use std::arch::x86_64::*;
228 ///
229 /// # fn main() {
230 /// # #[target_feature(enable = "avx")]
231 /// # unsafe fn foo() {
232 /// let four_zeros = _mm256_setzero_pd();
233 /// let four_ones = _mm256_set1_pd(1.0);
234 /// let four_floats = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
235 /// # }
236 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
237 /// # }
238 /// ```
239 #[stable(feature = "simd_x86", since = "1.27.0")]
240 pub struct __m256d(f64, f64, f64, f64);
241
242 /// 512-bit wide integer vector type, x86-specific
243 ///
244 /// This type is the same as the `__m512i` type defined by Intel,
245 /// representing a 512-bit SIMD register. Usage of this type typically
246 /// corresponds to the `avx512*` and up target features for x86/x86_64.
247 ///
248 /// Internally this type may be viewed as:
249 ///
250 /// * `i8x64` - sixty-four `i8` variables packed together
251 /// * `i16x32` - thirty-two `i16` variables packed together
252 /// * `i32x16` - sixteen `i32` variables packed together
253 /// * `i64x8` - eight `i64` variables packed together
254 ///
255 /// (as well as unsigned versions). Each intrinsic may interpret the
256 /// internal bits differently, check the documentation of the intrinsic
257 /// to see how it's being used.
258 ///
259 /// Note that this means that an instance of `__m512i` typically just means
260 /// a "bag of bits" which is left up to interpretation at the point of use.
261 #[stable(feature = "simd_avx512_types", since = "CURRENT_RUSTC_VERSION")]
262 pub struct __m512i(i64, i64, i64, i64, i64, i64, i64, i64);
263
264 /// 512-bit wide set of sixteen `f32` types, x86-specific
265 ///
266 /// This type is the same as the `__m512` type defined by Intel,
267 /// representing a 512-bit SIMD register which internally is consisted of
268 /// eight packed `f32` instances. Usage of this type typically corresponds
269 /// to the `avx512*` and up target features for x86/x86_64.
270 ///
271 /// Note that unlike `__m512i`, the integer version of the 512-bit
272 /// registers, this `__m512` type has *one* interpretation. Each instance
273 /// of `__m512` always corresponds to `f32x16`, or sixteen `f32` types
274 /// packed together.
275 ///
276 /// Most intrinsics using `__m512` are prefixed with `_mm512_` and are
277 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
278 /// "pd" which is used for `__m512d`.
279 #[stable(feature = "simd_avx512_types", since = "CURRENT_RUSTC_VERSION")]
280 pub struct __m512(
281 f32, f32, f32, f32, f32, f32, f32, f32,
282 f32, f32, f32, f32, f32, f32, f32, f32,
283 );
284
285 /// 512-bit wide set of eight `f64` types, x86-specific
286 ///
287 /// This type is the same as the `__m512d` type defined by Intel,
288 /// representing a 512-bit SIMD register which internally is consisted of
289 /// eight packed `f64` instances. Usage of this type typically corresponds
290 /// to the `avx` and up target features for x86/x86_64.
291 ///
292 /// Note that unlike `__m512i`, the integer version of the 512-bit
293 /// registers, this `__m512d` type has *one* interpretation. Each instance
294 /// of `__m512d` always corresponds to `f64x4`, or eight `f64` types packed
295 /// together.
296 ///
297 /// Most intrinsics using `__m512d` are prefixed with `_mm512_` and are
298 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
299 /// "ps" which is used for `__m512`.
300 #[stable(feature = "simd_avx512_types", since = "CURRENT_RUSTC_VERSION")]
301 pub struct __m512d(f64, f64, f64, f64, f64, f64, f64, f64);
302
303 /// 128-bit wide set of eight `u16` types, x86-specific
304 ///
305 /// This type is representing a 128-bit SIMD register which internally is consisted of
306 /// eight packed `u16` instances. Its purpose is for bf16 related intrinsic
307 /// implementations.
308 pub struct __m128bh(u16, u16, u16, u16, u16, u16, u16, u16);
309
310 /// 256-bit wide set of 16 `u16` types, x86-specific
311 ///
312 /// This type is the same as the `__m256bh` type defined by Intel,
313 /// representing a 256-bit SIMD register which internally is consisted of
314 /// 16 packed `u16` instances. Its purpose is for bf16 related intrinsic
315 /// implementations.
316 pub struct __m256bh(
317 u16, u16, u16, u16, u16, u16, u16, u16,
318 u16, u16, u16, u16, u16, u16, u16, u16
319 );
320
321 /// 512-bit wide set of 32 `u16` types, x86-specific
322 ///
323 /// This type is the same as the `__m512bh` type defined by Intel,
324 /// representing a 512-bit SIMD register which internally is consisted of
325 /// 32 packed `u16` instances. Its purpose is for bf16 related intrinsic
326 /// implementations.
327 pub struct __m512bh(
328 u16, u16, u16, u16, u16, u16, u16, u16,
329 u16, u16, u16, u16, u16, u16, u16, u16,
330 u16, u16, u16, u16, u16, u16, u16, u16,
331 u16, u16, u16, u16, u16, u16, u16, u16
332 );
333}
334
335/// The `__mmask64` type used in AVX-512 intrinsics, a 64-bit integer
336#[allow(non_camel_case_types)]
337pub type __mmask64 = u64;
338
339/// The `__mmask32` type used in AVX-512 intrinsics, a 32-bit integer
340#[allow(non_camel_case_types)]
341pub type __mmask32 = u32;
342
343/// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer
344#[allow(non_camel_case_types)]
345pub type __mmask16 = u16;
346
347/// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer
348#[allow(non_camel_case_types)]
349pub type __mmask8 = u8;
350
351/// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics.
352#[allow(non_camel_case_types)]
353pub type _MM_CMPINT_ENUM = i32;
354
355/// The `MM_MANTISSA_NORM_ENUM` type used to specify mantissa normalized operations in AVX-512 intrinsics.
356#[allow(non_camel_case_types)]
357pub type _MM_MANTISSA_NORM_ENUM = i32;
358
359/// The `MM_MANTISSA_SIGN_ENUM` type used to specify mantissa signed operations in AVX-512 intrinsics.
360#[allow(non_camel_case_types)]
361pub type _MM_MANTISSA_SIGN_ENUM = i32;
362
363/// The `MM_PERM_ENUM` type used to specify shuffle operations in AVX-512 intrinsics.
364#[allow(non_camel_case_types)]
365pub type _MM_PERM_ENUM = i32;
366
367#[cfg(test)]
368mod test;
369#[cfg(test)]
370pub use self::test::*;
371
372#[allow(non_camel_case_types)]
373#[unstable(feature = "stdsimd_internal", issue = "none")]
374pub(crate) trait m128iExt: Sized {
375 fn as_m128i(self) -> __m128i;
376
377 #[inline]
378 fn as_u8x16(self) -> crate::core_arch::simd::u8x16 {
379 unsafe { transmute(self.as_m128i()) }
380 }
381
382 #[inline]
383 fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
384 unsafe { transmute(self.as_m128i()) }
385 }
386
387 #[inline]
388 fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
389 unsafe { transmute(self.as_m128i()) }
390 }
391
392 #[inline]
393 fn as_u64x2(self) -> crate::core_arch::simd::u64x2 {
394 unsafe { transmute(self.as_m128i()) }
395 }
396
397 #[inline]
398 fn as_i8x16(self) -> crate::core_arch::simd::i8x16 {
399 unsafe { transmute(self.as_m128i()) }
400 }
401
402 #[inline]
403 fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
404 unsafe { transmute(self.as_m128i()) }
405 }
406
407 #[inline]
408 fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
409 unsafe { transmute(self.as_m128i()) }
410 }
411
412 #[inline]
413 fn as_i64x2(self) -> crate::core_arch::simd::i64x2 {
414 unsafe { transmute(self.as_m128i()) }
415 }
416}
417
418impl m128iExt for __m128i {
419 #[inline]
420 fn as_m128i(self) -> Self {
421 self
422 }
423}
424
425#[allow(non_camel_case_types)]
426#[unstable(feature = "stdsimd_internal", issue = "none")]
427pub(crate) trait m256iExt: Sized {
428 fn as_m256i(self) -> __m256i;
429
430 #[inline]
431 fn as_u8x32(self) -> crate::core_arch::simd::u8x32 {
432 unsafe { transmute(self.as_m256i()) }
433 }
434
435 #[inline]
436 fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
437 unsafe { transmute(self.as_m256i()) }
438 }
439
440 #[inline]
441 fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
442 unsafe { transmute(self.as_m256i()) }
443 }
444
445 #[inline]
446 fn as_u64x4(self) -> crate::core_arch::simd::u64x4 {
447 unsafe { transmute(self.as_m256i()) }
448 }
449
450 #[inline]
451 fn as_i8x32(self) -> crate::core_arch::simd::i8x32 {
452 unsafe { transmute(self.as_m256i()) }
453 }
454
455 #[inline]
456 fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
457 unsafe { transmute(self.as_m256i()) }
458 }
459
460 #[inline]
461 fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
462 unsafe { transmute(self.as_m256i()) }
463 }
464
465 #[inline]
466 fn as_i64x4(self) -> crate::core_arch::simd::i64x4 {
467 unsafe { transmute(self.as_m256i()) }
468 }
469}
470
471impl m256iExt for __m256i {
472 #[inline]
473 fn as_m256i(self) -> Self {
474 self
475 }
476}
477
478#[allow(non_camel_case_types)]
479#[unstable(feature = "stdsimd_internal", issue = "none")]
480pub(crate) trait m128Ext: Sized {
481 fn as_m128(self) -> __m128;
482
483 #[inline]
484 fn as_f32x4(self) -> crate::core_arch::simd::f32x4 {
485 unsafe { transmute(self.as_m128()) }
486 }
487}
488
489impl m128Ext for __m128 {
490 #[inline]
491 fn as_m128(self) -> Self {
492 self
493 }
494}
495
496#[allow(non_camel_case_types)]
497#[unstable(feature = "stdsimd_internal", issue = "none")]
498pub(crate) trait m128dExt: Sized {
499 fn as_m128d(self) -> __m128d;
500
501 #[inline]
502 fn as_f64x2(self) -> crate::core_arch::simd::f64x2 {
503 unsafe { transmute(self.as_m128d()) }
504 }
505}
506
507impl m128dExt for __m128d {
508 #[inline]
509 fn as_m128d(self) -> Self {
510 self
511 }
512}
513
514#[allow(non_camel_case_types)]
515#[unstable(feature = "stdsimd_internal", issue = "none")]
516pub(crate) trait m256Ext: Sized {
517 fn as_m256(self) -> __m256;
518
519 #[inline]
520 fn as_f32x8(self) -> crate::core_arch::simd::f32x8 {
521 unsafe { transmute(self.as_m256()) }
522 }
523}
524
525impl m256Ext for __m256 {
526 #[inline]
527 fn as_m256(self) -> Self {
528 self
529 }
530}
531
532#[allow(non_camel_case_types)]
533#[unstable(feature = "stdsimd_internal", issue = "none")]
534pub(crate) trait m256dExt: Sized {
535 fn as_m256d(self) -> __m256d;
536
537 #[inline]
538 fn as_f64x4(self) -> crate::core_arch::simd::f64x4 {
539 unsafe { transmute(self.as_m256d()) }
540 }
541}
542
543impl m256dExt for __m256d {
544 #[inline]
545 fn as_m256d(self) -> Self {
546 self
547 }
548}
549
550#[allow(non_camel_case_types)]
551#[unstable(feature = "stdsimd_internal", issue = "none")]
552pub(crate) trait m512iExt: Sized {
553 fn as_m512i(self) -> __m512i;
554
555 #[inline]
556 fn as_u8x64(self) -> crate::core_arch::simd::u8x64 {
557 unsafe { transmute(self.as_m512i()) }
558 }
559
560 #[inline]
561 fn as_i8x64(self) -> crate::core_arch::simd::i8x64 {
562 unsafe { transmute(self.as_m512i()) }
563 }
564
565 #[inline]
566 fn as_u16x32(self) -> crate::core_arch::simd::u16x32 {
567 unsafe { transmute(self.as_m512i()) }
568 }
569
570 #[inline]
571 fn as_i16x32(self) -> crate::core_arch::simd::i16x32 {
572 unsafe { transmute(self.as_m512i()) }
573 }
574
575 #[inline]
576 fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
577 unsafe { transmute(self.as_m512i()) }
578 }
579
580 #[inline]
581 fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
582 unsafe { transmute(self.as_m512i()) }
583 }
584
585 #[inline]
586 fn as_u64x8(self) -> crate::core_arch::simd::u64x8 {
587 unsafe { transmute(self.as_m512i()) }
588 }
589
590 #[inline]
591 fn as_i64x8(self) -> crate::core_arch::simd::i64x8 {
592 unsafe { transmute(self.as_m512i()) }
593 }
594}
595
596impl m512iExt for __m512i {
597 #[inline]
598 fn as_m512i(self) -> Self {
599 self
600 }
601}
602
603#[allow(non_camel_case_types)]
604#[unstable(feature = "stdsimd_internal", issue = "none")]
605pub(crate) trait m512Ext: Sized {
606 fn as_m512(self) -> __m512;
607
608 #[inline]
609 fn as_f32x16(self) -> crate::core_arch::simd::f32x16 {
610 unsafe { transmute(self.as_m512()) }
611 }
612}
613
614impl m512Ext for __m512 {
615 #[inline]
616 fn as_m512(self) -> Self {
617 self
618 }
619}
620
621#[allow(non_camel_case_types)]
622#[unstable(feature = "stdsimd_internal", issue = "none")]
623pub(crate) trait m512dExt: Sized {
624 fn as_m512d(self) -> __m512d;
625
626 #[inline]
627 fn as_f64x8(self) -> crate::core_arch::simd::f64x8 {
628 unsafe { transmute(self.as_m512d()) }
629 }
630}
631
632impl m512dExt for __m512d {
633 #[inline]
634 fn as_m512d(self) -> Self {
635 self
636 }
637}
638
639#[allow(non_camel_case_types)]
640#[unstable(feature = "stdsimd_internal", issue = "none")]
641pub(crate) trait m128bhExt: Sized {
642 fn as_m128bh(self) -> __m128bh;
643
644 #[inline]
645 fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
646 unsafe { transmute(self.as_m128bh()) }
647 }
648
649 #[inline]
650 fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
651 unsafe { transmute(self.as_m128bh()) }
652 }
653
654 #[inline]
655 fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
656 unsafe { transmute(self.as_m128bh()) }
657 }
658
659 #[inline]
660 fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
661 unsafe { transmute(self.as_m128bh()) }
662 }
663}
664
665impl m128bhExt for __m128bh {
666 #[inline]
667 fn as_m128bh(self) -> Self {
668 self
669 }
670}
671
672#[allow(non_camel_case_types)]
673#[unstable(feature = "stdsimd_internal", issue = "none")]
674pub(crate) trait m256bhExt: Sized {
675 fn as_m256bh(self) -> __m256bh;
676
677 #[inline]
678 fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
679 unsafe { transmute(self.as_m256bh()) }
680 }
681
682 #[inline]
683 fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
684 unsafe { transmute(self.as_m256bh()) }
685 }
686
687 #[inline]
688 fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
689 unsafe { transmute(self.as_m256bh()) }
690 }
691
692 #[inline]
693 fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
694 unsafe { transmute(self.as_m256bh()) }
695 }
696}
697
698impl m256bhExt for __m256bh {
699 #[inline]
700 fn as_m256bh(self) -> Self {
701 self
702 }
703}
704
705#[allow(non_camel_case_types)]
706#[unstable(feature = "stdsimd_internal", issue = "none")]
707pub(crate) trait m512bhExt: Sized {
708 fn as_m512bh(self) -> __m512bh;
709
710 #[inline]
711 fn as_u16x32(self) -> crate::core_arch::simd::u16x32 {
712 unsafe { transmute(self.as_m512bh()) }
713 }
714
715 #[inline]
716 fn as_i16x32(self) -> crate::core_arch::simd::i16x32 {
717 unsafe { transmute(self.as_m512bh()) }
718 }
719
720 #[inline]
721 fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
722 unsafe { transmute(self.as_m512bh()) }
723 }
724
725 #[inline]
726 fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
727 unsafe { transmute(self.as_m512bh()) }
728 }
729}
730
731impl m512bhExt for __m512bh {
732 #[inline]
733 fn as_m512bh(self) -> Self {
734 self
735 }
736}
737
738mod eflags;
739pub use self::eflags::*;
740
741mod fxsr;
742pub use self::fxsr::*;
743
744mod bswap;
745pub use self::bswap::*;
746
747mod rdtsc;
748pub use self::rdtsc::*;
749
750mod cpuid;
751pub use self::cpuid::*;
752mod xsave;
753pub use self::xsave::*;
754
755mod sse;
756pub use self::sse::*;
757mod sse2;
758pub use self::sse2::*;
759mod sse3;
760pub use self::sse3::*;
761mod ssse3;
762pub use self::ssse3::*;
763mod sse41;
764pub use self::sse41::*;
765mod sse42;
766pub use self::sse42::*;
767mod avx;
768pub use self::avx::*;
769mod avx2;
770pub use self::avx2::*;
771mod fma;
772pub use self::fma::*;
773
774mod abm;
775pub use self::abm::*;
776mod bmi1;
777pub use self::bmi1::*;
778
779mod bmi2;
780pub use self::bmi2::*;
781
782#[cfg(not(stdarch_intel_sde))]
783mod sse4a;
784#[cfg(not(stdarch_intel_sde))]
785pub use self::sse4a::*;
786
787#[cfg(not(stdarch_intel_sde))]
788mod tbm;
789#[cfg(not(stdarch_intel_sde))]
790pub use self::tbm::*;
791
792mod pclmulqdq;
793pub use self::pclmulqdq::*;
794
795mod aes;
796pub use self::aes::*;
797
798mod rdrand;
799pub use self::rdrand::*;
800
801mod sha;
802pub use self::sha::*;
803
804mod adx;
805pub use self::adx::*;
806
807#[cfg(test)]
808use stdarch_test::assert_instr;
809
810mod avx512f;
811pub use self::avx512f::*;
812
813mod avx512bw;
814pub use self::avx512bw::*;
815
816mod avx512cd;
817pub use self::avx512cd::*;
818
819mod avx512ifma;
820pub use self::avx512ifma::*;
821
822mod avx512vbmi;
823pub use self::avx512vbmi::*;
824
825mod avx512vbmi2;
826pub use self::avx512vbmi2::*;
827
828mod avx512vnni;
829pub use self::avx512vnni::*;
830
831mod avx512bitalg;
832pub use self::avx512bitalg::*;
833
834mod gfni;
835pub use self::gfni::*;
836
837mod avx512vpopcntdq;
838pub use self::avx512vpopcntdq::*;
839
840mod vaes;
841pub use self::vaes::*;
842
843mod vpclmulqdq;
844pub use self::vpclmulqdq::*;
845
846mod bt;
847pub use self::bt::*;
848
849mod rtm;
850pub use self::rtm::*;
851
852mod f16c;
853pub use self::f16c::*;
854
855mod avx512bf16;
856pub use self::avx512bf16::*;
857