| 1 | //! Memory Protection Unit |
| 2 | |
| 3 | use volatile_register::{RO, RW}; |
| 4 | |
| 5 | /// Register block for ARMv7-M |
| 6 | #[cfg (not(armv8m))] |
| 7 | #[repr (C)] |
| 8 | pub struct RegisterBlock { |
| 9 | /// Type |
| 10 | pub _type: RO<u32>, |
| 11 | /// Control |
| 12 | pub ctrl: RW<u32>, |
| 13 | /// Region Number |
| 14 | pub rnr: RW<u32>, |
| 15 | /// Region Base Address |
| 16 | pub rbar: RW<u32>, |
| 17 | /// Region Attribute and Size |
| 18 | pub rasr: RW<u32>, |
| 19 | /// Alias 1 of RBAR |
| 20 | pub rbar_a1: RW<u32>, |
| 21 | /// Alias 1 of RASR |
| 22 | pub rasr_a1: RW<u32>, |
| 23 | /// Alias 2 of RBAR |
| 24 | pub rbar_a2: RW<u32>, |
| 25 | /// Alias 2 of RASR |
| 26 | pub rasr_a2: RW<u32>, |
| 27 | /// Alias 3 of RBAR |
| 28 | pub rbar_a3: RW<u32>, |
| 29 | /// Alias 3 of RASR |
| 30 | pub rasr_a3: RW<u32>, |
| 31 | } |
| 32 | |
| 33 | /// Register block for ARMv8-M |
| 34 | #[cfg (armv8m)] |
| 35 | #[repr (C)] |
| 36 | pub struct RegisterBlock { |
| 37 | /// Type |
| 38 | pub _type: RO<u32>, |
| 39 | /// Control |
| 40 | pub ctrl: RW<u32>, |
| 41 | /// Region Number |
| 42 | pub rnr: RW<u32>, |
| 43 | /// Region Base Address |
| 44 | pub rbar: RW<u32>, |
| 45 | /// Region Limit Address |
| 46 | pub rlar: RW<u32>, |
| 47 | /// Alias 1 of RBAR |
| 48 | pub rbar_a1: RW<u32>, |
| 49 | /// Alias 1 of RLAR |
| 50 | pub rlar_a1: RW<u32>, |
| 51 | /// Alias 2 of RBAR |
| 52 | pub rbar_a2: RW<u32>, |
| 53 | /// Alias 2 of RLAR |
| 54 | pub rlar_a2: RW<u32>, |
| 55 | /// Alias 3 of RBAR |
| 56 | pub rbar_a3: RW<u32>, |
| 57 | /// Alias 3 of RLAR |
| 58 | pub rlar_a3: RW<u32>, |
| 59 | |
| 60 | // Reserved word at offset 0xBC |
| 61 | _reserved: u32, |
| 62 | |
| 63 | /// Memory Attribute Indirection register 0 and 1 |
| 64 | pub mair: [RW<u32>; 2], |
| 65 | } |
| 66 | |