1//! Processor core registers
2//!
3//! The following registers can only be accessed in PRIVILEGED mode:
4//!
5//! - BASEPRI
6//! - CONTROL
7//! - FAULTMASK
8//! - MSP
9//! - PRIMASK
10//!
11//! The rest of registers (see list below) can be accessed in either, PRIVILEGED
12//! or UNPRIVILEGED, mode.
13//!
14//! - APSR
15//! - LR
16//! - PC
17//! - PSP
18//!
19//! The following registers are NOT available on ARMv6-M devices
20//! (`thumbv6m-none-eabi`):
21//!
22//! - BASEPRI
23//! - FAULTMASK
24//!
25//! The following registers are only available for devices with an FPU:
26//!
27//! - FPSCR
28//!
29//! # References
30//!
31//! - Cortex-M* Devices Generic User Guide - Section 2.1.3 Core registers
32
33#[cfg(all(not(armv6m), not(armv8m_base)))]
34pub mod basepri;
35
36#[cfg(all(not(armv6m), not(armv8m_base)))]
37pub mod basepri_max;
38
39pub mod control;
40
41#[cfg(all(not(armv6m), not(armv8m_base)))]
42pub mod faultmask;
43
44#[cfg(has_fpu)]
45pub mod fpscr;
46
47pub mod msp;
48
49pub mod primask;
50
51pub mod psp;
52
53#[cfg(armv8m_main)]
54pub mod msplim;
55
56#[cfg(armv8m_main)]
57pub mod psplim;
58
59// Accessing these registers requires inline assembly because their contents are tied to the current
60// stack frame
61#[cfg(feature = "inline-asm")]
62pub mod apsr;
63
64#[cfg(feature = "inline-asm")]
65pub mod lr;
66
67#[cfg(feature = "inline-asm")]
68pub mod pc;
69