1// SPDX-License-Identifier: Apache-2.0 OR MIT
2
3use core::ops;
4
5// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/9384f1eb2b356364e201ad38545e03c837d55f3a/crossbeam-utils/src/cache_padded.rs.
6/// Pads and aligns a value to the length of a cache line.
7// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
8// lines at a time, so we have to align to 128 bytes rather than 64.
9//
10// Sources:
11// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
12// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
13//
14// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
15//
16// Sources:
17// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
18//
19// powerpc64 has 128-byte cache line size.
20//
21// Sources:
22// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
23// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/powerpc/include/asm/cache.h#L26
24#[cfg_attr(
25 any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "powerpc64"),
26 repr(align(128))
27)]
28// arm, mips, mips64, sparc, and hexagon have 32-byte cache line size.
29//
30// Sources:
31// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
32// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
33// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
34// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
35// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L17
36// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/hexagon/include/asm/cache.h#L12
37#[cfg_attr(
38 any(
39 target_arch = "arm",
40 target_arch = "mips",
41 target_arch = "mips32r6",
42 target_arch = "mips64",
43 target_arch = "mips64r6",
44 target_arch = "sparc",
45 target_arch = "hexagon",
46 ),
47 repr(align(32))
48)]
49// m68k has 16-byte cache line size.
50//
51// Sources:
52// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/m68k/include/asm/cache.h#L9
53#[cfg_attr(target_arch = "m68k", repr(align(16)))]
54// s390x has 256-byte cache line size.
55//
56// Sources:
57// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
58// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/s390/include/asm/cache.h#L13
59#[cfg_attr(target_arch = "s390x", repr(align(256)))]
60// x86, wasm, riscv, and sparc64 have 64-byte cache line size.
61//
62// Sources:
63// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
64// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
65// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10
66// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L19
67//
68// All others are assumed to have 64-byte cache line size.
69#[cfg_attr(
70 not(any(
71 target_arch = "x86_64",
72 target_arch = "aarch64",
73 target_arch = "powerpc64",
74 target_arch = "arm",
75 target_arch = "mips",
76 target_arch = "mips32r6",
77 target_arch = "mips64",
78 target_arch = "mips64r6",
79 target_arch = "sparc",
80 target_arch = "hexagon",
81 target_arch = "m68k",
82 target_arch = "s390x",
83 )),
84 repr(align(64))
85)]
86pub(crate) struct CachePadded<T> {
87 value: T,
88}
89
90impl<T> CachePadded<T> {
91 #[inline]
92 pub(crate) const fn new(value: T) -> Self {
93 Self { value }
94 }
95}
96
97impl<T> ops::Deref for CachePadded<T> {
98 type Target = T;
99
100 #[inline]
101 fn deref(&self) -> &Self::Target {
102 &self.value
103 }
104}
105
106// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.7/crossbeam-utils/src/backoff.rs.
107// Adjusted to reduce spinning.
108/// Performs exponential backoff in spin loops.
109pub(crate) struct Backoff {
110 step: u32,
111}
112
113// https://github.com/oneapi-src/oneTBB/blob/v2021.5.0/include/oneapi/tbb/detail/_utils.h#L46-L48
114const SPIN_LIMIT: u32 = 4;
115
116impl Backoff {
117 #[inline]
118 pub(crate) const fn new() -> Self {
119 Self { step: 0 }
120 }
121
122 #[inline]
123 pub(crate) fn snooze(&mut self) {
124 if self.step <= SPIN_LIMIT {
125 for _ in 0..1 << self.step {
126 #[allow(deprecated)]
127 core::sync::atomic::spin_loop_hint();
128 }
129 self.step += 1;
130 } else {
131 #[cfg(not(feature = "std"))]
132 for _ in 0..1 << self.step {
133 #[allow(deprecated)]
134 core::sync::atomic::spin_loop_hint();
135 }
136
137 #[cfg(feature = "std")]
138 std::thread::yield_now();
139 }
140 }
141}
142