1// Copyright 2024 Brian Smith.
2//
3// Permission to use, copy, modify, and/or distribute this software for any
4// purpose with or without fee is hereby granted, provided that the above
5// copyright notice and this permission notice appear in all copies.
6//
7// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHORS DISCLAIM ALL WARRANTIES
8// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
10// SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12// OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13// CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14
15use super::{BlockLen, CHAINING_WORDS};
16use crate::{cpu, polyfill::slice::AsChunks};
17use cfg_if::cfg_if;
18use core::num::Wrapping;
19
20pub(in super::super) const SHA512_BLOCK_LEN: BlockLen = BlockLen::_1024;
21
22pub type State64 = [Wrapping<u64>; CHAINING_WORDS];
23
24pub(crate) fn block_data_order_64(
25 state: &mut State64,
26 data: AsChunks<u8, { SHA512_BLOCK_LEN.into() }>,
27 cpu: cpu::Features,
28) {
29 cfg_if! {
30 if #[cfg(all(target_arch = "aarch64", target_endian = "little"))] {
31 use cpu::{GetFeature as _, arm::Sha512};
32 if let Some(cpu) = cpu.get_feature() {
33 sha2_64_ffi!(unsafe { Sha512 => sha512_block_data_order_hw }, state, data, cpu)
34 } else {
35 sha2_64_ffi!(unsafe { () => sha512_block_data_order_nohw }, state, data, ())
36 }
37 } else if #[cfg(all(target_arch = "arm", target_endian = "little"))] {
38 use cpu::{GetFeature as _, arm::Neon};
39 if let Some(cpu) = cpu.get_feature() {
40 sha2_64_ffi!(unsafe { Neon => sha512_block_data_order_neon }, state, data, cpu)
41 } else {
42 sha2_64_ffi!(unsafe { () => sha512_block_data_order_nohw }, state, data, ())
43 }
44 } else if #[cfg(target_arch = "x86_64")] {
45 use cpu::{GetFeature as _, intel::{Avx, IntelCpu}};
46 if let Some(cpu) = cpu.get_feature() {
47 // Pre-Zen AMD CPUs had microcoded SHLD/SHRD which makes the
48 // AVX version slow. We're also unsure of the side channel
49 // ramifications of those microcoded instructions.
50 sha2_64_ffi!(unsafe { (Avx, IntelCpu) => sha512_block_data_order_avx },
51 state, data, cpu);
52 } else {
53 sha2_64_ffi!(unsafe { () => sha512_block_data_order_nohw }, state, data, ())
54 }
55 } else {
56 let _ = cpu; // Unneeded.
57 *state = super::fallback::block_data_order(*state, data)
58 }
59 }
60}
61