1//! This module implements minimal run-time feature detection for x86.
2//!
3//! The features are detected using the `detect_features` function below.
4//! This function uses the CPUID instruction to read the feature flags from the
5//! CPU and encodes them in a `usize` where each bit position represents
6//! whether a feature is available (bit is set) or unavailable (bit is cleared).
7//!
8//! The enum `Feature` is used to map bit positions to feature names, and the
9//! the `__crate::detect::check_for!` macro is used to map string literals (e.g.,
10//! "avx") to these bit positions (e.g., `Feature::avx`).
11//!
12//! The run-time feature detection is performed by the
13//! `__crate::detect::check_for(Feature) -> bool` function. On its first call,
14//! this functions queries the CPU for the available features and stores them
15//! in a global `AtomicUsize` variable. The query is performed by just checking
16//! whether the feature bit in this global variable is set or cleared.
17
18features! {
19 @TARGET: x86;
20 @CFG: any(target_arch = "x86", target_arch = "x86_64");
21 @MACRO_NAME: is_x86_feature_detected;
22 @MACRO_ATTRS:
23 /// A macro to test at *runtime* whether a CPU feature is available on
24 /// x86/x86-64 platforms.
25 ///
26 /// This macro is provided in the standard library and will detect at runtime
27 /// whether the specified CPU feature is detected. This does **not** resolve at
28 /// compile time unless the specified feature is already enabled for the entire
29 /// crate. Runtime detection currently relies mostly on the `cpuid` instruction.
30 ///
31 /// This macro only takes one argument which is a string literal of the feature
32 /// being tested for. The feature names supported are the lowercase versions of
33 /// the ones defined by Intel in [their documentation][docs].
34 ///
35 /// ## Supported arguments
36 ///
37 /// This macro supports the same names that `#[target_feature]` supports. Unlike
38 /// `#[target_feature]`, however, this macro does not support names separated
39 /// with a comma. Instead testing for multiple features must be done through
40 /// separate macro invocations for now.
41 ///
42 /// Supported arguments are:
43 ///
44 /// * `"aes"`
45 /// * `"pclmulqdq"`
46 /// * `"rdrand"`
47 /// * `"rdseed"`
48 /// * `"tsc"`
49 /// * `"mmx"`
50 /// * `"sse"`
51 /// * `"sse2"`
52 /// * `"sse3"`
53 /// * `"ssse3"`
54 /// * `"sse4.1"`
55 /// * `"sse4.2"`
56 /// * `"sse4a"`
57 /// * `"sha"`
58 /// * `"avx"`
59 /// * `"avx2"`
60 /// * `"avx512f"`
61 /// * `"avx512cd"`
62 /// * `"avx512er"`
63 /// * `"avx512pf"`
64 /// * `"avx512bw"`
65 /// * `"avx512dq"`
66 /// * `"avx512vl"`
67 /// * `"avx512ifma"`
68 /// * `"avx512vbmi"`
69 /// * `"avx512vpopcntdq"`
70 /// * `"avx512vbmi2"`
71 /// * `"gfni"`
72 /// * `"vaes"`
73 /// * `"vpclmulqdq"`
74 /// * `"avx512vnni"`
75 /// * `"avx512bitalg"`
76 /// * `"avx512bf16"`
77 /// * `"avx512vp2intersect"`
78 /// * `"f16c"`
79 /// * `"fma"`
80 /// * `"bmi1"`
81 /// * `"bmi2"`
82 /// * `"abm"`
83 /// * `"lzcnt"`
84 /// * `"tbm"`
85 /// * `"popcnt"`
86 /// * `"fxsr"`
87 /// * `"xsave"`
88 /// * `"xsaveopt"`
89 /// * `"xsaves"`
90 /// * `"xsavec"`
91 /// * `"cmpxchg16b"`
92 /// * `"adx"`
93 /// * `"rtm"`
94 /// * `"movbe"`
95 /// * `"ermsb"`
96 ///
97 /// [docs]: https://software.intel.com/sites/landingpage/IntrinsicsGuide
98 #[stable(feature = "simd_x86", since = "1.27.0")]
99 @BIND_FEATURE_NAME: "abm"; "lzcnt"; // abm is a synonym for lzcnt
100 @BIND_FEATURE_NAME: "avx512gfni"; "gfni"; #[deprecated(since = "1.67.0", note = "the `avx512gfni` feature has been renamed to `gfni`")];
101 @BIND_FEATURE_NAME: "avx512vaes"; "vaes"; #[deprecated(since = "1.67.0", note = "the `avx512vaes` feature has been renamed to `vaes`")];
102 @BIND_FEATURE_NAME: "avx512vpclmulqdq"; "vpclmulqdq"; #[deprecated(since = "1.67.0", note = "the `avx512vpclmulqdq` feature has been renamed to `vpclmulqdq`")];
103 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] aes: "aes";
104 /// AES (Advanced Encryption Standard New Instructions AES-NI)
105 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] pclmulqdq: "pclmulqdq";
106 /// CLMUL (Carry-less Multiplication)
107 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdrand: "rdrand";
108 /// RDRAND
109 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdseed: "rdseed";
110 /// RDSEED
111 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tsc: "tsc";
112 /// TSC (Time Stamp Counter)
113 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] mmx: "mmx";
114 /// MMX (MultiMedia eXtensions)
115 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse: "sse";
116 /// SSE (Streaming SIMD Extensions)
117 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse2: "sse2";
118 /// SSE2 (Streaming SIMD Extensions 2)
119 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse3: "sse3";
120 /// SSE3 (Streaming SIMD Extensions 3)
121 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] ssse3: "ssse3";
122 /// SSSE3 (Supplemental Streaming SIMD Extensions 3)
123 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_1: "sse4.1";
124 /// SSE4.1 (Streaming SIMD Extensions 4.1)
125 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_2: "sse4.2";
126 /// SSE4.2 (Streaming SIMD Extensions 4.2)
127 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4a: "sse4a";
128 /// SSE4a (Streaming SIMD Extensions 4a)
129 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sha: "sha";
130 /// SHA
131 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx: "avx";
132 /// AVX (Advanced Vector Extensions)
133 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx2: "avx2";
134 /// AVX2 (Advanced Vector Extensions 2)
135 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512f: "avx512f" ;
136 /// AVX-512 F (Foundation)
137 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512cd: "avx512cd" ;
138 /// AVX-512 CD (Conflict Detection Instructions)
139 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512er: "avx512er";
140 /// AVX-512 ER (Expo nential and Reciprocal Instructions)
141 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512pf: "avx512pf";
142 /// AVX-512 PF (Prefetch Instructions)
143 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bw: "avx512bw";
144 /// AVX-512 BW (Byte and Word Instructions)
145 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512dq: "avx512dq";
146 /// AVX-512 DQ (Doubleword and Quadword)
147 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vl: "avx512vl";
148 /// AVX-512 VL (Vector Length Extensions)
149 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512ifma: "avx512ifma";
150 /// AVX-512 IFMA (Integer Fused Multiply Add)
151 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi: "avx512vbmi";
152 /// AVX-512 VBMI (Vector Byte Manipulation Instructions)
153 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vpopcntdq: "avx512vpopcntdq";
154 /// AVX-512 VPOPCNTDQ (Vector Population Count Doubleword and
155 /// Quadword)
156 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi2: "avx512vbmi2";
157 /// AVX-512 VBMI2 (Additional byte, word, dword and qword capabilities)
158 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] gfni: "gfni";
159 /// AVX-512 GFNI (Galois Field New Instruction)
160 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] vaes: "vaes";
161 /// AVX-512 VAES (Vector AES instruction)
162 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] vpclmulqdq: "vpclmulqdq";
163 /// AVX-512 VPCLMULQDQ (Vector PCLMULQDQ instructions)
164 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vnni: "avx512vnni";
165 /// AVX-512 VNNI (Vector Neural Network Instructions)
166 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bitalg: "avx512bitalg";
167 /// AVX-512 BITALG (Support for VPOPCNT\[B,W\] and VPSHUFBITQMB)
168 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bf16: "avx512bf16";
169 /// AVX-512 BF16 (BFLOAT16 instructions)
170 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vp2intersect: "avx512vp2intersect";
171 /// AVX-512 P2INTERSECT
172 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] f16c: "f16c";
173 /// F16C (Conversions between IEEE-754 `binary16` and `binary32` formats)
174 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fma: "fma";
175 /// FMA (Fused Multiply Add)
176 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi1: "bmi1" ;
177 /// BMI1 (Bit Manipulation Instructions 1)
178 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi2: "bmi2" ;
179 /// BMI2 (Bit Manipulation Instructions 2)
180 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] lzcnt: "lzcnt";
181 /// ABM (Advanced Bit Manipulation) / LZCNT (Leading Zero Count)
182 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tbm: "tbm";
183 /// TBM (Trailing Bit Manipulation)
184 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] popcnt: "popcnt";
185 /// POPCNT (Population Count)
186 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fxsr: "fxsr";
187 /// FXSR (Floating-point context fast save and restore)
188 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsave: "xsave";
189 /// XSAVE (Save Processor Extended States)
190 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaveopt: "xsaveopt";
191 /// XSAVEOPT (Save Processor Extended States Optimized)
192 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaves: "xsaves";
193 /// XSAVES (Save Processor Extended States Supervisor)
194 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsavec: "xsavec";
195 /// XSAVEC (Save Processor Extended States Compacted)
196 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] cmpxchg16b: "cmpxchg16b";
197 /// CMPXCH16B (16-byte compare-and-swap instruction)
198 @FEATURE: #[stable(feature = "simd_x86_adx", since = "1.33.0")] adx: "adx";
199 /// ADX, Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
200 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rtm: "rtm";
201 /// RTM, Intel (Restricted Transactional Memory)
202 @FEATURE: #[stable(feature = "movbe_target_feature", since = "1.67.0")] movbe: "movbe";
203 /// MOVBE (Move Data After Swapping Bytes)
204 @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] ermsb: "ermsb";
205 /// ERMSB, Enhanced REP MOVSB and STOSB
206}
207