1/// Alliance Memory AS4C16M32MSA SDRAM
2#[allow(unused)]
3
4pub mod as4c16m32msa_6 {
5 use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming};
6
7 const BURST_LENGTH_1: u16 = 0x0000;
8 const BURST_LENGTH_2: u16 = 0x0001;
9 const BURST_LENGTH_4: u16 = 0x0002;
10 const BURST_LENGTH_8: u16 = 0x0004;
11 const BURST_TYPE_SEQUENTIAL: u16 = 0x0000;
12 const BURST_TYPE_INTERLEAVED: u16 = 0x0008;
13 const CAS_LATENCY_1: u16 = 0x0010;
14 const CAS_LATENCY_2: u16 = 0x0020;
15 const CAS_LATENCY_3: u16 = 0x0030;
16 const OPERATING_MODE_STANDARD: u16 = 0x0000;
17 const WRITEBURST_MODE_PROGRAMMED: u16 = 0x0000;
18 const WRITEBURST_MODE_SINGLE: u16 = 0x0200;
19
20 /// As4c16m32msa
21 #[derive(Clone, Copy, Debug, PartialEq)]
22 pub struct As4c16m32msa {}
23
24 impl SdramChip for As4c16m32msa {
25 /// Value of the mode register
26 const MODE_REGISTER: u16 = BURST_LENGTH_1
27 | BURST_TYPE_SEQUENTIAL
28 | CAS_LATENCY_3
29 | OPERATING_MODE_STANDARD
30 | WRITEBURST_MODE_SINGLE;
31
32 // 166MHz = 6.024ns per clock cycle
33
34 /// Timing Parameters
35 const TIMING: SdramTiming = SdramTiming {
36 startup_delay_ns: 200_000, // 200 µs
37 max_sd_clock_hz: 166_000_000, // 166 MHz
38 refresh_period_ns: 7_813, // 64ms / (8192 rows) = 7812.5ns
39 mode_register_to_active: 2, // tMRD = 2 cycles
40 exit_self_refresh: 14, // tXSR = 80ns
41 active_to_precharge: 8, // tRAS = 48ns
42 row_cycle: 10, // tRC = 60ns
43 row_precharge: 3, // tRP = 18ns
44 row_to_column: 3, // tRCD = 18ns
45 };
46
47 /// SDRAM controller configuration
48 const CONFIG: SdramConfiguration = SdramConfiguration {
49 column_bits: 9, // A0-A8
50 row_bits: 13, // A0-A12
51 memory_data_width: 32, // 32-bit
52 internal_banks: 4, // 4 internal banks
53 cas_latency: 3, // CAS latency = 3
54 write_protection: false,
55 read_burst: true,
56 read_pipe_delay_cycles: 0,
57 };
58 }
59}
60