1/// ISI IS42S16400J SDRAM
2#[allow(unused)]
3
4/// Speed Grade 7
5pub mod is42s16400j_7 {
6 use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming};
7
8 const BURST_LENGTH_1: u16 = 0x0000;
9 const BURST_LENGTH_2: u16 = 0x0001;
10 const BURST_LENGTH_4: u16 = 0x0002;
11 const BURST_LENGTH_8: u16 = 0x0004;
12 const BURST_TYPE_SEQUENTIAL: u16 = 0x0000;
13 const BURST_TYPE_INTERLEAVED: u16 = 0x0008;
14 const CAS_LATENCY_2: u16 = 0x0020;
15 const CAS_LATENCY_3: u16 = 0x0030;
16 const OPERATING_MODE_STANDARD: u16 = 0x0000;
17 const WRITEBURST_MODE_PROGRAMMED: u16 = 0x0000;
18 const WRITEBURST_MODE_SINGLE: u16 = 0x0200;
19
20 /// Is42s16400j with Speed Grade 7
21 ///
22 /// Configured with CAS latency 2, limited 100MHz
23 #[derive(Clone, Copy, Debug, PartialEq)]
24 pub struct Is42s16400j {}
25
26 impl SdramChip for Is42s16400j {
27 /// Value of the mode register
28 const MODE_REGISTER: u16 = BURST_LENGTH_1
29 | BURST_TYPE_SEQUENTIAL
30 | CAS_LATENCY_2
31 | OPERATING_MODE_STANDARD
32 | WRITEBURST_MODE_SINGLE;
33
34 /// Timing Parameters
35 const TIMING: SdramTiming = SdramTiming {
36 startup_delay_ns: 100_000, // 100 µs
37 max_sd_clock_hz: 100_000_000, // 100 MHz
38 refresh_period_ns: 15_625, // 64ms / (4096 rows) = 15625ns
39 mode_register_to_active: 2, // tMRD = 2 cycles
40 exit_self_refresh: 7, // tXSR = 70ns
41 active_to_precharge: 4, // tRAS = 42ns
42 row_cycle: 7, // tRC = 63ns
43 row_precharge: 2, // tRP = 15ns
44 row_to_column: 2, // tRCD = 15ns
45 };
46
47 /// SDRAM controller configuration
48 const CONFIG: SdramConfiguration = SdramConfiguration {
49 column_bits: 8,
50 row_bits: 12,
51 memory_data_width: 16, // 16-bit
52 internal_banks: 4, // 4 internal banks
53 cas_latency: 2, // CAS latency = 2
54 write_protection: false,
55 read_burst: true,
56 read_pipe_delay_cycles: 0,
57 };
58 }
59}
60