1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Flexible memory controller
4//!
5//! With the caveat that SDCMR:MRD is 13-bits wide on these parts:
6//!
7//! Used by: stm32f469, stm32f479
8//! Used by: stm32f745, stm32f765, stm32f7x6, stm32f7x7, stm32f7x9
9//!
10//! With the caveat that BCR1:{FMCEN,BMAP} are not included:
11//!
12//! Used by: stm32h743, stm32h743v, stm32h747cm4, stm32h747cm7, stm32h753, stm32h753v
13
14use super::super::register::{RORegister, RWRegister};
15#[cfg(not(feature = "nosync"))]
16use core::marker::PhantomData;
17
18/// SRAM/NOR-Flash chip-select control register 1
19pub mod BCR1 {
20
21 /// CCLKEN
22 pub mod CCLKEN {
23 /// Offset (20 bits)
24 pub const offset: u32 = 20;
25 /// Mask (1 bit: 1 << 20)
26 pub const mask: u32 = 1 << offset;
27 /// Read-only values (empty)
28 pub mod R {}
29 /// Write-only values (empty)
30 pub mod W {}
31 /// Read-write values
32 pub mod RW {
33
34 /// 0b1: The FMC_CLK is only generated during the synchronous memory access (read/write transaction)
35 pub const Enabled: u32 = 0b1;
36
37 /// 0b0: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set
38 pub const Disabled: u32 = 0b0;
39 }
40 }
41
42 /// CBURSTRW
43 pub mod CBURSTRW {
44 /// Offset (19 bits)
45 pub const offset: u32 = 19;
46 /// Mask (1 bit: 1 << 19)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values
53 pub mod RW {
54
55 /// 0b1: Write operations are performed in synchronous mode
56 pub const Enabled: u32 = 0b1;
57
58 /// 0b0: Write operations are always performed in asynchronous mode
59 pub const Disabled: u32 = 0b0;
60 }
61 }
62
63 /// ASYNCWAIT
64 pub mod ASYNCWAIT {
65 /// Offset (15 bits)
66 pub const offset: u32 = 15;
67 /// Mask (1 bit: 1 << 15)
68 pub const mask: u32 = 1 << offset;
69 /// Read-only values (empty)
70 pub mod R {}
71 /// Write-only values (empty)
72 pub mod W {}
73 /// Read-write values
74 pub mod RW {
75
76 /// 0b0: Wait signal not used in asynchronous mode
77 pub const Disabled: u32 = 0b0;
78
79 /// 0b1: Wait signal used even in asynchronous mode
80 pub const Enabled: u32 = 0b1;
81 }
82 }
83
84 /// EXTMOD
85 pub mod EXTMOD {
86 /// Offset (14 bits)
87 pub const offset: u32 = 14;
88 /// Mask (1 bit: 1 << 14)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values
95 pub mod RW {
96
97 /// 0b0: Values inside the FMC_BWTR are not taken into account
98 pub const Disabled: u32 = 0b0;
99
100 /// 0b1: Values inside the FMC_BWTR are taken into account
101 pub const Enabled: u32 = 0b1;
102 }
103 }
104
105 /// WAITEN
106 pub mod WAITEN {
107 /// Offset (13 bits)
108 pub const offset: u32 = 13;
109 /// Mask (1 bit: 1 << 13)
110 pub const mask: u32 = 1 << offset;
111 /// Read-only values (empty)
112 pub mod R {}
113 /// Write-only values (empty)
114 pub mod W {}
115 /// Read-write values
116 pub mod RW {
117
118 /// 0b0: Values inside the FMC_BWTR are taken into account
119 pub const Disabled: u32 = 0b0;
120
121 /// 0b1: NWAIT signal enabled
122 pub const Enabled: u32 = 0b1;
123 }
124 }
125
126 /// WREN
127 pub mod WREN {
128 /// Offset (12 bits)
129 pub const offset: u32 = 12;
130 /// Mask (1 bit: 1 << 12)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values
137 pub mod RW {
138
139 /// 0b0: Write operations disabled for the bank by the FMC
140 pub const Disabled: u32 = 0b0;
141
142 /// 0b1: Write operations enabled for the bank by the FMC
143 pub const Enabled: u32 = 0b1;
144 }
145 }
146
147 /// WAITCFG
148 pub mod WAITCFG {
149 /// Offset (11 bits)
150 pub const offset: u32 = 11;
151 /// Mask (1 bit: 1 << 11)
152 pub const mask: u32 = 1 << offset;
153 /// Read-only values (empty)
154 pub mod R {}
155 /// Write-only values (empty)
156 pub mod W {}
157 /// Read-write values
158 pub mod RW {
159
160 /// 0b0: NWAIT signal is active one data cycle before wait state
161 pub const BeforeWaitState: u32 = 0b0;
162
163 /// 0b1: NWAIT signal is active during wait state
164 pub const DuringWaitState: u32 = 0b1;
165 }
166 }
167
168 /// WAITPOL
169 pub mod WAITPOL {
170 /// Offset (9 bits)
171 pub const offset: u32 = 9;
172 /// Mask (1 bit: 1 << 9)
173 pub const mask: u32 = 1 << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values
179 pub mod RW {
180
181 /// 0b0: NWAIT active low
182 pub const ActiveLow: u32 = 0b0;
183
184 /// 0b1: NWAIT active high
185 pub const ActiveHigh: u32 = 0b1;
186 }
187 }
188
189 /// BURSTEN
190 pub mod BURSTEN {
191 /// Offset (8 bits)
192 pub const offset: u32 = 8;
193 /// Mask (1 bit: 1 << 8)
194 pub const mask: u32 = 1 << offset;
195 /// Read-only values (empty)
196 pub mod R {}
197 /// Write-only values (empty)
198 pub mod W {}
199 /// Read-write values
200 pub mod RW {
201
202 /// 0b0: Burst mode disabled
203 pub const Disabled: u32 = 0b0;
204
205 /// 0b1: Burst mode enabled
206 pub const Enabled: u32 = 0b1;
207 }
208 }
209
210 /// FACCEN
211 pub mod FACCEN {
212 /// Offset (6 bits)
213 pub const offset: u32 = 6;
214 /// Mask (1 bit: 1 << 6)
215 pub const mask: u32 = 1 << offset;
216 /// Read-only values (empty)
217 pub mod R {}
218 /// Write-only values (empty)
219 pub mod W {}
220 /// Read-write values
221 pub mod RW {
222
223 /// 0b0: Corresponding NOR Flash memory access is disabled
224 pub const Disabled: u32 = 0b0;
225
226 /// 0b1: Corresponding NOR Flash memory access is enabled
227 pub const Enabled: u32 = 0b1;
228 }
229 }
230
231 /// MWID
232 pub mod MWID {
233 /// Offset (4 bits)
234 pub const offset: u32 = 4;
235 /// Mask (2 bits: 0b11 << 4)
236 pub const mask: u32 = 0b11 << offset;
237 /// Read-only values (empty)
238 pub mod R {}
239 /// Write-only values (empty)
240 pub mod W {}
241 /// Read-write values
242 pub mod RW {
243
244 /// 0b00: Memory data bus width 8 bits
245 pub const Bits8: u32 = 0b00;
246
247 /// 0b01: Memory data bus width 16 bits
248 pub const Bits16: u32 = 0b01;
249
250 /// 0b10: Memory data bus width 32 bits
251 pub const Bits32: u32 = 0b10;
252 }
253 }
254
255 /// MTYP
256 pub mod MTYP {
257 /// Offset (2 bits)
258 pub const offset: u32 = 2;
259 /// Mask (2 bits: 0b11 << 2)
260 pub const mask: u32 = 0b11 << offset;
261 /// Read-only values (empty)
262 pub mod R {}
263 /// Write-only values (empty)
264 pub mod W {}
265 /// Read-write values
266 pub mod RW {
267
268 /// 0b00: SRAM memory type
269 pub const SRAM: u32 = 0b00;
270
271 /// 0b01: PSRAM (CRAM) memory type
272 pub const PSRAM: u32 = 0b01;
273
274 /// 0b10: NOR Flash/OneNAND Flash
275 pub const Flash: u32 = 0b10;
276 }
277 }
278
279 /// MUXEN
280 pub mod MUXEN {
281 /// Offset (1 bits)
282 pub const offset: u32 = 1;
283 /// Mask (1 bit: 1 << 1)
284 pub const mask: u32 = 1 << offset;
285 /// Read-only values (empty)
286 pub mod R {}
287 /// Write-only values (empty)
288 pub mod W {}
289 /// Read-write values
290 pub mod RW {
291
292 /// 0b0: Address/Data non-multiplexed
293 pub const Disabled: u32 = 0b0;
294
295 /// 0b1: Address/Data multiplexed on databus
296 pub const Enabled: u32 = 0b1;
297 }
298 }
299
300 /// MBKEN
301 pub mod MBKEN {
302 /// Offset (0 bits)
303 pub const offset: u32 = 0;
304 /// Mask (1 bit: 1 << 0)
305 pub const mask: u32 = 1 << offset;
306 /// Read-only values (empty)
307 pub mod R {}
308 /// Write-only values (empty)
309 pub mod W {}
310 /// Read-write values
311 pub mod RW {
312
313 /// 0b0: Corresponding memory bank is disabled
314 pub const Disabled: u32 = 0b0;
315
316 /// 0b1: Corresponding memory bank is enabled
317 pub const Enabled: u32 = 0b1;
318 }
319 }
320
321 /// WRAPMOD
322 pub mod WRAPMOD {
323 /// Offset (10 bits)
324 pub const offset: u32 = 10;
325 /// Mask (1 bit: 1 << 10)
326 pub const mask: u32 = 1 << offset;
327 /// Read-only values (empty)
328 pub mod R {}
329 /// Write-only values (empty)
330 pub mod W {}
331 /// Read-write values (empty)
332 pub mod RW {}
333 }
334
335 /// Write FIFO disable
336 pub mod WFDIS {
337 /// Offset (21 bits)
338 pub const offset: u32 = 21;
339 /// Mask (1 bit: 1 << 21)
340 pub const mask: u32 = 1 << offset;
341 /// Read-only values (empty)
342 pub mod R {}
343 /// Write-only values (empty)
344 pub mod W {}
345 /// Read-write values
346 pub mod RW {
347
348 /// 0b0: Write FIFO enabled
349 pub const Enabled: u32 = 0b0;
350
351 /// 0b1: Write FIFO disabled
352 pub const Disabled: u32 = 0b1;
353 }
354 }
355
356 /// CRAM page size
357 pub mod CPSIZE {
358 /// Offset (16 bits)
359 pub const offset: u32 = 16;
360 /// Mask (3 bits: 0b111 << 16)
361 pub const mask: u32 = 0b111 << offset;
362 /// Read-only values (empty)
363 pub mod R {}
364 /// Write-only values (empty)
365 pub mod W {}
366 /// Read-write values
367 pub mod RW {
368
369 /// 0b000: No burst split when crossing page boundary
370 pub const NoBurstSplit: u32 = 0b000;
371
372 /// 0b001: 128 bytes CRAM page size
373 pub const Bytes128: u32 = 0b001;
374
375 /// 0b010: 256 bytes CRAM page size
376 pub const Bytes256: u32 = 0b010;
377
378 /// 0b011: 512 bytes CRAM page size
379 pub const Bytes512: u32 = 0b011;
380
381 /// 0b100: 1024 bytes CRAM page size
382 pub const Bytes1024: u32 = 0b100;
383 }
384 }
385}
386
387/// SRAM/NOR-Flash chip-select timing register 1
388pub mod BTR1 {
389
390 /// ACCMOD
391 pub mod ACCMOD {
392 /// Offset (28 bits)
393 pub const offset: u32 = 28;
394 /// Mask (2 bits: 0b11 << 28)
395 pub const mask: u32 = 0b11 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values
401 pub mod RW {
402
403 /// 0b00: Access mode A
404 pub const A: u32 = 0b00;
405
406 /// 0b01: Access mode B
407 pub const B: u32 = 0b01;
408
409 /// 0b10: Access mode C
410 pub const C: u32 = 0b10;
411
412 /// 0b11: Access mode D
413 pub const D: u32 = 0b11;
414 }
415 }
416
417 /// DATLAT
418 pub mod DATLAT {
419 /// Offset (24 bits)
420 pub const offset: u32 = 24;
421 /// Mask (4 bits: 0b1111 << 24)
422 pub const mask: u32 = 0b1111 << offset;
423 /// Read-only values (empty)
424 pub mod R {}
425 /// Write-only values (empty)
426 pub mod W {}
427 /// Read-write values (empty)
428 pub mod RW {}
429 }
430
431 /// CLKDIV
432 pub mod CLKDIV {
433 /// Offset (20 bits)
434 pub const offset: u32 = 20;
435 /// Mask (4 bits: 0b1111 << 20)
436 pub const mask: u32 = 0b1111 << offset;
437 /// Read-only values (empty)
438 pub mod R {}
439 /// Write-only values (empty)
440 pub mod W {}
441 /// Read-write values (empty)
442 pub mod RW {}
443 }
444
445 /// BUSTURN
446 pub mod BUSTURN {
447 /// Offset (16 bits)
448 pub const offset: u32 = 16;
449 /// Mask (4 bits: 0b1111 << 16)
450 pub const mask: u32 = 0b1111 << offset;
451 /// Read-only values (empty)
452 pub mod R {}
453 /// Write-only values (empty)
454 pub mod W {}
455 /// Read-write values (empty)
456 pub mod RW {}
457 }
458
459 /// DATAST
460 pub mod DATAST {
461 /// Offset (8 bits)
462 pub const offset: u32 = 8;
463 /// Mask (8 bits: 0xff << 8)
464 pub const mask: u32 = 0xff << offset;
465 /// Read-only values (empty)
466 pub mod R {}
467 /// Write-only values (empty)
468 pub mod W {}
469 /// Read-write values (empty)
470 pub mod RW {}
471 }
472
473 /// ADDHLD
474 pub mod ADDHLD {
475 /// Offset (4 bits)
476 pub const offset: u32 = 4;
477 /// Mask (4 bits: 0b1111 << 4)
478 pub const mask: u32 = 0b1111 << offset;
479 /// Read-only values (empty)
480 pub mod R {}
481 /// Write-only values (empty)
482 pub mod W {}
483 /// Read-write values (empty)
484 pub mod RW {}
485 }
486
487 /// ADDSET
488 pub mod ADDSET {
489 /// Offset (0 bits)
490 pub const offset: u32 = 0;
491 /// Mask (4 bits: 0b1111 << 0)
492 pub const mask: u32 = 0b1111 << offset;
493 /// Read-only values (empty)
494 pub mod R {}
495 /// Write-only values (empty)
496 pub mod W {}
497 /// Read-write values (empty)
498 pub mod RW {}
499 }
500}
501
502/// SRAM/NOR-Flash chip-select timing register 1
503pub mod BTR2 {
504 pub use super::BTR1::ACCMOD;
505 pub use super::BTR1::ADDHLD;
506 pub use super::BTR1::ADDSET;
507 pub use super::BTR1::BUSTURN;
508 pub use super::BTR1::CLKDIV;
509 pub use super::BTR1::DATAST;
510 pub use super::BTR1::DATLAT;
511}
512
513/// SRAM/NOR-Flash chip-select timing register 1
514pub mod BTR3 {
515 pub use super::BTR1::ACCMOD;
516 pub use super::BTR1::ADDHLD;
517 pub use super::BTR1::ADDSET;
518 pub use super::BTR1::BUSTURN;
519 pub use super::BTR1::CLKDIV;
520 pub use super::BTR1::DATAST;
521 pub use super::BTR1::DATLAT;
522}
523
524/// SRAM/NOR-Flash chip-select timing register 1
525pub mod BTR4 {
526 pub use super::BTR1::ACCMOD;
527 pub use super::BTR1::ADDHLD;
528 pub use super::BTR1::ADDSET;
529 pub use super::BTR1::BUSTURN;
530 pub use super::BTR1::CLKDIV;
531 pub use super::BTR1::DATAST;
532 pub use super::BTR1::DATLAT;
533}
534
535/// SRAM/NOR-Flash chip-select control register 2
536pub mod BCR2 {
537
538 /// CBURSTRW
539 pub mod CBURSTRW {
540 /// Offset (19 bits)
541 pub const offset: u32 = 19;
542 /// Mask (1 bit: 1 << 19)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values
549 pub mod RW {
550
551 /// 0b1: Write operations are performed in synchronous mode
552 pub const Enabled: u32 = 0b1;
553
554 /// 0b0: Write operations are always performed in asynchronous mode
555 pub const Disabled: u32 = 0b0;
556 }
557 }
558
559 /// ASYNCWAIT
560 pub mod ASYNCWAIT {
561 /// Offset (15 bits)
562 pub const offset: u32 = 15;
563 /// Mask (1 bit: 1 << 15)
564 pub const mask: u32 = 1 << offset;
565 /// Read-only values (empty)
566 pub mod R {}
567 /// Write-only values (empty)
568 pub mod W {}
569 /// Read-write values
570 pub mod RW {
571
572 /// 0b0: Wait signal not used in asynchronous mode
573 pub const Disabled: u32 = 0b0;
574
575 /// 0b1: Wait signal used even in asynchronous mode
576 pub const Enabled: u32 = 0b1;
577 }
578 }
579
580 /// EXTMOD
581 pub mod EXTMOD {
582 /// Offset (14 bits)
583 pub const offset: u32 = 14;
584 /// Mask (1 bit: 1 << 14)
585 pub const mask: u32 = 1 << offset;
586 /// Read-only values (empty)
587 pub mod R {}
588 /// Write-only values (empty)
589 pub mod W {}
590 /// Read-write values
591 pub mod RW {
592
593 /// 0b0: Values inside the FMC_BWTR are not taken into account
594 pub const Disabled: u32 = 0b0;
595
596 /// 0b1: Values inside the FMC_BWTR are taken into account
597 pub const Enabled: u32 = 0b1;
598 }
599 }
600
601 /// WAITEN
602 pub mod WAITEN {
603 /// Offset (13 bits)
604 pub const offset: u32 = 13;
605 /// Mask (1 bit: 1 << 13)
606 pub const mask: u32 = 1 << offset;
607 /// Read-only values (empty)
608 pub mod R {}
609 /// Write-only values (empty)
610 pub mod W {}
611 /// Read-write values
612 pub mod RW {
613
614 /// 0b0: Values inside the FMC_BWTR are taken into account
615 pub const Disabled: u32 = 0b0;
616
617 /// 0b1: NWAIT signal enabled
618 pub const Enabled: u32 = 0b1;
619 }
620 }
621
622 /// WREN
623 pub mod WREN {
624 /// Offset (12 bits)
625 pub const offset: u32 = 12;
626 /// Mask (1 bit: 1 << 12)
627 pub const mask: u32 = 1 << offset;
628 /// Read-only values (empty)
629 pub mod R {}
630 /// Write-only values (empty)
631 pub mod W {}
632 /// Read-write values
633 pub mod RW {
634
635 /// 0b0: Write operations disabled for the bank by the FMC
636 pub const Disabled: u32 = 0b0;
637
638 /// 0b1: Write operations enabled for the bank by the FMC
639 pub const Enabled: u32 = 0b1;
640 }
641 }
642
643 /// WAITCFG
644 pub mod WAITCFG {
645 /// Offset (11 bits)
646 pub const offset: u32 = 11;
647 /// Mask (1 bit: 1 << 11)
648 pub const mask: u32 = 1 << offset;
649 /// Read-only values (empty)
650 pub mod R {}
651 /// Write-only values (empty)
652 pub mod W {}
653 /// Read-write values
654 pub mod RW {
655
656 /// 0b0: NWAIT signal is active one data cycle before wait state
657 pub const BeforeWaitState: u32 = 0b0;
658
659 /// 0b1: NWAIT signal is active during wait state
660 pub const DuringWaitState: u32 = 0b1;
661 }
662 }
663
664 /// WRAPMOD
665 pub mod WRAPMOD {
666 /// Offset (10 bits)
667 pub const offset: u32 = 10;
668 /// Mask (1 bit: 1 << 10)
669 pub const mask: u32 = 1 << offset;
670 /// Read-only values (empty)
671 pub mod R {}
672 /// Write-only values (empty)
673 pub mod W {}
674 /// Read-write values (empty)
675 pub mod RW {}
676 }
677
678 /// WAITPOL
679 pub mod WAITPOL {
680 /// Offset (9 bits)
681 pub const offset: u32 = 9;
682 /// Mask (1 bit: 1 << 9)
683 pub const mask: u32 = 1 << offset;
684 /// Read-only values (empty)
685 pub mod R {}
686 /// Write-only values (empty)
687 pub mod W {}
688 /// Read-write values
689 pub mod RW {
690
691 /// 0b0: NWAIT active low
692 pub const ActiveLow: u32 = 0b0;
693
694 /// 0b1: NWAIT active high
695 pub const ActiveHigh: u32 = 0b1;
696 }
697 }
698
699 /// BURSTEN
700 pub mod BURSTEN {
701 /// Offset (8 bits)
702 pub const offset: u32 = 8;
703 /// Mask (1 bit: 1 << 8)
704 pub const mask: u32 = 1 << offset;
705 /// Read-only values (empty)
706 pub mod R {}
707 /// Write-only values (empty)
708 pub mod W {}
709 /// Read-write values
710 pub mod RW {
711
712 /// 0b0: Burst mode disabled
713 pub const Disabled: u32 = 0b0;
714
715 /// 0b1: Burst mode enabled
716 pub const Enabled: u32 = 0b1;
717 }
718 }
719
720 /// FACCEN
721 pub mod FACCEN {
722 /// Offset (6 bits)
723 pub const offset: u32 = 6;
724 /// Mask (1 bit: 1 << 6)
725 pub const mask: u32 = 1 << offset;
726 /// Read-only values (empty)
727 pub mod R {}
728 /// Write-only values (empty)
729 pub mod W {}
730 /// Read-write values
731 pub mod RW {
732
733 /// 0b0: Corresponding NOR Flash memory access is disabled
734 pub const Disabled: u32 = 0b0;
735
736 /// 0b1: Corresponding NOR Flash memory access is enabled
737 pub const Enabled: u32 = 0b1;
738 }
739 }
740
741 /// MWID
742 pub mod MWID {
743 /// Offset (4 bits)
744 pub const offset: u32 = 4;
745 /// Mask (2 bits: 0b11 << 4)
746 pub const mask: u32 = 0b11 << offset;
747 /// Read-only values (empty)
748 pub mod R {}
749 /// Write-only values (empty)
750 pub mod W {}
751 /// Read-write values
752 pub mod RW {
753
754 /// 0b00: Memory data bus width 8 bits
755 pub const Bits8: u32 = 0b00;
756
757 /// 0b01: Memory data bus width 16 bits
758 pub const Bits16: u32 = 0b01;
759
760 /// 0b10: Memory data bus width 32 bits
761 pub const Bits32: u32 = 0b10;
762 }
763 }
764
765 /// MTYP
766 pub mod MTYP {
767 /// Offset (2 bits)
768 pub const offset: u32 = 2;
769 /// Mask (2 bits: 0b11 << 2)
770 pub const mask: u32 = 0b11 << offset;
771 /// Read-only values (empty)
772 pub mod R {}
773 /// Write-only values (empty)
774 pub mod W {}
775 /// Read-write values
776 pub mod RW {
777
778 /// 0b00: SRAM memory type
779 pub const SRAM: u32 = 0b00;
780
781 /// 0b01: PSRAM (CRAM) memory type
782 pub const PSRAM: u32 = 0b01;
783
784 /// 0b10: NOR Flash/OneNAND Flash
785 pub const Flash: u32 = 0b10;
786 }
787 }
788
789 /// MUXEN
790 pub mod MUXEN {
791 /// Offset (1 bits)
792 pub const offset: u32 = 1;
793 /// Mask (1 bit: 1 << 1)
794 pub const mask: u32 = 1 << offset;
795 /// Read-only values (empty)
796 pub mod R {}
797 /// Write-only values (empty)
798 pub mod W {}
799 /// Read-write values
800 pub mod RW {
801
802 /// 0b0: Address/Data non-multiplexed
803 pub const Disabled: u32 = 0b0;
804
805 /// 0b1: Address/Data multiplexed on databus
806 pub const Enabled: u32 = 0b1;
807 }
808 }
809
810 /// MBKEN
811 pub mod MBKEN {
812 /// Offset (0 bits)
813 pub const offset: u32 = 0;
814 /// Mask (1 bit: 1 << 0)
815 pub const mask: u32 = 1 << offset;
816 /// Read-only values (empty)
817 pub mod R {}
818 /// Write-only values (empty)
819 pub mod W {}
820 /// Read-write values
821 pub mod RW {
822
823 /// 0b0: Corresponding memory bank is disabled
824 pub const Disabled: u32 = 0b0;
825
826 /// 0b1: Corresponding memory bank is enabled
827 pub const Enabled: u32 = 0b1;
828 }
829 }
830
831 /// CRAM page size
832 pub mod CPSIZE {
833 /// Offset (16 bits)
834 pub const offset: u32 = 16;
835 /// Mask (3 bits: 0b111 << 16)
836 pub const mask: u32 = 0b111 << offset;
837 /// Read-only values (empty)
838 pub mod R {}
839 /// Write-only values (empty)
840 pub mod W {}
841 /// Read-write values
842 pub mod RW {
843
844 /// 0b000: No burst split when crossing page boundary
845 pub const NoBurstSplit: u32 = 0b000;
846
847 /// 0b001: 128 bytes CRAM page size
848 pub const Bytes128: u32 = 0b001;
849
850 /// 0b010: 256 bytes CRAM page size
851 pub const Bytes256: u32 = 0b010;
852
853 /// 0b011: 512 bytes CRAM page size
854 pub const Bytes512: u32 = 0b011;
855
856 /// 0b100: 1024 bytes CRAM page size
857 pub const Bytes1024: u32 = 0b100;
858 }
859 }
860}
861
862/// SRAM/NOR-Flash chip-select control register 2
863pub mod BCR3 {
864 pub use super::BCR2::ASYNCWAIT;
865 pub use super::BCR2::BURSTEN;
866 pub use super::BCR2::CBURSTRW;
867 pub use super::BCR2::CPSIZE;
868 pub use super::BCR2::EXTMOD;
869 pub use super::BCR2::FACCEN;
870 pub use super::BCR2::MBKEN;
871 pub use super::BCR2::MTYP;
872 pub use super::BCR2::MUXEN;
873 pub use super::BCR2::MWID;
874 pub use super::BCR2::WAITCFG;
875 pub use super::BCR2::WAITEN;
876 pub use super::BCR2::WAITPOL;
877 pub use super::BCR2::WRAPMOD;
878 pub use super::BCR2::WREN;
879}
880
881/// SRAM/NOR-Flash chip-select control register 2
882pub mod BCR4 {
883 pub use super::BCR2::ASYNCWAIT;
884 pub use super::BCR2::BURSTEN;
885 pub use super::BCR2::CBURSTRW;
886 pub use super::BCR2::CPSIZE;
887 pub use super::BCR2::EXTMOD;
888 pub use super::BCR2::FACCEN;
889 pub use super::BCR2::MBKEN;
890 pub use super::BCR2::MTYP;
891 pub use super::BCR2::MUXEN;
892 pub use super::BCR2::MWID;
893 pub use super::BCR2::WAITCFG;
894 pub use super::BCR2::WAITEN;
895 pub use super::BCR2::WAITPOL;
896 pub use super::BCR2::WRAPMOD;
897 pub use super::BCR2::WREN;
898}
899
900/// PC Card/NAND Flash control register
901pub mod PCR {
902
903 /// ECCPS
904 pub mod ECCPS {
905 /// Offset (17 bits)
906 pub const offset: u32 = 17;
907 /// Mask (3 bits: 0b111 << 17)
908 pub const mask: u32 = 0b111 << offset;
909 /// Read-only values (empty)
910 pub mod R {}
911 /// Write-only values (empty)
912 pub mod W {}
913 /// Read-write values
914 pub mod RW {
915
916 /// 0b000: ECC page size 256 bytes
917 pub const Bytes256: u32 = 0b000;
918
919 /// 0b001: ECC page size 512 bytes
920 pub const Bytes512: u32 = 0b001;
921
922 /// 0b010: ECC page size 1024 bytes
923 pub const Bytes1024: u32 = 0b010;
924
925 /// 0b011: ECC page size 2048 bytes
926 pub const Bytes2048: u32 = 0b011;
927
928 /// 0b100: ECC page size 4096 bytes
929 pub const Bytes4096: u32 = 0b100;
930
931 /// 0b101: ECC page size 8192 bytes
932 pub const Bytes8192: u32 = 0b101;
933 }
934 }
935
936 /// TAR
937 pub mod TAR {
938 /// Offset (13 bits)
939 pub const offset: u32 = 13;
940 /// Mask (4 bits: 0b1111 << 13)
941 pub const mask: u32 = 0b1111 << offset;
942 /// Read-only values (empty)
943 pub mod R {}
944 /// Write-only values (empty)
945 pub mod W {}
946 /// Read-write values (empty)
947 pub mod RW {}
948 }
949
950 /// TCLR
951 pub mod TCLR {
952 /// Offset (9 bits)
953 pub const offset: u32 = 9;
954 /// Mask (4 bits: 0b1111 << 9)
955 pub const mask: u32 = 0b1111 << offset;
956 /// Read-only values (empty)
957 pub mod R {}
958 /// Write-only values (empty)
959 pub mod W {}
960 /// Read-write values (empty)
961 pub mod RW {}
962 }
963
964 /// ECCEN
965 pub mod ECCEN {
966 /// Offset (6 bits)
967 pub const offset: u32 = 6;
968 /// Mask (1 bit: 1 << 6)
969 pub const mask: u32 = 1 << offset;
970 /// Read-only values (empty)
971 pub mod R {}
972 /// Write-only values (empty)
973 pub mod W {}
974 /// Read-write values
975 pub mod RW {
976
977 /// 0b0: ECC logic is disabled and reset
978 pub const Disabled: u32 = 0b0;
979
980 /// 0b1: ECC logic is enabled
981 pub const Enabled: u32 = 0b1;
982 }
983 }
984
985 /// PWID
986 pub mod PWID {
987 /// Offset (4 bits)
988 pub const offset: u32 = 4;
989 /// Mask (2 bits: 0b11 << 4)
990 pub const mask: u32 = 0b11 << offset;
991 /// Read-only values (empty)
992 pub mod R {}
993 /// Write-only values (empty)
994 pub mod W {}
995 /// Read-write values
996 pub mod RW {
997
998 /// 0b00: External memory device width 8 bits
999 pub const Bits8: u32 = 0b00;
1000
1001 /// 0b01: External memory device width 16 bits
1002 pub const Bits16: u32 = 0b01;
1003 }
1004 }
1005
1006 /// PTYP
1007 pub mod PTYP {
1008 /// Offset (3 bits)
1009 pub const offset: u32 = 3;
1010 /// Mask (1 bit: 1 << 3)
1011 pub const mask: u32 = 1 << offset;
1012 /// Read-only values (empty)
1013 pub mod R {}
1014 /// Write-only values (empty)
1015 pub mod W {}
1016 /// Read-write values
1017 pub mod RW {
1018
1019 /// 0b1: NAND Flash
1020 pub const NANDFlash: u32 = 0b1;
1021 }
1022 }
1023
1024 /// PBKEN
1025 pub mod PBKEN {
1026 /// Offset (2 bits)
1027 pub const offset: u32 = 2;
1028 /// Mask (1 bit: 1 << 2)
1029 pub const mask: u32 = 1 << offset;
1030 /// Read-only values (empty)
1031 pub mod R {}
1032 /// Write-only values (empty)
1033 pub mod W {}
1034 /// Read-write values
1035 pub mod RW {
1036
1037 /// 0b0: Corresponding memory bank is disabled
1038 pub const Disabled: u32 = 0b0;
1039
1040 /// 0b1: Corresponding memory bank is enabled
1041 pub const Enabled: u32 = 0b1;
1042 }
1043 }
1044
1045 /// PWAITEN
1046 pub mod PWAITEN {
1047 /// Offset (1 bits)
1048 pub const offset: u32 = 1;
1049 /// Mask (1 bit: 1 << 1)
1050 pub const mask: u32 = 1 << offset;
1051 /// Read-only values (empty)
1052 pub mod R {}
1053 /// Write-only values (empty)
1054 pub mod W {}
1055 /// Read-write values
1056 pub mod RW {
1057
1058 /// 0b0: Wait feature disabled
1059 pub const Disabled: u32 = 0b0;
1060
1061 /// 0b1: Wait feature enabled
1062 pub const Enabled: u32 = 0b1;
1063 }
1064 }
1065}
1066
1067/// FIFO status and interrupt register
1068pub mod SR {
1069
1070 /// FEMPT
1071 pub mod FEMPT {
1072 /// Offset (6 bits)
1073 pub const offset: u32 = 6;
1074 /// Mask (1 bit: 1 << 6)
1075 pub const mask: u32 = 1 << offset;
1076 /// Read-only values (empty)
1077 pub mod R {}
1078 /// Write-only values (empty)
1079 pub mod W {}
1080 /// Read-write values
1081 pub mod RW {
1082
1083 /// 0b0: FIFO not empty
1084 pub const NotEmpty: u32 = 0b0;
1085
1086 /// 0b1: FIFO empty
1087 pub const Empty: u32 = 0b1;
1088 }
1089 }
1090
1091 /// IFEN
1092 pub mod IFEN {
1093 /// Offset (5 bits)
1094 pub const offset: u32 = 5;
1095 /// Mask (1 bit: 1 << 5)
1096 pub const mask: u32 = 1 << offset;
1097 /// Read-only values (empty)
1098 pub mod R {}
1099 /// Write-only values (empty)
1100 pub mod W {}
1101 /// Read-write values
1102 pub mod RW {
1103
1104 /// 0b0: Interrupt falling edge detection request disabled
1105 pub const Disabled: u32 = 0b0;
1106
1107 /// 0b1: Interrupt falling edge detection request enabled
1108 pub const Enabled: u32 = 0b1;
1109 }
1110 }
1111
1112 /// ILEN
1113 pub mod ILEN {
1114 /// Offset (4 bits)
1115 pub const offset: u32 = 4;
1116 /// Mask (1 bit: 1 << 4)
1117 pub const mask: u32 = 1 << offset;
1118 /// Read-only values (empty)
1119 pub mod R {}
1120 /// Write-only values (empty)
1121 pub mod W {}
1122 /// Read-write values
1123 pub mod RW {
1124
1125 /// 0b0: Interrupt high-level detection request disabled
1126 pub const Disabled: u32 = 0b0;
1127
1128 /// 0b1: Interrupt high-level detection request enabled
1129 pub const Enabled: u32 = 0b1;
1130 }
1131 }
1132
1133 /// IREN
1134 pub mod IREN {
1135 /// Offset (3 bits)
1136 pub const offset: u32 = 3;
1137 /// Mask (1 bit: 1 << 3)
1138 pub const mask: u32 = 1 << offset;
1139 /// Read-only values (empty)
1140 pub mod R {}
1141 /// Write-only values (empty)
1142 pub mod W {}
1143 /// Read-write values
1144 pub mod RW {
1145
1146 /// 0b0: Interrupt rising edge detection request disabled
1147 pub const Disabled: u32 = 0b0;
1148
1149 /// 0b1: Interrupt rising edge detection request enabled
1150 pub const Enabled: u32 = 0b1;
1151 }
1152 }
1153
1154 /// IFS
1155 pub mod IFS {
1156 /// Offset (2 bits)
1157 pub const offset: u32 = 2;
1158 /// Mask (1 bit: 1 << 2)
1159 pub const mask: u32 = 1 << offset;
1160 /// Read-only values (empty)
1161 pub mod R {}
1162 /// Write-only values (empty)
1163 pub mod W {}
1164 /// Read-write values
1165 pub mod RW {
1166
1167 /// 0b0: Interrupt falling edge did not occur
1168 pub const DidNotOccur: u32 = 0b0;
1169
1170 /// 0b1: Interrupt falling edge occurred
1171 pub const Occurred: u32 = 0b1;
1172 }
1173 }
1174
1175 /// ILS
1176 pub mod ILS {
1177 /// Offset (1 bits)
1178 pub const offset: u32 = 1;
1179 /// Mask (1 bit: 1 << 1)
1180 pub const mask: u32 = 1 << offset;
1181 /// Read-only values (empty)
1182 pub mod R {}
1183 /// Write-only values (empty)
1184 pub mod W {}
1185 /// Read-write values
1186 pub mod RW {
1187
1188 /// 0b0: Interrupt high-level did not occur
1189 pub const DidNotOccur: u32 = 0b0;
1190
1191 /// 0b1: Interrupt high-level occurred
1192 pub const Occurred: u32 = 0b1;
1193 }
1194 }
1195
1196 /// IRS
1197 pub mod IRS {
1198 /// Offset (0 bits)
1199 pub const offset: u32 = 0;
1200 /// Mask (1 bit: 1 << 0)
1201 pub const mask: u32 = 1 << offset;
1202 /// Read-only values (empty)
1203 pub mod R {}
1204 /// Write-only values (empty)
1205 pub mod W {}
1206 /// Read-write values
1207 pub mod RW {
1208
1209 /// 0b0: Interrupt rising edge did not occur
1210 pub const DidNotOccur: u32 = 0b0;
1211
1212 /// 0b1: Interrupt rising edge occurred
1213 pub const Occurred: u32 = 0b1;
1214 }
1215 }
1216}
1217
1218/// Common memory space timing register
1219pub mod PMEM {
1220
1221 /// MEMHIZx
1222 pub mod MEMHIZ {
1223 /// Offset (24 bits)
1224 pub const offset: u32 = 24;
1225 /// Mask (8 bits: 0xff << 24)
1226 pub const mask: u32 = 0xff << offset;
1227 /// Read-only values (empty)
1228 pub mod R {}
1229 /// Write-only values (empty)
1230 pub mod W {}
1231 /// Read-write values (empty)
1232 pub mod RW {}
1233 }
1234
1235 /// MEMHOLDx
1236 pub mod MEMHOLD {
1237 /// Offset (16 bits)
1238 pub const offset: u32 = 16;
1239 /// Mask (8 bits: 0xff << 16)
1240 pub const mask: u32 = 0xff << offset;
1241 /// Read-only values (empty)
1242 pub mod R {}
1243 /// Write-only values (empty)
1244 pub mod W {}
1245 /// Read-write values (empty)
1246 pub mod RW {}
1247 }
1248
1249 /// MEMWAITx
1250 pub mod MEMWAIT {
1251 /// Offset (8 bits)
1252 pub const offset: u32 = 8;
1253 /// Mask (8 bits: 0xff << 8)
1254 pub const mask: u32 = 0xff << offset;
1255 /// Read-only values (empty)
1256 pub mod R {}
1257 /// Write-only values (empty)
1258 pub mod W {}
1259 /// Read-write values (empty)
1260 pub mod RW {}
1261 }
1262
1263 /// MEMSETx
1264 pub mod MEMSET {
1265 /// Offset (0 bits)
1266 pub const offset: u32 = 0;
1267 /// Mask (8 bits: 0xff << 0)
1268 pub const mask: u32 = 0xff << offset;
1269 /// Read-only values (empty)
1270 pub mod R {}
1271 /// Write-only values (empty)
1272 pub mod W {}
1273 /// Read-write values (empty)
1274 pub mod RW {}
1275 }
1276}
1277
1278/// Attribute memory space timing register
1279pub mod PATT {
1280
1281 /// ATTHIZx
1282 pub mod ATTHIZ {
1283 /// Offset (24 bits)
1284 pub const offset: u32 = 24;
1285 /// Mask (8 bits: 0xff << 24)
1286 pub const mask: u32 = 0xff << offset;
1287 /// Read-only values (empty)
1288 pub mod R {}
1289 /// Write-only values (empty)
1290 pub mod W {}
1291 /// Read-write values (empty)
1292 pub mod RW {}
1293 }
1294
1295 /// ATTHOLDx
1296 pub mod ATTHOLD {
1297 /// Offset (16 bits)
1298 pub const offset: u32 = 16;
1299 /// Mask (8 bits: 0xff << 16)
1300 pub const mask: u32 = 0xff << offset;
1301 /// Read-only values (empty)
1302 pub mod R {}
1303 /// Write-only values (empty)
1304 pub mod W {}
1305 /// Read-write values (empty)
1306 pub mod RW {}
1307 }
1308
1309 /// ATTWAITx
1310 pub mod ATTWAIT {
1311 /// Offset (8 bits)
1312 pub const offset: u32 = 8;
1313 /// Mask (8 bits: 0xff << 8)
1314 pub const mask: u32 = 0xff << offset;
1315 /// Read-only values (empty)
1316 pub mod R {}
1317 /// Write-only values (empty)
1318 pub mod W {}
1319 /// Read-write values (empty)
1320 pub mod RW {}
1321 }
1322
1323 /// ATTSETx
1324 pub mod ATTSET {
1325 /// Offset (0 bits)
1326 pub const offset: u32 = 0;
1327 /// Mask (8 bits: 0xff << 0)
1328 pub const mask: u32 = 0xff << offset;
1329 /// Read-only values (empty)
1330 pub mod R {}
1331 /// Write-only values (empty)
1332 pub mod W {}
1333 /// Read-write values (empty)
1334 pub mod RW {}
1335 }
1336}
1337
1338/// ECC result register
1339pub mod ECCR {
1340
1341 /// ECCx
1342 pub mod ECC {
1343 /// Offset (0 bits)
1344 pub const offset: u32 = 0;
1345 /// Mask (32 bits: 0xffffffff << 0)
1346 pub const mask: u32 = 0xffffffff << offset;
1347 /// Read-only values (empty)
1348 pub mod R {}
1349 /// Write-only values (empty)
1350 pub mod W {}
1351 /// Read-write values (empty)
1352 pub mod RW {}
1353 }
1354}
1355
1356/// SRAM/NOR-Flash write timing registers 1
1357pub mod BWTR1 {
1358
1359 /// ACCMOD
1360 pub mod ACCMOD {
1361 /// Offset (28 bits)
1362 pub const offset: u32 = 28;
1363 /// Mask (2 bits: 0b11 << 28)
1364 pub const mask: u32 = 0b11 << offset;
1365 /// Read-only values (empty)
1366 pub mod R {}
1367 /// Write-only values (empty)
1368 pub mod W {}
1369 /// Read-write values
1370 pub mod RW {
1371
1372 /// 0b00: Access mode A
1373 pub const A: u32 = 0b00;
1374
1375 /// 0b01: Access mode B
1376 pub const B: u32 = 0b01;
1377
1378 /// 0b10: Access mode C
1379 pub const C: u32 = 0b10;
1380
1381 /// 0b11: Access mode D
1382 pub const D: u32 = 0b11;
1383 }
1384 }
1385
1386 /// CLKDIV
1387 pub mod CLKDIV {
1388 /// Offset (20 bits)
1389 pub const offset: u32 = 20;
1390 /// Mask (4 bits: 0b1111 << 20)
1391 pub const mask: u32 = 0b1111 << offset;
1392 /// Read-only values (empty)
1393 pub mod R {}
1394 /// Write-only values (empty)
1395 pub mod W {}
1396 /// Read-write values (empty)
1397 pub mod RW {}
1398 }
1399
1400 /// DATAST
1401 pub mod DATAST {
1402 /// Offset (8 bits)
1403 pub const offset: u32 = 8;
1404 /// Mask (8 bits: 0xff << 8)
1405 pub const mask: u32 = 0xff << offset;
1406 /// Read-only values (empty)
1407 pub mod R {}
1408 /// Write-only values (empty)
1409 pub mod W {}
1410 /// Read-write values (empty)
1411 pub mod RW {}
1412 }
1413
1414 /// ADDHLD
1415 pub mod ADDHLD {
1416 /// Offset (4 bits)
1417 pub const offset: u32 = 4;
1418 /// Mask (4 bits: 0b1111 << 4)
1419 pub const mask: u32 = 0b1111 << offset;
1420 /// Read-only values (empty)
1421 pub mod R {}
1422 /// Write-only values (empty)
1423 pub mod W {}
1424 /// Read-write values (empty)
1425 pub mod RW {}
1426 }
1427
1428 /// ADDSET
1429 pub mod ADDSET {
1430 /// Offset (0 bits)
1431 pub const offset: u32 = 0;
1432 /// Mask (4 bits: 0b1111 << 0)
1433 pub const mask: u32 = 0b1111 << offset;
1434 /// Read-only values (empty)
1435 pub mod R {}
1436 /// Write-only values (empty)
1437 pub mod W {}
1438 /// Read-write values (empty)
1439 pub mod RW {}
1440 }
1441
1442 /// Bus turnaround phase duration
1443 pub mod BUSTURN {
1444 /// Offset (16 bits)
1445 pub const offset: u32 = 16;
1446 /// Mask (4 bits: 0b1111 << 16)
1447 pub const mask: u32 = 0b1111 << offset;
1448 /// Read-only values (empty)
1449 pub mod R {}
1450 /// Write-only values (empty)
1451 pub mod W {}
1452 /// Read-write values (empty)
1453 pub mod RW {}
1454 }
1455}
1456
1457/// SRAM/NOR-Flash write timing registers 1
1458pub mod BWTR2 {
1459 pub use super::BWTR1::ACCMOD;
1460 pub use super::BWTR1::ADDHLD;
1461 pub use super::BWTR1::ADDSET;
1462 pub use super::BWTR1::BUSTURN;
1463 pub use super::BWTR1::CLKDIV;
1464 pub use super::BWTR1::DATAST;
1465}
1466
1467/// SRAM/NOR-Flash write timing registers 1
1468pub mod BWTR3 {
1469 pub use super::BWTR1::ACCMOD;
1470 pub use super::BWTR1::ADDHLD;
1471 pub use super::BWTR1::ADDSET;
1472 pub use super::BWTR1::BUSTURN;
1473 pub use super::BWTR1::CLKDIV;
1474 pub use super::BWTR1::DATAST;
1475}
1476
1477/// SRAM/NOR-Flash write timing registers 1
1478pub mod BWTR4 {
1479 pub use super::BWTR1::ACCMOD;
1480 pub use super::BWTR1::ADDHLD;
1481 pub use super::BWTR1::ADDSET;
1482 pub use super::BWTR1::BUSTURN;
1483 pub use super::BWTR1::CLKDIV;
1484 pub use super::BWTR1::DATAST;
1485}
1486
1487/// SDRAM Control Register 1
1488pub mod SDCR1 {
1489
1490 /// Number of column address bits
1491 pub mod NC {
1492 /// Offset (0 bits)
1493 pub const offset: u32 = 0;
1494 /// Mask (2 bits: 0b11 << 0)
1495 pub const mask: u32 = 0b11 << offset;
1496 /// Read-only values (empty)
1497 pub mod R {}
1498 /// Write-only values (empty)
1499 pub mod W {}
1500 /// Read-write values
1501 pub mod RW {
1502
1503 /// 0b00: 8 bits
1504 pub const Bits8: u32 = 0b00;
1505
1506 /// 0b01: 9 bits
1507 pub const Bits9: u32 = 0b01;
1508
1509 /// 0b10: 10 bits
1510 pub const Bits10: u32 = 0b10;
1511
1512 /// 0b11: 11 bits
1513 pub const Bits11: u32 = 0b11;
1514 }
1515 }
1516
1517 /// Number of row address bits
1518 pub mod NR {
1519 /// Offset (2 bits)
1520 pub const offset: u32 = 2;
1521 /// Mask (2 bits: 0b11 << 2)
1522 pub const mask: u32 = 0b11 << offset;
1523 /// Read-only values (empty)
1524 pub mod R {}
1525 /// Write-only values (empty)
1526 pub mod W {}
1527 /// Read-write values
1528 pub mod RW {
1529
1530 /// 0b00: 11 bits
1531 pub const Bits11: u32 = 0b00;
1532
1533 /// 0b01: 12 bits
1534 pub const Bits12: u32 = 0b01;
1535
1536 /// 0b10: 13 bits
1537 pub const Bits13: u32 = 0b10;
1538 }
1539 }
1540
1541 /// Memory data bus width
1542 pub mod MWID {
1543 /// Offset (4 bits)
1544 pub const offset: u32 = 4;
1545 /// Mask (2 bits: 0b11 << 4)
1546 pub const mask: u32 = 0b11 << offset;
1547 /// Read-only values (empty)
1548 pub mod R {}
1549 /// Write-only values (empty)
1550 pub mod W {}
1551 /// Read-write values
1552 pub mod RW {
1553
1554 /// 0b00: Memory data bus width 8 bits
1555 pub const Bits8: u32 = 0b00;
1556
1557 /// 0b01: Memory data bus width 16 bits
1558 pub const Bits16: u32 = 0b01;
1559
1560 /// 0b10: Memory data bus width 32 bits
1561 pub const Bits32: u32 = 0b10;
1562 }
1563 }
1564
1565 /// Number of internal banks
1566 pub mod NB {
1567 /// Offset (6 bits)
1568 pub const offset: u32 = 6;
1569 /// Mask (1 bit: 1 << 6)
1570 pub const mask: u32 = 1 << offset;
1571 /// Read-only values (empty)
1572 pub mod R {}
1573 /// Write-only values (empty)
1574 pub mod W {}
1575 /// Read-write values
1576 pub mod RW {
1577
1578 /// 0b0: Two internal Banks
1579 pub const NB2: u32 = 0b0;
1580
1581 /// 0b1: Four internal Banks
1582 pub const NB4: u32 = 0b1;
1583 }
1584 }
1585
1586 /// CAS latency
1587 pub mod CAS {
1588 /// Offset (7 bits)
1589 pub const offset: u32 = 7;
1590 /// Mask (2 bits: 0b11 << 7)
1591 pub const mask: u32 = 0b11 << offset;
1592 /// Read-only values (empty)
1593 pub mod R {}
1594 /// Write-only values (empty)
1595 pub mod W {}
1596 /// Read-write values
1597 pub mod RW {
1598
1599 /// 0b01: 1 cycle
1600 pub const Clocks1: u32 = 0b01;
1601
1602 /// 0b10: 2 cycles
1603 pub const Clocks2: u32 = 0b10;
1604
1605 /// 0b11: 3 cycles
1606 pub const Clocks3: u32 = 0b11;
1607 }
1608 }
1609
1610 /// Write protection
1611 pub mod WP {
1612 /// Offset (9 bits)
1613 pub const offset: u32 = 9;
1614 /// Mask (1 bit: 1 << 9)
1615 pub const mask: u32 = 1 << offset;
1616 /// Read-only values (empty)
1617 pub mod R {}
1618 /// Write-only values (empty)
1619 pub mod W {}
1620 /// Read-write values
1621 pub mod RW {
1622
1623 /// 0b0: Write accesses allowed
1624 pub const Disabled: u32 = 0b0;
1625
1626 /// 0b1: Write accesses ignored
1627 pub const Enabled: u32 = 0b1;
1628 }
1629 }
1630
1631 /// SDRAM clock configuration
1632 pub mod SDCLK {
1633 /// Offset (10 bits)
1634 pub const offset: u32 = 10;
1635 /// Mask (2 bits: 0b11 << 10)
1636 pub const mask: u32 = 0b11 << offset;
1637 /// Read-only values (empty)
1638 pub mod R {}
1639 /// Write-only values (empty)
1640 pub mod W {}
1641 /// Read-write values
1642 pub mod RW {
1643
1644 /// 0b00: SDCLK clock disabled
1645 pub const Disabled: u32 = 0b00;
1646
1647 /// 0b10: SDCLK period = 2 x HCLK period
1648 pub const Div2: u32 = 0b10;
1649
1650 /// 0b11: SDCLK period = 3 x HCLK period
1651 pub const Div3: u32 = 0b11;
1652 }
1653 }
1654
1655 /// Burst read
1656 pub mod RBURST {
1657 /// Offset (12 bits)
1658 pub const offset: u32 = 12;
1659 /// Mask (1 bit: 1 << 12)
1660 pub const mask: u32 = 1 << offset;
1661 /// Read-only values (empty)
1662 pub mod R {}
1663 /// Write-only values (empty)
1664 pub mod W {}
1665 /// Read-write values
1666 pub mod RW {
1667
1668 /// 0b0: Single read requests are not managed as bursts
1669 pub const Disabled: u32 = 0b0;
1670
1671 /// 0b1: Single read requests are always managed as bursts
1672 pub const Enabled: u32 = 0b1;
1673 }
1674 }
1675
1676 /// Read pipe
1677 pub mod RPIPE {
1678 /// Offset (13 bits)
1679 pub const offset: u32 = 13;
1680 /// Mask (2 bits: 0b11 << 13)
1681 pub const mask: u32 = 0b11 << offset;
1682 /// Read-only values (empty)
1683 pub mod R {}
1684 /// Write-only values (empty)
1685 pub mod W {}
1686 /// Read-write values
1687 pub mod RW {
1688
1689 /// 0b00: No clock cycle delay
1690 pub const NoDelay: u32 = 0b00;
1691
1692 /// 0b01: One clock cycle delay
1693 pub const Clocks1: u32 = 0b01;
1694
1695 /// 0b10: Two clock cycles delay
1696 pub const Clocks2: u32 = 0b10;
1697 }
1698 }
1699}
1700
1701/// SDRAM Control Register 1
1702pub mod SDCR2 {
1703 pub use super::SDCR1::CAS;
1704 pub use super::SDCR1::MWID;
1705 pub use super::SDCR1::NB;
1706 pub use super::SDCR1::NC;
1707 pub use super::SDCR1::NR;
1708 pub use super::SDCR1::RBURST;
1709 pub use super::SDCR1::RPIPE;
1710 pub use super::SDCR1::SDCLK;
1711 pub use super::SDCR1::WP;
1712}
1713
1714/// SDRAM Timing register 1
1715pub mod SDTR1 {
1716
1717 /// Load Mode Register to Active
1718 pub mod TMRD {
1719 /// Offset (0 bits)
1720 pub const offset: u32 = 0;
1721 /// Mask (4 bits: 0b1111 << 0)
1722 pub const mask: u32 = 0b1111 << offset;
1723 /// Read-only values (empty)
1724 pub mod R {}
1725 /// Write-only values (empty)
1726 pub mod W {}
1727 /// Read-write values (empty)
1728 pub mod RW {}
1729 }
1730
1731 /// Exit self-refresh delay
1732 pub mod TXSR {
1733 /// Offset (4 bits)
1734 pub const offset: u32 = 4;
1735 /// Mask (4 bits: 0b1111 << 4)
1736 pub const mask: u32 = 0b1111 << offset;
1737 /// Read-only values (empty)
1738 pub mod R {}
1739 /// Write-only values (empty)
1740 pub mod W {}
1741 /// Read-write values (empty)
1742 pub mod RW {}
1743 }
1744
1745 /// Self refresh time
1746 pub mod TRAS {
1747 /// Offset (8 bits)
1748 pub const offset: u32 = 8;
1749 /// Mask (4 bits: 0b1111 << 8)
1750 pub const mask: u32 = 0b1111 << offset;
1751 /// Read-only values (empty)
1752 pub mod R {}
1753 /// Write-only values (empty)
1754 pub mod W {}
1755 /// Read-write values (empty)
1756 pub mod RW {}
1757 }
1758
1759 /// Row cycle delay
1760 pub mod TRC {
1761 /// Offset (12 bits)
1762 pub const offset: u32 = 12;
1763 /// Mask (4 bits: 0b1111 << 12)
1764 pub const mask: u32 = 0b1111 << offset;
1765 /// Read-only values (empty)
1766 pub mod R {}
1767 /// Write-only values (empty)
1768 pub mod W {}
1769 /// Read-write values (empty)
1770 pub mod RW {}
1771 }
1772
1773 /// Recovery delay
1774 pub mod TWR {
1775 /// Offset (16 bits)
1776 pub const offset: u32 = 16;
1777 /// Mask (4 bits: 0b1111 << 16)
1778 pub const mask: u32 = 0b1111 << offset;
1779 /// Read-only values (empty)
1780 pub mod R {}
1781 /// Write-only values (empty)
1782 pub mod W {}
1783 /// Read-write values (empty)
1784 pub mod RW {}
1785 }
1786
1787 /// Row precharge delay
1788 pub mod TRP {
1789 /// Offset (20 bits)
1790 pub const offset: u32 = 20;
1791 /// Mask (4 bits: 0b1111 << 20)
1792 pub const mask: u32 = 0b1111 << offset;
1793 /// Read-only values (empty)
1794 pub mod R {}
1795 /// Write-only values (empty)
1796 pub mod W {}
1797 /// Read-write values (empty)
1798 pub mod RW {}
1799 }
1800
1801 /// Row to column delay
1802 pub mod TRCD {
1803 /// Offset (24 bits)
1804 pub const offset: u32 = 24;
1805 /// Mask (4 bits: 0b1111 << 24)
1806 pub const mask: u32 = 0b1111 << offset;
1807 /// Read-only values (empty)
1808 pub mod R {}
1809 /// Write-only values (empty)
1810 pub mod W {}
1811 /// Read-write values (empty)
1812 pub mod RW {}
1813 }
1814}
1815
1816/// SDRAM Timing register 1
1817pub mod SDTR2 {
1818 pub use super::SDTR1::TMRD;
1819 pub use super::SDTR1::TRAS;
1820 pub use super::SDTR1::TRC;
1821 pub use super::SDTR1::TRCD;
1822 pub use super::SDTR1::TRP;
1823 pub use super::SDTR1::TWR;
1824 pub use super::SDTR1::TXSR;
1825}
1826
1827/// SDRAM Command Mode register
1828pub mod SDCMR {
1829
1830 /// Command mode
1831 pub mod MODE {
1832 /// Offset (0 bits)
1833 pub const offset: u32 = 0;
1834 /// Mask (3 bits: 0b111 << 0)
1835 pub const mask: u32 = 0b111 << offset;
1836 /// Read-only values (empty)
1837 pub mod R {}
1838 /// Write-only values (empty)
1839 pub mod W {}
1840 /// Read-write values
1841 pub mod RW {
1842
1843 /// 0b000: Normal Mode
1844 pub const Normal: u32 = 0b000;
1845
1846 /// 0b001: Clock Configuration Enable
1847 pub const ClockConfigurationEnable: u32 = 0b001;
1848
1849 /// 0b010: PALL (All Bank Precharge) command
1850 pub const PALL: u32 = 0b010;
1851
1852 /// 0b011: Auto-refresh command
1853 pub const AutoRefreshCommand: u32 = 0b011;
1854
1855 /// 0b100: Load Mode Resgier
1856 pub const LoadModeRegister: u32 = 0b100;
1857
1858 /// 0b101: Self-refresh command
1859 pub const SelfRefreshCommand: u32 = 0b101;
1860
1861 /// 0b110: Power-down command
1862 pub const PowerDownCommand: u32 = 0b110;
1863 }
1864 }
1865
1866 /// Command target bank 2
1867 pub mod CTB2 {
1868 /// Offset (3 bits)
1869 pub const offset: u32 = 3;
1870 /// Mask (1 bit: 1 << 3)
1871 pub const mask: u32 = 1 << offset;
1872 /// Read-only values (empty)
1873 pub mod R {}
1874 /// Write-only values (empty)
1875 pub mod W {}
1876 /// Read-write values
1877 pub mod RW {
1878
1879 /// 0b0: Command not issued to SDRAM Bank 1
1880 pub const NotIssued: u32 = 0b0;
1881
1882 /// 0b1: Command issued to SDRAM Bank 1
1883 pub const Issued: u32 = 0b1;
1884 }
1885 }
1886
1887 /// Command target bank 1
1888 pub mod CTB1 {
1889 /// Offset (4 bits)
1890 pub const offset: u32 = 4;
1891 /// Mask (1 bit: 1 << 4)
1892 pub const mask: u32 = 1 << offset;
1893 /// Read-only values (empty)
1894 pub mod R {}
1895 /// Write-only values (empty)
1896 pub mod W {}
1897 pub use super::CTB2::RW;
1898 }
1899
1900 /// Number of Auto-refresh
1901 pub mod NRFS {
1902 /// Offset (5 bits)
1903 pub const offset: u32 = 5;
1904 /// Mask (4 bits: 0b1111 << 5)
1905 pub const mask: u32 = 0b1111 << offset;
1906 /// Read-only values (empty)
1907 pub mod R {}
1908 /// Write-only values (empty)
1909 pub mod W {}
1910 /// Read-write values (empty)
1911 pub mod RW {}
1912 }
1913
1914 /// Mode Register definition
1915 pub mod MRD {
1916 /// Offset (9 bits)
1917 pub const offset: u32 = 9;
1918 /// Mask (14 bits: 0x3fff << 9)
1919 pub const mask: u32 = 0x3fff << offset;
1920 /// Read-only values (empty)
1921 pub mod R {}
1922 /// Write-only values (empty)
1923 pub mod W {}
1924 /// Read-write values (empty)
1925 pub mod RW {}
1926 }
1927}
1928
1929/// SDRAM Refresh Timer register
1930pub mod SDRTR {
1931
1932 /// Clear Refresh error flag
1933 pub mod CRE {
1934 /// Offset (0 bits)
1935 pub const offset: u32 = 0;
1936 /// Mask (1 bit: 1 << 0)
1937 pub const mask: u32 = 1 << offset;
1938 /// Read-only values (empty)
1939 pub mod R {}
1940 /// Write-only values (empty)
1941 pub mod W {}
1942 /// Read-write values
1943 pub mod RW {
1944
1945 /// 0b1: Refresh Error Flag is cleared
1946 pub const Clear: u32 = 0b1;
1947 }
1948 }
1949
1950 /// Refresh Timer Count
1951 pub mod COUNT {
1952 /// Offset (1 bits)
1953 pub const offset: u32 = 1;
1954 /// Mask (13 bits: 0x1fff << 1)
1955 pub const mask: u32 = 0x1fff << offset;
1956 /// Read-only values (empty)
1957 pub mod R {}
1958 /// Write-only values (empty)
1959 pub mod W {}
1960 /// Read-write values (empty)
1961 pub mod RW {}
1962 }
1963
1964 /// RES Interrupt Enable
1965 pub mod REIE {
1966 /// Offset (14 bits)
1967 pub const offset: u32 = 14;
1968 /// Mask (1 bit: 1 << 14)
1969 pub const mask: u32 = 1 << offset;
1970 /// Read-only values (empty)
1971 pub mod R {}
1972 /// Write-only values (empty)
1973 pub mod W {}
1974 /// Read-write values
1975 pub mod RW {
1976
1977 /// 0b0: Interrupt is disabled
1978 pub const Disabled: u32 = 0b0;
1979
1980 /// 0b1: Interrupt is generated if RE = 1
1981 pub const Enabled: u32 = 0b1;
1982 }
1983 }
1984}
1985
1986/// SDRAM Status register
1987pub mod SDSR {
1988
1989 /// Refresh error flag
1990 pub mod RE {
1991 /// Offset (0 bits)
1992 pub const offset: u32 = 0;
1993 /// Mask (1 bit: 1 << 0)
1994 pub const mask: u32 = 1 << offset;
1995 /// Read-only values (empty)
1996 pub mod R {}
1997 /// Write-only values (empty)
1998 pub mod W {}
1999 /// Read-write values
2000 pub mod RW {
2001
2002 /// 0b0: No refresh error has been detected
2003 pub const NoError: u32 = 0b0;
2004
2005 /// 0b1: A refresh error has been detected
2006 pub const Error: u32 = 0b1;
2007 }
2008 }
2009
2010 /// Status Mode for Bank 1
2011 pub mod MODES1 {
2012 /// Offset (1 bits)
2013 pub const offset: u32 = 1;
2014 /// Mask (2 bits: 0b11 << 1)
2015 pub const mask: u32 = 0b11 << offset;
2016 /// Read-only values (empty)
2017 pub mod R {}
2018 /// Write-only values (empty)
2019 pub mod W {}
2020 /// Read-write values
2021 pub mod RW {
2022
2023 /// 0b00: Normal Mode
2024 pub const Normal: u32 = 0b00;
2025
2026 /// 0b01: Self-refresh mode
2027 pub const SelfRefresh: u32 = 0b01;
2028
2029 /// 0b10: Power-down mode
2030 pub const PowerDown: u32 = 0b10;
2031 }
2032 }
2033
2034 /// Status Mode for Bank 2
2035 pub mod MODES2 {
2036 /// Offset (3 bits)
2037 pub const offset: u32 = 3;
2038 /// Mask (2 bits: 0b11 << 3)
2039 pub const mask: u32 = 0b11 << offset;
2040 /// Read-only values (empty)
2041 pub mod R {}
2042 /// Write-only values (empty)
2043 pub mod W {}
2044 pub use super::MODES1::RW;
2045 }
2046
2047 /// Busy status
2048 pub mod BUSY {
2049 /// Offset (5 bits)
2050 pub const offset: u32 = 5;
2051 /// Mask (1 bit: 1 << 5)
2052 pub const mask: u32 = 1 << offset;
2053 /// Read-only values (empty)
2054 pub mod R {}
2055 /// Write-only values (empty)
2056 pub mod W {}
2057 /// Read-write values
2058 pub mod RW {
2059
2060 /// 0b0: SDRAM Controller is ready to accept a new request
2061 pub const NotBusy: u32 = 0b0;
2062
2063 /// 0b1: SDRAM Controller is not ready to accept a new request
2064 pub const Busy: u32 = 0b1;
2065 }
2066 }
2067}
2068#[repr(C)]
2069pub struct RegisterBlock {
2070 /// SRAM/NOR-Flash chip-select control register 1
2071 pub BCR1: RWRegister<u32>,
2072
2073 /// SRAM/NOR-Flash chip-select timing register 1
2074 pub BTR1: RWRegister<u32>,
2075
2076 /// SRAM/NOR-Flash chip-select control register 2
2077 pub BCR2: RWRegister<u32>,
2078
2079 /// SRAM/NOR-Flash chip-select timing register 1
2080 pub BTR2: RWRegister<u32>,
2081
2082 /// SRAM/NOR-Flash chip-select control register 2
2083 pub BCR3: RWRegister<u32>,
2084
2085 /// SRAM/NOR-Flash chip-select timing register 1
2086 pub BTR3: RWRegister<u32>,
2087
2088 /// SRAM/NOR-Flash chip-select control register 2
2089 pub BCR4: RWRegister<u32>,
2090
2091 /// SRAM/NOR-Flash chip-select timing register 1
2092 pub BTR4: RWRegister<u32>,
2093
2094 _reserved1: [u32; 24],
2095
2096 /// PC Card/NAND Flash control register
2097 pub PCR: RWRegister<u32>,
2098
2099 /// FIFO status and interrupt register
2100 pub SR: RWRegister<u32>,
2101
2102 /// Common memory space timing register
2103 pub PMEM: RWRegister<u32>,
2104
2105 /// Attribute memory space timing register
2106 pub PATT: RWRegister<u32>,
2107
2108 _reserved2: [u32; 1],
2109
2110 /// ECC result register
2111 pub ECCR: RORegister<u32>,
2112
2113 _reserved3: [u32; 27],
2114
2115 /// SRAM/NOR-Flash write timing registers 1
2116 pub BWTR1: RWRegister<u32>,
2117
2118 _reserved4: [u32; 1],
2119
2120 /// SRAM/NOR-Flash write timing registers 1
2121 pub BWTR2: RWRegister<u32>,
2122
2123 _reserved5: [u32; 1],
2124
2125 /// SRAM/NOR-Flash write timing registers 1
2126 pub BWTR3: RWRegister<u32>,
2127
2128 _reserved6: [u32; 1],
2129
2130 /// SRAM/NOR-Flash write timing registers 1
2131 pub BWTR4: RWRegister<u32>,
2132
2133 _reserved7: [u32; 8],
2134
2135 /// SDRAM Control Register 1
2136 pub SDCR1: RWRegister<u32>,
2137
2138 /// SDRAM Control Register 1
2139 pub SDCR2: RWRegister<u32>,
2140
2141 /// SDRAM Timing register 1
2142 pub SDTR1: RWRegister<u32>,
2143
2144 /// SDRAM Timing register 1
2145 pub SDTR2: RWRegister<u32>,
2146
2147 /// SDRAM Command Mode register
2148 pub SDCMR: RWRegister<u32>,
2149
2150 /// SDRAM Refresh Timer register
2151 pub SDRTR: RWRegister<u32>,
2152
2153 /// SDRAM Status register
2154 pub SDSR: RORegister<u32>,
2155}
2156pub struct ResetValues {
2157 pub BCR1: u32,
2158 pub BTR1: u32,
2159 pub BCR2: u32,
2160 pub BTR2: u32,
2161 pub BCR3: u32,
2162 pub BTR3: u32,
2163 pub BCR4: u32,
2164 pub BTR4: u32,
2165 pub PCR: u32,
2166 pub SR: u32,
2167 pub PMEM: u32,
2168 pub PATT: u32,
2169 pub ECCR: u32,
2170 pub BWTR1: u32,
2171 pub BWTR2: u32,
2172 pub BWTR3: u32,
2173 pub BWTR4: u32,
2174 pub SDCR1: u32,
2175 pub SDCR2: u32,
2176 pub SDTR1: u32,
2177 pub SDTR2: u32,
2178 pub SDCMR: u32,
2179 pub SDRTR: u32,
2180 pub SDSR: u32,
2181}
2182#[cfg(not(feature = "nosync"))]
2183pub struct Instance {
2184 pub(crate) addr: u32,
2185 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2186}
2187#[cfg(not(feature = "nosync"))]
2188impl ::core::ops::Deref for Instance {
2189 type Target = RegisterBlock;
2190 #[inline(always)]
2191 fn deref(&self) -> &RegisterBlock {
2192 unsafe { &*(self.addr as *const _) }
2193 }
2194}
2195#[cfg(feature = "rtic")]
2196unsafe impl Send for Instance {}
2197