1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "ADC1."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Adc {
9 ptr: *mut u8,
10}
11unsafe impl Send for Adc {}
12unsafe impl Sync for Adc {}
13impl Adc {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "ADC interrupt and status register."]
23 #[inline(always)]
24 pub const fn isr(self) -> crate::common::Reg<regs::Isr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "ADC interrupt enable register."]
28 #[inline(always)]
29 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "ADC control register."]
33 #[inline(always)]
34 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "ADC configuration register."]
38 #[inline(always)]
39 pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "ADC configuration register 2."]
43 #[inline(always)]
44 pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "sampling time register 1-2"]
48 #[inline(always)]
49 pub const fn smpr(self, n: usize) -> crate::common::Reg<regs::Smpr, crate::common::RW> {
50 assert!(n < 2usize);
51 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 4usize) as _) }
52 }
53 #[doc = "ADC channel preselection register."]
54 #[inline(always)]
55 pub const fn pcsel(self) -> crate::common::Reg<regs::Pcsel, crate::common::RW> {
56 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
57 }
58 #[doc = "ADC regular sequence register 1."]
59 #[inline(always)]
60 pub const fn sqr1(self) -> crate::common::Reg<regs::Sqr1, crate::common::RW> {
61 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
62 }
63 #[doc = "ADC regular sequence register 2."]
64 #[inline(always)]
65 pub const fn sqr2(self) -> crate::common::Reg<regs::Sqr2, crate::common::RW> {
66 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
67 }
68 #[doc = "ADC regular sequence register 3."]
69 #[inline(always)]
70 pub const fn sqr3(self) -> crate::common::Reg<regs::Sqr3, crate::common::RW> {
71 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
72 }
73 #[doc = "ADC regular sequence register 4."]
74 #[inline(always)]
75 pub const fn sqr4(self) -> crate::common::Reg<regs::Sqr4, crate::common::RW> {
76 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
77 }
78 #[doc = "ADC regular Data Register."]
79 #[inline(always)]
80 pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::R> {
81 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
82 }
83 #[doc = "ADC injected sequence register."]
84 #[inline(always)]
85 pub const fn jsqr(self) -> crate::common::Reg<regs::Jsqr, crate::common::RW> {
86 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
87 }
88 #[doc = "ADC offset register."]
89 #[inline(always)]
90 pub const fn ofr(self, n: usize) -> crate::common::Reg<regs::Ofr, crate::common::RW> {
91 assert!(n < 4usize);
92 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize + n * 4usize) as _) }
93 }
94 #[doc = "ADC gain compensation register."]
95 #[inline(always)]
96 pub const fn gcomp(self) -> crate::common::Reg<regs::Gcomp, crate::common::RW> {
97 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
98 }
99 #[doc = "ADC injected data register."]
100 #[inline(always)]
101 pub const fn jdr(self, n: usize) -> crate::common::Reg<regs::Jdr, crate::common::R> {
102 assert!(n < 4usize);
103 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) }
104 }
105 #[doc = "ADC analog watchdog 2 configuration register."]
106 #[inline(always)]
107 pub const fn awd2cr(self) -> crate::common::Reg<regs::Awd2cr, crate::common::RW> {
108 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
109 }
110 #[doc = "ADC analog watchdog 3 configuration register."]
111 #[inline(always)]
112 pub const fn awd3cr(self) -> crate::common::Reg<regs::Awd3cr, crate::common::RW> {
113 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
114 }
115 #[doc = "ADC watchdog threshold register 1."]
116 #[inline(always)]
117 pub const fn ltr1(self) -> crate::common::Reg<regs::Ltr1, crate::common::RW> {
118 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) }
119 }
120 #[doc = "ADC watchdog threshold register 1."]
121 #[inline(always)]
122 pub const fn htr1(self) -> crate::common::Reg<regs::Htr1, crate::common::RW> {
123 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) }
124 }
125 #[doc = "ADC watchdog lower threshold register 2."]
126 #[inline(always)]
127 pub const fn ltr2(self) -> crate::common::Reg<regs::Ltr2, crate::common::RW> {
128 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) }
129 }
130 #[doc = "ADC watchdog higher threshold register 2."]
131 #[inline(always)]
132 pub const fn htr2(self) -> crate::common::Reg<regs::Htr2, crate::common::RW> {
133 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) }
134 }
135 #[doc = "ADC watchdog lower threshold register 3."]
136 #[inline(always)]
137 pub const fn ltr3(self) -> crate::common::Reg<regs::Ltr3, crate::common::RW> {
138 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) }
139 }
140 #[doc = "ADC watchdog higher threshold register 3."]
141 #[inline(always)]
142 pub const fn htr3(self) -> crate::common::Reg<regs::Htr3, crate::common::RW> {
143 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) }
144 }
145 #[doc = "ADC differential mode selection register."]
146 #[inline(always)]
147 pub const fn difsel(self) -> crate::common::Reg<regs::Difsel, crate::common::RW> {
148 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
149 }
150 #[doc = "ADC user control register."]
151 #[inline(always)]
152 pub const fn calfact(self) -> crate::common::Reg<regs::Calfact, crate::common::RW> {
153 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
154 }
155 #[doc = "ADC calibration factor register."]
156 #[inline(always)]
157 pub const fn calfact2(self) -> crate::common::Reg<regs::Calfact2, crate::common::RW> {
158 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) }
159 }
160}
161#[doc = "ADC4."]
162#[derive(Copy, Clone, Eq, PartialEq)]
163pub struct Adc4 {
164 ptr: *mut u8,
165}
166unsafe impl Send for Adc4 {}
167unsafe impl Sync for Adc4 {}
168impl Adc4 {
169 #[inline(always)]
170 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
171 Self { ptr: ptr as _ }
172 }
173 #[inline(always)]
174 pub const fn as_ptr(&self) -> *mut () {
175 self.ptr as _
176 }
177 #[doc = "ADC interrupt and status register."]
178 #[inline(always)]
179 pub const fn isr(self) -> crate::common::Reg<regs::Adc4Isr, crate::common::RW> {
180 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
181 }
182 #[doc = "ADC interrupt enable register."]
183 #[inline(always)]
184 pub const fn ier(self) -> crate::common::Reg<regs::Adc4Ier, crate::common::RW> {
185 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
186 }
187 #[doc = "ADC control register."]
188 #[inline(always)]
189 pub const fn cr(self) -> crate::common::Reg<regs::Adc4Cr, crate::common::RW> {
190 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
191 }
192 #[doc = "ADC configuration register."]
193 #[inline(always)]
194 pub const fn cfgr1(self) -> crate::common::Reg<regs::Adc4Cfgr1, crate::common::RW> {
195 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
196 }
197 #[doc = "ADC configuration register 2."]
198 #[inline(always)]
199 pub const fn cfgr2(self) -> crate::common::Reg<regs::Adc4Cfgr2, crate::common::RW> {
200 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
201 }
202 #[doc = "ADC sample time register."]
203 #[inline(always)]
204 pub const fn smpr(self) -> crate::common::Reg<regs::Adc4Smpr, crate::common::RW> {
205 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
206 }
207 #[doc = "ADC watchdog threshold register."]
208 #[inline(always)]
209 pub const fn awd1tr(self) -> crate::common::Reg<regs::Adc4Awdtr, crate::common::RW> {
210 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
211 }
212 #[doc = "ADC watchdog threshold register."]
213 #[inline(always)]
214 pub const fn awd2tr(self) -> crate::common::Reg<regs::Adc4Awdtr, crate::common::RW> {
215 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
216 }
217 #[doc = "ADC channel selection register \\[alternate\\]."]
218 #[inline(always)]
219 pub const fn chselrmod0(self) -> crate::common::Reg<regs::Adc4Chselrmod0, crate::common::RW> {
220 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
221 }
222 #[doc = "ADC channel selection register \\[alternate\\]."]
223 #[inline(always)]
224 pub const fn chselrmod1(self) -> crate::common::Reg<regs::Adc4Chselrmod1, crate::common::RW> {
225 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
226 }
227 #[doc = "ADC watchdog threshold register."]
228 #[inline(always)]
229 pub const fn awd3tr(self) -> crate::common::Reg<regs::Adc4Awdtr, crate::common::RW> {
230 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
231 }
232 #[doc = "ADC data register."]
233 #[inline(always)]
234 pub const fn dr(self) -> crate::common::Reg<regs::Adc4Dr, crate::common::R> {
235 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
236 }
237 #[doc = "ADC power register."]
238 #[inline(always)]
239 pub const fn pwrr(self) -> crate::common::Reg<regs::Adc4Pwrr, crate::common::RW> {
240 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
241 }
242 #[doc = "ADC Analog Watchdog 2 Configuration register."]
243 #[inline(always)]
244 pub const fn awd2cr(self) -> crate::common::Reg<regs::Adc4Awdcr, crate::common::RW> {
245 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
246 }
247 #[doc = "ADC Analog Watchdog 3 Configuration register."]
248 #[inline(always)]
249 pub const fn awd3cr(self) -> crate::common::Reg<regs::Adc4Awdcr, crate::common::RW> {
250 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
251 }
252 #[doc = "ADC Calibration factor."]
253 #[inline(always)]
254 pub const fn calfact(self) -> crate::common::Reg<regs::Adc4Calfact, crate::common::RW> {
255 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
256 }
257 #[doc = "ADC option register."]
258 #[inline(always)]
259 pub const fn or(self) -> crate::common::Reg<regs::Adc4Or, crate::common::RW> {
260 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) }
261 }
262 #[doc = "ADC common configuration register."]
263 #[inline(always)]
264 pub const fn ccr(self) -> crate::common::Reg<regs::Adc4Ccr, crate::common::RW> {
265 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) }
266 }
267}
268pub mod regs {
269 #[doc = "ADC Analog Watchdog Configuration register."]
270 #[repr(transparent)]
271 #[derive(Copy, Clone, Eq, PartialEq)]
272 pub struct Adc4Awdcr(pub u32);
273 impl Adc4Awdcr {
274 #[doc = "AWDCH0."]
275 #[inline(always)]
276 pub const fn awdch(&self, n: usize) -> bool {
277 assert!(n < 24usize);
278 let offs = 0usize + n * 1usize;
279 let val = (self.0 >> offs) & 0x01;
280 val != 0
281 }
282 #[doc = "AWDCH0."]
283 #[inline(always)]
284 pub fn set_awdch(&mut self, n: usize, val: bool) {
285 assert!(n < 24usize);
286 let offs = 0usize + n * 1usize;
287 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
288 }
289 }
290 impl Default for Adc4Awdcr {
291 #[inline(always)]
292 fn default() -> Adc4Awdcr {
293 Adc4Awdcr(0)
294 }
295 }
296 impl core::fmt::Debug for Adc4Awdcr {
297 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
298 f.debug_struct("Adc4Awdcr")
299 .field(
300 "awdch",
301 &[
302 self.awdch(0usize),
303 self.awdch(1usize),
304 self.awdch(2usize),
305 self.awdch(3usize),
306 self.awdch(4usize),
307 self.awdch(5usize),
308 self.awdch(6usize),
309 self.awdch(7usize),
310 self.awdch(8usize),
311 self.awdch(9usize),
312 self.awdch(10usize),
313 self.awdch(11usize),
314 self.awdch(12usize),
315 self.awdch(13usize),
316 self.awdch(14usize),
317 self.awdch(15usize),
318 self.awdch(16usize),
319 self.awdch(17usize),
320 self.awdch(18usize),
321 self.awdch(19usize),
322 self.awdch(20usize),
323 self.awdch(21usize),
324 self.awdch(22usize),
325 self.awdch(23usize),
326 ],
327 )
328 .finish()
329 }
330 }
331 #[cfg(feature = "defmt")]
332 impl defmt::Format for Adc4Awdcr {
333 fn format(&self, f: defmt::Formatter) {
334 #[derive(defmt :: Format)]
335 struct Adc4Awdcr {
336 awdch: [bool; 24usize],
337 }
338 let proxy = Adc4Awdcr {
339 awdch: [
340 self.awdch(0usize),
341 self.awdch(1usize),
342 self.awdch(2usize),
343 self.awdch(3usize),
344 self.awdch(4usize),
345 self.awdch(5usize),
346 self.awdch(6usize),
347 self.awdch(7usize),
348 self.awdch(8usize),
349 self.awdch(9usize),
350 self.awdch(10usize),
351 self.awdch(11usize),
352 self.awdch(12usize),
353 self.awdch(13usize),
354 self.awdch(14usize),
355 self.awdch(15usize),
356 self.awdch(16usize),
357 self.awdch(17usize),
358 self.awdch(18usize),
359 self.awdch(19usize),
360 self.awdch(20usize),
361 self.awdch(21usize),
362 self.awdch(22usize),
363 self.awdch(23usize),
364 ],
365 };
366 defmt::write!(f, "{}", proxy)
367 }
368 }
369 #[doc = "ADC watchdog threshold register."]
370 #[repr(transparent)]
371 #[derive(Copy, Clone, Eq, PartialEq)]
372 pub struct Adc4Awdtr(pub u32);
373 impl Adc4Awdtr {
374 #[doc = "LT3."]
375 #[inline(always)]
376 pub const fn lt3(&self) -> u16 {
377 let val = (self.0 >> 0usize) & 0x0fff;
378 val as u16
379 }
380 #[doc = "LT3."]
381 #[inline(always)]
382 pub fn set_lt3(&mut self, val: u16) {
383 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
384 }
385 #[doc = "HT3."]
386 #[inline(always)]
387 pub const fn ht3(&self) -> u16 {
388 let val = (self.0 >> 16usize) & 0x0fff;
389 val as u16
390 }
391 #[doc = "HT3."]
392 #[inline(always)]
393 pub fn set_ht3(&mut self, val: u16) {
394 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
395 }
396 }
397 impl Default for Adc4Awdtr {
398 #[inline(always)]
399 fn default() -> Adc4Awdtr {
400 Adc4Awdtr(0)
401 }
402 }
403 impl core::fmt::Debug for Adc4Awdtr {
404 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
405 f.debug_struct("Adc4Awdtr")
406 .field("lt3", &self.lt3())
407 .field("ht3", &self.ht3())
408 .finish()
409 }
410 }
411 #[cfg(feature = "defmt")]
412 impl defmt::Format for Adc4Awdtr {
413 fn format(&self, f: defmt::Formatter) {
414 #[derive(defmt :: Format)]
415 struct Adc4Awdtr {
416 lt3: u16,
417 ht3: u16,
418 }
419 let proxy = Adc4Awdtr {
420 lt3: self.lt3(),
421 ht3: self.ht3(),
422 };
423 defmt::write!(f, "{}", proxy)
424 }
425 }
426 #[doc = "ADC Calibration factor."]
427 #[repr(transparent)]
428 #[derive(Copy, Clone, Eq, PartialEq)]
429 pub struct Adc4Calfact(pub u32);
430 impl Adc4Calfact {
431 #[doc = "CALFACT."]
432 #[inline(always)]
433 pub const fn calfact(&self) -> u8 {
434 let val = (self.0 >> 0usize) & 0x7f;
435 val as u8
436 }
437 #[doc = "CALFACT."]
438 #[inline(always)]
439 pub fn set_calfact(&mut self, val: u8) {
440 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
441 }
442 }
443 impl Default for Adc4Calfact {
444 #[inline(always)]
445 fn default() -> Adc4Calfact {
446 Adc4Calfact(0)
447 }
448 }
449 impl core::fmt::Debug for Adc4Calfact {
450 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
451 f.debug_struct("Adc4Calfact").field("calfact", &self.calfact()).finish()
452 }
453 }
454 #[cfg(feature = "defmt")]
455 impl defmt::Format for Adc4Calfact {
456 fn format(&self, f: defmt::Formatter) {
457 #[derive(defmt :: Format)]
458 struct Adc4Calfact {
459 calfact: u8,
460 }
461 let proxy = Adc4Calfact {
462 calfact: self.calfact(),
463 };
464 defmt::write!(f, "{}", proxy)
465 }
466 }
467 #[doc = "ADC common configuration register."]
468 #[repr(transparent)]
469 #[derive(Copy, Clone, Eq, PartialEq)]
470 pub struct Adc4Ccr(pub u32);
471 impl Adc4Ccr {
472 #[doc = "PRESC."]
473 #[inline(always)]
474 pub const fn presc(&self) -> super::vals::Adc4Presc {
475 let val = (self.0 >> 18usize) & 0x0f;
476 super::vals::Adc4Presc::from_bits(val as u8)
477 }
478 #[doc = "PRESC."]
479 #[inline(always)]
480 pub fn set_presc(&mut self, val: super::vals::Adc4Presc) {
481 self.0 = (self.0 & !(0x0f << 18usize)) | (((val.to_bits() as u32) & 0x0f) << 18usize);
482 }
483 #[doc = "VREFEN."]
484 #[inline(always)]
485 pub const fn vrefen(&self) -> bool {
486 let val = (self.0 >> 22usize) & 0x01;
487 val != 0
488 }
489 #[doc = "VREFEN."]
490 #[inline(always)]
491 pub fn set_vrefen(&mut self, val: bool) {
492 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
493 }
494 #[doc = "VSENSESEL."]
495 #[inline(always)]
496 pub const fn vsensesel(&self) -> bool {
497 let val = (self.0 >> 23usize) & 0x01;
498 val != 0
499 }
500 #[doc = "VSENSESEL."]
501 #[inline(always)]
502 pub fn set_vsensesel(&mut self, val: bool) {
503 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
504 }
505 #[doc = "VBATEN."]
506 #[inline(always)]
507 pub const fn vbaten(&self) -> bool {
508 let val = (self.0 >> 24usize) & 0x01;
509 val != 0
510 }
511 #[doc = "VBATEN."]
512 #[inline(always)]
513 pub fn set_vbaten(&mut self, val: bool) {
514 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
515 }
516 }
517 impl Default for Adc4Ccr {
518 #[inline(always)]
519 fn default() -> Adc4Ccr {
520 Adc4Ccr(0)
521 }
522 }
523 impl core::fmt::Debug for Adc4Ccr {
524 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
525 f.debug_struct("Adc4Ccr")
526 .field("presc", &self.presc())
527 .field("vrefen", &self.vrefen())
528 .field("vsensesel", &self.vsensesel())
529 .field("vbaten", &self.vbaten())
530 .finish()
531 }
532 }
533 #[cfg(feature = "defmt")]
534 impl defmt::Format for Adc4Ccr {
535 fn format(&self, f: defmt::Formatter) {
536 #[derive(defmt :: Format)]
537 struct Adc4Ccr {
538 presc: super::vals::Adc4Presc,
539 vrefen: bool,
540 vsensesel: bool,
541 vbaten: bool,
542 }
543 let proxy = Adc4Ccr {
544 presc: self.presc(),
545 vrefen: self.vrefen(),
546 vsensesel: self.vsensesel(),
547 vbaten: self.vbaten(),
548 };
549 defmt::write!(f, "{}", proxy)
550 }
551 }
552 #[doc = "ADC configuration register."]
553 #[repr(transparent)]
554 #[derive(Copy, Clone, Eq, PartialEq)]
555 pub struct Adc4Cfgr1(pub u32);
556 impl Adc4Cfgr1 {
557 #[doc = "DMAEN."]
558 #[inline(always)]
559 pub const fn dmaen(&self) -> bool {
560 let val = (self.0 >> 0usize) & 0x01;
561 val != 0
562 }
563 #[doc = "DMAEN."]
564 #[inline(always)]
565 pub fn set_dmaen(&mut self, val: bool) {
566 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
567 }
568 #[doc = "DMACFG."]
569 #[inline(always)]
570 pub const fn dmacfg(&self) -> super::vals::Adc4Dmacfg {
571 let val = (self.0 >> 1usize) & 0x01;
572 super::vals::Adc4Dmacfg::from_bits(val as u8)
573 }
574 #[doc = "DMACFG."]
575 #[inline(always)]
576 pub fn set_dmacfg(&mut self, val: super::vals::Adc4Dmacfg) {
577 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
578 }
579 #[doc = "RES."]
580 #[inline(always)]
581 pub const fn res(&self) -> super::vals::Adc4Res {
582 let val = (self.0 >> 2usize) & 0x03;
583 super::vals::Adc4Res::from_bits(val as u8)
584 }
585 #[doc = "RES."]
586 #[inline(always)]
587 pub fn set_res(&mut self, val: super::vals::Adc4Res) {
588 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
589 }
590 #[doc = "SCANDIR."]
591 #[inline(always)]
592 pub const fn scandir(&self) -> bool {
593 let val = (self.0 >> 4usize) & 0x01;
594 val != 0
595 }
596 #[doc = "SCANDIR."]
597 #[inline(always)]
598 pub fn set_scandir(&mut self, val: bool) {
599 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
600 }
601 #[doc = "ALIGN."]
602 #[inline(always)]
603 pub const fn align(&self) -> bool {
604 let val = (self.0 >> 5usize) & 0x01;
605 val != 0
606 }
607 #[doc = "ALIGN."]
608 #[inline(always)]
609 pub fn set_align(&mut self, val: bool) {
610 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
611 }
612 #[doc = "EXTSEL."]
613 #[inline(always)]
614 pub const fn extsel(&self) -> u8 {
615 let val = (self.0 >> 6usize) & 0x07;
616 val as u8
617 }
618 #[doc = "EXTSEL."]
619 #[inline(always)]
620 pub fn set_extsel(&mut self, val: u8) {
621 self.0 = (self.0 & !(0x07 << 6usize)) | (((val as u32) & 0x07) << 6usize);
622 }
623 #[doc = "EXTEN."]
624 #[inline(always)]
625 pub const fn exten(&self) -> super::vals::Adc4Exten {
626 let val = (self.0 >> 10usize) & 0x03;
627 super::vals::Adc4Exten::from_bits(val as u8)
628 }
629 #[doc = "EXTEN."]
630 #[inline(always)]
631 pub fn set_exten(&mut self, val: super::vals::Adc4Exten) {
632 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
633 }
634 #[doc = "OVRMOD."]
635 #[inline(always)]
636 pub const fn ovrmod(&self) -> bool {
637 let val = (self.0 >> 12usize) & 0x01;
638 val != 0
639 }
640 #[doc = "OVRMOD."]
641 #[inline(always)]
642 pub fn set_ovrmod(&mut self, val: bool) {
643 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
644 }
645 #[doc = "CONT."]
646 #[inline(always)]
647 pub const fn cont(&self) -> bool {
648 let val = (self.0 >> 13usize) & 0x01;
649 val != 0
650 }
651 #[doc = "CONT."]
652 #[inline(always)]
653 pub fn set_cont(&mut self, val: bool) {
654 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
655 }
656 #[doc = "WAIT."]
657 #[inline(always)]
658 pub const fn wait(&self) -> bool {
659 let val = (self.0 >> 14usize) & 0x01;
660 val != 0
661 }
662 #[doc = "WAIT."]
663 #[inline(always)]
664 pub fn set_wait(&mut self, val: bool) {
665 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
666 }
667 #[doc = "DISCEN."]
668 #[inline(always)]
669 pub const fn discen(&self) -> bool {
670 let val = (self.0 >> 16usize) & 0x01;
671 val != 0
672 }
673 #[doc = "DISCEN."]
674 #[inline(always)]
675 pub fn set_discen(&mut self, val: bool) {
676 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
677 }
678 #[doc = "CHSELRMOD."]
679 #[inline(always)]
680 pub const fn chselrmod(&self) -> bool {
681 let val = (self.0 >> 21usize) & 0x01;
682 val != 0
683 }
684 #[doc = "CHSELRMOD."]
685 #[inline(always)]
686 pub fn set_chselrmod(&mut self, val: bool) {
687 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
688 }
689 #[doc = "AWD1SGL."]
690 #[inline(always)]
691 pub const fn awd1sgl(&self) -> bool {
692 let val = (self.0 >> 22usize) & 0x01;
693 val != 0
694 }
695 #[doc = "AWD1SGL."]
696 #[inline(always)]
697 pub fn set_awd1sgl(&mut self, val: bool) {
698 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
699 }
700 #[doc = "AWD1EN."]
701 #[inline(always)]
702 pub const fn awd1en(&self) -> bool {
703 let val = (self.0 >> 23usize) & 0x01;
704 val != 0
705 }
706 #[doc = "AWD1EN."]
707 #[inline(always)]
708 pub fn set_awd1en(&mut self, val: bool) {
709 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
710 }
711 #[doc = "AWD1CH."]
712 #[inline(always)]
713 pub const fn awd1ch(&self) -> u8 {
714 let val = (self.0 >> 26usize) & 0x1f;
715 val as u8
716 }
717 #[doc = "AWD1CH."]
718 #[inline(always)]
719 pub fn set_awd1ch(&mut self, val: u8) {
720 self.0 = (self.0 & !(0x1f << 26usize)) | (((val as u32) & 0x1f) << 26usize);
721 }
722 }
723 impl Default for Adc4Cfgr1 {
724 #[inline(always)]
725 fn default() -> Adc4Cfgr1 {
726 Adc4Cfgr1(0)
727 }
728 }
729 impl core::fmt::Debug for Adc4Cfgr1 {
730 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
731 f.debug_struct("Adc4Cfgr1")
732 .field("dmaen", &self.dmaen())
733 .field("dmacfg", &self.dmacfg())
734 .field("res", &self.res())
735 .field("scandir", &self.scandir())
736 .field("align", &self.align())
737 .field("extsel", &self.extsel())
738 .field("exten", &self.exten())
739 .field("ovrmod", &self.ovrmod())
740 .field("cont", &self.cont())
741 .field("wait", &self.wait())
742 .field("discen", &self.discen())
743 .field("chselrmod", &self.chselrmod())
744 .field("awd1sgl", &self.awd1sgl())
745 .field("awd1en", &self.awd1en())
746 .field("awd1ch", &self.awd1ch())
747 .finish()
748 }
749 }
750 #[cfg(feature = "defmt")]
751 impl defmt::Format for Adc4Cfgr1 {
752 fn format(&self, f: defmt::Formatter) {
753 #[derive(defmt :: Format)]
754 struct Adc4Cfgr1 {
755 dmaen: bool,
756 dmacfg: super::vals::Adc4Dmacfg,
757 res: super::vals::Adc4Res,
758 scandir: bool,
759 align: bool,
760 extsel: u8,
761 exten: super::vals::Adc4Exten,
762 ovrmod: bool,
763 cont: bool,
764 wait: bool,
765 discen: bool,
766 chselrmod: bool,
767 awd1sgl: bool,
768 awd1en: bool,
769 awd1ch: u8,
770 }
771 let proxy = Adc4Cfgr1 {
772 dmaen: self.dmaen(),
773 dmacfg: self.dmacfg(),
774 res: self.res(),
775 scandir: self.scandir(),
776 align: self.align(),
777 extsel: self.extsel(),
778 exten: self.exten(),
779 ovrmod: self.ovrmod(),
780 cont: self.cont(),
781 wait: self.wait(),
782 discen: self.discen(),
783 chselrmod: self.chselrmod(),
784 awd1sgl: self.awd1sgl(),
785 awd1en: self.awd1en(),
786 awd1ch: self.awd1ch(),
787 };
788 defmt::write!(f, "{}", proxy)
789 }
790 }
791 #[doc = "ADC configuration register 2."]
792 #[repr(transparent)]
793 #[derive(Copy, Clone, Eq, PartialEq)]
794 pub struct Adc4Cfgr2(pub u32);
795 impl Adc4Cfgr2 {
796 #[doc = "OVSE."]
797 #[inline(always)]
798 pub const fn ovse(&self) -> bool {
799 let val = (self.0 >> 0usize) & 0x01;
800 val != 0
801 }
802 #[doc = "OVSE."]
803 #[inline(always)]
804 pub fn set_ovse(&mut self, val: bool) {
805 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
806 }
807 #[doc = "OVSR."]
808 #[inline(always)]
809 pub const fn ovsr(&self) -> super::vals::Adc4OversamplingRatio {
810 let val = (self.0 >> 2usize) & 0x07;
811 super::vals::Adc4OversamplingRatio::from_bits(val as u8)
812 }
813 #[doc = "OVSR."]
814 #[inline(always)]
815 pub fn set_ovsr(&mut self, val: super::vals::Adc4OversamplingRatio) {
816 self.0 = (self.0 & !(0x07 << 2usize)) | (((val.to_bits() as u32) & 0x07) << 2usize);
817 }
818 #[doc = "OVSS."]
819 #[inline(always)]
820 pub const fn ovss(&self) -> u8 {
821 let val = (self.0 >> 5usize) & 0x0f;
822 val as u8
823 }
824 #[doc = "OVSS."]
825 #[inline(always)]
826 pub fn set_ovss(&mut self, val: u8) {
827 self.0 = (self.0 & !(0x0f << 5usize)) | (((val as u32) & 0x0f) << 5usize);
828 }
829 #[doc = "TOVS."]
830 #[inline(always)]
831 pub const fn tovs(&self) -> bool {
832 let val = (self.0 >> 9usize) & 0x01;
833 val != 0
834 }
835 #[doc = "TOVS."]
836 #[inline(always)]
837 pub fn set_tovs(&mut self, val: bool) {
838 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
839 }
840 #[doc = "LFTRIG."]
841 #[inline(always)]
842 pub const fn lftrig(&self) -> bool {
843 let val = (self.0 >> 29usize) & 0x01;
844 val != 0
845 }
846 #[doc = "LFTRIG."]
847 #[inline(always)]
848 pub fn set_lftrig(&mut self, val: bool) {
849 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
850 }
851 }
852 impl Default for Adc4Cfgr2 {
853 #[inline(always)]
854 fn default() -> Adc4Cfgr2 {
855 Adc4Cfgr2(0)
856 }
857 }
858 impl core::fmt::Debug for Adc4Cfgr2 {
859 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
860 f.debug_struct("Adc4Cfgr2")
861 .field("ovse", &self.ovse())
862 .field("ovsr", &self.ovsr())
863 .field("ovss", &self.ovss())
864 .field("tovs", &self.tovs())
865 .field("lftrig", &self.lftrig())
866 .finish()
867 }
868 }
869 #[cfg(feature = "defmt")]
870 impl defmt::Format for Adc4Cfgr2 {
871 fn format(&self, f: defmt::Formatter) {
872 #[derive(defmt :: Format)]
873 struct Adc4Cfgr2 {
874 ovse: bool,
875 ovsr: super::vals::Adc4OversamplingRatio,
876 ovss: u8,
877 tovs: bool,
878 lftrig: bool,
879 }
880 let proxy = Adc4Cfgr2 {
881 ovse: self.ovse(),
882 ovsr: self.ovsr(),
883 ovss: self.ovss(),
884 tovs: self.tovs(),
885 lftrig: self.lftrig(),
886 };
887 defmt::write!(f, "{}", proxy)
888 }
889 }
890 #[doc = "ADC channel selection register \\[alternate\\]."]
891 #[repr(transparent)]
892 #[derive(Copy, Clone, Eq, PartialEq)]
893 pub struct Adc4Chselrmod0(pub u32);
894 impl Adc4Chselrmod0 {
895 #[doc = "CHSEL."]
896 #[inline(always)]
897 pub const fn chsel(&self, n: usize) -> bool {
898 assert!(n < 24usize);
899 let offs = 0usize + n * 1usize;
900 let val = (self.0 >> offs) & 0x01;
901 val != 0
902 }
903 #[doc = "CHSEL."]
904 #[inline(always)]
905 pub fn set_chsel(&mut self, n: usize, val: bool) {
906 assert!(n < 24usize);
907 let offs = 0usize + n * 1usize;
908 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
909 }
910 }
911 impl Default for Adc4Chselrmod0 {
912 #[inline(always)]
913 fn default() -> Adc4Chselrmod0 {
914 Adc4Chselrmod0(0)
915 }
916 }
917 impl core::fmt::Debug for Adc4Chselrmod0 {
918 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
919 f.debug_struct("Adc4Chselrmod0")
920 .field(
921 "chsel",
922 &[
923 self.chsel(0usize),
924 self.chsel(1usize),
925 self.chsel(2usize),
926 self.chsel(3usize),
927 self.chsel(4usize),
928 self.chsel(5usize),
929 self.chsel(6usize),
930 self.chsel(7usize),
931 self.chsel(8usize),
932 self.chsel(9usize),
933 self.chsel(10usize),
934 self.chsel(11usize),
935 self.chsel(12usize),
936 self.chsel(13usize),
937 self.chsel(14usize),
938 self.chsel(15usize),
939 self.chsel(16usize),
940 self.chsel(17usize),
941 self.chsel(18usize),
942 self.chsel(19usize),
943 self.chsel(20usize),
944 self.chsel(21usize),
945 self.chsel(22usize),
946 self.chsel(23usize),
947 ],
948 )
949 .finish()
950 }
951 }
952 #[cfg(feature = "defmt")]
953 impl defmt::Format for Adc4Chselrmod0 {
954 fn format(&self, f: defmt::Formatter) {
955 #[derive(defmt :: Format)]
956 struct Adc4Chselrmod0 {
957 chsel: [bool; 24usize],
958 }
959 let proxy = Adc4Chselrmod0 {
960 chsel: [
961 self.chsel(0usize),
962 self.chsel(1usize),
963 self.chsel(2usize),
964 self.chsel(3usize),
965 self.chsel(4usize),
966 self.chsel(5usize),
967 self.chsel(6usize),
968 self.chsel(7usize),
969 self.chsel(8usize),
970 self.chsel(9usize),
971 self.chsel(10usize),
972 self.chsel(11usize),
973 self.chsel(12usize),
974 self.chsel(13usize),
975 self.chsel(14usize),
976 self.chsel(15usize),
977 self.chsel(16usize),
978 self.chsel(17usize),
979 self.chsel(18usize),
980 self.chsel(19usize),
981 self.chsel(20usize),
982 self.chsel(21usize),
983 self.chsel(22usize),
984 self.chsel(23usize),
985 ],
986 };
987 defmt::write!(f, "{}", proxy)
988 }
989 }
990 #[doc = "ADC channel selection register \\[alternate\\]."]
991 #[repr(transparent)]
992 #[derive(Copy, Clone, Eq, PartialEq)]
993 pub struct Adc4Chselrmod1(pub u32);
994 impl Adc4Chselrmod1 {
995 #[doc = "SQ"]
996 #[inline(always)]
997 pub const fn sq(&self, n: usize) -> u8 {
998 assert!(n < 8usize);
999 let offs = 0usize + n * 4usize;
1000 let val = (self.0 >> offs) & 0x0f;
1001 val as u8
1002 }
1003 #[doc = "SQ"]
1004 #[inline(always)]
1005 pub fn set_sq(&mut self, n: usize, val: u8) {
1006 assert!(n < 8usize);
1007 let offs = 0usize + n * 4usize;
1008 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
1009 }
1010 }
1011 impl Default for Adc4Chselrmod1 {
1012 #[inline(always)]
1013 fn default() -> Adc4Chselrmod1 {
1014 Adc4Chselrmod1(0)
1015 }
1016 }
1017 impl core::fmt::Debug for Adc4Chselrmod1 {
1018 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1019 f.debug_struct("Adc4Chselrmod1")
1020 .field(
1021 "sq",
1022 &[
1023 self.sq(0usize),
1024 self.sq(1usize),
1025 self.sq(2usize),
1026 self.sq(3usize),
1027 self.sq(4usize),
1028 self.sq(5usize),
1029 self.sq(6usize),
1030 self.sq(7usize),
1031 ],
1032 )
1033 .finish()
1034 }
1035 }
1036 #[cfg(feature = "defmt")]
1037 impl defmt::Format for Adc4Chselrmod1 {
1038 fn format(&self, f: defmt::Formatter) {
1039 #[derive(defmt :: Format)]
1040 struct Adc4Chselrmod1 {
1041 sq: [u8; 8usize],
1042 }
1043 let proxy = Adc4Chselrmod1 {
1044 sq: [
1045 self.sq(0usize),
1046 self.sq(1usize),
1047 self.sq(2usize),
1048 self.sq(3usize),
1049 self.sq(4usize),
1050 self.sq(5usize),
1051 self.sq(6usize),
1052 self.sq(7usize),
1053 ],
1054 };
1055 defmt::write!(f, "{}", proxy)
1056 }
1057 }
1058 #[doc = "ADC control register."]
1059 #[repr(transparent)]
1060 #[derive(Copy, Clone, Eq, PartialEq)]
1061 pub struct Adc4Cr(pub u32);
1062 impl Adc4Cr {
1063 #[doc = "ADEN."]
1064 #[inline(always)]
1065 pub const fn aden(&self) -> bool {
1066 let val = (self.0 >> 0usize) & 0x01;
1067 val != 0
1068 }
1069 #[doc = "ADEN."]
1070 #[inline(always)]
1071 pub fn set_aden(&mut self, val: bool) {
1072 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1073 }
1074 #[doc = "ADDIS."]
1075 #[inline(always)]
1076 pub const fn addis(&self) -> bool {
1077 let val = (self.0 >> 1usize) & 0x01;
1078 val != 0
1079 }
1080 #[doc = "ADDIS."]
1081 #[inline(always)]
1082 pub fn set_addis(&mut self, val: bool) {
1083 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1084 }
1085 #[doc = "ADSTART."]
1086 #[inline(always)]
1087 pub const fn adstart(&self) -> bool {
1088 let val = (self.0 >> 2usize) & 0x01;
1089 val != 0
1090 }
1091 #[doc = "ADSTART."]
1092 #[inline(always)]
1093 pub fn set_adstart(&mut self, val: bool) {
1094 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1095 }
1096 #[doc = "ADSTP."]
1097 #[inline(always)]
1098 pub const fn adstp(&self) -> bool {
1099 let val = (self.0 >> 4usize) & 0x01;
1100 val != 0
1101 }
1102 #[doc = "ADSTP."]
1103 #[inline(always)]
1104 pub fn set_adstp(&mut self, val: bool) {
1105 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1106 }
1107 #[doc = "ADVREGEN."]
1108 #[inline(always)]
1109 pub const fn advregen(&self) -> bool {
1110 let val = (self.0 >> 28usize) & 0x01;
1111 val != 0
1112 }
1113 #[doc = "ADVREGEN."]
1114 #[inline(always)]
1115 pub fn set_advregen(&mut self, val: bool) {
1116 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1117 }
1118 #[doc = "ADCAL."]
1119 #[inline(always)]
1120 pub const fn adcal(&self) -> bool {
1121 let val = (self.0 >> 31usize) & 0x01;
1122 val != 0
1123 }
1124 #[doc = "ADCAL."]
1125 #[inline(always)]
1126 pub fn set_adcal(&mut self, val: bool) {
1127 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1128 }
1129 }
1130 impl Default for Adc4Cr {
1131 #[inline(always)]
1132 fn default() -> Adc4Cr {
1133 Adc4Cr(0)
1134 }
1135 }
1136 impl core::fmt::Debug for Adc4Cr {
1137 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1138 f.debug_struct("Adc4Cr")
1139 .field("aden", &self.aden())
1140 .field("addis", &self.addis())
1141 .field("adstart", &self.adstart())
1142 .field("adstp", &self.adstp())
1143 .field("advregen", &self.advregen())
1144 .field("adcal", &self.adcal())
1145 .finish()
1146 }
1147 }
1148 #[cfg(feature = "defmt")]
1149 impl defmt::Format for Adc4Cr {
1150 fn format(&self, f: defmt::Formatter) {
1151 #[derive(defmt :: Format)]
1152 struct Adc4Cr {
1153 aden: bool,
1154 addis: bool,
1155 adstart: bool,
1156 adstp: bool,
1157 advregen: bool,
1158 adcal: bool,
1159 }
1160 let proxy = Adc4Cr {
1161 aden: self.aden(),
1162 addis: self.addis(),
1163 adstart: self.adstart(),
1164 adstp: self.adstp(),
1165 advregen: self.advregen(),
1166 adcal: self.adcal(),
1167 };
1168 defmt::write!(f, "{}", proxy)
1169 }
1170 }
1171 #[doc = "ADC data register."]
1172 #[repr(transparent)]
1173 #[derive(Copy, Clone, Eq, PartialEq)]
1174 pub struct Adc4Dr(pub u32);
1175 impl Adc4Dr {
1176 #[doc = "DATA."]
1177 #[inline(always)]
1178 pub const fn data(&self) -> u16 {
1179 let val = (self.0 >> 0usize) & 0xffff;
1180 val as u16
1181 }
1182 #[doc = "DATA."]
1183 #[inline(always)]
1184 pub fn set_data(&mut self, val: u16) {
1185 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1186 }
1187 }
1188 impl Default for Adc4Dr {
1189 #[inline(always)]
1190 fn default() -> Adc4Dr {
1191 Adc4Dr(0)
1192 }
1193 }
1194 impl core::fmt::Debug for Adc4Dr {
1195 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1196 f.debug_struct("Adc4Dr").field("data", &self.data()).finish()
1197 }
1198 }
1199 #[cfg(feature = "defmt")]
1200 impl defmt::Format for Adc4Dr {
1201 fn format(&self, f: defmt::Formatter) {
1202 #[derive(defmt :: Format)]
1203 struct Adc4Dr {
1204 data: u16,
1205 }
1206 let proxy = Adc4Dr { data: self.data() };
1207 defmt::write!(f, "{}", proxy)
1208 }
1209 }
1210 #[doc = "ADC interrupt enable register."]
1211 #[repr(transparent)]
1212 #[derive(Copy, Clone, Eq, PartialEq)]
1213 pub struct Adc4Ier(pub u32);
1214 impl Adc4Ier {
1215 #[doc = "ADRDYIE."]
1216 #[inline(always)]
1217 pub const fn adrdyie(&self) -> bool {
1218 let val = (self.0 >> 0usize) & 0x01;
1219 val != 0
1220 }
1221 #[doc = "ADRDYIE."]
1222 #[inline(always)]
1223 pub fn set_adrdyie(&mut self, val: bool) {
1224 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1225 }
1226 #[doc = "EOSMPIE."]
1227 #[inline(always)]
1228 pub const fn eosmpie(&self) -> bool {
1229 let val = (self.0 >> 1usize) & 0x01;
1230 val != 0
1231 }
1232 #[doc = "EOSMPIE."]
1233 #[inline(always)]
1234 pub fn set_eosmpie(&mut self, val: bool) {
1235 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1236 }
1237 #[doc = "EOCIE."]
1238 #[inline(always)]
1239 pub const fn eocie(&self) -> bool {
1240 let val = (self.0 >> 2usize) & 0x01;
1241 val != 0
1242 }
1243 #[doc = "EOCIE."]
1244 #[inline(always)]
1245 pub fn set_eocie(&mut self, val: bool) {
1246 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1247 }
1248 #[doc = "EOSIE."]
1249 #[inline(always)]
1250 pub const fn eosie(&self) -> bool {
1251 let val = (self.0 >> 3usize) & 0x01;
1252 val != 0
1253 }
1254 #[doc = "EOSIE."]
1255 #[inline(always)]
1256 pub fn set_eosie(&mut self, val: bool) {
1257 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1258 }
1259 #[doc = "OVRIE."]
1260 #[inline(always)]
1261 pub const fn ovrie(&self) -> bool {
1262 let val = (self.0 >> 4usize) & 0x01;
1263 val != 0
1264 }
1265 #[doc = "OVRIE."]
1266 #[inline(always)]
1267 pub fn set_ovrie(&mut self, val: bool) {
1268 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1269 }
1270 #[doc = "AWD1IE."]
1271 #[inline(always)]
1272 pub const fn awdie(&self, n: usize) -> bool {
1273 assert!(n < 3usize);
1274 let offs = 7usize + n * 1usize;
1275 let val = (self.0 >> offs) & 0x01;
1276 val != 0
1277 }
1278 #[doc = "AWD1IE."]
1279 #[inline(always)]
1280 pub fn set_awdie(&mut self, n: usize, val: bool) {
1281 assert!(n < 3usize);
1282 let offs = 7usize + n * 1usize;
1283 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1284 }
1285 #[doc = "EOCALIE."]
1286 #[inline(always)]
1287 pub const fn eocalie(&self) -> bool {
1288 let val = (self.0 >> 11usize) & 0x01;
1289 val != 0
1290 }
1291 #[doc = "EOCALIE."]
1292 #[inline(always)]
1293 pub fn set_eocalie(&mut self, val: bool) {
1294 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1295 }
1296 #[doc = "LDORDYIE."]
1297 #[inline(always)]
1298 pub const fn ldordyie(&self) -> bool {
1299 let val = (self.0 >> 12usize) & 0x01;
1300 val != 0
1301 }
1302 #[doc = "LDORDYIE."]
1303 #[inline(always)]
1304 pub fn set_ldordyie(&mut self, val: bool) {
1305 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1306 }
1307 }
1308 impl Default for Adc4Ier {
1309 #[inline(always)]
1310 fn default() -> Adc4Ier {
1311 Adc4Ier(0)
1312 }
1313 }
1314 impl core::fmt::Debug for Adc4Ier {
1315 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1316 f.debug_struct("Adc4Ier")
1317 .field("adrdyie", &self.adrdyie())
1318 .field("eosmpie", &self.eosmpie())
1319 .field("eocie", &self.eocie())
1320 .field("eosie", &self.eosie())
1321 .field("ovrie", &self.ovrie())
1322 .field("awdie", &[self.awdie(0usize), self.awdie(1usize), self.awdie(2usize)])
1323 .field("eocalie", &self.eocalie())
1324 .field("ldordyie", &self.ldordyie())
1325 .finish()
1326 }
1327 }
1328 #[cfg(feature = "defmt")]
1329 impl defmt::Format for Adc4Ier {
1330 fn format(&self, f: defmt::Formatter) {
1331 #[derive(defmt :: Format)]
1332 struct Adc4Ier {
1333 adrdyie: bool,
1334 eosmpie: bool,
1335 eocie: bool,
1336 eosie: bool,
1337 ovrie: bool,
1338 awdie: [bool; 3usize],
1339 eocalie: bool,
1340 ldordyie: bool,
1341 }
1342 let proxy = Adc4Ier {
1343 adrdyie: self.adrdyie(),
1344 eosmpie: self.eosmpie(),
1345 eocie: self.eocie(),
1346 eosie: self.eosie(),
1347 ovrie: self.ovrie(),
1348 awdie: [self.awdie(0usize), self.awdie(1usize), self.awdie(2usize)],
1349 eocalie: self.eocalie(),
1350 ldordyie: self.ldordyie(),
1351 };
1352 defmt::write!(f, "{}", proxy)
1353 }
1354 }
1355 #[doc = "ADC interrupt and status register."]
1356 #[repr(transparent)]
1357 #[derive(Copy, Clone, Eq, PartialEq)]
1358 pub struct Adc4Isr(pub u32);
1359 impl Adc4Isr {
1360 #[doc = "ADRDY."]
1361 #[inline(always)]
1362 pub const fn adrdy(&self) -> bool {
1363 let val = (self.0 >> 0usize) & 0x01;
1364 val != 0
1365 }
1366 #[doc = "ADRDY."]
1367 #[inline(always)]
1368 pub fn set_adrdy(&mut self, val: bool) {
1369 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1370 }
1371 #[doc = "EOSMP."]
1372 #[inline(always)]
1373 pub const fn eosmp(&self) -> bool {
1374 let val = (self.0 >> 1usize) & 0x01;
1375 val != 0
1376 }
1377 #[doc = "EOSMP."]
1378 #[inline(always)]
1379 pub fn set_eosmp(&mut self, val: bool) {
1380 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1381 }
1382 #[doc = "EOC."]
1383 #[inline(always)]
1384 pub const fn eoc(&self) -> bool {
1385 let val = (self.0 >> 2usize) & 0x01;
1386 val != 0
1387 }
1388 #[doc = "EOC."]
1389 #[inline(always)]
1390 pub fn set_eoc(&mut self, val: bool) {
1391 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1392 }
1393 #[doc = "EOS."]
1394 #[inline(always)]
1395 pub const fn eos(&self) -> bool {
1396 let val = (self.0 >> 3usize) & 0x01;
1397 val != 0
1398 }
1399 #[doc = "EOS."]
1400 #[inline(always)]
1401 pub fn set_eos(&mut self, val: bool) {
1402 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1403 }
1404 #[doc = "OVR."]
1405 #[inline(always)]
1406 pub const fn ovr(&self) -> bool {
1407 let val = (self.0 >> 4usize) & 0x01;
1408 val != 0
1409 }
1410 #[doc = "OVR."]
1411 #[inline(always)]
1412 pub fn set_ovr(&mut self, val: bool) {
1413 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1414 }
1415 #[doc = "AWD1."]
1416 #[inline(always)]
1417 pub const fn awd(&self, n: usize) -> bool {
1418 assert!(n < 3usize);
1419 let offs = 7usize + n * 1usize;
1420 let val = (self.0 >> offs) & 0x01;
1421 val != 0
1422 }
1423 #[doc = "AWD1."]
1424 #[inline(always)]
1425 pub fn set_awd(&mut self, n: usize, val: bool) {
1426 assert!(n < 3usize);
1427 let offs = 7usize + n * 1usize;
1428 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1429 }
1430 #[doc = "EOCAL."]
1431 #[inline(always)]
1432 pub const fn eocal(&self) -> bool {
1433 let val = (self.0 >> 11usize) & 0x01;
1434 val != 0
1435 }
1436 #[doc = "EOCAL."]
1437 #[inline(always)]
1438 pub fn set_eocal(&mut self, val: bool) {
1439 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1440 }
1441 #[doc = "LDORDY."]
1442 #[inline(always)]
1443 pub const fn ldordy(&self) -> bool {
1444 let val = (self.0 >> 12usize) & 0x01;
1445 val != 0
1446 }
1447 #[doc = "LDORDY."]
1448 #[inline(always)]
1449 pub fn set_ldordy(&mut self, val: bool) {
1450 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1451 }
1452 }
1453 impl Default for Adc4Isr {
1454 #[inline(always)]
1455 fn default() -> Adc4Isr {
1456 Adc4Isr(0)
1457 }
1458 }
1459 impl core::fmt::Debug for Adc4Isr {
1460 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1461 f.debug_struct("Adc4Isr")
1462 .field("adrdy", &self.adrdy())
1463 .field("eosmp", &self.eosmp())
1464 .field("eoc", &self.eoc())
1465 .field("eos", &self.eos())
1466 .field("ovr", &self.ovr())
1467 .field("awd", &[self.awd(0usize), self.awd(1usize), self.awd(2usize)])
1468 .field("eocal", &self.eocal())
1469 .field("ldordy", &self.ldordy())
1470 .finish()
1471 }
1472 }
1473 #[cfg(feature = "defmt")]
1474 impl defmt::Format for Adc4Isr {
1475 fn format(&self, f: defmt::Formatter) {
1476 #[derive(defmt :: Format)]
1477 struct Adc4Isr {
1478 adrdy: bool,
1479 eosmp: bool,
1480 eoc: bool,
1481 eos: bool,
1482 ovr: bool,
1483 awd: [bool; 3usize],
1484 eocal: bool,
1485 ldordy: bool,
1486 }
1487 let proxy = Adc4Isr {
1488 adrdy: self.adrdy(),
1489 eosmp: self.eosmp(),
1490 eoc: self.eoc(),
1491 eos: self.eos(),
1492 ovr: self.ovr(),
1493 awd: [self.awd(0usize), self.awd(1usize), self.awd(2usize)],
1494 eocal: self.eocal(),
1495 ldordy: self.ldordy(),
1496 };
1497 defmt::write!(f, "{}", proxy)
1498 }
1499 }
1500 #[doc = "ADC option register."]
1501 #[repr(transparent)]
1502 #[derive(Copy, Clone, Eq, PartialEq)]
1503 pub struct Adc4Or(pub u32);
1504 impl Adc4Or {
1505 #[doc = "CHN21SEL."]
1506 #[inline(always)]
1507 pub const fn chn21sel(&self) -> bool {
1508 let val = (self.0 >> 0usize) & 0x01;
1509 val != 0
1510 }
1511 #[doc = "CHN21SEL."]
1512 #[inline(always)]
1513 pub fn set_chn21sel(&mut self, val: bool) {
1514 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1515 }
1516 }
1517 impl Default for Adc4Or {
1518 #[inline(always)]
1519 fn default() -> Adc4Or {
1520 Adc4Or(0)
1521 }
1522 }
1523 impl core::fmt::Debug for Adc4Or {
1524 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1525 f.debug_struct("Adc4Or").field("chn21sel", &self.chn21sel()).finish()
1526 }
1527 }
1528 #[cfg(feature = "defmt")]
1529 impl defmt::Format for Adc4Or {
1530 fn format(&self, f: defmt::Formatter) {
1531 #[derive(defmt :: Format)]
1532 struct Adc4Or {
1533 chn21sel: bool,
1534 }
1535 let proxy = Adc4Or {
1536 chn21sel: self.chn21sel(),
1537 };
1538 defmt::write!(f, "{}", proxy)
1539 }
1540 }
1541 #[doc = "ADC data register."]
1542 #[repr(transparent)]
1543 #[derive(Copy, Clone, Eq, PartialEq)]
1544 pub struct Adc4Pwrr(pub u32);
1545 impl Adc4Pwrr {
1546 #[doc = "AUTOFF."]
1547 #[inline(always)]
1548 pub const fn autoff(&self) -> bool {
1549 let val = (self.0 >> 0usize) & 0x01;
1550 val != 0
1551 }
1552 #[doc = "AUTOFF."]
1553 #[inline(always)]
1554 pub fn set_autoff(&mut self, val: bool) {
1555 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1556 }
1557 #[doc = "DPD."]
1558 #[inline(always)]
1559 pub const fn dpd(&self) -> bool {
1560 let val = (self.0 >> 1usize) & 0x01;
1561 val != 0
1562 }
1563 #[doc = "DPD."]
1564 #[inline(always)]
1565 pub fn set_dpd(&mut self, val: bool) {
1566 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1567 }
1568 #[doc = "VREFPROT."]
1569 #[inline(always)]
1570 pub const fn vrefprot(&self) -> bool {
1571 let val = (self.0 >> 2usize) & 0x01;
1572 val != 0
1573 }
1574 #[doc = "VREFPROT."]
1575 #[inline(always)]
1576 pub fn set_vrefprot(&mut self, val: bool) {
1577 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1578 }
1579 #[doc = "VREFSECSMP."]
1580 #[inline(always)]
1581 pub const fn vrefsecsmp(&self) -> bool {
1582 let val = (self.0 >> 3usize) & 0x01;
1583 val != 0
1584 }
1585 #[doc = "VREFSECSMP."]
1586 #[inline(always)]
1587 pub fn set_vrefsecsmp(&mut self, val: bool) {
1588 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1589 }
1590 }
1591 impl Default for Adc4Pwrr {
1592 #[inline(always)]
1593 fn default() -> Adc4Pwrr {
1594 Adc4Pwrr(0)
1595 }
1596 }
1597 impl core::fmt::Debug for Adc4Pwrr {
1598 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1599 f.debug_struct("Adc4Pwrr")
1600 .field("autoff", &self.autoff())
1601 .field("dpd", &self.dpd())
1602 .field("vrefprot", &self.vrefprot())
1603 .field("vrefsecsmp", &self.vrefsecsmp())
1604 .finish()
1605 }
1606 }
1607 #[cfg(feature = "defmt")]
1608 impl defmt::Format for Adc4Pwrr {
1609 fn format(&self, f: defmt::Formatter) {
1610 #[derive(defmt :: Format)]
1611 struct Adc4Pwrr {
1612 autoff: bool,
1613 dpd: bool,
1614 vrefprot: bool,
1615 vrefsecsmp: bool,
1616 }
1617 let proxy = Adc4Pwrr {
1618 autoff: self.autoff(),
1619 dpd: self.dpd(),
1620 vrefprot: self.vrefprot(),
1621 vrefsecsmp: self.vrefsecsmp(),
1622 };
1623 defmt::write!(f, "{}", proxy)
1624 }
1625 }
1626 #[doc = "ADC sample time register."]
1627 #[repr(transparent)]
1628 #[derive(Copy, Clone, Eq, PartialEq)]
1629 pub struct Adc4Smpr(pub u32);
1630 impl Adc4Smpr {
1631 #[doc = "SMP1."]
1632 #[inline(always)]
1633 pub const fn smp(&self, n: usize) -> super::vals::Adc4SampleTime {
1634 assert!(n < 2usize);
1635 let offs = 0usize + n * 4usize;
1636 let val = (self.0 >> offs) & 0x07;
1637 super::vals::Adc4SampleTime::from_bits(val as u8)
1638 }
1639 #[doc = "SMP1."]
1640 #[inline(always)]
1641 pub fn set_smp(&mut self, n: usize, val: super::vals::Adc4SampleTime) {
1642 assert!(n < 2usize);
1643 let offs = 0usize + n * 4usize;
1644 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32) & 0x07) << offs);
1645 }
1646 #[doc = "SMPSEL0."]
1647 #[inline(always)]
1648 pub const fn smpsel(&self, n: usize) -> bool {
1649 assert!(n < 24usize);
1650 let offs = 8usize + n * 1usize;
1651 let val = (self.0 >> offs) & 0x01;
1652 val != 0
1653 }
1654 #[doc = "SMPSEL0."]
1655 #[inline(always)]
1656 pub fn set_smpsel(&mut self, n: usize, val: bool) {
1657 assert!(n < 24usize);
1658 let offs = 8usize + n * 1usize;
1659 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1660 }
1661 }
1662 impl Default for Adc4Smpr {
1663 #[inline(always)]
1664 fn default() -> Adc4Smpr {
1665 Adc4Smpr(0)
1666 }
1667 }
1668 impl core::fmt::Debug for Adc4Smpr {
1669 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1670 f.debug_struct("Adc4Smpr")
1671 .field("smp", &[self.smp(0usize), self.smp(1usize)])
1672 .field(
1673 "smpsel",
1674 &[
1675 self.smpsel(0usize),
1676 self.smpsel(1usize),
1677 self.smpsel(2usize),
1678 self.smpsel(3usize),
1679 self.smpsel(4usize),
1680 self.smpsel(5usize),
1681 self.smpsel(6usize),
1682 self.smpsel(7usize),
1683 self.smpsel(8usize),
1684 self.smpsel(9usize),
1685 self.smpsel(10usize),
1686 self.smpsel(11usize),
1687 self.smpsel(12usize),
1688 self.smpsel(13usize),
1689 self.smpsel(14usize),
1690 self.smpsel(15usize),
1691 self.smpsel(16usize),
1692 self.smpsel(17usize),
1693 self.smpsel(18usize),
1694 self.smpsel(19usize),
1695 self.smpsel(20usize),
1696 self.smpsel(21usize),
1697 self.smpsel(22usize),
1698 self.smpsel(23usize),
1699 ],
1700 )
1701 .finish()
1702 }
1703 }
1704 #[cfg(feature = "defmt")]
1705 impl defmt::Format for Adc4Smpr {
1706 fn format(&self, f: defmt::Formatter) {
1707 #[derive(defmt :: Format)]
1708 struct Adc4Smpr {
1709 smp: [super::vals::Adc4SampleTime; 2usize],
1710 smpsel: [bool; 24usize],
1711 }
1712 let proxy = Adc4Smpr {
1713 smp: [self.smp(0usize), self.smp(1usize)],
1714 smpsel: [
1715 self.smpsel(0usize),
1716 self.smpsel(1usize),
1717 self.smpsel(2usize),
1718 self.smpsel(3usize),
1719 self.smpsel(4usize),
1720 self.smpsel(5usize),
1721 self.smpsel(6usize),
1722 self.smpsel(7usize),
1723 self.smpsel(8usize),
1724 self.smpsel(9usize),
1725 self.smpsel(10usize),
1726 self.smpsel(11usize),
1727 self.smpsel(12usize),
1728 self.smpsel(13usize),
1729 self.smpsel(14usize),
1730 self.smpsel(15usize),
1731 self.smpsel(16usize),
1732 self.smpsel(17usize),
1733 self.smpsel(18usize),
1734 self.smpsel(19usize),
1735 self.smpsel(20usize),
1736 self.smpsel(21usize),
1737 self.smpsel(22usize),
1738 self.smpsel(23usize),
1739 ],
1740 };
1741 defmt::write!(f, "{}", proxy)
1742 }
1743 }
1744 #[doc = "ADC analog watchdog 2 configuration register."]
1745 #[repr(transparent)]
1746 #[derive(Copy, Clone, Eq, PartialEq)]
1747 pub struct Awd2cr(pub u32);
1748 impl Awd2cr {
1749 #[doc = "AWD2CH."]
1750 #[inline(always)]
1751 pub const fn awd2ch(&self, n: usize) -> bool {
1752 assert!(n < 20usize);
1753 let offs = 0usize + n * 1usize;
1754 let val = (self.0 >> offs) & 0x01;
1755 val != 0
1756 }
1757 #[doc = "AWD2CH."]
1758 #[inline(always)]
1759 pub fn set_awd2ch(&mut self, n: usize, val: bool) {
1760 assert!(n < 20usize);
1761 let offs = 0usize + n * 1usize;
1762 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1763 }
1764 }
1765 impl Default for Awd2cr {
1766 #[inline(always)]
1767 fn default() -> Awd2cr {
1768 Awd2cr(0)
1769 }
1770 }
1771 impl core::fmt::Debug for Awd2cr {
1772 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1773 f.debug_struct("Awd2cr")
1774 .field(
1775 "awd2ch",
1776 &[
1777 self.awd2ch(0usize),
1778 self.awd2ch(1usize),
1779 self.awd2ch(2usize),
1780 self.awd2ch(3usize),
1781 self.awd2ch(4usize),
1782 self.awd2ch(5usize),
1783 self.awd2ch(6usize),
1784 self.awd2ch(7usize),
1785 self.awd2ch(8usize),
1786 self.awd2ch(9usize),
1787 self.awd2ch(10usize),
1788 self.awd2ch(11usize),
1789 self.awd2ch(12usize),
1790 self.awd2ch(13usize),
1791 self.awd2ch(14usize),
1792 self.awd2ch(15usize),
1793 self.awd2ch(16usize),
1794 self.awd2ch(17usize),
1795 self.awd2ch(18usize),
1796 self.awd2ch(19usize),
1797 ],
1798 )
1799 .finish()
1800 }
1801 }
1802 #[cfg(feature = "defmt")]
1803 impl defmt::Format for Awd2cr {
1804 fn format(&self, f: defmt::Formatter) {
1805 #[derive(defmt :: Format)]
1806 struct Awd2cr {
1807 awd2ch: [bool; 20usize],
1808 }
1809 let proxy = Awd2cr {
1810 awd2ch: [
1811 self.awd2ch(0usize),
1812 self.awd2ch(1usize),
1813 self.awd2ch(2usize),
1814 self.awd2ch(3usize),
1815 self.awd2ch(4usize),
1816 self.awd2ch(5usize),
1817 self.awd2ch(6usize),
1818 self.awd2ch(7usize),
1819 self.awd2ch(8usize),
1820 self.awd2ch(9usize),
1821 self.awd2ch(10usize),
1822 self.awd2ch(11usize),
1823 self.awd2ch(12usize),
1824 self.awd2ch(13usize),
1825 self.awd2ch(14usize),
1826 self.awd2ch(15usize),
1827 self.awd2ch(16usize),
1828 self.awd2ch(17usize),
1829 self.awd2ch(18usize),
1830 self.awd2ch(19usize),
1831 ],
1832 };
1833 defmt::write!(f, "{}", proxy)
1834 }
1835 }
1836 #[doc = "ADC analog watchdog 3 configuration register."]
1837 #[repr(transparent)]
1838 #[derive(Copy, Clone, Eq, PartialEq)]
1839 pub struct Awd3cr(pub u32);
1840 impl Awd3cr {
1841 #[doc = "AWD3CH."]
1842 #[inline(always)]
1843 pub const fn awd3ch(&self, n: usize) -> bool {
1844 assert!(n < 20usize);
1845 let offs = 0usize + n * 1usize;
1846 let val = (self.0 >> offs) & 0x01;
1847 val != 0
1848 }
1849 #[doc = "AWD3CH."]
1850 #[inline(always)]
1851 pub fn set_awd3ch(&mut self, n: usize, val: bool) {
1852 assert!(n < 20usize);
1853 let offs = 0usize + n * 1usize;
1854 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1855 }
1856 }
1857 impl Default for Awd3cr {
1858 #[inline(always)]
1859 fn default() -> Awd3cr {
1860 Awd3cr(0)
1861 }
1862 }
1863 impl core::fmt::Debug for Awd3cr {
1864 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1865 f.debug_struct("Awd3cr")
1866 .field(
1867 "awd3ch",
1868 &[
1869 self.awd3ch(0usize),
1870 self.awd3ch(1usize),
1871 self.awd3ch(2usize),
1872 self.awd3ch(3usize),
1873 self.awd3ch(4usize),
1874 self.awd3ch(5usize),
1875 self.awd3ch(6usize),
1876 self.awd3ch(7usize),
1877 self.awd3ch(8usize),
1878 self.awd3ch(9usize),
1879 self.awd3ch(10usize),
1880 self.awd3ch(11usize),
1881 self.awd3ch(12usize),
1882 self.awd3ch(13usize),
1883 self.awd3ch(14usize),
1884 self.awd3ch(15usize),
1885 self.awd3ch(16usize),
1886 self.awd3ch(17usize),
1887 self.awd3ch(18usize),
1888 self.awd3ch(19usize),
1889 ],
1890 )
1891 .finish()
1892 }
1893 }
1894 #[cfg(feature = "defmt")]
1895 impl defmt::Format for Awd3cr {
1896 fn format(&self, f: defmt::Formatter) {
1897 #[derive(defmt :: Format)]
1898 struct Awd3cr {
1899 awd3ch: [bool; 20usize],
1900 }
1901 let proxy = Awd3cr {
1902 awd3ch: [
1903 self.awd3ch(0usize),
1904 self.awd3ch(1usize),
1905 self.awd3ch(2usize),
1906 self.awd3ch(3usize),
1907 self.awd3ch(4usize),
1908 self.awd3ch(5usize),
1909 self.awd3ch(6usize),
1910 self.awd3ch(7usize),
1911 self.awd3ch(8usize),
1912 self.awd3ch(9usize),
1913 self.awd3ch(10usize),
1914 self.awd3ch(11usize),
1915 self.awd3ch(12usize),
1916 self.awd3ch(13usize),
1917 self.awd3ch(14usize),
1918 self.awd3ch(15usize),
1919 self.awd3ch(16usize),
1920 self.awd3ch(17usize),
1921 self.awd3ch(18usize),
1922 self.awd3ch(19usize),
1923 ],
1924 };
1925 defmt::write!(f, "{}", proxy)
1926 }
1927 }
1928 #[doc = "ADC user control register."]
1929 #[repr(transparent)]
1930 #[derive(Copy, Clone, Eq, PartialEq)]
1931 pub struct Calfact(pub u32);
1932 impl Calfact {
1933 #[doc = "I_APB_ADDR."]
1934 #[inline(always)]
1935 pub const fn i_apb_addr(&self) -> u8 {
1936 let val = (self.0 >> 0usize) & 0xff;
1937 val as u8
1938 }
1939 #[doc = "I_APB_ADDR."]
1940 #[inline(always)]
1941 pub fn set_i_apb_addr(&mut self, val: u8) {
1942 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1943 }
1944 #[doc = "I_APB_DATA."]
1945 #[inline(always)]
1946 pub const fn i_apb_data(&self) -> u8 {
1947 let val = (self.0 >> 8usize) & 0xff;
1948 val as u8
1949 }
1950 #[doc = "I_APB_DATA."]
1951 #[inline(always)]
1952 pub fn set_i_apb_data(&mut self, val: u8) {
1953 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
1954 }
1955 #[doc = "VALIDITY."]
1956 #[inline(always)]
1957 pub const fn validity(&self) -> bool {
1958 let val = (self.0 >> 16usize) & 0x01;
1959 val != 0
1960 }
1961 #[doc = "VALIDITY."]
1962 #[inline(always)]
1963 pub fn set_validity(&mut self, val: bool) {
1964 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1965 }
1966 #[doc = "LATCH_COEF."]
1967 #[inline(always)]
1968 pub const fn latch_coef(&self) -> bool {
1969 let val = (self.0 >> 24usize) & 0x01;
1970 val != 0
1971 }
1972 #[doc = "LATCH_COEF."]
1973 #[inline(always)]
1974 pub fn set_latch_coef(&mut self, val: bool) {
1975 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1976 }
1977 #[doc = "CAPTURE_COEF."]
1978 #[inline(always)]
1979 pub const fn capture_coef(&self) -> bool {
1980 let val = (self.0 >> 25usize) & 0x01;
1981 val != 0
1982 }
1983 #[doc = "CAPTURE_COEF."]
1984 #[inline(always)]
1985 pub fn set_capture_coef(&mut self, val: bool) {
1986 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
1987 }
1988 }
1989 impl Default for Calfact {
1990 #[inline(always)]
1991 fn default() -> Calfact {
1992 Calfact(0)
1993 }
1994 }
1995 impl core::fmt::Debug for Calfact {
1996 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1997 f.debug_struct("Calfact")
1998 .field("i_apb_addr", &self.i_apb_addr())
1999 .field("i_apb_data", &self.i_apb_data())
2000 .field("validity", &self.validity())
2001 .field("latch_coef", &self.latch_coef())
2002 .field("capture_coef", &self.capture_coef())
2003 .finish()
2004 }
2005 }
2006 #[cfg(feature = "defmt")]
2007 impl defmt::Format for Calfact {
2008 fn format(&self, f: defmt::Formatter) {
2009 #[derive(defmt :: Format)]
2010 struct Calfact {
2011 i_apb_addr: u8,
2012 i_apb_data: u8,
2013 validity: bool,
2014 latch_coef: bool,
2015 capture_coef: bool,
2016 }
2017 let proxy = Calfact {
2018 i_apb_addr: self.i_apb_addr(),
2019 i_apb_data: self.i_apb_data(),
2020 validity: self.validity(),
2021 latch_coef: self.latch_coef(),
2022 capture_coef: self.capture_coef(),
2023 };
2024 defmt::write!(f, "{}", proxy)
2025 }
2026 }
2027 #[doc = "ADC calibration factor register."]
2028 #[repr(transparent)]
2029 #[derive(Copy, Clone, Eq, PartialEq)]
2030 pub struct Calfact2(pub u32);
2031 impl Calfact2 {
2032 #[doc = "CALFACT."]
2033 #[inline(always)]
2034 pub const fn calfact(&self) -> u32 {
2035 let val = (self.0 >> 0usize) & 0xffff_ffff;
2036 val as u32
2037 }
2038 #[doc = "CALFACT."]
2039 #[inline(always)]
2040 pub fn set_calfact(&mut self, val: u32) {
2041 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2042 }
2043 }
2044 impl Default for Calfact2 {
2045 #[inline(always)]
2046 fn default() -> Calfact2 {
2047 Calfact2(0)
2048 }
2049 }
2050 impl core::fmt::Debug for Calfact2 {
2051 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2052 f.debug_struct("Calfact2").field("calfact", &self.calfact()).finish()
2053 }
2054 }
2055 #[cfg(feature = "defmt")]
2056 impl defmt::Format for Calfact2 {
2057 fn format(&self, f: defmt::Formatter) {
2058 #[derive(defmt :: Format)]
2059 struct Calfact2 {
2060 calfact: u32,
2061 }
2062 let proxy = Calfact2 {
2063 calfact: self.calfact(),
2064 };
2065 defmt::write!(f, "{}", proxy)
2066 }
2067 }
2068 #[doc = "ADC configuration register."]
2069 #[repr(transparent)]
2070 #[derive(Copy, Clone, Eq, PartialEq)]
2071 pub struct Cfgr(pub u32);
2072 impl Cfgr {
2073 #[doc = "DMNGT."]
2074 #[inline(always)]
2075 pub const fn dmngt(&self) -> super::vals::Dmngt {
2076 let val = (self.0 >> 0usize) & 0x03;
2077 super::vals::Dmngt::from_bits(val as u8)
2078 }
2079 #[doc = "DMNGT."]
2080 #[inline(always)]
2081 pub fn set_dmngt(&mut self, val: super::vals::Dmngt) {
2082 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
2083 }
2084 #[doc = "RES."]
2085 #[inline(always)]
2086 pub const fn res(&self) -> super::vals::Res {
2087 let val = (self.0 >> 2usize) & 0x03;
2088 super::vals::Res::from_bits(val as u8)
2089 }
2090 #[doc = "RES."]
2091 #[inline(always)]
2092 pub fn set_res(&mut self, val: super::vals::Res) {
2093 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
2094 }
2095 #[doc = "EXTSEL."]
2096 #[inline(always)]
2097 pub const fn extsel(&self) -> u8 {
2098 let val = (self.0 >> 5usize) & 0x1f;
2099 val as u8
2100 }
2101 #[doc = "EXTSEL."]
2102 #[inline(always)]
2103 pub fn set_extsel(&mut self, val: u8) {
2104 self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
2105 }
2106 #[doc = "EXTEN."]
2107 #[inline(always)]
2108 pub const fn exten(&self) -> super::vals::Exten {
2109 let val = (self.0 >> 10usize) & 0x03;
2110 super::vals::Exten::from_bits(val as u8)
2111 }
2112 #[doc = "EXTEN."]
2113 #[inline(always)]
2114 pub fn set_exten(&mut self, val: super::vals::Exten) {
2115 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
2116 }
2117 #[doc = "OVRMOD."]
2118 #[inline(always)]
2119 pub const fn ovrmod(&self) -> bool {
2120 let val = (self.0 >> 12usize) & 0x01;
2121 val != 0
2122 }
2123 #[doc = "OVRMOD."]
2124 #[inline(always)]
2125 pub fn set_ovrmod(&mut self, val: bool) {
2126 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2127 }
2128 #[doc = "CONT."]
2129 #[inline(always)]
2130 pub const fn cont(&self) -> bool {
2131 let val = (self.0 >> 13usize) & 0x01;
2132 val != 0
2133 }
2134 #[doc = "CONT."]
2135 #[inline(always)]
2136 pub fn set_cont(&mut self, val: bool) {
2137 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2138 }
2139 #[doc = "AUTDLY."]
2140 #[inline(always)]
2141 pub const fn autdly(&self) -> bool {
2142 let val = (self.0 >> 14usize) & 0x01;
2143 val != 0
2144 }
2145 #[doc = "AUTDLY."]
2146 #[inline(always)]
2147 pub fn set_autdly(&mut self, val: bool) {
2148 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2149 }
2150 #[doc = "DISCEN."]
2151 #[inline(always)]
2152 pub const fn discen(&self) -> bool {
2153 let val = (self.0 >> 16usize) & 0x01;
2154 val != 0
2155 }
2156 #[doc = "DISCEN."]
2157 #[inline(always)]
2158 pub fn set_discen(&mut self, val: bool) {
2159 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2160 }
2161 #[doc = "DISCNUM."]
2162 #[inline(always)]
2163 pub const fn discnum(&self) -> u8 {
2164 let val = (self.0 >> 17usize) & 0x07;
2165 val as u8
2166 }
2167 #[doc = "DISCNUM."]
2168 #[inline(always)]
2169 pub fn set_discnum(&mut self, val: u8) {
2170 self.0 = (self.0 & !(0x07 << 17usize)) | (((val as u32) & 0x07) << 17usize);
2171 }
2172 #[doc = "JDISCEN."]
2173 #[inline(always)]
2174 pub const fn jdiscen(&self) -> bool {
2175 let val = (self.0 >> 20usize) & 0x01;
2176 val != 0
2177 }
2178 #[doc = "JDISCEN."]
2179 #[inline(always)]
2180 pub fn set_jdiscen(&mut self, val: bool) {
2181 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
2182 }
2183 #[doc = "AWD1SGL."]
2184 #[inline(always)]
2185 pub const fn awd1sgl(&self) -> bool {
2186 let val = (self.0 >> 22usize) & 0x01;
2187 val != 0
2188 }
2189 #[doc = "AWD1SGL."]
2190 #[inline(always)]
2191 pub fn set_awd1sgl(&mut self, val: bool) {
2192 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
2193 }
2194 #[doc = "AWD1EN."]
2195 #[inline(always)]
2196 pub const fn awd1en(&self) -> bool {
2197 let val = (self.0 >> 23usize) & 0x01;
2198 val != 0
2199 }
2200 #[doc = "AWD1EN."]
2201 #[inline(always)]
2202 pub fn set_awd1en(&mut self, val: bool) {
2203 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
2204 }
2205 #[doc = "JAWD1EN."]
2206 #[inline(always)]
2207 pub const fn jawd1en(&self) -> bool {
2208 let val = (self.0 >> 24usize) & 0x01;
2209 val != 0
2210 }
2211 #[doc = "JAWD1EN."]
2212 #[inline(always)]
2213 pub fn set_jawd1en(&mut self, val: bool) {
2214 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2215 }
2216 #[doc = "JAUTO."]
2217 #[inline(always)]
2218 pub const fn jauto(&self) -> bool {
2219 let val = (self.0 >> 25usize) & 0x01;
2220 val != 0
2221 }
2222 #[doc = "JAUTO."]
2223 #[inline(always)]
2224 pub fn set_jauto(&mut self, val: bool) {
2225 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
2226 }
2227 #[doc = "AWD1CH."]
2228 #[inline(always)]
2229 pub const fn awd1ch(&self) -> u8 {
2230 let val = (self.0 >> 26usize) & 0x1f;
2231 val as u8
2232 }
2233 #[doc = "AWD1CH."]
2234 #[inline(always)]
2235 pub fn set_awd1ch(&mut self, val: u8) {
2236 self.0 = (self.0 & !(0x1f << 26usize)) | (((val as u32) & 0x1f) << 26usize);
2237 }
2238 }
2239 impl Default for Cfgr {
2240 #[inline(always)]
2241 fn default() -> Cfgr {
2242 Cfgr(0)
2243 }
2244 }
2245 impl core::fmt::Debug for Cfgr {
2246 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2247 f.debug_struct("Cfgr")
2248 .field("dmngt", &self.dmngt())
2249 .field("res", &self.res())
2250 .field("extsel", &self.extsel())
2251 .field("exten", &self.exten())
2252 .field("ovrmod", &self.ovrmod())
2253 .field("cont", &self.cont())
2254 .field("autdly", &self.autdly())
2255 .field("discen", &self.discen())
2256 .field("discnum", &self.discnum())
2257 .field("jdiscen", &self.jdiscen())
2258 .field("awd1sgl", &self.awd1sgl())
2259 .field("awd1en", &self.awd1en())
2260 .field("jawd1en", &self.jawd1en())
2261 .field("jauto", &self.jauto())
2262 .field("awd1ch", &self.awd1ch())
2263 .finish()
2264 }
2265 }
2266 #[cfg(feature = "defmt")]
2267 impl defmt::Format for Cfgr {
2268 fn format(&self, f: defmt::Formatter) {
2269 #[derive(defmt :: Format)]
2270 struct Cfgr {
2271 dmngt: super::vals::Dmngt,
2272 res: super::vals::Res,
2273 extsel: u8,
2274 exten: super::vals::Exten,
2275 ovrmod: bool,
2276 cont: bool,
2277 autdly: bool,
2278 discen: bool,
2279 discnum: u8,
2280 jdiscen: bool,
2281 awd1sgl: bool,
2282 awd1en: bool,
2283 jawd1en: bool,
2284 jauto: bool,
2285 awd1ch: u8,
2286 }
2287 let proxy = Cfgr {
2288 dmngt: self.dmngt(),
2289 res: self.res(),
2290 extsel: self.extsel(),
2291 exten: self.exten(),
2292 ovrmod: self.ovrmod(),
2293 cont: self.cont(),
2294 autdly: self.autdly(),
2295 discen: self.discen(),
2296 discnum: self.discnum(),
2297 jdiscen: self.jdiscen(),
2298 awd1sgl: self.awd1sgl(),
2299 awd1en: self.awd1en(),
2300 jawd1en: self.jawd1en(),
2301 jauto: self.jauto(),
2302 awd1ch: self.awd1ch(),
2303 };
2304 defmt::write!(f, "{}", proxy)
2305 }
2306 }
2307 #[doc = "ADC configuration register 2."]
2308 #[repr(transparent)]
2309 #[derive(Copy, Clone, Eq, PartialEq)]
2310 pub struct Cfgr2(pub u32);
2311 impl Cfgr2 {
2312 #[doc = "ROVSE."]
2313 #[inline(always)]
2314 pub const fn rovse(&self) -> bool {
2315 let val = (self.0 >> 0usize) & 0x01;
2316 val != 0
2317 }
2318 #[doc = "ROVSE."]
2319 #[inline(always)]
2320 pub fn set_rovse(&mut self, val: bool) {
2321 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2322 }
2323 #[doc = "JOVSE."]
2324 #[inline(always)]
2325 pub const fn jovse(&self) -> bool {
2326 let val = (self.0 >> 1usize) & 0x01;
2327 val != 0
2328 }
2329 #[doc = "JOVSE."]
2330 #[inline(always)]
2331 pub fn set_jovse(&mut self, val: bool) {
2332 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2333 }
2334 #[doc = "OVSS."]
2335 #[inline(always)]
2336 pub const fn ovss(&self) -> u8 {
2337 let val = (self.0 >> 5usize) & 0x0f;
2338 val as u8
2339 }
2340 #[doc = "OVSS."]
2341 #[inline(always)]
2342 pub fn set_ovss(&mut self, val: u8) {
2343 self.0 = (self.0 & !(0x0f << 5usize)) | (((val as u32) & 0x0f) << 5usize);
2344 }
2345 #[doc = "TROVS."]
2346 #[inline(always)]
2347 pub const fn trovs(&self) -> bool {
2348 let val = (self.0 >> 9usize) & 0x01;
2349 val != 0
2350 }
2351 #[doc = "TROVS."]
2352 #[inline(always)]
2353 pub fn set_trovs(&mut self, val: bool) {
2354 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2355 }
2356 #[doc = "ROVSM."]
2357 #[inline(always)]
2358 pub const fn rovsm(&self) -> bool {
2359 let val = (self.0 >> 10usize) & 0x01;
2360 val != 0
2361 }
2362 #[doc = "ROVSM."]
2363 #[inline(always)]
2364 pub fn set_rovsm(&mut self, val: bool) {
2365 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2366 }
2367 #[doc = "BULB."]
2368 #[inline(always)]
2369 pub const fn bulb(&self) -> bool {
2370 let val = (self.0 >> 13usize) & 0x01;
2371 val != 0
2372 }
2373 #[doc = "BULB."]
2374 #[inline(always)]
2375 pub fn set_bulb(&mut self, val: bool) {
2376 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2377 }
2378 #[doc = "SWTRIG."]
2379 #[inline(always)]
2380 pub const fn swtrig(&self) -> bool {
2381 let val = (self.0 >> 14usize) & 0x01;
2382 val != 0
2383 }
2384 #[doc = "SWTRIG."]
2385 #[inline(always)]
2386 pub fn set_swtrig(&mut self, val: bool) {
2387 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2388 }
2389 #[doc = "SMPTRIG."]
2390 #[inline(always)]
2391 pub const fn smptrig(&self) -> bool {
2392 let val = (self.0 >> 15usize) & 0x01;
2393 val != 0
2394 }
2395 #[doc = "SMPTRIG."]
2396 #[inline(always)]
2397 pub fn set_smptrig(&mut self, val: bool) {
2398 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2399 }
2400 #[doc = "OSVR."]
2401 #[inline(always)]
2402 pub const fn osvr(&self) -> u16 {
2403 let val = (self.0 >> 16usize) & 0x03ff;
2404 val as u16
2405 }
2406 #[doc = "OSVR."]
2407 #[inline(always)]
2408 pub fn set_osvr(&mut self, val: u16) {
2409 self.0 = (self.0 & !(0x03ff << 16usize)) | (((val as u32) & 0x03ff) << 16usize);
2410 }
2411 #[doc = "LFTRIG."]
2412 #[inline(always)]
2413 pub const fn lftrig(&self) -> bool {
2414 let val = (self.0 >> 27usize) & 0x01;
2415 val != 0
2416 }
2417 #[doc = "LFTRIG."]
2418 #[inline(always)]
2419 pub fn set_lftrig(&mut self, val: bool) {
2420 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2421 }
2422 #[doc = "LSHIFT."]
2423 #[inline(always)]
2424 pub const fn lshift(&self) -> u8 {
2425 let val = (self.0 >> 28usize) & 0x0f;
2426 val as u8
2427 }
2428 #[doc = "LSHIFT."]
2429 #[inline(always)]
2430 pub fn set_lshift(&mut self, val: u8) {
2431 self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
2432 }
2433 }
2434 impl Default for Cfgr2 {
2435 #[inline(always)]
2436 fn default() -> Cfgr2 {
2437 Cfgr2(0)
2438 }
2439 }
2440 impl core::fmt::Debug for Cfgr2 {
2441 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2442 f.debug_struct("Cfgr2")
2443 .field("rovse", &self.rovse())
2444 .field("jovse", &self.jovse())
2445 .field("ovss", &self.ovss())
2446 .field("trovs", &self.trovs())
2447 .field("rovsm", &self.rovsm())
2448 .field("bulb", &self.bulb())
2449 .field("swtrig", &self.swtrig())
2450 .field("smptrig", &self.smptrig())
2451 .field("osvr", &self.osvr())
2452 .field("lftrig", &self.lftrig())
2453 .field("lshift", &self.lshift())
2454 .finish()
2455 }
2456 }
2457 #[cfg(feature = "defmt")]
2458 impl defmt::Format for Cfgr2 {
2459 fn format(&self, f: defmt::Formatter) {
2460 #[derive(defmt :: Format)]
2461 struct Cfgr2 {
2462 rovse: bool,
2463 jovse: bool,
2464 ovss: u8,
2465 trovs: bool,
2466 rovsm: bool,
2467 bulb: bool,
2468 swtrig: bool,
2469 smptrig: bool,
2470 osvr: u16,
2471 lftrig: bool,
2472 lshift: u8,
2473 }
2474 let proxy = Cfgr2 {
2475 rovse: self.rovse(),
2476 jovse: self.jovse(),
2477 ovss: self.ovss(),
2478 trovs: self.trovs(),
2479 rovsm: self.rovsm(),
2480 bulb: self.bulb(),
2481 swtrig: self.swtrig(),
2482 smptrig: self.smptrig(),
2483 osvr: self.osvr(),
2484 lftrig: self.lftrig(),
2485 lshift: self.lshift(),
2486 };
2487 defmt::write!(f, "{}", proxy)
2488 }
2489 }
2490 #[doc = "ADC control register."]
2491 #[repr(transparent)]
2492 #[derive(Copy, Clone, Eq, PartialEq)]
2493 pub struct Cr(pub u32);
2494 impl Cr {
2495 #[doc = "ADEN."]
2496 #[inline(always)]
2497 pub const fn aden(&self) -> bool {
2498 let val = (self.0 >> 0usize) & 0x01;
2499 val != 0
2500 }
2501 #[doc = "ADEN."]
2502 #[inline(always)]
2503 pub fn set_aden(&mut self, val: bool) {
2504 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2505 }
2506 #[doc = "ADDIS."]
2507 #[inline(always)]
2508 pub const fn addis(&self) -> bool {
2509 let val = (self.0 >> 1usize) & 0x01;
2510 val != 0
2511 }
2512 #[doc = "ADDIS."]
2513 #[inline(always)]
2514 pub fn set_addis(&mut self, val: bool) {
2515 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2516 }
2517 #[doc = "ADSTART."]
2518 #[inline(always)]
2519 pub const fn adstart(&self) -> bool {
2520 let val = (self.0 >> 2usize) & 0x01;
2521 val != 0
2522 }
2523 #[doc = "ADSTART."]
2524 #[inline(always)]
2525 pub fn set_adstart(&mut self, val: bool) {
2526 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2527 }
2528 #[doc = "JADSTART."]
2529 #[inline(always)]
2530 pub const fn jadstart(&self) -> bool {
2531 let val = (self.0 >> 3usize) & 0x01;
2532 val != 0
2533 }
2534 #[doc = "JADSTART."]
2535 #[inline(always)]
2536 pub fn set_jadstart(&mut self, val: bool) {
2537 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2538 }
2539 #[doc = "ADSTP."]
2540 #[inline(always)]
2541 pub const fn adstp(&self) -> super::vals::Adstp {
2542 let val = (self.0 >> 4usize) & 0x01;
2543 super::vals::Adstp::from_bits(val as u8)
2544 }
2545 #[doc = "ADSTP."]
2546 #[inline(always)]
2547 pub fn set_adstp(&mut self, val: super::vals::Adstp) {
2548 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
2549 }
2550 #[doc = "JADSTP."]
2551 #[inline(always)]
2552 pub const fn jadstp(&self) -> bool {
2553 let val = (self.0 >> 5usize) & 0x01;
2554 val != 0
2555 }
2556 #[doc = "JADSTP."]
2557 #[inline(always)]
2558 pub fn set_jadstp(&mut self, val: bool) {
2559 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2560 }
2561 #[doc = "ADCALLIN."]
2562 #[inline(always)]
2563 pub const fn adcallin(&self) -> bool {
2564 let val = (self.0 >> 16usize) & 0x01;
2565 val != 0
2566 }
2567 #[doc = "ADCALLIN."]
2568 #[inline(always)]
2569 pub fn set_adcallin(&mut self, val: bool) {
2570 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2571 }
2572 #[doc = "CALINDEX."]
2573 #[inline(always)]
2574 pub const fn calindex(&self) -> u8 {
2575 let val = (self.0 >> 24usize) & 0x0f;
2576 val as u8
2577 }
2578 #[doc = "CALINDEX."]
2579 #[inline(always)]
2580 pub fn set_calindex(&mut self, val: u8) {
2581 self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
2582 }
2583 #[doc = "ADVREGEN."]
2584 #[inline(always)]
2585 pub const fn advregen(&self) -> bool {
2586 let val = (self.0 >> 28usize) & 0x01;
2587 val != 0
2588 }
2589 #[doc = "ADVREGEN."]
2590 #[inline(always)]
2591 pub fn set_advregen(&mut self, val: bool) {
2592 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2593 }
2594 #[doc = "DEEPPWD."]
2595 #[inline(always)]
2596 pub const fn deeppwd(&self) -> bool {
2597 let val = (self.0 >> 29usize) & 0x01;
2598 val != 0
2599 }
2600 #[doc = "DEEPPWD."]
2601 #[inline(always)]
2602 pub fn set_deeppwd(&mut self, val: bool) {
2603 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
2604 }
2605 #[doc = "ADCAL."]
2606 #[inline(always)]
2607 pub const fn adcal(&self) -> bool {
2608 let val = (self.0 >> 31usize) & 0x01;
2609 val != 0
2610 }
2611 #[doc = "ADCAL."]
2612 #[inline(always)]
2613 pub fn set_adcal(&mut self, val: bool) {
2614 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2615 }
2616 }
2617 impl Default for Cr {
2618 #[inline(always)]
2619 fn default() -> Cr {
2620 Cr(0)
2621 }
2622 }
2623 impl core::fmt::Debug for Cr {
2624 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2625 f.debug_struct("Cr")
2626 .field("aden", &self.aden())
2627 .field("addis", &self.addis())
2628 .field("adstart", &self.adstart())
2629 .field("jadstart", &self.jadstart())
2630 .field("adstp", &self.adstp())
2631 .field("jadstp", &self.jadstp())
2632 .field("adcallin", &self.adcallin())
2633 .field("calindex", &self.calindex())
2634 .field("advregen", &self.advregen())
2635 .field("deeppwd", &self.deeppwd())
2636 .field("adcal", &self.adcal())
2637 .finish()
2638 }
2639 }
2640 #[cfg(feature = "defmt")]
2641 impl defmt::Format for Cr {
2642 fn format(&self, f: defmt::Formatter) {
2643 #[derive(defmt :: Format)]
2644 struct Cr {
2645 aden: bool,
2646 addis: bool,
2647 adstart: bool,
2648 jadstart: bool,
2649 adstp: super::vals::Adstp,
2650 jadstp: bool,
2651 adcallin: bool,
2652 calindex: u8,
2653 advregen: bool,
2654 deeppwd: bool,
2655 adcal: bool,
2656 }
2657 let proxy = Cr {
2658 aden: self.aden(),
2659 addis: self.addis(),
2660 adstart: self.adstart(),
2661 jadstart: self.jadstart(),
2662 adstp: self.adstp(),
2663 jadstp: self.jadstp(),
2664 adcallin: self.adcallin(),
2665 calindex: self.calindex(),
2666 advregen: self.advregen(),
2667 deeppwd: self.deeppwd(),
2668 adcal: self.adcal(),
2669 };
2670 defmt::write!(f, "{}", proxy)
2671 }
2672 }
2673 #[doc = "ADC differential mode selection register."]
2674 #[repr(transparent)]
2675 #[derive(Copy, Clone, Eq, PartialEq)]
2676 pub struct Difsel(pub u32);
2677 impl Difsel {
2678 #[doc = "channel differential or single-ended mode for channel"]
2679 #[inline(always)]
2680 pub const fn difsel(&self, n: usize) -> super::vals::Difsel {
2681 assert!(n < 20usize);
2682 let offs = 0usize + n * 1usize;
2683 let val = (self.0 >> offs) & 0x01;
2684 super::vals::Difsel::from_bits(val as u8)
2685 }
2686 #[doc = "channel differential or single-ended mode for channel"]
2687 #[inline(always)]
2688 pub fn set_difsel(&mut self, n: usize, val: super::vals::Difsel) {
2689 assert!(n < 20usize);
2690 let offs = 0usize + n * 1usize;
2691 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
2692 }
2693 }
2694 impl Default for Difsel {
2695 #[inline(always)]
2696 fn default() -> Difsel {
2697 Difsel(0)
2698 }
2699 }
2700 impl core::fmt::Debug for Difsel {
2701 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2702 f.debug_struct("Difsel")
2703 .field(
2704 "difsel",
2705 &[
2706 self.difsel(0usize),
2707 self.difsel(1usize),
2708 self.difsel(2usize),
2709 self.difsel(3usize),
2710 self.difsel(4usize),
2711 self.difsel(5usize),
2712 self.difsel(6usize),
2713 self.difsel(7usize),
2714 self.difsel(8usize),
2715 self.difsel(9usize),
2716 self.difsel(10usize),
2717 self.difsel(11usize),
2718 self.difsel(12usize),
2719 self.difsel(13usize),
2720 self.difsel(14usize),
2721 self.difsel(15usize),
2722 self.difsel(16usize),
2723 self.difsel(17usize),
2724 self.difsel(18usize),
2725 self.difsel(19usize),
2726 ],
2727 )
2728 .finish()
2729 }
2730 }
2731 #[cfg(feature = "defmt")]
2732 impl defmt::Format for Difsel {
2733 fn format(&self, f: defmt::Formatter) {
2734 #[derive(defmt :: Format)]
2735 struct Difsel {
2736 difsel: [super::vals::Difsel; 20usize],
2737 }
2738 let proxy = Difsel {
2739 difsel: [
2740 self.difsel(0usize),
2741 self.difsel(1usize),
2742 self.difsel(2usize),
2743 self.difsel(3usize),
2744 self.difsel(4usize),
2745 self.difsel(5usize),
2746 self.difsel(6usize),
2747 self.difsel(7usize),
2748 self.difsel(8usize),
2749 self.difsel(9usize),
2750 self.difsel(10usize),
2751 self.difsel(11usize),
2752 self.difsel(12usize),
2753 self.difsel(13usize),
2754 self.difsel(14usize),
2755 self.difsel(15usize),
2756 self.difsel(16usize),
2757 self.difsel(17usize),
2758 self.difsel(18usize),
2759 self.difsel(19usize),
2760 ],
2761 };
2762 defmt::write!(f, "{}", proxy)
2763 }
2764 }
2765 #[doc = "ADC regular Data Register."]
2766 #[repr(transparent)]
2767 #[derive(Copy, Clone, Eq, PartialEq)]
2768 pub struct Dr(pub u32);
2769 impl Dr {
2770 #[doc = "RDATA."]
2771 #[inline(always)]
2772 pub const fn rdata(&self) -> u32 {
2773 let val = (self.0 >> 0usize) & 0xffff_ffff;
2774 val as u32
2775 }
2776 #[doc = "RDATA."]
2777 #[inline(always)]
2778 pub fn set_rdata(&mut self, val: u32) {
2779 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2780 }
2781 }
2782 impl Default for Dr {
2783 #[inline(always)]
2784 fn default() -> Dr {
2785 Dr(0)
2786 }
2787 }
2788 impl core::fmt::Debug for Dr {
2789 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2790 f.debug_struct("Dr").field("rdata", &self.rdata()).finish()
2791 }
2792 }
2793 #[cfg(feature = "defmt")]
2794 impl defmt::Format for Dr {
2795 fn format(&self, f: defmt::Formatter) {
2796 #[derive(defmt :: Format)]
2797 struct Dr {
2798 rdata: u32,
2799 }
2800 let proxy = Dr { rdata: self.rdata() };
2801 defmt::write!(f, "{}", proxy)
2802 }
2803 }
2804 #[doc = "ADC gain compensation register."]
2805 #[repr(transparent)]
2806 #[derive(Copy, Clone, Eq, PartialEq)]
2807 pub struct Gcomp(pub u32);
2808 impl Gcomp {
2809 #[doc = "GCOMPCOEFF."]
2810 #[inline(always)]
2811 pub const fn gcompcoeff(&self) -> u16 {
2812 let val = (self.0 >> 0usize) & 0x3fff;
2813 val as u16
2814 }
2815 #[doc = "GCOMPCOEFF."]
2816 #[inline(always)]
2817 pub fn set_gcompcoeff(&mut self, val: u16) {
2818 self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
2819 }
2820 #[doc = "GCOMP."]
2821 #[inline(always)]
2822 pub const fn gcomp(&self) -> bool {
2823 let val = (self.0 >> 31usize) & 0x01;
2824 val != 0
2825 }
2826 #[doc = "GCOMP."]
2827 #[inline(always)]
2828 pub fn set_gcomp(&mut self, val: bool) {
2829 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2830 }
2831 }
2832 impl Default for Gcomp {
2833 #[inline(always)]
2834 fn default() -> Gcomp {
2835 Gcomp(0)
2836 }
2837 }
2838 impl core::fmt::Debug for Gcomp {
2839 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2840 f.debug_struct("Gcomp")
2841 .field("gcompcoeff", &self.gcompcoeff())
2842 .field("gcomp", &self.gcomp())
2843 .finish()
2844 }
2845 }
2846 #[cfg(feature = "defmt")]
2847 impl defmt::Format for Gcomp {
2848 fn format(&self, f: defmt::Formatter) {
2849 #[derive(defmt :: Format)]
2850 struct Gcomp {
2851 gcompcoeff: u16,
2852 gcomp: bool,
2853 }
2854 let proxy = Gcomp {
2855 gcompcoeff: self.gcompcoeff(),
2856 gcomp: self.gcomp(),
2857 };
2858 defmt::write!(f, "{}", proxy)
2859 }
2860 }
2861 #[doc = "ADC watchdog threshold register 1."]
2862 #[repr(transparent)]
2863 #[derive(Copy, Clone, Eq, PartialEq)]
2864 pub struct Htr1(pub u32);
2865 impl Htr1 {
2866 #[doc = "HTR1."]
2867 #[inline(always)]
2868 pub const fn htr1(&self) -> u32 {
2869 let val = (self.0 >> 0usize) & 0x01ff_ffff;
2870 val as u32
2871 }
2872 #[doc = "HTR1."]
2873 #[inline(always)]
2874 pub fn set_htr1(&mut self, val: u32) {
2875 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
2876 }
2877 #[doc = "AWDFILT1."]
2878 #[inline(always)]
2879 pub const fn awdfilt1(&self) -> u8 {
2880 let val = (self.0 >> 29usize) & 0x07;
2881 val as u8
2882 }
2883 #[doc = "AWDFILT1."]
2884 #[inline(always)]
2885 pub fn set_awdfilt1(&mut self, val: u8) {
2886 self.0 = (self.0 & !(0x07 << 29usize)) | (((val as u32) & 0x07) << 29usize);
2887 }
2888 }
2889 impl Default for Htr1 {
2890 #[inline(always)]
2891 fn default() -> Htr1 {
2892 Htr1(0)
2893 }
2894 }
2895 impl core::fmt::Debug for Htr1 {
2896 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2897 f.debug_struct("Htr1")
2898 .field("htr1", &self.htr1())
2899 .field("awdfilt1", &self.awdfilt1())
2900 .finish()
2901 }
2902 }
2903 #[cfg(feature = "defmt")]
2904 impl defmt::Format for Htr1 {
2905 fn format(&self, f: defmt::Formatter) {
2906 #[derive(defmt :: Format)]
2907 struct Htr1 {
2908 htr1: u32,
2909 awdfilt1: u8,
2910 }
2911 let proxy = Htr1 {
2912 htr1: self.htr1(),
2913 awdfilt1: self.awdfilt1(),
2914 };
2915 defmt::write!(f, "{}", proxy)
2916 }
2917 }
2918 #[doc = "ADC watchdog higher threshold register 2."]
2919 #[repr(transparent)]
2920 #[derive(Copy, Clone, Eq, PartialEq)]
2921 pub struct Htr2(pub u32);
2922 impl Htr2 {
2923 #[doc = "HTR2."]
2924 #[inline(always)]
2925 pub const fn htr2(&self) -> u32 {
2926 let val = (self.0 >> 0usize) & 0x01ff_ffff;
2927 val as u32
2928 }
2929 #[doc = "HTR2."]
2930 #[inline(always)]
2931 pub fn set_htr2(&mut self, val: u32) {
2932 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
2933 }
2934 }
2935 impl Default for Htr2 {
2936 #[inline(always)]
2937 fn default() -> Htr2 {
2938 Htr2(0)
2939 }
2940 }
2941 impl core::fmt::Debug for Htr2 {
2942 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2943 f.debug_struct("Htr2").field("htr2", &self.htr2()).finish()
2944 }
2945 }
2946 #[cfg(feature = "defmt")]
2947 impl defmt::Format for Htr2 {
2948 fn format(&self, f: defmt::Formatter) {
2949 #[derive(defmt :: Format)]
2950 struct Htr2 {
2951 htr2: u32,
2952 }
2953 let proxy = Htr2 { htr2: self.htr2() };
2954 defmt::write!(f, "{}", proxy)
2955 }
2956 }
2957 #[doc = "ADC watchdog higher threshold register 3."]
2958 #[repr(transparent)]
2959 #[derive(Copy, Clone, Eq, PartialEq)]
2960 pub struct Htr3(pub u32);
2961 impl Htr3 {
2962 #[doc = "HTR3."]
2963 #[inline(always)]
2964 pub const fn htr3(&self) -> u32 {
2965 let val = (self.0 >> 0usize) & 0x01ff_ffff;
2966 val as u32
2967 }
2968 #[doc = "HTR3."]
2969 #[inline(always)]
2970 pub fn set_htr3(&mut self, val: u32) {
2971 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
2972 }
2973 }
2974 impl Default for Htr3 {
2975 #[inline(always)]
2976 fn default() -> Htr3 {
2977 Htr3(0)
2978 }
2979 }
2980 impl core::fmt::Debug for Htr3 {
2981 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2982 f.debug_struct("Htr3").field("htr3", &self.htr3()).finish()
2983 }
2984 }
2985 #[cfg(feature = "defmt")]
2986 impl defmt::Format for Htr3 {
2987 fn format(&self, f: defmt::Formatter) {
2988 #[derive(defmt :: Format)]
2989 struct Htr3 {
2990 htr3: u32,
2991 }
2992 let proxy = Htr3 { htr3: self.htr3() };
2993 defmt::write!(f, "{}", proxy)
2994 }
2995 }
2996 #[doc = "ADC interrupt enable register."]
2997 #[repr(transparent)]
2998 #[derive(Copy, Clone, Eq, PartialEq)]
2999 pub struct Ier(pub u32);
3000 impl Ier {
3001 #[doc = "ADRDYIE."]
3002 #[inline(always)]
3003 pub const fn adrdyie(&self) -> bool {
3004 let val = (self.0 >> 0usize) & 0x01;
3005 val != 0
3006 }
3007 #[doc = "ADRDYIE."]
3008 #[inline(always)]
3009 pub fn set_adrdyie(&mut self, val: bool) {
3010 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3011 }
3012 #[doc = "EOSMPIE."]
3013 #[inline(always)]
3014 pub const fn eosmpie(&self) -> bool {
3015 let val = (self.0 >> 1usize) & 0x01;
3016 val != 0
3017 }
3018 #[doc = "EOSMPIE."]
3019 #[inline(always)]
3020 pub fn set_eosmpie(&mut self, val: bool) {
3021 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3022 }
3023 #[doc = "EOCIE."]
3024 #[inline(always)]
3025 pub const fn eocie(&self) -> bool {
3026 let val = (self.0 >> 2usize) & 0x01;
3027 val != 0
3028 }
3029 #[doc = "EOCIE."]
3030 #[inline(always)]
3031 pub fn set_eocie(&mut self, val: bool) {
3032 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3033 }
3034 #[doc = "EOSIE."]
3035 #[inline(always)]
3036 pub const fn eosie(&self) -> bool {
3037 let val = (self.0 >> 3usize) & 0x01;
3038 val != 0
3039 }
3040 #[doc = "EOSIE."]
3041 #[inline(always)]
3042 pub fn set_eosie(&mut self, val: bool) {
3043 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3044 }
3045 #[doc = "OVRIE."]
3046 #[inline(always)]
3047 pub const fn ovrie(&self) -> bool {
3048 let val = (self.0 >> 4usize) & 0x01;
3049 val != 0
3050 }
3051 #[doc = "OVRIE."]
3052 #[inline(always)]
3053 pub fn set_ovrie(&mut self, val: bool) {
3054 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3055 }
3056 #[doc = "JEOCIE."]
3057 #[inline(always)]
3058 pub const fn jeocie(&self) -> bool {
3059 let val = (self.0 >> 5usize) & 0x01;
3060 val != 0
3061 }
3062 #[doc = "JEOCIE."]
3063 #[inline(always)]
3064 pub fn set_jeocie(&mut self, val: bool) {
3065 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3066 }
3067 #[doc = "JEOSIE."]
3068 #[inline(always)]
3069 pub const fn jeosie(&self) -> bool {
3070 let val = (self.0 >> 6usize) & 0x01;
3071 val != 0
3072 }
3073 #[doc = "JEOSIE."]
3074 #[inline(always)]
3075 pub fn set_jeosie(&mut self, val: bool) {
3076 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3077 }
3078 #[doc = "AWD1IE."]
3079 #[inline(always)]
3080 pub const fn awdie(&self, n: usize) -> bool {
3081 assert!(n < 3usize);
3082 let offs = 7usize + n * 1usize;
3083 let val = (self.0 >> offs) & 0x01;
3084 val != 0
3085 }
3086 #[doc = "AWD1IE."]
3087 #[inline(always)]
3088 pub fn set_awdie(&mut self, n: usize, val: bool) {
3089 assert!(n < 3usize);
3090 let offs = 7usize + n * 1usize;
3091 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3092 }
3093 }
3094 impl Default for Ier {
3095 #[inline(always)]
3096 fn default() -> Ier {
3097 Ier(0)
3098 }
3099 }
3100 impl core::fmt::Debug for Ier {
3101 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3102 f.debug_struct("Ier")
3103 .field("adrdyie", &self.adrdyie())
3104 .field("eosmpie", &self.eosmpie())
3105 .field("eocie", &self.eocie())
3106 .field("eosie", &self.eosie())
3107 .field("ovrie", &self.ovrie())
3108 .field("jeocie", &self.jeocie())
3109 .field("jeosie", &self.jeosie())
3110 .field("awdie", &[self.awdie(0usize), self.awdie(1usize), self.awdie(2usize)])
3111 .finish()
3112 }
3113 }
3114 #[cfg(feature = "defmt")]
3115 impl defmt::Format for Ier {
3116 fn format(&self, f: defmt::Formatter) {
3117 #[derive(defmt :: Format)]
3118 struct Ier {
3119 adrdyie: bool,
3120 eosmpie: bool,
3121 eocie: bool,
3122 eosie: bool,
3123 ovrie: bool,
3124 jeocie: bool,
3125 jeosie: bool,
3126 awdie: [bool; 3usize],
3127 }
3128 let proxy = Ier {
3129 adrdyie: self.adrdyie(),
3130 eosmpie: self.eosmpie(),
3131 eocie: self.eocie(),
3132 eosie: self.eosie(),
3133 ovrie: self.ovrie(),
3134 jeocie: self.jeocie(),
3135 jeosie: self.jeosie(),
3136 awdie: [self.awdie(0usize), self.awdie(1usize), self.awdie(2usize)],
3137 };
3138 defmt::write!(f, "{}", proxy)
3139 }
3140 }
3141 #[doc = "ADC interrupt and status register."]
3142 #[repr(transparent)]
3143 #[derive(Copy, Clone, Eq, PartialEq)]
3144 pub struct Isr(pub u32);
3145 impl Isr {
3146 #[doc = "ADRDY."]
3147 #[inline(always)]
3148 pub const fn adrdy(&self) -> bool {
3149 let val = (self.0 >> 0usize) & 0x01;
3150 val != 0
3151 }
3152 #[doc = "ADRDY."]
3153 #[inline(always)]
3154 pub fn set_adrdy(&mut self, val: bool) {
3155 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3156 }
3157 #[doc = "EOSMP."]
3158 #[inline(always)]
3159 pub const fn eosmp(&self) -> bool {
3160 let val = (self.0 >> 1usize) & 0x01;
3161 val != 0
3162 }
3163 #[doc = "EOSMP."]
3164 #[inline(always)]
3165 pub fn set_eosmp(&mut self, val: bool) {
3166 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3167 }
3168 #[doc = "EOC."]
3169 #[inline(always)]
3170 pub const fn eoc(&self) -> bool {
3171 let val = (self.0 >> 2usize) & 0x01;
3172 val != 0
3173 }
3174 #[doc = "EOC."]
3175 #[inline(always)]
3176 pub fn set_eoc(&mut self, val: bool) {
3177 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3178 }
3179 #[doc = "EOS."]
3180 #[inline(always)]
3181 pub const fn eos(&self) -> bool {
3182 let val = (self.0 >> 3usize) & 0x01;
3183 val != 0
3184 }
3185 #[doc = "EOS."]
3186 #[inline(always)]
3187 pub fn set_eos(&mut self, val: bool) {
3188 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3189 }
3190 #[doc = "OVR."]
3191 #[inline(always)]
3192 pub const fn ovr(&self) -> bool {
3193 let val = (self.0 >> 4usize) & 0x01;
3194 val != 0
3195 }
3196 #[doc = "OVR."]
3197 #[inline(always)]
3198 pub fn set_ovr(&mut self, val: bool) {
3199 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3200 }
3201 #[doc = "JEOC."]
3202 #[inline(always)]
3203 pub const fn jeoc(&self) -> bool {
3204 let val = (self.0 >> 5usize) & 0x01;
3205 val != 0
3206 }
3207 #[doc = "JEOC."]
3208 #[inline(always)]
3209 pub fn set_jeoc(&mut self, val: bool) {
3210 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3211 }
3212 #[doc = "JEOS."]
3213 #[inline(always)]
3214 pub const fn jeos(&self) -> bool {
3215 let val = (self.0 >> 6usize) & 0x01;
3216 val != 0
3217 }
3218 #[doc = "JEOS."]
3219 #[inline(always)]
3220 pub fn set_jeos(&mut self, val: bool) {
3221 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3222 }
3223 #[doc = "AWD1."]
3224 #[inline(always)]
3225 pub const fn awd(&self, n: usize) -> bool {
3226 assert!(n < 3usize);
3227 let offs = 7usize + n * 1usize;
3228 let val = (self.0 >> offs) & 0x01;
3229 val != 0
3230 }
3231 #[doc = "AWD1."]
3232 #[inline(always)]
3233 pub fn set_awd(&mut self, n: usize, val: bool) {
3234 assert!(n < 3usize);
3235 let offs = 7usize + n * 1usize;
3236 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3237 }
3238 #[doc = "LDORDY."]
3239 #[inline(always)]
3240 pub const fn ldordy(&self) -> bool {
3241 let val = (self.0 >> 12usize) & 0x01;
3242 val != 0
3243 }
3244 #[doc = "LDORDY."]
3245 #[inline(always)]
3246 pub fn set_ldordy(&mut self, val: bool) {
3247 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
3248 }
3249 }
3250 impl Default for Isr {
3251 #[inline(always)]
3252 fn default() -> Isr {
3253 Isr(0)
3254 }
3255 }
3256 impl core::fmt::Debug for Isr {
3257 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3258 f.debug_struct("Isr")
3259 .field("adrdy", &self.adrdy())
3260 .field("eosmp", &self.eosmp())
3261 .field("eoc", &self.eoc())
3262 .field("eos", &self.eos())
3263 .field("ovr", &self.ovr())
3264 .field("jeoc", &self.jeoc())
3265 .field("jeos", &self.jeos())
3266 .field("awd", &[self.awd(0usize), self.awd(1usize), self.awd(2usize)])
3267 .field("ldordy", &self.ldordy())
3268 .finish()
3269 }
3270 }
3271 #[cfg(feature = "defmt")]
3272 impl defmt::Format for Isr {
3273 fn format(&self, f: defmt::Formatter) {
3274 #[derive(defmt :: Format)]
3275 struct Isr {
3276 adrdy: bool,
3277 eosmp: bool,
3278 eoc: bool,
3279 eos: bool,
3280 ovr: bool,
3281 jeoc: bool,
3282 jeos: bool,
3283 awd: [bool; 3usize],
3284 ldordy: bool,
3285 }
3286 let proxy = Isr {
3287 adrdy: self.adrdy(),
3288 eosmp: self.eosmp(),
3289 eoc: self.eoc(),
3290 eos: self.eos(),
3291 ovr: self.ovr(),
3292 jeoc: self.jeoc(),
3293 jeos: self.jeos(),
3294 awd: [self.awd(0usize), self.awd(1usize), self.awd(2usize)],
3295 ldordy: self.ldordy(),
3296 };
3297 defmt::write!(f, "{}", proxy)
3298 }
3299 }
3300 #[doc = "ADC injected data register."]
3301 #[repr(transparent)]
3302 #[derive(Copy, Clone, Eq, PartialEq)]
3303 pub struct Jdr(pub u32);
3304 impl Jdr {
3305 #[doc = "JDATA."]
3306 #[inline(always)]
3307 pub const fn jdata(&self) -> u32 {
3308 let val = (self.0 >> 0usize) & 0xffff_ffff;
3309 val as u32
3310 }
3311 #[doc = "JDATA."]
3312 #[inline(always)]
3313 pub fn set_jdata(&mut self, val: u32) {
3314 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
3315 }
3316 }
3317 impl Default for Jdr {
3318 #[inline(always)]
3319 fn default() -> Jdr {
3320 Jdr(0)
3321 }
3322 }
3323 impl core::fmt::Debug for Jdr {
3324 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3325 f.debug_struct("Jdr").field("jdata", &self.jdata()).finish()
3326 }
3327 }
3328 #[cfg(feature = "defmt")]
3329 impl defmt::Format for Jdr {
3330 fn format(&self, f: defmt::Formatter) {
3331 #[derive(defmt :: Format)]
3332 struct Jdr {
3333 jdata: u32,
3334 }
3335 let proxy = Jdr { jdata: self.jdata() };
3336 defmt::write!(f, "{}", proxy)
3337 }
3338 }
3339 #[doc = "ADC injected sequence register."]
3340 #[repr(transparent)]
3341 #[derive(Copy, Clone, Eq, PartialEq)]
3342 pub struct Jsqr(pub u32);
3343 impl Jsqr {
3344 #[doc = "JL."]
3345 #[inline(always)]
3346 pub const fn jl(&self) -> u8 {
3347 let val = (self.0 >> 0usize) & 0x03;
3348 val as u8
3349 }
3350 #[doc = "JL."]
3351 #[inline(always)]
3352 pub fn set_jl(&mut self, val: u8) {
3353 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
3354 }
3355 #[doc = "JEXTSEL."]
3356 #[inline(always)]
3357 pub const fn jextsel(&self) -> u8 {
3358 let val = (self.0 >> 2usize) & 0x1f;
3359 val as u8
3360 }
3361 #[doc = "JEXTSEL."]
3362 #[inline(always)]
3363 pub fn set_jextsel(&mut self, val: u8) {
3364 self.0 = (self.0 & !(0x1f << 2usize)) | (((val as u32) & 0x1f) << 2usize);
3365 }
3366 #[doc = "JEXTEN."]
3367 #[inline(always)]
3368 pub const fn jexten(&self) -> u8 {
3369 let val = (self.0 >> 7usize) & 0x03;
3370 val as u8
3371 }
3372 #[doc = "JEXTEN."]
3373 #[inline(always)]
3374 pub fn set_jexten(&mut self, val: u8) {
3375 self.0 = (self.0 & !(0x03 << 7usize)) | (((val as u32) & 0x03) << 7usize);
3376 }
3377 #[doc = "JSQ1."]
3378 #[inline(always)]
3379 pub const fn jsq(&self, n: usize) -> u8 {
3380 assert!(n < 4usize);
3381 let offs = 9usize + n * 6usize;
3382 let val = (self.0 >> offs) & 0x1f;
3383 val as u8
3384 }
3385 #[doc = "JSQ1."]
3386 #[inline(always)]
3387 pub fn set_jsq(&mut self, n: usize, val: u8) {
3388 assert!(n < 4usize);
3389 let offs = 9usize + n * 6usize;
3390 self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
3391 }
3392 }
3393 impl Default for Jsqr {
3394 #[inline(always)]
3395 fn default() -> Jsqr {
3396 Jsqr(0)
3397 }
3398 }
3399 impl core::fmt::Debug for Jsqr {
3400 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3401 f.debug_struct("Jsqr")
3402 .field("jl", &self.jl())
3403 .field("jextsel", &self.jextsel())
3404 .field("jexten", &self.jexten())
3405 .field(
3406 "jsq",
3407 &[self.jsq(0usize), self.jsq(1usize), self.jsq(2usize), self.jsq(3usize)],
3408 )
3409 .finish()
3410 }
3411 }
3412 #[cfg(feature = "defmt")]
3413 impl defmt::Format for Jsqr {
3414 fn format(&self, f: defmt::Formatter) {
3415 #[derive(defmt :: Format)]
3416 struct Jsqr {
3417 jl: u8,
3418 jextsel: u8,
3419 jexten: u8,
3420 jsq: [u8; 4usize],
3421 }
3422 let proxy = Jsqr {
3423 jl: self.jl(),
3424 jextsel: self.jextsel(),
3425 jexten: self.jexten(),
3426 jsq: [self.jsq(0usize), self.jsq(1usize), self.jsq(2usize), self.jsq(3usize)],
3427 };
3428 defmt::write!(f, "{}", proxy)
3429 }
3430 }
3431 #[doc = "ADC watchdog threshold register 1."]
3432 #[repr(transparent)]
3433 #[derive(Copy, Clone, Eq, PartialEq)]
3434 pub struct Ltr1(pub u32);
3435 impl Ltr1 {
3436 #[doc = "LTR1."]
3437 #[inline(always)]
3438 pub const fn ltr1(&self) -> u32 {
3439 let val = (self.0 >> 0usize) & 0x01ff_ffff;
3440 val as u32
3441 }
3442 #[doc = "LTR1."]
3443 #[inline(always)]
3444 pub fn set_ltr1(&mut self, val: u32) {
3445 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
3446 }
3447 }
3448 impl Default for Ltr1 {
3449 #[inline(always)]
3450 fn default() -> Ltr1 {
3451 Ltr1(0)
3452 }
3453 }
3454 impl core::fmt::Debug for Ltr1 {
3455 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3456 f.debug_struct("Ltr1").field("ltr1", &self.ltr1()).finish()
3457 }
3458 }
3459 #[cfg(feature = "defmt")]
3460 impl defmt::Format for Ltr1 {
3461 fn format(&self, f: defmt::Formatter) {
3462 #[derive(defmt :: Format)]
3463 struct Ltr1 {
3464 ltr1: u32,
3465 }
3466 let proxy = Ltr1 { ltr1: self.ltr1() };
3467 defmt::write!(f, "{}", proxy)
3468 }
3469 }
3470 #[doc = "ADC watchdog lower threshold register 2."]
3471 #[repr(transparent)]
3472 #[derive(Copy, Clone, Eq, PartialEq)]
3473 pub struct Ltr2(pub u32);
3474 impl Ltr2 {
3475 #[doc = "LTR2."]
3476 #[inline(always)]
3477 pub const fn ltr2(&self) -> u32 {
3478 let val = (self.0 >> 0usize) & 0x01ff_ffff;
3479 val as u32
3480 }
3481 #[doc = "LTR2."]
3482 #[inline(always)]
3483 pub fn set_ltr2(&mut self, val: u32) {
3484 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
3485 }
3486 }
3487 impl Default for Ltr2 {
3488 #[inline(always)]
3489 fn default() -> Ltr2 {
3490 Ltr2(0)
3491 }
3492 }
3493 impl core::fmt::Debug for Ltr2 {
3494 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3495 f.debug_struct("Ltr2").field("ltr2", &self.ltr2()).finish()
3496 }
3497 }
3498 #[cfg(feature = "defmt")]
3499 impl defmt::Format for Ltr2 {
3500 fn format(&self, f: defmt::Formatter) {
3501 #[derive(defmt :: Format)]
3502 struct Ltr2 {
3503 ltr2: u32,
3504 }
3505 let proxy = Ltr2 { ltr2: self.ltr2() };
3506 defmt::write!(f, "{}", proxy)
3507 }
3508 }
3509 #[doc = "ADC watchdog lower threshold register 3."]
3510 #[repr(transparent)]
3511 #[derive(Copy, Clone, Eq, PartialEq)]
3512 pub struct Ltr3(pub u32);
3513 impl Ltr3 {
3514 #[doc = "LTR3."]
3515 #[inline(always)]
3516 pub const fn ltr3(&self) -> u32 {
3517 let val = (self.0 >> 0usize) & 0x01ff_ffff;
3518 val as u32
3519 }
3520 #[doc = "LTR3."]
3521 #[inline(always)]
3522 pub fn set_ltr3(&mut self, val: u32) {
3523 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
3524 }
3525 }
3526 impl Default for Ltr3 {
3527 #[inline(always)]
3528 fn default() -> Ltr3 {
3529 Ltr3(0)
3530 }
3531 }
3532 impl core::fmt::Debug for Ltr3 {
3533 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3534 f.debug_struct("Ltr3").field("ltr3", &self.ltr3()).finish()
3535 }
3536 }
3537 #[cfg(feature = "defmt")]
3538 impl defmt::Format for Ltr3 {
3539 fn format(&self, f: defmt::Formatter) {
3540 #[derive(defmt :: Format)]
3541 struct Ltr3 {
3542 ltr3: u32,
3543 }
3544 let proxy = Ltr3 { ltr3: self.ltr3() };
3545 defmt::write!(f, "{}", proxy)
3546 }
3547 }
3548 #[doc = "ADC offset register."]
3549 #[repr(transparent)]
3550 #[derive(Copy, Clone, Eq, PartialEq)]
3551 pub struct Ofr(pub u32);
3552 impl Ofr {
3553 #[doc = "OFFSET."]
3554 #[inline(always)]
3555 pub const fn offset(&self) -> u32 {
3556 let val = (self.0 >> 0usize) & 0x00ff_ffff;
3557 val as u32
3558 }
3559 #[doc = "OFFSET."]
3560 #[inline(always)]
3561 pub fn set_offset(&mut self, val: u32) {
3562 self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
3563 }
3564 #[doc = "POSOFF."]
3565 #[inline(always)]
3566 pub const fn posoff(&self) -> bool {
3567 let val = (self.0 >> 24usize) & 0x01;
3568 val != 0
3569 }
3570 #[doc = "POSOFF."]
3571 #[inline(always)]
3572 pub fn set_posoff(&mut self, val: bool) {
3573 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3574 }
3575 #[doc = "USAT."]
3576 #[inline(always)]
3577 pub const fn usat(&self) -> bool {
3578 let val = (self.0 >> 25usize) & 0x01;
3579 val != 0
3580 }
3581 #[doc = "USAT."]
3582 #[inline(always)]
3583 pub fn set_usat(&mut self, val: bool) {
3584 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
3585 }
3586 #[doc = "SSAT."]
3587 #[inline(always)]
3588 pub const fn ssat(&self) -> bool {
3589 let val = (self.0 >> 26usize) & 0x01;
3590 val != 0
3591 }
3592 #[doc = "SSAT."]
3593 #[inline(always)]
3594 pub fn set_ssat(&mut self, val: bool) {
3595 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
3596 }
3597 #[doc = "OFFSET_CH."]
3598 #[inline(always)]
3599 pub const fn offset_ch(&self) -> u8 {
3600 let val = (self.0 >> 27usize) & 0x1f;
3601 val as u8
3602 }
3603 #[doc = "OFFSET_CH."]
3604 #[inline(always)]
3605 pub fn set_offset_ch(&mut self, val: u8) {
3606 self.0 = (self.0 & !(0x1f << 27usize)) | (((val as u32) & 0x1f) << 27usize);
3607 }
3608 }
3609 impl Default for Ofr {
3610 #[inline(always)]
3611 fn default() -> Ofr {
3612 Ofr(0)
3613 }
3614 }
3615 impl core::fmt::Debug for Ofr {
3616 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3617 f.debug_struct("Ofr")
3618 .field("offset", &self.offset())
3619 .field("posoff", &self.posoff())
3620 .field("usat", &self.usat())
3621 .field("ssat", &self.ssat())
3622 .field("offset_ch", &self.offset_ch())
3623 .finish()
3624 }
3625 }
3626 #[cfg(feature = "defmt")]
3627 impl defmt::Format for Ofr {
3628 fn format(&self, f: defmt::Formatter) {
3629 #[derive(defmt :: Format)]
3630 struct Ofr {
3631 offset: u32,
3632 posoff: bool,
3633 usat: bool,
3634 ssat: bool,
3635 offset_ch: u8,
3636 }
3637 let proxy = Ofr {
3638 offset: self.offset(),
3639 posoff: self.posoff(),
3640 usat: self.usat(),
3641 ssat: self.ssat(),
3642 offset_ch: self.offset_ch(),
3643 };
3644 defmt::write!(f, "{}", proxy)
3645 }
3646 }
3647 #[doc = "ADC channel preselection register."]
3648 #[repr(transparent)]
3649 #[derive(Copy, Clone, Eq, PartialEq)]
3650 pub struct Pcsel(pub u32);
3651 impl Pcsel {
3652 #[doc = "PCSEL."]
3653 #[inline(always)]
3654 pub const fn pcsel(&self, n: usize) -> super::vals::Pcsel {
3655 assert!(n < 20usize);
3656 let offs = 0usize + n * 1usize;
3657 let val = (self.0 >> offs) & 0x01;
3658 super::vals::Pcsel::from_bits(val as u8)
3659 }
3660 #[doc = "PCSEL."]
3661 #[inline(always)]
3662 pub fn set_pcsel(&mut self, n: usize, val: super::vals::Pcsel) {
3663 assert!(n < 20usize);
3664 let offs = 0usize + n * 1usize;
3665 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
3666 }
3667 }
3668 impl Default for Pcsel {
3669 #[inline(always)]
3670 fn default() -> Pcsel {
3671 Pcsel(0)
3672 }
3673 }
3674 impl core::fmt::Debug for Pcsel {
3675 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3676 f.debug_struct("Pcsel")
3677 .field(
3678 "pcsel",
3679 &[
3680 self.pcsel(0usize),
3681 self.pcsel(1usize),
3682 self.pcsel(2usize),
3683 self.pcsel(3usize),
3684 self.pcsel(4usize),
3685 self.pcsel(5usize),
3686 self.pcsel(6usize),
3687 self.pcsel(7usize),
3688 self.pcsel(8usize),
3689 self.pcsel(9usize),
3690 self.pcsel(10usize),
3691 self.pcsel(11usize),
3692 self.pcsel(12usize),
3693 self.pcsel(13usize),
3694 self.pcsel(14usize),
3695 self.pcsel(15usize),
3696 self.pcsel(16usize),
3697 self.pcsel(17usize),
3698 self.pcsel(18usize),
3699 self.pcsel(19usize),
3700 ],
3701 )
3702 .finish()
3703 }
3704 }
3705 #[cfg(feature = "defmt")]
3706 impl defmt::Format for Pcsel {
3707 fn format(&self, f: defmt::Formatter) {
3708 #[derive(defmt :: Format)]
3709 struct Pcsel {
3710 pcsel: [super::vals::Pcsel; 20usize],
3711 }
3712 let proxy = Pcsel {
3713 pcsel: [
3714 self.pcsel(0usize),
3715 self.pcsel(1usize),
3716 self.pcsel(2usize),
3717 self.pcsel(3usize),
3718 self.pcsel(4usize),
3719 self.pcsel(5usize),
3720 self.pcsel(6usize),
3721 self.pcsel(7usize),
3722 self.pcsel(8usize),
3723 self.pcsel(9usize),
3724 self.pcsel(10usize),
3725 self.pcsel(11usize),
3726 self.pcsel(12usize),
3727 self.pcsel(13usize),
3728 self.pcsel(14usize),
3729 self.pcsel(15usize),
3730 self.pcsel(16usize),
3731 self.pcsel(17usize),
3732 self.pcsel(18usize),
3733 self.pcsel(19usize),
3734 ],
3735 };
3736 defmt::write!(f, "{}", proxy)
3737 }
3738 }
3739 #[doc = "ADC sample time register 1."]
3740 #[repr(transparent)]
3741 #[derive(Copy, Clone, Eq, PartialEq)]
3742 pub struct Smpr(pub u32);
3743 impl Smpr {
3744 #[doc = "SMP0."]
3745 #[inline(always)]
3746 pub const fn smp(&self, n: usize) -> super::vals::SampleTime {
3747 assert!(n < 10usize);
3748 let offs = 0usize + n * 3usize;
3749 let val = (self.0 >> offs) & 0x07;
3750 super::vals::SampleTime::from_bits(val as u8)
3751 }
3752 #[doc = "SMP0."]
3753 #[inline(always)]
3754 pub fn set_smp(&mut self, n: usize, val: super::vals::SampleTime) {
3755 assert!(n < 10usize);
3756 let offs = 0usize + n * 3usize;
3757 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32) & 0x07) << offs);
3758 }
3759 }
3760 impl Default for Smpr {
3761 #[inline(always)]
3762 fn default() -> Smpr {
3763 Smpr(0)
3764 }
3765 }
3766 impl core::fmt::Debug for Smpr {
3767 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3768 f.debug_struct("Smpr")
3769 .field(
3770 "smp",
3771 &[
3772 self.smp(0usize),
3773 self.smp(1usize),
3774 self.smp(2usize),
3775 self.smp(3usize),
3776 self.smp(4usize),
3777 self.smp(5usize),
3778 self.smp(6usize),
3779 self.smp(7usize),
3780 self.smp(8usize),
3781 self.smp(9usize),
3782 ],
3783 )
3784 .finish()
3785 }
3786 }
3787 #[cfg(feature = "defmt")]
3788 impl defmt::Format for Smpr {
3789 fn format(&self, f: defmt::Formatter) {
3790 #[derive(defmt :: Format)]
3791 struct Smpr {
3792 smp: [super::vals::SampleTime; 10usize],
3793 }
3794 let proxy = Smpr {
3795 smp: [
3796 self.smp(0usize),
3797 self.smp(1usize),
3798 self.smp(2usize),
3799 self.smp(3usize),
3800 self.smp(4usize),
3801 self.smp(5usize),
3802 self.smp(6usize),
3803 self.smp(7usize),
3804 self.smp(8usize),
3805 self.smp(9usize),
3806 ],
3807 };
3808 defmt::write!(f, "{}", proxy)
3809 }
3810 }
3811 #[doc = "ADC regular sequence register 1."]
3812 #[repr(transparent)]
3813 #[derive(Copy, Clone, Eq, PartialEq)]
3814 pub struct Sqr1(pub u32);
3815 impl Sqr1 {
3816 #[doc = "L."]
3817 #[inline(always)]
3818 pub const fn l(&self) -> u8 {
3819 let val = (self.0 >> 0usize) & 0x0f;
3820 val as u8
3821 }
3822 #[doc = "L."]
3823 #[inline(always)]
3824 pub fn set_l(&mut self, val: u8) {
3825 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3826 }
3827 #[doc = "SQ1."]
3828 #[inline(always)]
3829 pub const fn sq(&self, n: usize) -> u8 {
3830 assert!(n < 4usize);
3831 let offs = 6usize + n * 6usize;
3832 let val = (self.0 >> offs) & 0x1f;
3833 val as u8
3834 }
3835 #[doc = "SQ1."]
3836 #[inline(always)]
3837 pub fn set_sq(&mut self, n: usize, val: u8) {
3838 assert!(n < 4usize);
3839 let offs = 6usize + n * 6usize;
3840 self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
3841 }
3842 }
3843 impl Default for Sqr1 {
3844 #[inline(always)]
3845 fn default() -> Sqr1 {
3846 Sqr1(0)
3847 }
3848 }
3849 impl core::fmt::Debug for Sqr1 {
3850 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3851 f.debug_struct("Sqr1")
3852 .field("l", &self.l())
3853 .field(
3854 "sq",
3855 &[self.sq(0usize), self.sq(1usize), self.sq(2usize), self.sq(3usize)],
3856 )
3857 .finish()
3858 }
3859 }
3860 #[cfg(feature = "defmt")]
3861 impl defmt::Format for Sqr1 {
3862 fn format(&self, f: defmt::Formatter) {
3863 #[derive(defmt :: Format)]
3864 struct Sqr1 {
3865 l: u8,
3866 sq: [u8; 4usize],
3867 }
3868 let proxy = Sqr1 {
3869 l: self.l(),
3870 sq: [self.sq(0usize), self.sq(1usize), self.sq(2usize), self.sq(3usize)],
3871 };
3872 defmt::write!(f, "{}", proxy)
3873 }
3874 }
3875 #[doc = "ADC regular sequence register 2."]
3876 #[repr(transparent)]
3877 #[derive(Copy, Clone, Eq, PartialEq)]
3878 pub struct Sqr2(pub u32);
3879 impl Sqr2 {
3880 #[doc = "SQ5."]
3881 #[inline(always)]
3882 pub const fn sq(&self, n: usize) -> u8 {
3883 assert!(n < 5usize);
3884 let offs = 0usize + n * 6usize;
3885 let val = (self.0 >> offs) & 0x1f;
3886 val as u8
3887 }
3888 #[doc = "SQ5."]
3889 #[inline(always)]
3890 pub fn set_sq(&mut self, n: usize, val: u8) {
3891 assert!(n < 5usize);
3892 let offs = 0usize + n * 6usize;
3893 self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
3894 }
3895 }
3896 impl Default for Sqr2 {
3897 #[inline(always)]
3898 fn default() -> Sqr2 {
3899 Sqr2(0)
3900 }
3901 }
3902 impl core::fmt::Debug for Sqr2 {
3903 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3904 f.debug_struct("Sqr2")
3905 .field(
3906 "sq",
3907 &[
3908 self.sq(0usize),
3909 self.sq(1usize),
3910 self.sq(2usize),
3911 self.sq(3usize),
3912 self.sq(4usize),
3913 ],
3914 )
3915 .finish()
3916 }
3917 }
3918 #[cfg(feature = "defmt")]
3919 impl defmt::Format for Sqr2 {
3920 fn format(&self, f: defmt::Formatter) {
3921 #[derive(defmt :: Format)]
3922 struct Sqr2 {
3923 sq: [u8; 5usize],
3924 }
3925 let proxy = Sqr2 {
3926 sq: [
3927 self.sq(0usize),
3928 self.sq(1usize),
3929 self.sq(2usize),
3930 self.sq(3usize),
3931 self.sq(4usize),
3932 ],
3933 };
3934 defmt::write!(f, "{}", proxy)
3935 }
3936 }
3937 #[doc = "ADC regular sequence register 3."]
3938 #[repr(transparent)]
3939 #[derive(Copy, Clone, Eq, PartialEq)]
3940 pub struct Sqr3(pub u32);
3941 impl Sqr3 {
3942 #[doc = "SQ10."]
3943 #[inline(always)]
3944 pub const fn sq(&self, n: usize) -> u8 {
3945 assert!(n < 5usize);
3946 let offs = 0usize + n * 6usize;
3947 let val = (self.0 >> offs) & 0x1f;
3948 val as u8
3949 }
3950 #[doc = "SQ10."]
3951 #[inline(always)]
3952 pub fn set_sq(&mut self, n: usize, val: u8) {
3953 assert!(n < 5usize);
3954 let offs = 0usize + n * 6usize;
3955 self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
3956 }
3957 }
3958 impl Default for Sqr3 {
3959 #[inline(always)]
3960 fn default() -> Sqr3 {
3961 Sqr3(0)
3962 }
3963 }
3964 impl core::fmt::Debug for Sqr3 {
3965 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3966 f.debug_struct("Sqr3")
3967 .field(
3968 "sq",
3969 &[
3970 self.sq(0usize),
3971 self.sq(1usize),
3972 self.sq(2usize),
3973 self.sq(3usize),
3974 self.sq(4usize),
3975 ],
3976 )
3977 .finish()
3978 }
3979 }
3980 #[cfg(feature = "defmt")]
3981 impl defmt::Format for Sqr3 {
3982 fn format(&self, f: defmt::Formatter) {
3983 #[derive(defmt :: Format)]
3984 struct Sqr3 {
3985 sq: [u8; 5usize],
3986 }
3987 let proxy = Sqr3 {
3988 sq: [
3989 self.sq(0usize),
3990 self.sq(1usize),
3991 self.sq(2usize),
3992 self.sq(3usize),
3993 self.sq(4usize),
3994 ],
3995 };
3996 defmt::write!(f, "{}", proxy)
3997 }
3998 }
3999 #[doc = "ADC regular sequence register 4."]
4000 #[repr(transparent)]
4001 #[derive(Copy, Clone, Eq, PartialEq)]
4002 pub struct Sqr4(pub u32);
4003 impl Sqr4 {
4004 #[doc = "SQ15."]
4005 #[inline(always)]
4006 pub const fn sq(&self, n: usize) -> u8 {
4007 assert!(n < 2usize);
4008 let offs = 0usize + n * 6usize;
4009 let val = (self.0 >> offs) & 0x1f;
4010 val as u8
4011 }
4012 #[doc = "SQ15."]
4013 #[inline(always)]
4014 pub fn set_sq(&mut self, n: usize, val: u8) {
4015 assert!(n < 2usize);
4016 let offs = 0usize + n * 6usize;
4017 self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
4018 }
4019 }
4020 impl Default for Sqr4 {
4021 #[inline(always)]
4022 fn default() -> Sqr4 {
4023 Sqr4(0)
4024 }
4025 }
4026 impl core::fmt::Debug for Sqr4 {
4027 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4028 f.debug_struct("Sqr4")
4029 .field("sq", &[self.sq(0usize), self.sq(1usize)])
4030 .finish()
4031 }
4032 }
4033 #[cfg(feature = "defmt")]
4034 impl defmt::Format for Sqr4 {
4035 fn format(&self, f: defmt::Formatter) {
4036 #[derive(defmt :: Format)]
4037 struct Sqr4 {
4038 sq: [u8; 2usize],
4039 }
4040 let proxy = Sqr4 {
4041 sq: [self.sq(0usize), self.sq(1usize)],
4042 };
4043 defmt::write!(f, "{}", proxy)
4044 }
4045 }
4046}
4047pub mod vals {
4048 #[repr(u8)]
4049 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4050 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4051 pub enum Adc4Dmacfg {
4052 #[doc = "DMA One Shot mode selected"]
4053 ONE_SHOT = 0x0,
4054 #[doc = "DMA Circular mode selected"]
4055 CIRCULAR = 0x01,
4056 }
4057 impl Adc4Dmacfg {
4058 #[inline(always)]
4059 pub const fn from_bits(val: u8) -> Adc4Dmacfg {
4060 unsafe { core::mem::transmute(val & 0x01) }
4061 }
4062 #[inline(always)]
4063 pub const fn to_bits(self) -> u8 {
4064 unsafe { core::mem::transmute(self) }
4065 }
4066 }
4067 impl From<u8> for Adc4Dmacfg {
4068 #[inline(always)]
4069 fn from(val: u8) -> Adc4Dmacfg {
4070 Adc4Dmacfg::from_bits(val)
4071 }
4072 }
4073 impl From<Adc4Dmacfg> for u8 {
4074 #[inline(always)]
4075 fn from(val: Adc4Dmacfg) -> u8 {
4076 Adc4Dmacfg::to_bits(val)
4077 }
4078 }
4079 #[repr(u8)]
4080 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4081 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4082 pub enum Adc4Exten {
4083 #[doc = "Trigger detection disabled"]
4084 DISABLED = 0x0,
4085 #[doc = "Trigger detection on the rising edge"]
4086 RISING_EDGE = 0x01,
4087 #[doc = "Trigger detection on the falling edge"]
4088 FALLING_EDGE = 0x02,
4089 #[doc = "Trigger detection on both the rising and falling edges"]
4090 BOTH_EDGES = 0x03,
4091 }
4092 impl Adc4Exten {
4093 #[inline(always)]
4094 pub const fn from_bits(val: u8) -> Adc4Exten {
4095 unsafe { core::mem::transmute(val & 0x03) }
4096 }
4097 #[inline(always)]
4098 pub const fn to_bits(self) -> u8 {
4099 unsafe { core::mem::transmute(self) }
4100 }
4101 }
4102 impl From<u8> for Adc4Exten {
4103 #[inline(always)]
4104 fn from(val: u8) -> Adc4Exten {
4105 Adc4Exten::from_bits(val)
4106 }
4107 }
4108 impl From<Adc4Exten> for u8 {
4109 #[inline(always)]
4110 fn from(val: Adc4Exten) -> u8 {
4111 Adc4Exten::to_bits(val)
4112 }
4113 }
4114 #[repr(u8)]
4115 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4116 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4117 pub enum Adc4OversamplingRatio {
4118 #[doc = "Oversample 2 times"]
4119 OVERSAMPLE2X = 0x0,
4120 #[doc = "Oversample 4 times"]
4121 OVERSAMPLE4X = 0x01,
4122 #[doc = "Oversample 8 times"]
4123 OVERSAMPLE8X = 0x02,
4124 #[doc = "Oversample 16 times"]
4125 OVERSAMPLE16X = 0x03,
4126 #[doc = "Oversample 32 times"]
4127 OVERSAMPLE32X = 0x04,
4128 #[doc = "Oversample 64 times"]
4129 OVERSAMPLE64X = 0x05,
4130 #[doc = "Oversample 128 times"]
4131 OVERSAMPLE128X = 0x06,
4132 #[doc = "Oversample 256 times"]
4133 OVERSAMPLE256X = 0x07,
4134 }
4135 impl Adc4OversamplingRatio {
4136 #[inline(always)]
4137 pub const fn from_bits(val: u8) -> Adc4OversamplingRatio {
4138 unsafe { core::mem::transmute(val & 0x07) }
4139 }
4140 #[inline(always)]
4141 pub const fn to_bits(self) -> u8 {
4142 unsafe { core::mem::transmute(self) }
4143 }
4144 }
4145 impl From<u8> for Adc4OversamplingRatio {
4146 #[inline(always)]
4147 fn from(val: u8) -> Adc4OversamplingRatio {
4148 Adc4OversamplingRatio::from_bits(val)
4149 }
4150 }
4151 impl From<Adc4OversamplingRatio> for u8 {
4152 #[inline(always)]
4153 fn from(val: Adc4OversamplingRatio) -> u8 {
4154 Adc4OversamplingRatio::to_bits(val)
4155 }
4156 }
4157 #[repr(u8)]
4158 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4159 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4160 pub enum Adc4Presc {
4161 #[doc = "adc_ker_ck_input not divided"]
4162 DIV1 = 0x0,
4163 #[doc = "adc_ker_ck_input divided by 2"]
4164 DIV2 = 0x01,
4165 #[doc = "adc_ker_ck_input divided by 4"]
4166 DIV4 = 0x02,
4167 #[doc = "adc_ker_ck_input divided by 6"]
4168 DIV6 = 0x03,
4169 #[doc = "adc_ker_ck_input divided by 8"]
4170 DIV8 = 0x04,
4171 #[doc = "adc_ker_ck_input divided by 10"]
4172 DIV10 = 0x05,
4173 #[doc = "adc_ker_ck_input divided by 12"]
4174 DIV12 = 0x06,
4175 #[doc = "adc_ker_ck_input divided by 16"]
4176 DIV16 = 0x07,
4177 #[doc = "adc_ker_ck_input divided by 32"]
4178 DIV32 = 0x08,
4179 #[doc = "adc_ker_ck_input divided by 64"]
4180 DIV64 = 0x09,
4181 #[doc = "adc_ker_ck_input divided by 128"]
4182 DIV128 = 0x0a,
4183 #[doc = "adc_ker_ck_input divided by 256"]
4184 DIV256 = 0x0b,
4185 _RESERVED_c = 0x0c,
4186 _RESERVED_d = 0x0d,
4187 _RESERVED_e = 0x0e,
4188 _RESERVED_f = 0x0f,
4189 }
4190 impl Adc4Presc {
4191 #[inline(always)]
4192 pub const fn from_bits(val: u8) -> Adc4Presc {
4193 unsafe { core::mem::transmute(val & 0x0f) }
4194 }
4195 #[inline(always)]
4196 pub const fn to_bits(self) -> u8 {
4197 unsafe { core::mem::transmute(self) }
4198 }
4199 }
4200 impl From<u8> for Adc4Presc {
4201 #[inline(always)]
4202 fn from(val: u8) -> Adc4Presc {
4203 Adc4Presc::from_bits(val)
4204 }
4205 }
4206 impl From<Adc4Presc> for u8 {
4207 #[inline(always)]
4208 fn from(val: Adc4Presc) -> u8 {
4209 Adc4Presc::to_bits(val)
4210 }
4211 }
4212 #[repr(u8)]
4213 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4214 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4215 pub enum Adc4Res {
4216 #[doc = "12-bit resolution"]
4217 BITS12 = 0x0,
4218 #[doc = "10-bit resolution"]
4219 BITS10 = 0x01,
4220 #[doc = "8-bit resolution"]
4221 BITS8 = 0x02,
4222 #[doc = "6-bit resolution"]
4223 BITS6 = 0x03,
4224 }
4225 impl Adc4Res {
4226 #[inline(always)]
4227 pub const fn from_bits(val: u8) -> Adc4Res {
4228 unsafe { core::mem::transmute(val & 0x03) }
4229 }
4230 #[inline(always)]
4231 pub const fn to_bits(self) -> u8 {
4232 unsafe { core::mem::transmute(self) }
4233 }
4234 }
4235 impl From<u8> for Adc4Res {
4236 #[inline(always)]
4237 fn from(val: u8) -> Adc4Res {
4238 Adc4Res::from_bits(val)
4239 }
4240 }
4241 impl From<Adc4Res> for u8 {
4242 #[inline(always)]
4243 fn from(val: Adc4Res) -> u8 {
4244 Adc4Res::to_bits(val)
4245 }
4246 }
4247 #[repr(u8)]
4248 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4249 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4250 pub enum Adc4SampleTime {
4251 #[doc = "1.5 ADC cycles"]
4252 CYCLES1_5 = 0x0,
4253 #[doc = "3.5 ADC cycles"]
4254 CYCLES3_5 = 0x01,
4255 #[doc = "7.5 ADC cycles"]
4256 CYCLES7_5 = 0x02,
4257 #[doc = "12.5 ADC cycles"]
4258 CYCLES12_5 = 0x03,
4259 #[doc = "19.5 ADC cycles"]
4260 CYCLES19_5 = 0x04,
4261 #[doc = "39.5 ADC cycles"]
4262 CYCLES39_5 = 0x05,
4263 #[doc = "79.5 ADC cycles"]
4264 CYCLES79_5 = 0x06,
4265 #[doc = "160.5 ADC cycles"]
4266 CYCLES814_5 = 0x07,
4267 }
4268 impl Adc4SampleTime {
4269 #[inline(always)]
4270 pub const fn from_bits(val: u8) -> Adc4SampleTime {
4271 unsafe { core::mem::transmute(val & 0x07) }
4272 }
4273 #[inline(always)]
4274 pub const fn to_bits(self) -> u8 {
4275 unsafe { core::mem::transmute(self) }
4276 }
4277 }
4278 impl From<u8> for Adc4SampleTime {
4279 #[inline(always)]
4280 fn from(val: u8) -> Adc4SampleTime {
4281 Adc4SampleTime::from_bits(val)
4282 }
4283 }
4284 impl From<Adc4SampleTime> for u8 {
4285 #[inline(always)]
4286 fn from(val: Adc4SampleTime) -> u8 {
4287 Adc4SampleTime::to_bits(val)
4288 }
4289 }
4290 #[repr(u8)]
4291 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4292 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4293 pub enum Adstp {
4294 _RESERVED_0 = 0x0,
4295 #[doc = "Stop conversion of channel"]
4296 STOP = 0x01,
4297 }
4298 impl Adstp {
4299 #[inline(always)]
4300 pub const fn from_bits(val: u8) -> Adstp {
4301 unsafe { core::mem::transmute(val & 0x01) }
4302 }
4303 #[inline(always)]
4304 pub const fn to_bits(self) -> u8 {
4305 unsafe { core::mem::transmute(self) }
4306 }
4307 }
4308 impl From<u8> for Adstp {
4309 #[inline(always)]
4310 fn from(val: u8) -> Adstp {
4311 Adstp::from_bits(val)
4312 }
4313 }
4314 impl From<Adstp> for u8 {
4315 #[inline(always)]
4316 fn from(val: Adstp) -> u8 {
4317 Adstp::to_bits(val)
4318 }
4319 }
4320 #[repr(u8)]
4321 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4322 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4323 pub enum Difsel {
4324 #[doc = "Input channel is configured in single-ended mode"]
4325 SINGLE_ENDED = 0x0,
4326 #[doc = "Input channel is configured in differential mode"]
4327 DIFFERENTIAL = 0x01,
4328 }
4329 impl Difsel {
4330 #[inline(always)]
4331 pub const fn from_bits(val: u8) -> Difsel {
4332 unsafe { core::mem::transmute(val & 0x01) }
4333 }
4334 #[inline(always)]
4335 pub const fn to_bits(self) -> u8 {
4336 unsafe { core::mem::transmute(self) }
4337 }
4338 }
4339 impl From<u8> for Difsel {
4340 #[inline(always)]
4341 fn from(val: u8) -> Difsel {
4342 Difsel::from_bits(val)
4343 }
4344 }
4345 impl From<Difsel> for u8 {
4346 #[inline(always)]
4347 fn from(val: Difsel) -> u8 {
4348 Difsel::to_bits(val)
4349 }
4350 }
4351 #[repr(u8)]
4352 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4353 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4354 pub enum Dmngt {
4355 #[doc = "Store output data in DR only"]
4356 DR = 0x0,
4357 #[doc = "DMA One Shot Mode selected"]
4358 DMA_ONE_SHOT = 0x01,
4359 #[doc = "MDF mode selected"]
4360 MDF = 0x02,
4361 #[doc = "DMA Circular Mode selected"]
4362 DMA_CIRCULAR = 0x03,
4363 }
4364 impl Dmngt {
4365 #[inline(always)]
4366 pub const fn from_bits(val: u8) -> Dmngt {
4367 unsafe { core::mem::transmute(val & 0x03) }
4368 }
4369 #[inline(always)]
4370 pub const fn to_bits(self) -> u8 {
4371 unsafe { core::mem::transmute(self) }
4372 }
4373 }
4374 impl From<u8> for Dmngt {
4375 #[inline(always)]
4376 fn from(val: u8) -> Dmngt {
4377 Dmngt::from_bits(val)
4378 }
4379 }
4380 impl From<Dmngt> for u8 {
4381 #[inline(always)]
4382 fn from(val: Dmngt) -> u8 {
4383 Dmngt::to_bits(val)
4384 }
4385 }
4386 #[repr(u8)]
4387 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4388 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4389 pub enum Exten {
4390 #[doc = "Trigger detection disabled"]
4391 DISABLED = 0x0,
4392 #[doc = "Trigger detection on the rising edge"]
4393 RISING_EDGE = 0x01,
4394 #[doc = "Trigger detection on the falling edge"]
4395 FALLING_EDGE = 0x02,
4396 #[doc = "Trigger detection on both the rising and falling edges"]
4397 BOTH_EDGES = 0x03,
4398 }
4399 impl Exten {
4400 #[inline(always)]
4401 pub const fn from_bits(val: u8) -> Exten {
4402 unsafe { core::mem::transmute(val & 0x03) }
4403 }
4404 #[inline(always)]
4405 pub const fn to_bits(self) -> u8 {
4406 unsafe { core::mem::transmute(self) }
4407 }
4408 }
4409 impl From<u8> for Exten {
4410 #[inline(always)]
4411 fn from(val: u8) -> Exten {
4412 Exten::from_bits(val)
4413 }
4414 }
4415 impl From<Exten> for u8 {
4416 #[inline(always)]
4417 fn from(val: Exten) -> u8 {
4418 Exten::to_bits(val)
4419 }
4420 }
4421 #[repr(u8)]
4422 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4423 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4424 pub enum Pcsel {
4425 #[doc = "Input channel x is not pre-selected"]
4426 NOT_PRESELECTED = 0x0,
4427 #[doc = "Pre-select input channel x"]
4428 PRESELECTED = 0x01,
4429 }
4430 impl Pcsel {
4431 #[inline(always)]
4432 pub const fn from_bits(val: u8) -> Pcsel {
4433 unsafe { core::mem::transmute(val & 0x01) }
4434 }
4435 #[inline(always)]
4436 pub const fn to_bits(self) -> u8 {
4437 unsafe { core::mem::transmute(self) }
4438 }
4439 }
4440 impl From<u8> for Pcsel {
4441 #[inline(always)]
4442 fn from(val: u8) -> Pcsel {
4443 Pcsel::from_bits(val)
4444 }
4445 }
4446 impl From<Pcsel> for u8 {
4447 #[inline(always)]
4448 fn from(val: Pcsel) -> u8 {
4449 Pcsel::to_bits(val)
4450 }
4451 }
4452 #[repr(u8)]
4453 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4454 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4455 pub enum Res {
4456 #[doc = "14-bit resolution"]
4457 BITS14 = 0x0,
4458 #[doc = "12-bit resolution"]
4459 BITS12 = 0x01,
4460 #[doc = "10-bit resolution"]
4461 BITS10 = 0x02,
4462 #[doc = "8-bit resolution"]
4463 BITS8 = 0x03,
4464 }
4465 impl Res {
4466 #[inline(always)]
4467 pub const fn from_bits(val: u8) -> Res {
4468 unsafe { core::mem::transmute(val & 0x03) }
4469 }
4470 #[inline(always)]
4471 pub const fn to_bits(self) -> u8 {
4472 unsafe { core::mem::transmute(self) }
4473 }
4474 }
4475 impl From<u8> for Res {
4476 #[inline(always)]
4477 fn from(val: u8) -> Res {
4478 Res::from_bits(val)
4479 }
4480 }
4481 impl From<Res> for u8 {
4482 #[inline(always)]
4483 fn from(val: Res) -> u8 {
4484 Res::to_bits(val)
4485 }
4486 }
4487 #[repr(u8)]
4488 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
4489 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
4490 pub enum SampleTime {
4491 #[doc = "1.5 ADC cycles"]
4492 CYCLES1_5 = 0x0,
4493 #[doc = "3.5 ADC cycles"]
4494 CYCLES3_5 = 0x01,
4495 #[doc = "7.5 ADC cycles"]
4496 CYCLES7_5 = 0x02,
4497 #[doc = "12.5 ADC cycles"]
4498 CYCLES12_5 = 0x03,
4499 #[doc = "19.5 ADC cycles"]
4500 CYCLES19_5 = 0x04,
4501 #[doc = "39.5 ADC cycles"]
4502 CYCLES39_5 = 0x05,
4503 #[doc = "79.5 ADC cycles"]
4504 CYCLES79_5 = 0x06,
4505 #[doc = "160.5 ADC cycles"]
4506 CYCLES160_5 = 0x07,
4507 }
4508 impl SampleTime {
4509 #[inline(always)]
4510 pub const fn from_bits(val: u8) -> SampleTime {
4511 unsafe { core::mem::transmute(val & 0x07) }
4512 }
4513 #[inline(always)]
4514 pub const fn to_bits(self) -> u8 {
4515 unsafe { core::mem::transmute(self) }
4516 }
4517 }
4518 impl From<u8> for SampleTime {
4519 #[inline(always)]
4520 fn from(val: u8) -> SampleTime {
4521 SampleTime::from_bits(val)
4522 }
4523 }
4524 impl From<SampleTime> for u8 {
4525 #[inline(always)]
4526 fn from(val: SampleTime) -> u8 {
4527 SampleTime::to_bits(val)
4528 }
4529 }
4530}
4531