1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Analog-to-Digital Converter."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct AdcCommon {
9 ptr: *mut u8,
10}
11unsafe impl Send for AdcCommon {}
12unsafe impl Sync for AdcCommon {}
13impl AdcCommon {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "ADC common status register."]
23 #[inline(always)]
24 pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::R> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "ADC_CCR system control register."]
28 #[inline(always)]
29 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
31 }
32 #[doc = "ADC common regular data register for dual mode."]
33 #[inline(always)]
34 pub const fn cdr(self) -> crate::common::Reg<regs::Cdr, crate::common::R> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
36 }
37 #[doc = "ADC common regular data register for 32-bit dual mode."]
38 #[inline(always)]
39 pub const fn cdr2(self) -> crate::common::Reg<regs::Cdr2, crate::common::R> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
41 }
42}
43pub mod regs {
44 #[doc = "ADC_CCR system control register."]
45 #[repr(transparent)]
46 #[derive(Copy, Clone, Eq, PartialEq)]
47 pub struct Ccr(pub u32);
48 impl Ccr {
49 #[doc = "Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
50 #[inline(always)]
51 pub const fn dual(&self) -> super::vals::Dual {
52 let val = (self.0 >> 0usize) & 0x1f;
53 super::vals::Dual::from_bits(val as u8)
54 }
55 #[doc = "Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
56 #[inline(always)]
57 pub fn set_dual(&mut self, val: super::vals::Dual) {
58 self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize);
59 }
60 #[doc = "Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
61 #[inline(always)]
62 pub const fn delay(&self) -> u8 {
63 let val = (self.0 >> 8usize) & 0x0f;
64 val as u8
65 }
66 #[doc = "Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
67 #[inline(always)]
68 pub fn set_delay(&mut self, val: u8) {
69 self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
70 }
71 #[doc = "Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)."]
72 #[inline(always)]
73 pub const fn damdf(&self) -> super::vals::Damdf {
74 let val = (self.0 >> 14usize) & 0x03;
75 super::vals::Damdf::from_bits(val as u8)
76 }
77 #[doc = "Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)."]
78 #[inline(always)]
79 pub fn set_damdf(&mut self, val: super::vals::Damdf) {
80 self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
81 }
82 #[doc = "ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
83 #[inline(always)]
84 pub const fn presc(&self) -> super::vals::Presc {
85 let val = (self.0 >> 18usize) & 0x0f;
86 super::vals::Presc::from_bits(val as u8)
87 }
88 #[doc = "ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
89 #[inline(always)]
90 pub fn set_presc(&mut self, val: super::vals::Presc) {
91 self.0 = (self.0 & !(0x0f << 18usize)) | (((val.to_bits() as u32) & 0x0f) << 18usize);
92 }
93 #[doc = "VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
94 #[inline(always)]
95 pub const fn vrefen(&self) -> bool {
96 let val = (self.0 >> 22usize) & 0x01;
97 val != 0
98 }
99 #[doc = "VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
100 #[inline(always)]
101 pub fn set_vrefen(&mut self, val: bool) {
102 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
103 }
104 #[doc = "Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
105 #[inline(always)]
106 pub const fn vsenseen(&self) -> bool {
107 let val = (self.0 >> 23usize) & 0x01;
108 val != 0
109 }
110 #[doc = "Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
111 #[inline(always)]
112 pub fn set_vsenseen(&mut self, val: bool) {
113 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
114 }
115 #[doc = "VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
116 #[inline(always)]
117 pub const fn vbaten(&self) -> bool {
118 let val = (self.0 >> 24usize) & 0x01;
119 val != 0
120 }
121 #[doc = "VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)."]
122 #[inline(always)]
123 pub fn set_vbaten(&mut self, val: bool) {
124 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
125 }
126 }
127 impl Default for Ccr {
128 #[inline(always)]
129 fn default() -> Ccr {
130 Ccr(0)
131 }
132 }
133 impl core::fmt::Debug for Ccr {
134 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135 f.debug_struct("Ccr")
136 .field("dual", &self.dual())
137 .field("delay", &self.delay())
138 .field("damdf", &self.damdf())
139 .field("presc", &self.presc())
140 .field("vrefen", &self.vrefen())
141 .field("vsenseen", &self.vsenseen())
142 .field("vbaten", &self.vbaten())
143 .finish()
144 }
145 }
146 #[cfg(feature = "defmt")]
147 impl defmt::Format for Ccr {
148 fn format(&self, f: defmt::Formatter) {
149 #[derive(defmt :: Format)]
150 struct Ccr {
151 dual: super::vals::Dual,
152 delay: u8,
153 damdf: super::vals::Damdf,
154 presc: super::vals::Presc,
155 vrefen: bool,
156 vsenseen: bool,
157 vbaten: bool,
158 }
159 let proxy = Ccr {
160 dual: self.dual(),
161 delay: self.delay(),
162 damdf: self.damdf(),
163 presc: self.presc(),
164 vrefen: self.vrefen(),
165 vsenseen: self.vsenseen(),
166 vbaten: self.vbaten(),
167 };
168 defmt::write!(f, "{}", proxy)
169 }
170 }
171 #[doc = "ADC common regular data register for dual mode."]
172 #[repr(transparent)]
173 #[derive(Copy, Clone, Eq, PartialEq)]
174 pub struct Cdr(pub u32);
175 impl Cdr {
176 #[doc = "Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF\\[1:0\\]
177= 11 mode, bits 15:8 contains SLV_ADC_DR\\[7:0\\], bits 7:0 contains MST_ADC_DR\\[7:0\\]."]
178 #[inline(always)]
179 pub const fn rdata_mst(&self) -> u16 {
180 let val = (self.0 >> 0usize) & 0xffff;
181 val as u16
182 }
183 #[doc = "Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF\\[1:0\\]
184= 11 mode, bits 15:8 contains SLV_ADC_DR\\[7:0\\], bits 7:0 contains MST_ADC_DR\\[7:0\\]."]
185 #[inline(always)]
186 pub fn set_rdata_mst(&mut self, val: u16) {
187 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
188 }
189 #[doc = "Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT))."]
190 #[inline(always)]
191 pub const fn rdata_slv(&self) -> u16 {
192 let val = (self.0 >> 16usize) & 0xffff;
193 val as u16
194 }
195 #[doc = "Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT))."]
196 #[inline(always)]
197 pub fn set_rdata_slv(&mut self, val: u16) {
198 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
199 }
200 }
201 impl Default for Cdr {
202 #[inline(always)]
203 fn default() -> Cdr {
204 Cdr(0)
205 }
206 }
207 impl core::fmt::Debug for Cdr {
208 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
209 f.debug_struct("Cdr")
210 .field("rdata_mst", &self.rdata_mst())
211 .field("rdata_slv", &self.rdata_slv())
212 .finish()
213 }
214 }
215 #[cfg(feature = "defmt")]
216 impl defmt::Format for Cdr {
217 fn format(&self, f: defmt::Formatter) {
218 #[derive(defmt :: Format)]
219 struct Cdr {
220 rdata_mst: u16,
221 rdata_slv: u16,
222 }
223 let proxy = Cdr {
224 rdata_mst: self.rdata_mst(),
225 rdata_slv: self.rdata_slv(),
226 };
227 defmt::write!(f, "{}", proxy)
228 }
229 }
230 #[doc = "ADC common regular data register for 32-bit dual mode."]
231 #[repr(transparent)]
232 #[derive(Copy, Clone, Eq, PartialEq)]
233 pub struct Cdr2(pub u32);
234 impl Cdr2 {
235 #[doc = "Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)."]
236 #[inline(always)]
237 pub const fn rdata_alt(&self) -> u32 {
238 let val = (self.0 >> 0usize) & 0xffff_ffff;
239 val as u32
240 }
241 #[doc = "Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)."]
242 #[inline(always)]
243 pub fn set_rdata_alt(&mut self, val: u32) {
244 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
245 }
246 }
247 impl Default for Cdr2 {
248 #[inline(always)]
249 fn default() -> Cdr2 {
250 Cdr2(0)
251 }
252 }
253 impl core::fmt::Debug for Cdr2 {
254 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
255 f.debug_struct("Cdr2").field("rdata_alt", &self.rdata_alt()).finish()
256 }
257 }
258 #[cfg(feature = "defmt")]
259 impl defmt::Format for Cdr2 {
260 fn format(&self, f: defmt::Formatter) {
261 #[derive(defmt :: Format)]
262 struct Cdr2 {
263 rdata_alt: u32,
264 }
265 let proxy = Cdr2 {
266 rdata_alt: self.rdata_alt(),
267 };
268 defmt::write!(f, "{}", proxy)
269 }
270 }
271 #[doc = "ADC common status register."]
272 #[repr(transparent)]
273 #[derive(Copy, Clone, Eq, PartialEq)]
274 pub struct Csr(pub u32);
275 impl Csr {
276 #[doc = "Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register."]
277 #[inline(always)]
278 pub const fn adrdy_mst(&self) -> bool {
279 let val = (self.0 >> 0usize) & 0x01;
280 val != 0
281 }
282 #[doc = "Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register."]
283 #[inline(always)]
284 pub fn set_adrdy_mst(&mut self, val: bool) {
285 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
286 }
287 #[doc = "End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register."]
288 #[inline(always)]
289 pub const fn eosmp_mst(&self) -> bool {
290 let val = (self.0 >> 1usize) & 0x01;
291 val != 0
292 }
293 #[doc = "End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register."]
294 #[inline(always)]
295 pub fn set_eosmp_mst(&mut self, val: bool) {
296 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
297 }
298 #[doc = "End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register."]
299 #[inline(always)]
300 pub const fn eoc_mst(&self) -> bool {
301 let val = (self.0 >> 2usize) & 0x01;
302 val != 0
303 }
304 #[doc = "End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register."]
305 #[inline(always)]
306 pub fn set_eoc_mst(&mut self, val: bool) {
307 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
308 }
309 #[doc = "End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register."]
310 #[inline(always)]
311 pub const fn eos_mst(&self) -> bool {
312 let val = (self.0 >> 3usize) & 0x01;
313 val != 0
314 }
315 #[doc = "End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register."]
316 #[inline(always)]
317 pub fn set_eos_mst(&mut self, val: bool) {
318 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
319 }
320 #[doc = "Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register."]
321 #[inline(always)]
322 pub const fn ovr_mst(&self) -> bool {
323 let val = (self.0 >> 4usize) & 0x01;
324 val != 0
325 }
326 #[doc = "Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register."]
327 #[inline(always)]
328 pub fn set_ovr_mst(&mut self, val: bool) {
329 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
330 }
331 #[doc = "End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register."]
332 #[inline(always)]
333 pub const fn jeoc_mst(&self) -> bool {
334 let val = (self.0 >> 5usize) & 0x01;
335 val != 0
336 }
337 #[doc = "End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register."]
338 #[inline(always)]
339 pub fn set_jeoc_mst(&mut self, val: bool) {
340 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
341 }
342 #[doc = "End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register."]
343 #[inline(always)]
344 pub const fn jeos_mst(&self) -> bool {
345 let val = (self.0 >> 6usize) & 0x01;
346 val != 0
347 }
348 #[doc = "End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register."]
349 #[inline(always)]
350 pub fn set_jeos_mst(&mut self, val: bool) {
351 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
352 }
353 #[doc = "Analog watchdog flags of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register."]
354 #[inline(always)]
355 pub const fn awd_mst(&self, n: usize) -> bool {
356 assert!(n < 3usize);
357 let offs = 7usize + n * 1usize;
358 let val = (self.0 >> offs) & 0x01;
359 val != 0
360 }
361 #[doc = "Analog watchdog flags of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register."]
362 #[inline(always)]
363 pub fn set_awd_mst(&mut self, n: usize, val: bool) {
364 assert!(n < 3usize);
365 let offs = 7usize + n * 1usize;
366 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
367 }
368 #[doc = "ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register."]
369 #[inline(always)]
370 pub const fn ldordy_mst(&self) -> bool {
371 let val = (self.0 >> 12usize) & 0x01;
372 val != 0
373 }
374 #[doc = "ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register."]
375 #[inline(always)]
376 pub fn set_ldordy_mst(&mut self, val: bool) {
377 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
378 }
379 #[doc = "Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register."]
380 #[inline(always)]
381 pub const fn adrdy_slv(&self) -> bool {
382 let val = (self.0 >> 16usize) & 0x01;
383 val != 0
384 }
385 #[doc = "Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register."]
386 #[inline(always)]
387 pub fn set_adrdy_slv(&mut self, val: bool) {
388 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
389 }
390 #[doc = "End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register."]
391 #[inline(always)]
392 pub const fn eosmp_slv(&self) -> bool {
393 let val = (self.0 >> 17usize) & 0x01;
394 val != 0
395 }
396 #[doc = "End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register."]
397 #[inline(always)]
398 pub fn set_eosmp_slv(&mut self, val: bool) {
399 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
400 }
401 #[doc = "End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register."]
402 #[inline(always)]
403 pub const fn eoc_slv(&self) -> bool {
404 let val = (self.0 >> 18usize) & 0x01;
405 val != 0
406 }
407 #[doc = "End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register."]
408 #[inline(always)]
409 pub fn set_eoc_slv(&mut self, val: bool) {
410 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
411 }
412 #[doc = "End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register."]
413 #[inline(always)]
414 pub const fn eos_slv(&self) -> bool {
415 let val = (self.0 >> 19usize) & 0x01;
416 val != 0
417 }
418 #[doc = "End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register."]
419 #[inline(always)]
420 pub fn set_eos_slv(&mut self, val: bool) {
421 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
422 }
423 #[doc = "Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register."]
424 #[inline(always)]
425 pub const fn ovr_slv(&self) -> bool {
426 let val = (self.0 >> 20usize) & 0x01;
427 val != 0
428 }
429 #[doc = "Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register."]
430 #[inline(always)]
431 pub fn set_ovr_slv(&mut self, val: bool) {
432 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
433 }
434 #[doc = "End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register."]
435 #[inline(always)]
436 pub const fn jeoc_slv(&self) -> bool {
437 let val = (self.0 >> 21usize) & 0x01;
438 val != 0
439 }
440 #[doc = "End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register."]
441 #[inline(always)]
442 pub fn set_jeoc_slv(&mut self, val: bool) {
443 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
444 }
445 #[doc = "End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register."]
446 #[inline(always)]
447 pub const fn jeos_slv(&self) -> bool {
448 let val = (self.0 >> 22usize) & 0x01;
449 val != 0
450 }
451 #[doc = "End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register."]
452 #[inline(always)]
453 pub fn set_jeos_slv(&mut self, val: bool) {
454 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
455 }
456 #[doc = "Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register."]
457 #[inline(always)]
458 pub const fn awd1_slv(&self, n: usize) -> bool {
459 assert!(n < 3usize);
460 let offs = 23usize + n * 1usize;
461 let val = (self.0 >> offs) & 0x01;
462 val != 0
463 }
464 #[doc = "Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register."]
465 #[inline(always)]
466 pub fn set_awd1_slv(&mut self, n: usize, val: bool) {
467 assert!(n < 3usize);
468 let offs = 23usize + n * 1usize;
469 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
470 }
471 #[doc = "ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register."]
472 #[inline(always)]
473 pub const fn ldordy_slv(&self) -> bool {
474 let val = (self.0 >> 28usize) & 0x01;
475 val != 0
476 }
477 #[doc = "ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register."]
478 #[inline(always)]
479 pub fn set_ldordy_slv(&mut self, val: bool) {
480 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
481 }
482 }
483 impl Default for Csr {
484 #[inline(always)]
485 fn default() -> Csr {
486 Csr(0)
487 }
488 }
489 impl core::fmt::Debug for Csr {
490 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
491 f.debug_struct("Csr")
492 .field("adrdy_mst", &self.adrdy_mst())
493 .field("eosmp_mst", &self.eosmp_mst())
494 .field("eoc_mst", &self.eoc_mst())
495 .field("eos_mst", &self.eos_mst())
496 .field("ovr_mst", &self.ovr_mst())
497 .field("jeoc_mst", &self.jeoc_mst())
498 .field("jeos_mst", &self.jeos_mst())
499 .field(
500 "awd_mst",
501 &[self.awd_mst(0usize), self.awd_mst(1usize), self.awd_mst(2usize)],
502 )
503 .field("ldordy_mst", &self.ldordy_mst())
504 .field("adrdy_slv", &self.adrdy_slv())
505 .field("eosmp_slv", &self.eosmp_slv())
506 .field("eoc_slv", &self.eoc_slv())
507 .field("eos_slv", &self.eos_slv())
508 .field("ovr_slv", &self.ovr_slv())
509 .field("jeoc_slv", &self.jeoc_slv())
510 .field("jeos_slv", &self.jeos_slv())
511 .field(
512 "awd1_slv",
513 &[self.awd1_slv(0usize), self.awd1_slv(1usize), self.awd1_slv(2usize)],
514 )
515 .field("ldordy_slv", &self.ldordy_slv())
516 .finish()
517 }
518 }
519 #[cfg(feature = "defmt")]
520 impl defmt::Format for Csr {
521 fn format(&self, f: defmt::Formatter) {
522 #[derive(defmt :: Format)]
523 struct Csr {
524 adrdy_mst: bool,
525 eosmp_mst: bool,
526 eoc_mst: bool,
527 eos_mst: bool,
528 ovr_mst: bool,
529 jeoc_mst: bool,
530 jeos_mst: bool,
531 awd_mst: [bool; 3usize],
532 ldordy_mst: bool,
533 adrdy_slv: bool,
534 eosmp_slv: bool,
535 eoc_slv: bool,
536 eos_slv: bool,
537 ovr_slv: bool,
538 jeoc_slv: bool,
539 jeos_slv: bool,
540 awd1_slv: [bool; 3usize],
541 ldordy_slv: bool,
542 }
543 let proxy = Csr {
544 adrdy_mst: self.adrdy_mst(),
545 eosmp_mst: self.eosmp_mst(),
546 eoc_mst: self.eoc_mst(),
547 eos_mst: self.eos_mst(),
548 ovr_mst: self.ovr_mst(),
549 jeoc_mst: self.jeoc_mst(),
550 jeos_mst: self.jeos_mst(),
551 awd_mst: [self.awd_mst(0usize), self.awd_mst(1usize), self.awd_mst(2usize)],
552 ldordy_mst: self.ldordy_mst(),
553 adrdy_slv: self.adrdy_slv(),
554 eosmp_slv: self.eosmp_slv(),
555 eoc_slv: self.eoc_slv(),
556 eos_slv: self.eos_slv(),
557 ovr_slv: self.ovr_slv(),
558 jeoc_slv: self.jeoc_slv(),
559 jeos_slv: self.jeos_slv(),
560 awd1_slv: [self.awd1_slv(0usize), self.awd1_slv(1usize), self.awd1_slv(2usize)],
561 ldordy_slv: self.ldordy_slv(),
562 };
563 defmt::write!(f, "{}", proxy)
564 }
565 }
566}
567pub mod vals {
568 #[repr(u8)]
569 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
570 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
571 pub enum Damdf {
572 #[doc = "Without data packing, CDR/CDR2 not used"]
573 NO_PACK = 0x0,
574 _RESERVED_1 = 0x01,
575 #[doc = "CDR formatted for 32-bit down to 10-bit resolution"]
576 FORMAT32TO10 = 0x02,
577 #[doc = "CDR formatted for 8-bit resolution"]
578 FORMAT8 = 0x03,
579 }
580 impl Damdf {
581 #[inline(always)]
582 pub const fn from_bits(val: u8) -> Damdf {
583 unsafe { core::mem::transmute(val & 0x03) }
584 }
585 #[inline(always)]
586 pub const fn to_bits(self) -> u8 {
587 unsafe { core::mem::transmute(self) }
588 }
589 }
590 impl From<u8> for Damdf {
591 #[inline(always)]
592 fn from(val: u8) -> Damdf {
593 Damdf::from_bits(val)
594 }
595 }
596 impl From<Damdf> for u8 {
597 #[inline(always)]
598 fn from(val: Damdf) -> u8 {
599 Damdf::to_bits(val)
600 }
601 }
602 #[repr(u8)]
603 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
604 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
605 pub enum Dual {
606 #[doc = "Independent mode"]
607 INDEPENDENT = 0x0,
608 #[doc = "Dual, combined regular simultaneous + injected simultaneous mode"]
609 DUAL_RJ = 0x01,
610 #[doc = "Dual, combined regular simultaneous + alternate trigger mode"]
611 DUAL_RA = 0x02,
612 #[doc = "Dual, combined interleaved mode + injected simultaneous mode"]
613 DUAL_IJ = 0x03,
614 _RESERVED_4 = 0x04,
615 #[doc = "Dual, injected simultaneous mode only"]
616 DUAL_J = 0x05,
617 #[doc = "Dual, regular simultaneous mode only"]
618 DUAL_R = 0x06,
619 #[doc = "Dual, interleaved mode only"]
620 DUAL_I = 0x07,
621 _RESERVED_8 = 0x08,
622 #[doc = "Dual, alternate trigger mode only"]
623 DUAL_A = 0x09,
624 _RESERVED_a = 0x0a,
625 _RESERVED_b = 0x0b,
626 _RESERVED_c = 0x0c,
627 _RESERVED_d = 0x0d,
628 _RESERVED_e = 0x0e,
629 _RESERVED_f = 0x0f,
630 _RESERVED_10 = 0x10,
631 _RESERVED_11 = 0x11,
632 _RESERVED_12 = 0x12,
633 _RESERVED_13 = 0x13,
634 _RESERVED_14 = 0x14,
635 _RESERVED_15 = 0x15,
636 _RESERVED_16 = 0x16,
637 _RESERVED_17 = 0x17,
638 _RESERVED_18 = 0x18,
639 _RESERVED_19 = 0x19,
640 _RESERVED_1a = 0x1a,
641 _RESERVED_1b = 0x1b,
642 _RESERVED_1c = 0x1c,
643 _RESERVED_1d = 0x1d,
644 _RESERVED_1e = 0x1e,
645 _RESERVED_1f = 0x1f,
646 }
647 impl Dual {
648 #[inline(always)]
649 pub const fn from_bits(val: u8) -> Dual {
650 unsafe { core::mem::transmute(val & 0x1f) }
651 }
652 #[inline(always)]
653 pub const fn to_bits(self) -> u8 {
654 unsafe { core::mem::transmute(self) }
655 }
656 }
657 impl From<u8> for Dual {
658 #[inline(always)]
659 fn from(val: u8) -> Dual {
660 Dual::from_bits(val)
661 }
662 }
663 impl From<Dual> for u8 {
664 #[inline(always)]
665 fn from(val: Dual) -> u8 {
666 Dual::to_bits(val)
667 }
668 }
669 #[repr(u8)]
670 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
671 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
672 pub enum Presc {
673 #[doc = "adc_ker_ck_input not divided"]
674 DIV1 = 0x0,
675 #[doc = "adc_ker_ck_input divided by 2"]
676 DIV2 = 0x01,
677 #[doc = "adc_ker_ck_input divided by 4"]
678 DIV4 = 0x02,
679 #[doc = "adc_ker_ck_input divided by 6"]
680 DIV6 = 0x03,
681 #[doc = "adc_ker_ck_input divided by 8"]
682 DIV8 = 0x04,
683 #[doc = "adc_ker_ck_input divided by 10"]
684 DIV10 = 0x05,
685 #[doc = "adc_ker_ck_input divided by 12"]
686 DIV12 = 0x06,
687 #[doc = "adc_ker_ck_input divided by 16"]
688 DIV16 = 0x07,
689 #[doc = "adc_ker_ck_input divided by 32"]
690 DIV32 = 0x08,
691 #[doc = "adc_ker_ck_input divided by 64"]
692 DIV64 = 0x09,
693 #[doc = "adc_ker_ck_input divided by 128"]
694 DIV128 = 0x0a,
695 #[doc = "adc_ker_ck_input divided by 256"]
696 DIV256 = 0x0b,
697 _RESERVED_c = 0x0c,
698 _RESERVED_d = 0x0d,
699 _RESERVED_e = 0x0e,
700 _RESERVED_f = 0x0f,
701 }
702 impl Presc {
703 #[inline(always)]
704 pub const fn from_bits(val: u8) -> Presc {
705 unsafe { core::mem::transmute(val & 0x0f) }
706 }
707 #[inline(always)]
708 pub const fn to_bits(self) -> u8 {
709 unsafe { core::mem::transmute(self) }
710 }
711 }
712 impl From<u8> for Presc {
713 #[inline(always)]
714 fn from(val: u8) -> Presc {
715 Presc::from_bits(val)
716 }
717 }
718 impl From<Presc> for u8 {
719 #[inline(always)]
720 fn from(val: Presc) -> u8 {
721 Presc::to_bits(val)
722 }
723 }
724}
725