1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "ADF."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Adf {
9 ptr: *mut u8,
10}
11unsafe impl Send for Adf {}
12unsafe impl Sync for Adf {}
13impl Adf {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "ADF Global Control Register."]
23 #[inline(always)]
24 pub const fn gcr(self) -> crate::common::Reg<regs::Gcr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "ADF clock generator control register."]
28 #[inline(always)]
29 pub const fn ckgcr(self) -> crate::common::Reg<regs::Ckgcr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "ADF serial interface control register 0."]
33 #[inline(always)]
34 pub const fn sitfcr(self) -> crate::common::Reg<regs::Sitfcr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
36 }
37 #[doc = "ADF bitstream matrix control register 0."]
38 #[inline(always)]
39 pub const fn bsmxcr(self) -> crate::common::Reg<regs::Bsmxcr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
41 }
42 #[doc = "ADF digital filter control register 0."]
43 #[inline(always)]
44 pub const fn dfltcr(self) -> crate::common::Reg<regs::Dfltcr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
46 }
47 #[doc = "ADF digital filer configuration register 0."]
48 #[inline(always)]
49 pub const fn dfltcicr(self) -> crate::common::Reg<regs::Dfltcicr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) }
51 }
52 #[doc = "ADF reshape filter configuration register 0."]
53 #[inline(always)]
54 pub const fn dfltrsfr(self) -> crate::common::Reg<regs::Dfltrsfr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
56 }
57 #[doc = "ADF delay control register 0."]
58 #[inline(always)]
59 pub const fn dlycr(self) -> crate::common::Reg<regs::Dlycr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
61 }
62 #[doc = "ADF DFLT0 interrupt enable register."]
63 #[inline(always)]
64 pub const fn dfltier(self) -> crate::common::Reg<regs::Dfltier, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) }
66 }
67 #[doc = "ADF DFLT0 interrupt status register 0."]
68 #[inline(always)]
69 pub const fn dfltisr(self) -> crate::common::Reg<regs::Dfltisr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) }
71 }
72 #[doc = "ADF SAD control register."]
73 #[inline(always)]
74 pub const fn sadcr(self) -> crate::common::Reg<regs::Sadcr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) }
76 }
77 #[doc = "ADF SAD configuration register."]
78 #[inline(always)]
79 pub const fn sadcfgr(self) -> crate::common::Reg<regs::Sadcfgr, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) }
81 }
82 #[doc = "ADF SAD sound level register."]
83 #[inline(always)]
84 pub const fn sadsdlvr(self) -> crate::common::Reg<regs::Sadsdlvr, crate::common::R> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
86 }
87 #[doc = "ADF SAD ambient noise level register."]
88 #[inline(always)]
89 pub const fn sadanlvr(self) -> crate::common::Reg<regs::Sadanlvr, crate::common::R> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
91 }
92 #[doc = "ADF digital filter data register 0."]
93 #[inline(always)]
94 pub const fn dfltdr(self) -> crate::common::Reg<regs::Dfltdr, crate::common::R> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) }
96 }
97}
98pub mod regs {
99 #[doc = "ADF bitstream matrix control register 0."]
100 #[repr(transparent)]
101 #[derive(Copy, Clone, Eq, PartialEq)]
102 pub struct Bsmxcr(pub u32);
103 impl Bsmxcr {
104 #[doc = "Bitstream selection."]
105 #[inline(always)]
106 pub const fn bssel(&self) -> super::vals::Bssel {
107 let val = (self.0 >> 0usize) & 0x1f;
108 super::vals::Bssel::from_bits(val as u8)
109 }
110 #[doc = "Bitstream selection."]
111 #[inline(always)]
112 pub fn set_bssel(&mut self, val: super::vals::Bssel) {
113 self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize);
114 }
115 #[doc = "BSMX active flag. This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL\\[4:0\\]
116can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled."]
117 #[inline(always)]
118 pub const fn bsmxactive(&self) -> bool {
119 let val = (self.0 >> 31usize) & 0x01;
120 val != 0
121 }
122 #[doc = "BSMX active flag. This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL\\[4:0\\]
123can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled."]
124 #[inline(always)]
125 pub fn set_bsmxactive(&mut self, val: bool) {
126 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
127 }
128 }
129 impl Default for Bsmxcr {
130 #[inline(always)]
131 fn default() -> Bsmxcr {
132 Bsmxcr(0)
133 }
134 }
135 impl core::fmt::Debug for Bsmxcr {
136 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
137 f.debug_struct("Bsmxcr")
138 .field("bssel", &self.bssel())
139 .field("bsmxactive", &self.bsmxactive())
140 .finish()
141 }
142 }
143 #[cfg(feature = "defmt")]
144 impl defmt::Format for Bsmxcr {
145 fn format(&self, f: defmt::Formatter) {
146 #[derive(defmt :: Format)]
147 struct Bsmxcr {
148 bssel: super::vals::Bssel,
149 bsmxactive: bool,
150 }
151 let proxy = Bsmxcr {
152 bssel: self.bssel(),
153 bsmxactive: self.bsmxactive(),
154 };
155 defmt::write!(f, "{}", proxy)
156 }
157 }
158 #[doc = "ADF clock generator control register."]
159 #[repr(transparent)]
160 #[derive(Copy, Clone, Eq, PartialEq)]
161 pub struct Ckgcr(pub u32);
162 impl Ckgcr {
163 #[doc = "Clock generator dividers enable."]
164 #[inline(always)]
165 pub const fn ckgden(&self) -> bool {
166 let val = (self.0 >> 0usize) & 0x01;
167 val != 0
168 }
169 #[doc = "Clock generator dividers enable."]
170 #[inline(always)]
171 pub fn set_ckgden(&mut self, val: bool) {
172 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
173 }
174 #[doc = "CCK0 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin."]
175 #[inline(always)]
176 pub const fn cck0en(&self) -> super::vals::Ccken {
177 let val = (self.0 >> 1usize) & 0x01;
178 super::vals::Ccken::from_bits(val as u8)
179 }
180 #[doc = "CCK0 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin."]
181 #[inline(always)]
182 pub fn set_cck0en(&mut self, val: super::vals::Ccken) {
183 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
184 }
185 #[doc = "CCK1 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin."]
186 #[inline(always)]
187 pub const fn cck1en(&self) -> super::vals::Ccken {
188 let val = (self.0 >> 2usize) & 0x01;
189 super::vals::Ccken::from_bits(val as u8)
190 }
191 #[doc = "CCK1 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin."]
192 #[inline(always)]
193 pub fn set_cck1en(&mut self, val: super::vals::Ccken) {
194 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
195 }
196 #[doc = "Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1)."]
197 #[inline(always)]
198 pub const fn ckgmod(&self) -> super::vals::Ckgmod {
199 let val = (self.0 >> 4usize) & 0x01;
200 super::vals::Ckgmod::from_bits(val as u8)
201 }
202 #[doc = "Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1)."]
203 #[inline(always)]
204 pub fn set_ckgmod(&mut self, val: super::vals::Ckgmod) {
205 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
206 }
207 #[doc = "CCK0 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin."]
208 #[inline(always)]
209 pub const fn cck0dir(&self) -> super::vals::Cckdir {
210 let val = (self.0 >> 5usize) & 0x01;
211 super::vals::Cckdir::from_bits(val as u8)
212 }
213 #[doc = "CCK0 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin."]
214 #[inline(always)]
215 pub fn set_cck0dir(&mut self, val: super::vals::Cckdir) {
216 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
217 }
218 #[doc = "CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin."]
219 #[inline(always)]
220 pub const fn cck1dir(&self) -> super::vals::Cckdir {
221 let val = (self.0 >> 6usize) & 0x01;
222 super::vals::Cckdir::from_bits(val as u8)
223 }
224 #[doc = "CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin."]
225 #[inline(always)]
226 pub fn set_cck1dir(&mut self, val: super::vals::Cckdir) {
227 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
228 }
229 #[doc = "CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0."]
230 #[inline(always)]
231 pub const fn trgsens(&self) -> super::vals::Trgsens {
232 let val = (self.0 >> 8usize) & 0x01;
233 super::vals::Trgsens::from_bits(val as u8)
234 }
235 #[doc = "CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0."]
236 #[inline(always)]
237 pub fn set_trgsens(&mut self, val: super::vals::Trgsens) {
238 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
239 }
240 #[doc = "Digital filter trigger signal selection. This bit is set and cleared by software. It is used to select the trigger signal for the digital filter. This bit is not significant if the CKGMOD = 0."]
241 #[inline(always)]
242 pub const fn trgsrc(&self) -> super::vals::Trgsrc {
243 let val = (self.0 >> 12usize) & 0x0f;
244 super::vals::Trgsrc::from_bits(val as u8)
245 }
246 #[doc = "Digital filter trigger signal selection. This bit is set and cleared by software. It is used to select the trigger signal for the digital filter. This bit is not significant if the CKGMOD = 0."]
247 #[inline(always)]
248 pub fn set_trgsrc(&mut self, val: super::vals::Trgsrc) {
249 self.0 = (self.0 & !(0x0f << 12usize)) | (((val.to_bits() as u32) & 0x0f) << 12usize);
250 }
251 #[doc = "Divider to control the CCK clock."]
252 #[inline(always)]
253 pub const fn cckdiv(&self) -> super::vals::Cckdiv {
254 let val = (self.0 >> 16usize) & 0x0f;
255 super::vals::Cckdiv::from_bits(val as u8)
256 }
257 #[doc = "Divider to control the CCK clock."]
258 #[inline(always)]
259 pub fn set_cckdiv(&mut self, val: super::vals::Cckdiv) {
260 self.0 = (self.0 & !(0x0f << 16usize)) | (((val.to_bits() as u32) & 0x0f) << 16usize);
261 }
262 #[doc = "Divider to control the serial interface clock."]
263 #[inline(always)]
264 pub const fn procdiv(&self) -> u8 {
265 let val = (self.0 >> 24usize) & 0x7f;
266 val as u8
267 }
268 #[doc = "Divider to control the serial interface clock."]
269 #[inline(always)]
270 pub fn set_procdiv(&mut self, val: u8) {
271 self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
272 }
273 #[doc = "Clock generator active flag."]
274 #[inline(always)]
275 pub const fn ckgactive(&self) -> bool {
276 let val = (self.0 >> 31usize) & 0x01;
277 val != 0
278 }
279 #[doc = "Clock generator active flag."]
280 #[inline(always)]
281 pub fn set_ckgactive(&mut self, val: bool) {
282 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
283 }
284 }
285 impl Default for Ckgcr {
286 #[inline(always)]
287 fn default() -> Ckgcr {
288 Ckgcr(0)
289 }
290 }
291 impl core::fmt::Debug for Ckgcr {
292 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
293 f.debug_struct("Ckgcr")
294 .field("ckgden", &self.ckgden())
295 .field("cck0en", &self.cck0en())
296 .field("cck1en", &self.cck1en())
297 .field("ckgmod", &self.ckgmod())
298 .field("cck0dir", &self.cck0dir())
299 .field("cck1dir", &self.cck1dir())
300 .field("trgsens", &self.trgsens())
301 .field("trgsrc", &self.trgsrc())
302 .field("cckdiv", &self.cckdiv())
303 .field("procdiv", &self.procdiv())
304 .field("ckgactive", &self.ckgactive())
305 .finish()
306 }
307 }
308 #[cfg(feature = "defmt")]
309 impl defmt::Format for Ckgcr {
310 fn format(&self, f: defmt::Formatter) {
311 #[derive(defmt :: Format)]
312 struct Ckgcr {
313 ckgden: bool,
314 cck0en: super::vals::Ccken,
315 cck1en: super::vals::Ccken,
316 ckgmod: super::vals::Ckgmod,
317 cck0dir: super::vals::Cckdir,
318 cck1dir: super::vals::Cckdir,
319 trgsens: super::vals::Trgsens,
320 trgsrc: super::vals::Trgsrc,
321 cckdiv: super::vals::Cckdiv,
322 procdiv: u8,
323 ckgactive: bool,
324 }
325 let proxy = Ckgcr {
326 ckgden: self.ckgden(),
327 cck0en: self.cck0en(),
328 cck1en: self.cck1en(),
329 ckgmod: self.ckgmod(),
330 cck0dir: self.cck0dir(),
331 cck1dir: self.cck1dir(),
332 trgsens: self.trgsens(),
333 trgsrc: self.trgsrc(),
334 cckdiv: self.cckdiv(),
335 procdiv: self.procdiv(),
336 ckgactive: self.ckgactive(),
337 };
338 defmt::write!(f, "{}", proxy)
339 }
340 }
341 #[doc = "ADF digital filer configuration register 0."]
342 #[repr(transparent)]
343 #[derive(Copy, Clone, Eq, PartialEq)]
344 pub struct Dfltcicr(pub u32);
345 impl Dfltcicr {
346 #[doc = "Source data for the digital filter."]
347 #[inline(always)]
348 pub const fn datsrc(&self) -> super::vals::Datsrc {
349 let val = (self.0 >> 0usize) & 0x03;
350 super::vals::Datsrc::from_bits(val as u8)
351 }
352 #[doc = "Source data for the digital filter."]
353 #[inline(always)]
354 pub fn set_datsrc(&mut self, val: super::vals::Datsrc) {
355 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
356 }
357 #[doc = "Select the CIC order."]
358 #[inline(always)]
359 pub const fn cicmod(&self) -> super::vals::Cicmod {
360 let val = (self.0 >> 4usize) & 0x07;
361 super::vals::Cicmod::from_bits(val as u8)
362 }
363 #[doc = "Select the CIC order."]
364 #[inline(always)]
365 pub fn set_cicmod(&mut self, val: super::vals::Cicmod) {
366 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
367 }
368 #[doc = "CIC decimation ratio selection. This bitfield is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1)."]
369 #[inline(always)]
370 pub const fn mcicd(&self) -> u16 {
371 let val = (self.0 >> 8usize) & 0x01ff;
372 val as u16
373 }
374 #[doc = "CIC decimation ratio selection. This bitfield is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1)."]
375 #[inline(always)]
376 pub fn set_mcicd(&mut self, val: u16) {
377 self.0 = (self.0 & !(0x01ff << 8usize)) | (((val as u32) & 0x01ff) << 8usize);
378 }
379 #[doc = "Scaling factor selection. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value."]
380 #[inline(always)]
381 pub const fn scale(&self) -> u8 {
382 let val = (self.0 >> 20usize) & 0x3f;
383 val as u8
384 }
385 #[doc = "Scaling factor selection. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value."]
386 #[inline(always)]
387 pub fn set_scale(&mut self, val: u8) {
388 self.0 = (self.0 & !(0x3f << 20usize)) | (((val as u32) & 0x3f) << 20usize);
389 }
390 }
391 impl Default for Dfltcicr {
392 #[inline(always)]
393 fn default() -> Dfltcicr {
394 Dfltcicr(0)
395 }
396 }
397 impl core::fmt::Debug for Dfltcicr {
398 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
399 f.debug_struct("Dfltcicr")
400 .field("datsrc", &self.datsrc())
401 .field("cicmod", &self.cicmod())
402 .field("mcicd", &self.mcicd())
403 .field("scale", &self.scale())
404 .finish()
405 }
406 }
407 #[cfg(feature = "defmt")]
408 impl defmt::Format for Dfltcicr {
409 fn format(&self, f: defmt::Formatter) {
410 #[derive(defmt :: Format)]
411 struct Dfltcicr {
412 datsrc: super::vals::Datsrc,
413 cicmod: super::vals::Cicmod,
414 mcicd: u16,
415 scale: u8,
416 }
417 let proxy = Dfltcicr {
418 datsrc: self.datsrc(),
419 cicmod: self.cicmod(),
420 mcicd: self.mcicd(),
421 scale: self.scale(),
422 };
423 defmt::write!(f, "{}", proxy)
424 }
425 }
426 #[doc = "ADF digital filter control register 0."]
427 #[repr(transparent)]
428 #[derive(Copy, Clone, Eq, PartialEq)]
429 pub struct Dfltcr(pub u32);
430 impl Dfltcr {
431 #[doc = "DFLT enable. This bit is set and reset by software. It is used to enable the digital filter."]
432 #[inline(always)]
433 pub const fn dflten(&self) -> bool {
434 let val = (self.0 >> 0usize) & 0x01;
435 val != 0
436 }
437 #[doc = "DFLT enable. This bit is set and reset by software. It is used to enable the digital filter."]
438 #[inline(always)]
439 pub fn set_dflten(&mut self, val: bool) {
440 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
441 }
442 #[doc = "DMA requests enable. This bit is set and reset by software. It is used to control the generation of DMA request to transfer the processed samples into the memory."]
443 #[inline(always)]
444 pub const fn dmaen(&self) -> bool {
445 let val = (self.0 >> 1usize) & 0x01;
446 val != 0
447 }
448 #[doc = "DMA requests enable. This bit is set and reset by software. It is used to control the generation of DMA request to transfer the processed samples into the memory."]
449 #[inline(always)]
450 pub fn set_dmaen(&mut self, val: bool) {
451 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
452 }
453 #[doc = "RXFIFO threshold selection."]
454 #[inline(always)]
455 pub const fn fth(&self) -> super::vals::Rxfifo {
456 let val = (self.0 >> 2usize) & 0x01;
457 super::vals::Rxfifo::from_bits(val as u8)
458 }
459 #[doc = "RXFIFO threshold selection."]
460 #[inline(always)]
461 pub fn set_fth(&mut self, val: super::vals::Rxfifo) {
462 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
463 }
464 #[doc = "DFLT trigger mode."]
465 #[inline(always)]
466 pub const fn acqmod(&self) -> super::vals::Acqmod {
467 let val = (self.0 >> 4usize) & 0x07;
468 super::vals::Acqmod::from_bits(val as u8)
469 }
470 #[doc = "DFLT trigger mode."]
471 #[inline(always)]
472 pub fn set_acqmod(&mut self, val: super::vals::Acqmod) {
473 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
474 }
475 #[doc = "DFLT trigger signal selection."]
476 #[inline(always)]
477 pub const fn trgsrc(&self) -> u8 {
478 let val = (self.0 >> 12usize) & 0x0f;
479 val as u8
480 }
481 #[doc = "DFLT trigger signal selection."]
482 #[inline(always)]
483 pub fn set_trgsrc(&mut self, val: u8) {
484 self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
485 }
486 #[doc = "Number of samples to be discarded."]
487 #[inline(always)]
488 pub const fn nbdis(&self) -> u8 {
489 let val = (self.0 >> 20usize) & 0xff;
490 val as u8
491 }
492 #[doc = "Number of samples to be discarded."]
493 #[inline(always)]
494 pub fn set_nbdis(&mut self, val: u8) {
495 self.0 = (self.0 & !(0xff << 20usize)) | (((val as u32) & 0xff) << 20usize);
496 }
497 #[doc = "DFLT run status flag."]
498 #[inline(always)]
499 pub const fn dfltrun(&self) -> bool {
500 let val = (self.0 >> 30usize) & 0x01;
501 val != 0
502 }
503 #[doc = "DFLT run status flag."]
504 #[inline(always)]
505 pub fn set_dfltrun(&mut self, val: bool) {
506 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
507 }
508 #[doc = "DFLT active flag."]
509 #[inline(always)]
510 pub const fn dfltactive(&self) -> bool {
511 let val = (self.0 >> 31usize) & 0x01;
512 val != 0
513 }
514 #[doc = "DFLT active flag."]
515 #[inline(always)]
516 pub fn set_dfltactive(&mut self, val: bool) {
517 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
518 }
519 }
520 impl Default for Dfltcr {
521 #[inline(always)]
522 fn default() -> Dfltcr {
523 Dfltcr(0)
524 }
525 }
526 impl core::fmt::Debug for Dfltcr {
527 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
528 f.debug_struct("Dfltcr")
529 .field("dflten", &self.dflten())
530 .field("dmaen", &self.dmaen())
531 .field("fth", &self.fth())
532 .field("acqmod", &self.acqmod())
533 .field("trgsrc", &self.trgsrc())
534 .field("nbdis", &self.nbdis())
535 .field("dfltrun", &self.dfltrun())
536 .field("dfltactive", &self.dfltactive())
537 .finish()
538 }
539 }
540 #[cfg(feature = "defmt")]
541 impl defmt::Format for Dfltcr {
542 fn format(&self, f: defmt::Formatter) {
543 #[derive(defmt :: Format)]
544 struct Dfltcr {
545 dflten: bool,
546 dmaen: bool,
547 fth: super::vals::Rxfifo,
548 acqmod: super::vals::Acqmod,
549 trgsrc: u8,
550 nbdis: u8,
551 dfltrun: bool,
552 dfltactive: bool,
553 }
554 let proxy = Dfltcr {
555 dflten: self.dflten(),
556 dmaen: self.dmaen(),
557 fth: self.fth(),
558 acqmod: self.acqmod(),
559 trgsrc: self.trgsrc(),
560 nbdis: self.nbdis(),
561 dfltrun: self.dfltrun(),
562 dfltactive: self.dfltactive(),
563 };
564 defmt::write!(f, "{}", proxy)
565 }
566 }
567 #[doc = "ADF digital filter data register 0."]
568 #[repr(transparent)]
569 #[derive(Copy, Clone, Eq, PartialEq)]
570 pub struct Dfltdr(pub u32);
571 impl Dfltdr {
572 #[doc = "DR. Data processed by DFT"]
573 #[inline(always)]
574 pub const fn dr(&self) -> u32 {
575 let val = (self.0 >> 8usize) & 0x00ff_ffff;
576 val as u32
577 }
578 #[doc = "DR. Data processed by DFT"]
579 #[inline(always)]
580 pub fn set_dr(&mut self, val: u32) {
581 self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
582 }
583 }
584 impl Default for Dfltdr {
585 #[inline(always)]
586 fn default() -> Dfltdr {
587 Dfltdr(0)
588 }
589 }
590 impl core::fmt::Debug for Dfltdr {
591 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
592 f.debug_struct("Dfltdr").field("dr", &self.dr()).finish()
593 }
594 }
595 #[cfg(feature = "defmt")]
596 impl defmt::Format for Dfltdr {
597 fn format(&self, f: defmt::Formatter) {
598 #[derive(defmt :: Format)]
599 struct Dfltdr {
600 dr: u32,
601 }
602 let proxy = Dfltdr { dr: self.dr() };
603 defmt::write!(f, "{}", proxy)
604 }
605 }
606 #[doc = "ADF DFLT interrupt enable register."]
607 #[repr(transparent)]
608 #[derive(Copy, Clone, Eq, PartialEq)]
609 pub struct Dfltier(pub u32);
610 impl Dfltier {
611 #[doc = "RXFIFO threshold interrupt enable."]
612 #[inline(always)]
613 pub const fn fthie(&self) -> bool {
614 let val = (self.0 >> 0usize) & 0x01;
615 val != 0
616 }
617 #[doc = "RXFIFO threshold interrupt enable."]
618 #[inline(always)]
619 pub fn set_fthie(&mut self, val: bool) {
620 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
621 }
622 #[doc = "Data overflow interrupt enable."]
623 #[inline(always)]
624 pub const fn dovrie(&self) -> bool {
625 let val = (self.0 >> 1usize) & 0x01;
626 val != 0
627 }
628 #[doc = "Data overflow interrupt enable."]
629 #[inline(always)]
630 pub fn set_dovrie(&mut self, val: bool) {
631 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
632 }
633 #[doc = "Saturation detection interrupt enable."]
634 #[inline(always)]
635 pub const fn satie(&self) -> bool {
636 let val = (self.0 >> 9usize) & 0x01;
637 val != 0
638 }
639 #[doc = "Saturation detection interrupt enable."]
640 #[inline(always)]
641 pub fn set_satie(&mut self, val: bool) {
642 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
643 }
644 #[doc = "Clock absence detection interrupt enable."]
645 #[inline(always)]
646 pub const fn ckabie(&self) -> bool {
647 let val = (self.0 >> 10usize) & 0x01;
648 val != 0
649 }
650 #[doc = "Clock absence detection interrupt enable."]
651 #[inline(always)]
652 pub fn set_ckabie(&mut self, val: bool) {
653 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
654 }
655 #[doc = "Reshape filter overrun interrupt enable."]
656 #[inline(always)]
657 pub const fn rfovrie(&self) -> bool {
658 let val = (self.0 >> 11usize) & 0x01;
659 val != 0
660 }
661 #[doc = "Reshape filter overrun interrupt enable."]
662 #[inline(always)]
663 pub fn set_rfovrie(&mut self, val: bool) {
664 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
665 }
666 #[doc = "Sound activity detection interrupt enable."]
667 #[inline(always)]
668 pub const fn sddetie(&self) -> bool {
669 let val = (self.0 >> 12usize) & 0x01;
670 val != 0
671 }
672 #[doc = "Sound activity detection interrupt enable."]
673 #[inline(always)]
674 pub fn set_sddetie(&mut self, val: bool) {
675 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
676 }
677 #[doc = "SAD sound-level value ready enable."]
678 #[inline(always)]
679 pub const fn sdlvlie(&self) -> bool {
680 let val = (self.0 >> 13usize) & 0x01;
681 val != 0
682 }
683 #[doc = "SAD sound-level value ready enable."]
684 #[inline(always)]
685 pub fn set_sdlvlie(&mut self, val: bool) {
686 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
687 }
688 }
689 impl Default for Dfltier {
690 #[inline(always)]
691 fn default() -> Dfltier {
692 Dfltier(0)
693 }
694 }
695 impl core::fmt::Debug for Dfltier {
696 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
697 f.debug_struct("Dfltier")
698 .field("fthie", &self.fthie())
699 .field("dovrie", &self.dovrie())
700 .field("satie", &self.satie())
701 .field("ckabie", &self.ckabie())
702 .field("rfovrie", &self.rfovrie())
703 .field("sddetie", &self.sddetie())
704 .field("sdlvlie", &self.sdlvlie())
705 .finish()
706 }
707 }
708 #[cfg(feature = "defmt")]
709 impl defmt::Format for Dfltier {
710 fn format(&self, f: defmt::Formatter) {
711 #[derive(defmt :: Format)]
712 struct Dfltier {
713 fthie: bool,
714 dovrie: bool,
715 satie: bool,
716 ckabie: bool,
717 rfovrie: bool,
718 sddetie: bool,
719 sdlvlie: bool,
720 }
721 let proxy = Dfltier {
722 fthie: self.fthie(),
723 dovrie: self.dovrie(),
724 satie: self.satie(),
725 ckabie: self.ckabie(),
726 rfovrie: self.rfovrie(),
727 sddetie: self.sddetie(),
728 sdlvlie: self.sdlvlie(),
729 };
730 defmt::write!(f, "{}", proxy)
731 }
732 }
733 #[doc = "ADF DFLT interrupt status register 0."]
734 #[repr(transparent)]
735 #[derive(Copy, Clone, Eq, PartialEq)]
736 pub struct Dfltisr(pub u32);
737 impl Dfltisr {
738 #[doc = "RXFIFO threshold flag."]
739 #[inline(always)]
740 pub const fn fthf(&self) -> bool {
741 let val = (self.0 >> 0usize) & 0x01;
742 val != 0
743 }
744 #[doc = "RXFIFO threshold flag."]
745 #[inline(always)]
746 pub fn set_fthf(&mut self, val: bool) {
747 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
748 }
749 #[doc = "Data overflow flag."]
750 #[inline(always)]
751 pub const fn dovrf(&self) -> bool {
752 let val = (self.0 >> 1usize) & 0x01;
753 val != 0
754 }
755 #[doc = "Data overflow flag."]
756 #[inline(always)]
757 pub fn set_dovrf(&mut self, val: bool) {
758 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
759 }
760 #[doc = "RXFIFO not empty flag."]
761 #[inline(always)]
762 pub const fn rxnef(&self) -> bool {
763 let val = (self.0 >> 3usize) & 0x01;
764 val != 0
765 }
766 #[doc = "RXFIFO not empty flag."]
767 #[inline(always)]
768 pub fn set_rxnef(&mut self, val: bool) {
769 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
770 }
771 #[doc = "Saturation detection flag."]
772 #[inline(always)]
773 pub const fn satf(&self) -> bool {
774 let val = (self.0 >> 9usize) & 0x01;
775 val != 0
776 }
777 #[doc = "Saturation detection flag."]
778 #[inline(always)]
779 pub fn set_satf(&mut self, val: bool) {
780 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
781 }
782 #[doc = "Clock absence detection flag."]
783 #[inline(always)]
784 pub const fn ckabf(&self) -> bool {
785 let val = (self.0 >> 10usize) & 0x01;
786 val != 0
787 }
788 #[doc = "Clock absence detection flag."]
789 #[inline(always)]
790 pub fn set_ckabf(&mut self, val: bool) {
791 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
792 }
793 #[doc = "Reshape filter overrun detection flag."]
794 #[inline(always)]
795 pub const fn rfovrf(&self) -> bool {
796 let val = (self.0 >> 11usize) & 0x01;
797 val != 0
798 }
799 #[doc = "Reshape filter overrun detection flag."]
800 #[inline(always)]
801 pub fn set_rfovrf(&mut self, val: bool) {
802 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
803 }
804 #[doc = "Sound activity detection flag."]
805 #[inline(always)]
806 pub const fn sddetf(&self) -> bool {
807 let val = (self.0 >> 12usize) & 0x01;
808 val != 0
809 }
810 #[doc = "Sound activity detection flag."]
811 #[inline(always)]
812 pub fn set_sddetf(&mut self, val: bool) {
813 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
814 }
815 #[doc = "Sound level value ready flag."]
816 #[inline(always)]
817 pub const fn sdlvlf(&self) -> bool {
818 let val = (self.0 >> 13usize) & 0x01;
819 val != 0
820 }
821 #[doc = "Sound level value ready flag."]
822 #[inline(always)]
823 pub fn set_sdlvlf(&mut self, val: bool) {
824 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
825 }
826 }
827 impl Default for Dfltisr {
828 #[inline(always)]
829 fn default() -> Dfltisr {
830 Dfltisr(0)
831 }
832 }
833 impl core::fmt::Debug for Dfltisr {
834 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
835 f.debug_struct("Dfltisr")
836 .field("fthf", &self.fthf())
837 .field("dovrf", &self.dovrf())
838 .field("rxnef", &self.rxnef())
839 .field("satf", &self.satf())
840 .field("ckabf", &self.ckabf())
841 .field("rfovrf", &self.rfovrf())
842 .field("sddetf", &self.sddetf())
843 .field("sdlvlf", &self.sdlvlf())
844 .finish()
845 }
846 }
847 #[cfg(feature = "defmt")]
848 impl defmt::Format for Dfltisr {
849 fn format(&self, f: defmt::Formatter) {
850 #[derive(defmt :: Format)]
851 struct Dfltisr {
852 fthf: bool,
853 dovrf: bool,
854 rxnef: bool,
855 satf: bool,
856 ckabf: bool,
857 rfovrf: bool,
858 sddetf: bool,
859 sdlvlf: bool,
860 }
861 let proxy = Dfltisr {
862 fthf: self.fthf(),
863 dovrf: self.dovrf(),
864 rxnef: self.rxnef(),
865 satf: self.satf(),
866 ckabf: self.ckabf(),
867 rfovrf: self.rfovrf(),
868 sddetf: self.sddetf(),
869 sdlvlf: self.sdlvlf(),
870 };
871 defmt::write!(f, "{}", proxy)
872 }
873 }
874 #[doc = "ADF reshape filter configuration register."]
875 #[repr(transparent)]
876 #[derive(Copy, Clone, Eq, PartialEq)]
877 pub struct Dfltrsfr(pub u32);
878 impl Dfltrsfr {
879 #[doc = "Reshaper filter bypass."]
880 #[inline(always)]
881 pub const fn rsfltbyp(&self) -> bool {
882 let val = (self.0 >> 0usize) & 0x01;
883 val != 0
884 }
885 #[doc = "Reshaper filter bypass."]
886 #[inline(always)]
887 pub fn set_rsfltbyp(&mut self, val: bool) {
888 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
889 }
890 #[doc = "Reshaper filter decimation ratio."]
891 #[inline(always)]
892 pub const fn rsfltd(&self) -> super::vals::Rsfltd {
893 let val = (self.0 >> 4usize) & 0x01;
894 super::vals::Rsfltd::from_bits(val as u8)
895 }
896 #[doc = "Reshaper filter decimation ratio."]
897 #[inline(always)]
898 pub fn set_rsfltd(&mut self, val: super::vals::Rsfltd) {
899 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
900 }
901 #[doc = "High-pass filter bypass. This bit is set and cleared by software. It is used to bypass the high-pass filter."]
902 #[inline(always)]
903 pub const fn hpfbyp(&self) -> bool {
904 let val = (self.0 >> 7usize) & 0x01;
905 val != 0
906 }
907 #[doc = "High-pass filter bypass. This bit is set and cleared by software. It is used to bypass the high-pass filter."]
908 #[inline(always)]
909 pub fn set_hpfbyp(&mut self, val: bool) {
910 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
911 }
912 #[doc = "High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input."]
913 #[inline(always)]
914 pub const fn hpfc(&self) -> super::vals::Hpfc {
915 let val = (self.0 >> 8usize) & 0x03;
916 super::vals::Hpfc::from_bits(val as u8)
917 }
918 #[doc = "High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input."]
919 #[inline(always)]
920 pub fn set_hpfc(&mut self, val: super::vals::Hpfc) {
921 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
922 }
923 }
924 impl Default for Dfltrsfr {
925 #[inline(always)]
926 fn default() -> Dfltrsfr {
927 Dfltrsfr(0)
928 }
929 }
930 impl core::fmt::Debug for Dfltrsfr {
931 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
932 f.debug_struct("Dfltrsfr")
933 .field("rsfltbyp", &self.rsfltbyp())
934 .field("rsfltd", &self.rsfltd())
935 .field("hpfbyp", &self.hpfbyp())
936 .field("hpfc", &self.hpfc())
937 .finish()
938 }
939 }
940 #[cfg(feature = "defmt")]
941 impl defmt::Format for Dfltrsfr {
942 fn format(&self, f: defmt::Formatter) {
943 #[derive(defmt :: Format)]
944 struct Dfltrsfr {
945 rsfltbyp: bool,
946 rsfltd: super::vals::Rsfltd,
947 hpfbyp: bool,
948 hpfc: super::vals::Hpfc,
949 }
950 let proxy = Dfltrsfr {
951 rsfltbyp: self.rsfltbyp(),
952 rsfltd: self.rsfltd(),
953 hpfbyp: self.hpfbyp(),
954 hpfc: self.hpfc(),
955 };
956 defmt::write!(f, "{}", proxy)
957 }
958 }
959 #[doc = "ADF delay control register."]
960 #[repr(transparent)]
961 #[derive(Copy, Clone, Eq, PartialEq)]
962 pub struct Dlycr(pub u32);
963 impl Dlycr {
964 #[doc = "Delay to apply to a bitstream. This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine."]
965 #[inline(always)]
966 pub const fn skpdly(&self) -> u8 {
967 let val = (self.0 >> 0usize) & 0x7f;
968 val as u8
969 }
970 #[doc = "Delay to apply to a bitstream. This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine."]
971 #[inline(always)]
972 pub fn set_skpdly(&mut self, val: u8) {
973 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
974 }
975 #[doc = "Skip busy flag."]
976 #[inline(always)]
977 pub const fn skpbf(&self) -> bool {
978 let val = (self.0 >> 31usize) & 0x01;
979 val != 0
980 }
981 #[doc = "Skip busy flag."]
982 #[inline(always)]
983 pub fn set_skpbf(&mut self, val: bool) {
984 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
985 }
986 }
987 impl Default for Dlycr {
988 #[inline(always)]
989 fn default() -> Dlycr {
990 Dlycr(0)
991 }
992 }
993 impl core::fmt::Debug for Dlycr {
994 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
995 f.debug_struct("Dlycr")
996 .field("skpdly", &self.skpdly())
997 .field("skpbf", &self.skpbf())
998 .finish()
999 }
1000 }
1001 #[cfg(feature = "defmt")]
1002 impl defmt::Format for Dlycr {
1003 fn format(&self, f: defmt::Formatter) {
1004 #[derive(defmt :: Format)]
1005 struct Dlycr {
1006 skpdly: u8,
1007 skpbf: bool,
1008 }
1009 let proxy = Dlycr {
1010 skpdly: self.skpdly(),
1011 skpbf: self.skpbf(),
1012 };
1013 defmt::write!(f, "{}", proxy)
1014 }
1015 }
1016 #[doc = "ADF Global Control Register."]
1017 #[repr(transparent)]
1018 #[derive(Copy, Clone, Eq, PartialEq)]
1019 pub struct Gcr(pub u32);
1020 impl Gcr {
1021 #[doc = "Trigger output control Set by software and reset by."]
1022 #[inline(always)]
1023 pub const fn trgo(&self) -> bool {
1024 let val = (self.0 >> 0usize) & 0x01;
1025 val != 0
1026 }
1027 #[doc = "Trigger output control Set by software and reset by."]
1028 #[inline(always)]
1029 pub fn set_trgo(&mut self, val: bool) {
1030 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1031 }
1032 }
1033 impl Default for Gcr {
1034 #[inline(always)]
1035 fn default() -> Gcr {
1036 Gcr(0)
1037 }
1038 }
1039 impl core::fmt::Debug for Gcr {
1040 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1041 f.debug_struct("Gcr").field("trgo", &self.trgo()).finish()
1042 }
1043 }
1044 #[cfg(feature = "defmt")]
1045 impl defmt::Format for Gcr {
1046 fn format(&self, f: defmt::Formatter) {
1047 #[derive(defmt :: Format)]
1048 struct Gcr {
1049 trgo: bool,
1050 }
1051 let proxy = Gcr { trgo: self.trgo() };
1052 defmt::write!(f, "{}", proxy)
1053 }
1054 }
1055 #[doc = "ADF SAD ambient noise level register. This bitfield is set by hardware. It contains the latest ambient noise level computed by the SAD. To refresh this bitfield, the SDLVLF flag must be cleared."]
1056 #[repr(transparent)]
1057 #[derive(Copy, Clone, Eq, PartialEq)]
1058 pub struct Sadanlvr(pub u32);
1059 impl Sadanlvr {
1060 #[doc = "ANLVL."]
1061 #[inline(always)]
1062 pub const fn anlvl(&self) -> u16 {
1063 let val = (self.0 >> 0usize) & 0x7fff;
1064 val as u16
1065 }
1066 #[doc = "ANLVL."]
1067 #[inline(always)]
1068 pub fn set_anlvl(&mut self, val: u16) {
1069 self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize);
1070 }
1071 }
1072 impl Default for Sadanlvr {
1073 #[inline(always)]
1074 fn default() -> Sadanlvr {
1075 Sadanlvr(0)
1076 }
1077 }
1078 impl core::fmt::Debug for Sadanlvr {
1079 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1080 f.debug_struct("Sadanlvr").field("anlvl", &self.anlvl()).finish()
1081 }
1082 }
1083 #[cfg(feature = "defmt")]
1084 impl defmt::Format for Sadanlvr {
1085 fn format(&self, f: defmt::Formatter) {
1086 #[derive(defmt :: Format)]
1087 struct Sadanlvr {
1088 anlvl: u16,
1089 }
1090 let proxy = Sadanlvr { anlvl: self.anlvl() };
1091 defmt::write!(f, "{}", proxy)
1092 }
1093 }
1094 #[doc = "ADF SAD configuration register."]
1095 #[repr(transparent)]
1096 #[derive(Copy, Clone, Eq, PartialEq)]
1097 pub struct Sadcfgr(pub u32);
1098 impl Sadcfgr {
1099 #[doc = "SNTHR."]
1100 #[inline(always)]
1101 pub const fn snthr(&self) -> super::vals::Snthr {
1102 let val = (self.0 >> 0usize) & 0x0f;
1103 super::vals::Snthr::from_bits(val as u8)
1104 }
1105 #[doc = "SNTHR."]
1106 #[inline(always)]
1107 pub fn set_snthr(&mut self, val: super::vals::Snthr) {
1108 self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize);
1109 }
1110 #[doc = "ANSLP."]
1111 #[inline(always)]
1112 pub const fn anslp(&self) -> u8 {
1113 let val = (self.0 >> 4usize) & 0x07;
1114 val as u8
1115 }
1116 #[doc = "ANSLP."]
1117 #[inline(always)]
1118 pub fn set_anslp(&mut self, val: u8) {
1119 self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
1120 }
1121 #[doc = "LFRNB."]
1122 #[inline(always)]
1123 pub const fn lfrnb(&self) -> super::vals::Lfrnb {
1124 let val = (self.0 >> 8usize) & 0x07;
1125 super::vals::Lfrnb::from_bits(val as u8)
1126 }
1127 #[doc = "LFRNB."]
1128 #[inline(always)]
1129 pub fn set_lfrnb(&mut self, val: super::vals::Lfrnb) {
1130 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
1131 }
1132 #[doc = "Hangover time window."]
1133 #[inline(always)]
1134 pub const fn hgovr(&self) -> super::vals::Hgovr {
1135 let val = (self.0 >> 12usize) & 0x07;
1136 super::vals::Hgovr::from_bits(val as u8)
1137 }
1138 #[doc = "Hangover time window."]
1139 #[inline(always)]
1140 pub fn set_hgovr(&mut self, val: super::vals::Hgovr) {
1141 self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
1142 }
1143 #[doc = "ANMIN."]
1144 #[inline(always)]
1145 pub const fn anmin(&self) -> u16 {
1146 let val = (self.0 >> 16usize) & 0x1fff;
1147 val as u16
1148 }
1149 #[doc = "ANMIN."]
1150 #[inline(always)]
1151 pub fn set_anmin(&mut self, val: u16) {
1152 self.0 = (self.0 & !(0x1fff << 16usize)) | (((val as u32) & 0x1fff) << 16usize);
1153 }
1154 }
1155 impl Default for Sadcfgr {
1156 #[inline(always)]
1157 fn default() -> Sadcfgr {
1158 Sadcfgr(0)
1159 }
1160 }
1161 impl core::fmt::Debug for Sadcfgr {
1162 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1163 f.debug_struct("Sadcfgr")
1164 .field("snthr", &self.snthr())
1165 .field("anslp", &self.anslp())
1166 .field("lfrnb", &self.lfrnb())
1167 .field("hgovr", &self.hgovr())
1168 .field("anmin", &self.anmin())
1169 .finish()
1170 }
1171 }
1172 #[cfg(feature = "defmt")]
1173 impl defmt::Format for Sadcfgr {
1174 fn format(&self, f: defmt::Formatter) {
1175 #[derive(defmt :: Format)]
1176 struct Sadcfgr {
1177 snthr: super::vals::Snthr,
1178 anslp: u8,
1179 lfrnb: super::vals::Lfrnb,
1180 hgovr: super::vals::Hgovr,
1181 anmin: u16,
1182 }
1183 let proxy = Sadcfgr {
1184 snthr: self.snthr(),
1185 anslp: self.anslp(),
1186 lfrnb: self.lfrnb(),
1187 hgovr: self.hgovr(),
1188 anmin: self.anmin(),
1189 };
1190 defmt::write!(f, "{}", proxy)
1191 }
1192 }
1193 #[doc = "ADF Sound activity detector (SAD) control register."]
1194 #[repr(transparent)]
1195 #[derive(Copy, Clone, Eq, PartialEq)]
1196 pub struct Sadcr(pub u32);
1197 impl Sadcr {
1198 #[doc = "Sound activity detector enable."]
1199 #[inline(always)]
1200 pub const fn saden(&self) -> bool {
1201 let val = (self.0 >> 0usize) & 0x01;
1202 val != 0
1203 }
1204 #[doc = "Sound activity detector enable."]
1205 #[inline(always)]
1206 pub fn set_saden(&mut self, val: bool) {
1207 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1208 }
1209 #[doc = "Data capture mode."]
1210 #[inline(always)]
1211 pub const fn datcap(&self) -> super::vals::Datcap {
1212 let val = (self.0 >> 1usize) & 0x03;
1213 super::vals::Datcap::from_bits(val as u8)
1214 }
1215 #[doc = "Data capture mode."]
1216 #[inline(always)]
1217 pub fn set_datcap(&mut self, val: super::vals::Datcap) {
1218 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
1219 }
1220 #[doc = "Sound trigger event configuration."]
1221 #[inline(always)]
1222 pub const fn detcfg(&self) -> super::vals::Detcfg {
1223 let val = (self.0 >> 3usize) & 0x01;
1224 super::vals::Detcfg::from_bits(val as u8)
1225 }
1226 #[doc = "Sound trigger event configuration."]
1227 #[inline(always)]
1228 pub fn set_detcfg(&mut self, val: super::vals::Detcfg) {
1229 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
1230 }
1231 #[doc = "SAD state."]
1232 #[inline(always)]
1233 pub const fn sadst(&self) -> super::vals::Sadst {
1234 let val = (self.0 >> 4usize) & 0x03;
1235 super::vals::Sadst::from_bits(val as u8)
1236 }
1237 #[doc = "SAD state."]
1238 #[inline(always)]
1239 pub fn set_sadst(&mut self, val: super::vals::Sadst) {
1240 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
1241 }
1242 #[doc = "Hysteresis enable."]
1243 #[inline(always)]
1244 pub const fn hysten(&self) -> bool {
1245 let val = (self.0 >> 7usize) & 0x01;
1246 val != 0
1247 }
1248 #[doc = "Hysteresis enable."]
1249 #[inline(always)]
1250 pub fn set_hysten(&mut self, val: bool) {
1251 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1252 }
1253 #[doc = "Frame size."]
1254 #[inline(always)]
1255 pub const fn frsize(&self) -> super::vals::Frsize {
1256 let val = (self.0 >> 8usize) & 0x07;
1257 super::vals::Frsize::from_bits(val as u8)
1258 }
1259 #[doc = "Frame size."]
1260 #[inline(always)]
1261 pub fn set_frsize(&mut self, val: super::vals::Frsize) {
1262 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
1263 }
1264 #[doc = "Sound activity detector working mode."]
1265 #[inline(always)]
1266 pub const fn sadmod(&self) -> super::vals::Sadmod {
1267 let val = (self.0 >> 12usize) & 0x03;
1268 super::vals::Sadmod::from_bits(val as u8)
1269 }
1270 #[doc = "Sound activity detector working mode."]
1271 #[inline(always)]
1272 pub fn set_sadmod(&mut self, val: super::vals::Sadmod) {
1273 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
1274 }
1275 #[doc = "SAD Active flag."]
1276 #[inline(always)]
1277 pub const fn sadactive(&self) -> bool {
1278 let val = (self.0 >> 31usize) & 0x01;
1279 val != 0
1280 }
1281 #[doc = "SAD Active flag."]
1282 #[inline(always)]
1283 pub fn set_sadactive(&mut self, val: bool) {
1284 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1285 }
1286 }
1287 impl Default for Sadcr {
1288 #[inline(always)]
1289 fn default() -> Sadcr {
1290 Sadcr(0)
1291 }
1292 }
1293 impl core::fmt::Debug for Sadcr {
1294 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1295 f.debug_struct("Sadcr")
1296 .field("saden", &self.saden())
1297 .field("datcap", &self.datcap())
1298 .field("detcfg", &self.detcfg())
1299 .field("sadst", &self.sadst())
1300 .field("hysten", &self.hysten())
1301 .field("frsize", &self.frsize())
1302 .field("sadmod", &self.sadmod())
1303 .field("sadactive", &self.sadactive())
1304 .finish()
1305 }
1306 }
1307 #[cfg(feature = "defmt")]
1308 impl defmt::Format for Sadcr {
1309 fn format(&self, f: defmt::Formatter) {
1310 #[derive(defmt :: Format)]
1311 struct Sadcr {
1312 saden: bool,
1313 datcap: super::vals::Datcap,
1314 detcfg: super::vals::Detcfg,
1315 sadst: super::vals::Sadst,
1316 hysten: bool,
1317 frsize: super::vals::Frsize,
1318 sadmod: super::vals::Sadmod,
1319 sadactive: bool,
1320 }
1321 let proxy = Sadcr {
1322 saden: self.saden(),
1323 datcap: self.datcap(),
1324 detcfg: self.detcfg(),
1325 sadst: self.sadst(),
1326 hysten: self.hysten(),
1327 frsize: self.frsize(),
1328 sadmod: self.sadmod(),
1329 sadactive: self.sadactive(),
1330 };
1331 defmt::write!(f, "{}", proxy)
1332 }
1333 }
1334 #[doc = "ADF SAD sound level register."]
1335 #[repr(transparent)]
1336 #[derive(Copy, Clone, Eq, PartialEq)]
1337 pub struct Sadsdlvr(pub u32);
1338 impl Sadsdlvr {
1339 #[doc = "Short term sound level. This bitfield is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared."]
1340 #[inline(always)]
1341 pub const fn sdlvl(&self) -> u16 {
1342 let val = (self.0 >> 0usize) & 0x7fff;
1343 val as u16
1344 }
1345 #[doc = "Short term sound level. This bitfield is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared."]
1346 #[inline(always)]
1347 pub fn set_sdlvl(&mut self, val: u16) {
1348 self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize);
1349 }
1350 }
1351 impl Default for Sadsdlvr {
1352 #[inline(always)]
1353 fn default() -> Sadsdlvr {
1354 Sadsdlvr(0)
1355 }
1356 }
1357 impl core::fmt::Debug for Sadsdlvr {
1358 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1359 f.debug_struct("Sadsdlvr").field("sdlvl", &self.sdlvl()).finish()
1360 }
1361 }
1362 #[cfg(feature = "defmt")]
1363 impl defmt::Format for Sadsdlvr {
1364 fn format(&self, f: defmt::Formatter) {
1365 #[derive(defmt :: Format)]
1366 struct Sadsdlvr {
1367 sdlvl: u16,
1368 }
1369 let proxy = Sadsdlvr { sdlvl: self.sdlvl() };
1370 defmt::write!(f, "{}", proxy)
1371 }
1372 }
1373 #[doc = "ADF serial interface control register 0."]
1374 #[repr(transparent)]
1375 #[derive(Copy, Clone, Eq, PartialEq)]
1376 pub struct Sitfcr(pub u32);
1377 impl Sitfcr {
1378 #[inline(always)]
1379 pub const fn sitfen(&self) -> bool {
1380 let val = (self.0 >> 0usize) & 0x01;
1381 val != 0
1382 }
1383 #[inline(always)]
1384 pub fn set_sitfen(&mut self, val: bool) {
1385 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1386 }
1387 #[inline(always)]
1388 pub const fn scksrc(&self) -> super::vals::Scksrc {
1389 let val = (self.0 >> 1usize) & 0x03;
1390 super::vals::Scksrc::from_bits(val as u8)
1391 }
1392 #[inline(always)]
1393 pub fn set_scksrc(&mut self, val: super::vals::Scksrc) {
1394 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
1395 }
1396 #[inline(always)]
1397 pub const fn sitfmod(&self) -> super::vals::Sitfmod {
1398 let val = (self.0 >> 4usize) & 0x03;
1399 super::vals::Sitfmod::from_bits(val as u8)
1400 }
1401 #[inline(always)]
1402 pub fn set_sitfmod(&mut self, val: super::vals::Sitfmod) {
1403 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
1404 }
1405 #[doc = "Manchester symbol threshold/SPI threshold. This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (seer to Manchester mode for details on computation). In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH\\[4:0\\]
1406values lower than four are invalid."]
1407 #[inline(always)]
1408 pub const fn sth(&self) -> u8 {
1409 let val = (self.0 >> 8usize) & 0x1f;
1410 val as u8
1411 }
1412 #[doc = "Manchester symbol threshold/SPI threshold. This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (seer to Manchester mode for details on computation). In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH\\[4:0\\]
1413values lower than four are invalid."]
1414 #[inline(always)]
1415 pub fn set_sth(&mut self, val: u8) {
1416 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
1417 }
1418 #[doc = "SITFACTIVE."]
1419 #[inline(always)]
1420 pub const fn sitfactive(&self) -> bool {
1421 let val = (self.0 >> 31usize) & 0x01;
1422 val != 0
1423 }
1424 #[doc = "SITFACTIVE."]
1425 #[inline(always)]
1426 pub fn set_sitfactive(&mut self, val: bool) {
1427 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1428 }
1429 }
1430 impl Default for Sitfcr {
1431 #[inline(always)]
1432 fn default() -> Sitfcr {
1433 Sitfcr(0)
1434 }
1435 }
1436 impl core::fmt::Debug for Sitfcr {
1437 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1438 f.debug_struct("Sitfcr")
1439 .field("sitfen", &self.sitfen())
1440 .field("scksrc", &self.scksrc())
1441 .field("sitfmod", &self.sitfmod())
1442 .field("sth", &self.sth())
1443 .field("sitfactive", &self.sitfactive())
1444 .finish()
1445 }
1446 }
1447 #[cfg(feature = "defmt")]
1448 impl defmt::Format for Sitfcr {
1449 fn format(&self, f: defmt::Formatter) {
1450 #[derive(defmt :: Format)]
1451 struct Sitfcr {
1452 sitfen: bool,
1453 scksrc: super::vals::Scksrc,
1454 sitfmod: super::vals::Sitfmod,
1455 sth: u8,
1456 sitfactive: bool,
1457 }
1458 let proxy = Sitfcr {
1459 sitfen: self.sitfen(),
1460 scksrc: self.scksrc(),
1461 sitfmod: self.sitfmod(),
1462 sth: self.sth(),
1463 sitfactive: self.sitfactive(),
1464 };
1465 defmt::write!(f, "{}", proxy)
1466 }
1467 }
1468}
1469pub mod vals {
1470 #[doc = "DFLT trigger mode. This bitfield is set and cleared by software. It is used to select the trigger mode of the DFLT0."]
1471 #[repr(u8)]
1472 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1473 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1474 pub enum Acqmod {
1475 #[doc = "Asynchronous continuous acquisition mode."]
1476 ASYNCHRONOUS_CONTINUOUS = 0x0,
1477 #[doc = "Asynchronous single-shot acquisition mode"]
1478 ASYNCHRONOUS_SINGLE_SHOT = 0x01,
1479 #[doc = "Synchronous continuous acquisition mode."]
1480 SYNCRONOUS_CONTINUOUS = 0x02,
1481 #[doc = "Synchronous single-shot acquisition mode."]
1482 SYNCRONOUS_SINGLE_SHOT = 0x03,
1483 #[doc = "Window continuous acquisition mode."]
1484 WINDOW_CONTINUOUS = 0x04,
1485 _RESERVED_5 = 0x05,
1486 _RESERVED_6 = 0x06,
1487 _RESERVED_7 = 0x07,
1488 }
1489 impl Acqmod {
1490 #[inline(always)]
1491 pub const fn from_bits(val: u8) -> Acqmod {
1492 unsafe { core::mem::transmute(val & 0x07) }
1493 }
1494 #[inline(always)]
1495 pub const fn to_bits(self) -> u8 {
1496 unsafe { core::mem::transmute(self) }
1497 }
1498 }
1499 impl From<u8> for Acqmod {
1500 #[inline(always)]
1501 fn from(val: u8) -> Acqmod {
1502 Acqmod::from_bits(val)
1503 }
1504 }
1505 impl From<Acqmod> for u8 {
1506 #[inline(always)]
1507 fn from(val: Acqmod) -> u8 {
1508 Acqmod::to_bits(val)
1509 }
1510 }
1511 #[doc = "Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0."]
1512 #[repr(u8)]
1513 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1514 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1515 pub enum Bssel {
1516 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1517 BS0_R = 0x0,
1518 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1519 BS0_F = 0x01,
1520 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1521 BS1_R = 0x02,
1522 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1523 BS1_F = 0x03,
1524 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1525 BS2_R = 0x04,
1526 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1527 BS2_F = 0x05,
1528 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1529 BS3_R = 0x06,
1530 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1531 BS3_F = 0x07,
1532 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1533 BS4_R = 0x08,
1534 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1535 BS4_F = 0x09,
1536 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1537 BS5_R = 0x0a,
1538 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1539 BS5_F = 0x0b,
1540 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1541 BS6_R = 0x0c,
1542 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1543 BS6_F = 0x0d,
1544 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1545 BS7_R = 0x0e,
1546 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1547 BS7_F = 0x0f,
1548 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1549 BS8_R = 0x10,
1550 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1551 BS8_F = 0x11,
1552 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1553 BS9_R = 0x12,
1554 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1555 BS9_F = 0x13,
1556 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1557 BS10_R = 0x14,
1558 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1559 BS10_F = 0x15,
1560 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1561 BS11_R = 0x16,
1562 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1563 BS11_F = 0x17,
1564 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1565 BS12_R = 0x18,
1566 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1567 BS12_F = 0x19,
1568 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1569 BS13_R = 0x1a,
1570 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1571 BS13_F = 0x1b,
1572 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1573 BS14_R = 0x1c,
1574 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1575 BS14_F = 0x1d,
1576 #[doc = "bsx_r provided to DFLTy (and SCDy)."]
1577 BS15_R = 0x1e,
1578 #[doc = "bsx_f provided to DFLTy (and SCDy)."]
1579 BS15_F = 0x1f,
1580 }
1581 impl Bssel {
1582 #[inline(always)]
1583 pub const fn from_bits(val: u8) -> Bssel {
1584 unsafe { core::mem::transmute(val & 0x1f) }
1585 }
1586 #[inline(always)]
1587 pub const fn to_bits(self) -> u8 {
1588 unsafe { core::mem::transmute(self) }
1589 }
1590 }
1591 impl From<u8> for Bssel {
1592 #[inline(always)]
1593 fn from(val: u8) -> Bssel {
1594 Bssel::from_bits(val)
1595 }
1596 }
1597 impl From<Bssel> for u8 {
1598 #[inline(always)]
1599 fn from(val: Bssel) -> u8 {
1600 Bssel::to_bits(val)
1601 }
1602 }
1603 #[doc = "CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin."]
1604 #[repr(u8)]
1605 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1606 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1607 pub enum Cckdir {
1608 #[doc = "CCK is an input."]
1609 INPUT = 0x0,
1610 #[doc = "CCK is an output."]
1611 OUTPUT = 0x01,
1612 }
1613 impl Cckdir {
1614 #[inline(always)]
1615 pub const fn from_bits(val: u8) -> Cckdir {
1616 unsafe { core::mem::transmute(val & 0x01) }
1617 }
1618 #[inline(always)]
1619 pub const fn to_bits(self) -> u8 {
1620 unsafe { core::mem::transmute(self) }
1621 }
1622 }
1623 impl From<u8> for Cckdir {
1624 #[inline(always)]
1625 fn from(val: u8) -> Cckdir {
1626 Cckdir::from_bits(val)
1627 }
1628 }
1629 impl From<Cckdir> for u8 {
1630 #[inline(always)]
1631 fn from(val: Cckdir) -> u8 {
1632 Cckdir::to_bits(val)
1633 }
1634 }
1635 #[doc = "Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin."]
1636 #[repr(u8)]
1637 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1638 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1639 pub enum Cckdiv {
1640 #[doc = "The ADF_CCK clock is adf_proc_ck."]
1641 DIV1 = 0x0,
1642 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 2."]
1643 DIV2 = 0x01,
1644 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 3."]
1645 DIV3 = 0x02,
1646 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 4."]
1647 DIV4 = 0x03,
1648 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 5."]
1649 DIV5 = 0x04,
1650 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 6."]
1651 DIV6 = 0x05,
1652 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 7."]
1653 DIV7 = 0x06,
1654 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 8."]
1655 DIV8 = 0x07,
1656 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 9."]
1657 DIV9 = 0x08,
1658 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 10."]
1659 DIV10 = 0x09,
1660 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 11."]
1661 DIV11 = 0x0a,
1662 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 12."]
1663 DIV12 = 0x0b,
1664 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 13."]
1665 DIV13 = 0x0c,
1666 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 14."]
1667 DIV14 = 0x0d,
1668 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 15."]
1669 DIV15 = 0x0e,
1670 #[doc = "The ADF_CCK clock is adf_proc_ck divided by 16."]
1671 DIV16 = 0x0f,
1672 }
1673 impl Cckdiv {
1674 #[inline(always)]
1675 pub const fn from_bits(val: u8) -> Cckdiv {
1676 unsafe { core::mem::transmute(val & 0x0f) }
1677 }
1678 #[inline(always)]
1679 pub const fn to_bits(self) -> u8 {
1680 unsafe { core::mem::transmute(self) }
1681 }
1682 }
1683 impl From<u8> for Cckdiv {
1684 #[inline(always)]
1685 fn from(val: u8) -> Cckdiv {
1686 Cckdiv::from_bits(val)
1687 }
1688 }
1689 impl From<Cckdiv> for u8 {
1690 #[inline(always)]
1691 fn from(val: Cckdiv) -> u8 {
1692 Cckdiv::to_bits(val)
1693 }
1694 }
1695 #[doc = "CCK clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin."]
1696 #[repr(u8)]
1697 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1698 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1699 pub enum Ccken {
1700 #[doc = "Bitstream clock not generated."]
1701 NOT_GENERATED = 0x0,
1702 #[doc = "Bitstream clock generated on the CCK pin."]
1703 GENERATED = 0x01,
1704 }
1705 impl Ccken {
1706 #[inline(always)]
1707 pub const fn from_bits(val: u8) -> Ccken {
1708 unsafe { core::mem::transmute(val & 0x01) }
1709 }
1710 #[inline(always)]
1711 pub const fn to_bits(self) -> u8 {
1712 unsafe { core::mem::transmute(self) }
1713 }
1714 }
1715 impl From<u8> for Ccken {
1716 #[inline(always)]
1717 fn from(val: u8) -> Ccken {
1718 Ccken::from_bits(val)
1719 }
1720 }
1721 impl From<Ccken> for u8 {
1722 #[inline(always)]
1723 fn from(val: Ccken) -> u8 {
1724 Ccken::to_bits(val)
1725 }
1726 }
1727 #[doc = "Select the CIC order. This bitfield is set and cleared by software. It is used to select the MCIC order."]
1728 #[repr(u8)]
1729 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1730 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1731 pub enum Cicmod {
1732 _RESERVED_0 = 0x0,
1733 _RESERVED_1 = 0x01,
1734 _RESERVED_2 = 0x02,
1735 _RESERVED_3 = 0x03,
1736 #[doc = "MCIC configured in single Sinc4 filter."]
1737 SINC4 = 0x04,
1738 #[doc = "MCIC configured in single Sinc5 filter."]
1739 SINC5 = 0x05,
1740 _RESERVED_6 = 0x06,
1741 _RESERVED_7 = 0x07,
1742 }
1743 impl Cicmod {
1744 #[inline(always)]
1745 pub const fn from_bits(val: u8) -> Cicmod {
1746 unsafe { core::mem::transmute(val & 0x07) }
1747 }
1748 #[inline(always)]
1749 pub const fn to_bits(self) -> u8 {
1750 unsafe { core::mem::transmute(self) }
1751 }
1752 }
1753 impl From<u8> for Cicmod {
1754 #[inline(always)]
1755 fn from(val: u8) -> Cicmod {
1756 Cicmod::from_bits(val)
1757 }
1758 }
1759 impl From<Cicmod> for u8 {
1760 #[inline(always)]
1761 fn from(val: Cicmod) -> u8 {
1762 Cicmod::to_bits(val)
1763 }
1764 }
1765 #[doc = "Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1)."]
1766 #[repr(u8)]
1767 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1768 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1769 pub enum Ckgmod {
1770 #[doc = "The kernel clock is provided to the dividers as soon as CKGDEN is set to 1."]
1771 IMMEDIATE = 0x0,
1772 #[doc = "The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met."]
1773 TRIGGER = 0x01,
1774 }
1775 impl Ckgmod {
1776 #[inline(always)]
1777 pub const fn from_bits(val: u8) -> Ckgmod {
1778 unsafe { core::mem::transmute(val & 0x01) }
1779 }
1780 #[inline(always)]
1781 pub const fn to_bits(self) -> u8 {
1782 unsafe { core::mem::transmute(self) }
1783 }
1784 }
1785 impl From<u8> for Ckgmod {
1786 #[inline(always)]
1787 fn from(val: u8) -> Ckgmod {
1788 Ckgmod::from_bits(val)
1789 }
1790 }
1791 impl From<Ckgmod> for u8 {
1792 #[inline(always)]
1793 fn from(val: Ckgmod) -> u8 {
1794 Ckgmod::to_bits(val)
1795 }
1796 }
1797 #[doc = "Data capture mode. This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory."]
1798 #[repr(u8)]
1799 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1800 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1801 pub enum Datcap {
1802 #[doc = "Samples from DFLT0 not transfered into the memory."]
1803 DISABLED = 0x0,
1804 #[doc = "Samples from DFLT0 transfered into the memory when SAD is in DETECT state."]
1805 ON_DETECTED = 0x01,
1806 #[doc = "Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled."]
1807 ENABLED = 0x02,
1808 _RESERVED_3 = 0x03,
1809 }
1810 impl Datcap {
1811 #[inline(always)]
1812 pub const fn from_bits(val: u8) -> Datcap {
1813 unsafe { core::mem::transmute(val & 0x03) }
1814 }
1815 #[inline(always)]
1816 pub const fn to_bits(self) -> u8 {
1817 unsafe { core::mem::transmute(self) }
1818 }
1819 }
1820 impl From<u8> for Datcap {
1821 #[inline(always)]
1822 fn from(val: u8) -> Datcap {
1823 Datcap::from_bits(val)
1824 }
1825 }
1826 impl From<Datcap> for u8 {
1827 #[inline(always)]
1828 fn from(val: Datcap) -> u8 {
1829 Datcap::to_bits(val)
1830 }
1831 }
1832 #[doc = "Source data for the digital filter."]
1833 #[repr(u8)]
1834 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1835 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1836 pub enum Datsrc {
1837 #[doc = "Stream coming from the BSMX selected"]
1838 BSMX = 0x0,
1839 _RESERVED_1 = 0x01,
1840 #[doc = "Stream coming from the ADCITF1 selected"]
1841 ADCITF1 = 0x02,
1842 #[doc = "Stream coming from the ADCITF2 selected"]
1843 ADCITF2 = 0x03,
1844 }
1845 impl Datsrc {
1846 #[inline(always)]
1847 pub const fn from_bits(val: u8) -> Datsrc {
1848 unsafe { core::mem::transmute(val & 0x03) }
1849 }
1850 #[inline(always)]
1851 pub const fn to_bits(self) -> u8 {
1852 unsafe { core::mem::transmute(self) }
1853 }
1854 }
1855 impl From<u8> for Datsrc {
1856 #[inline(always)]
1857 fn from(val: u8) -> Datsrc {
1858 Datsrc::from_bits(val)
1859 }
1860 }
1861 impl From<Datsrc> for u8 {
1862 #[inline(always)]
1863 fn from(val: Datsrc) -> u8 {
1864 Datsrc::to_bits(val)
1865 }
1866 }
1867 #[doc = "Sound trigger event configuration. This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state."]
1868 #[repr(u8)]
1869 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1870 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1871 pub enum Detcfg {
1872 #[doc = "sddet_evt generated when SAD enters the MONITOR state."]
1873 MONITOR = 0x0,
1874 #[doc = "sddet_evt generated when SAD enters or exits the DETECT state."]
1875 DETECT = 0x01,
1876 }
1877 impl Detcfg {
1878 #[inline(always)]
1879 pub const fn from_bits(val: u8) -> Detcfg {
1880 unsafe { core::mem::transmute(val & 0x01) }
1881 }
1882 #[inline(always)]
1883 pub const fn to_bits(self) -> u8 {
1884 unsafe { core::mem::transmute(self) }
1885 }
1886 }
1887 impl From<u8> for Detcfg {
1888 #[inline(always)]
1889 fn from(val: u8) -> Detcfg {
1890 Detcfg::from_bits(val)
1891 }
1892 }
1893 impl From<Detcfg> for u8 {
1894 #[inline(always)]
1895 fn from(val: Detcfg) -> u8 {
1896 Detcfg::to_bits(val)
1897 }
1898 }
1899 #[doc = "Frame size. This bitfield is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level."]
1900 #[repr(u8)]
1901 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1902 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1903 pub enum Frsize {
1904 #[doc = "8 sample."]
1905 SAMPLES8 = 0x0,
1906 #[doc = "16 samples."]
1907 SAMPLES16 = 0x01,
1908 #[doc = "32 samples."]
1909 SAMPLES32 = 0x02,
1910 #[doc = "64 samples."]
1911 SAMPLES64 = 0x03,
1912 #[doc = "128 samples."]
1913 SAMPLES128 = 0x04,
1914 #[doc = "256 samples."]
1915 SAMPLES256 = 0x05,
1916 #[doc = "512 samples."]
1917 SAMPLES512 = 0x06,
1918 _RESERVED_7 = 0x07,
1919 }
1920 impl Frsize {
1921 #[inline(always)]
1922 pub const fn from_bits(val: u8) -> Frsize {
1923 unsafe { core::mem::transmute(val & 0x07) }
1924 }
1925 #[inline(always)]
1926 pub const fn to_bits(self) -> u8 {
1927 unsafe { core::mem::transmute(self) }
1928 }
1929 }
1930 impl From<u8> for Frsize {
1931 #[inline(always)]
1932 fn from(val: u8) -> Frsize {
1933 Frsize::from_bits(val)
1934 }
1935 }
1936 impl From<Frsize> for u8 {
1937 #[inline(always)]
1938 fn from(val: Frsize) -> u8 {
1939 Frsize::to_bits(val)
1940 }
1941 }
1942 #[doc = "Hangover time window. This bitfield is set and cleared by software. It is used to select the hangover time window."]
1943 #[repr(u8)]
1944 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1945 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1946 pub enum Hgovr {
1947 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1948 FRAMES_4 = 0x0,
1949 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1950 FRAMES_8 = 0x01,
1951 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1952 FRAMES_16 = 0x02,
1953 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1954 FRAMES_32 = 0x03,
1955 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1956 FRAMES_64 = 0x04,
1957 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1958 FRAMES_128 = 0x05,
1959 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1960 FRAMES_256 = 0x06,
1961 #[doc = "SAD back to MONITOR state if sound is below threshold for 4 frames."]
1962 FRAMES_512 = 0x07,
1963 }
1964 impl Hgovr {
1965 #[inline(always)]
1966 pub const fn from_bits(val: u8) -> Hgovr {
1967 unsafe { core::mem::transmute(val & 0x07) }
1968 }
1969 #[inline(always)]
1970 pub const fn to_bits(self) -> u8 {
1971 unsafe { core::mem::transmute(self) }
1972 }
1973 }
1974 impl From<u8> for Hgovr {
1975 #[inline(always)]
1976 fn from(val: u8) -> Hgovr {
1977 Hgovr::from_bits(val)
1978 }
1979 }
1980 impl From<Hgovr> for u8 {
1981 #[inline(always)]
1982 fn from(val: Hgovr) -> u8 {
1983 Hgovr::to_bits(val)
1984 }
1985 }
1986 #[doc = "High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input."]
1987 #[repr(u8)]
1988 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1989 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1990 pub enum Hpfc {
1991 #[doc = "Cut-off frequency = 0.000625 x FPCM."]
1992 LOW = 0x0,
1993 #[doc = "Cut-off frequency = 0.00125 x FPCM."]
1994 MEDIUM = 0x01,
1995 #[doc = "Cut-off frequency = 0.00250 x FPCM"]
1996 HIGH = 0x02,
1997 #[doc = "Cut-off frequency = 0.00950 x FPCM"]
1998 MAXIMUM = 0x03,
1999 }
2000 impl Hpfc {
2001 #[inline(always)]
2002 pub const fn from_bits(val: u8) -> Hpfc {
2003 unsafe { core::mem::transmute(val & 0x03) }
2004 }
2005 #[inline(always)]
2006 pub const fn to_bits(self) -> u8 {
2007 unsafe { core::mem::transmute(self) }
2008 }
2009 }
2010 impl From<u8> for Hpfc {
2011 #[inline(always)]
2012 fn from(val: u8) -> Hpfc {
2013 Hpfc::from_bits(val)
2014 }
2015 }
2016 impl From<Hpfc> for u8 {
2017 #[inline(always)]
2018 fn from(val: Hpfc) -> u8 {
2019 Hpfc::to_bits(val)
2020 }
2021 }
2022 #[doc = "LFRNB. This bitfield is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level."]
2023 #[repr(u8)]
2024 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2025 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2026 pub enum Lfrnb {
2027 #[doc = "2 samples."]
2028 FRAMES_2 = 0x0,
2029 #[doc = "4 samples."]
2030 FRAMES_4 = 0x01,
2031 #[doc = "8 samples."]
2032 FRAMES_8 = 0x02,
2033 #[doc = "16 samples."]
2034 FRAMES_16 = 0x03,
2035 #[doc = "32 samples."]
2036 FRAMES_32 = 0x04,
2037 _RESERVED_5 = 0x05,
2038 _RESERVED_6 = 0x06,
2039 _RESERVED_7 = 0x07,
2040 }
2041 impl Lfrnb {
2042 #[inline(always)]
2043 pub const fn from_bits(val: u8) -> Lfrnb {
2044 unsafe { core::mem::transmute(val & 0x07) }
2045 }
2046 #[inline(always)]
2047 pub const fn to_bits(self) -> u8 {
2048 unsafe { core::mem::transmute(self) }
2049 }
2050 }
2051 impl From<u8> for Lfrnb {
2052 #[inline(always)]
2053 fn from(val: u8) -> Lfrnb {
2054 Lfrnb::from_bits(val)
2055 }
2056 }
2057 impl From<Lfrnb> for u8 {
2058 #[inline(always)]
2059 fn from(val: Lfrnb) -> u8 {
2060 Lfrnb::to_bits(val)
2061 }
2062 }
2063 #[doc = "Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter."]
2064 #[repr(u8)]
2065 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2066 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2067 pub enum Rsfltd {
2068 #[doc = "Decimation ratio is 4 (default value)."]
2069 DECIMATION4 = 0x0,
2070 #[doc = "Decimation ratio is 1."]
2071 DECIMATION1 = 0x01,
2072 }
2073 impl Rsfltd {
2074 #[inline(always)]
2075 pub const fn from_bits(val: u8) -> Rsfltd {
2076 unsafe { core::mem::transmute(val & 0x01) }
2077 }
2078 #[inline(always)]
2079 pub const fn to_bits(self) -> u8 {
2080 unsafe { core::mem::transmute(self) }
2081 }
2082 }
2083 impl From<u8> for Rsfltd {
2084 #[inline(always)]
2085 fn from(val: u8) -> Rsfltd {
2086 Rsfltd::from_bits(val)
2087 }
2088 }
2089 impl From<Rsfltd> for u8 {
2090 #[inline(always)]
2091 fn from(val: Rsfltd) -> u8 {
2092 Rsfltd::to_bits(val)
2093 }
2094 }
2095 #[doc = "RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold."]
2096 #[repr(u8)]
2097 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2098 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2099 pub enum Rxfifo {
2100 #[doc = "RXFIFO threshold event generated when the RXFIFO is not empty"]
2101 NOT_EMPTY = 0x0,
2102 #[doc = "RXFIFO threshold event generated when the RXFIFO is half-full"]
2103 HALF_FULL = 0x01,
2104 }
2105 impl Rxfifo {
2106 #[inline(always)]
2107 pub const fn from_bits(val: u8) -> Rxfifo {
2108 unsafe { core::mem::transmute(val & 0x01) }
2109 }
2110 #[inline(always)]
2111 pub const fn to_bits(self) -> u8 {
2112 unsafe { core::mem::transmute(self) }
2113 }
2114 }
2115 impl From<u8> for Rxfifo {
2116 #[inline(always)]
2117 fn from(val: u8) -> Rxfifo {
2118 Rxfifo::from_bits(val)
2119 }
2120 }
2121 impl From<Rxfifo> for u8 {
2122 #[inline(always)]
2123 fn from(val: Rxfifo) -> u8 {
2124 Rxfifo::to_bits(val)
2125 }
2126 }
2127 #[doc = "SAD working mode. This bitfield is set and cleared by software. It is used to define the way the SAD works"]
2128 #[repr(u8)]
2129 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2130 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2131 pub enum Sadmod {
2132 #[doc = "Threshold value computed according to the estimated ambient noise. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector."]
2133 THRESHOLD_ESTIMATED_AMBIENT_NOISE = 0x0,
2134 #[doc = "Threshold value equal to ANMIN\\[12:0\\], multiplied by the gain selected by SNTHR\\[3:0\\]
2135The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector."]
2136 THRESHOLD_MINIMUM_NOISELEVEL = 0x01,
2137 #[doc = "Threshold value given by 4 x ANMIN\\[12:0\\]. The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR\\[3:0\\]
2138is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode."]
2139 THRESHOLD_MINIMUM_NOISELEVELX4 = 0x02,
2140 _RESERVED_3 = 0x03,
2141 }
2142 impl Sadmod {
2143 #[inline(always)]
2144 pub const fn from_bits(val: u8) -> Sadmod {
2145 unsafe { core::mem::transmute(val & 0x03) }
2146 }
2147 #[inline(always)]
2148 pub const fn to_bits(self) -> u8 {
2149 unsafe { core::mem::transmute(self) }
2150 }
2151 }
2152 impl From<u8> for Sadmod {
2153 #[inline(always)]
2154 fn from(val: u8) -> Sadmod {
2155 Sadmod::from_bits(val)
2156 }
2157 }
2158 impl From<Sadmod> for u8 {
2159 #[inline(always)]
2160 fn from(val: Sadmod) -> u8 {
2161 Sadmod::to_bits(val)
2162 }
2163 }
2164 #[doc = "SAD state. This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1."]
2165 #[repr(u8)]
2166 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2167 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2168 pub enum Sadst {
2169 #[doc = "SAD in LEARN state."]
2170 LEARN = 0x0,
2171 #[doc = "SAD in MONITOR state."]
2172 MONITOR = 0x01,
2173 #[doc = "SAD in DETECT state."]
2174 DETECT = 0x02,
2175 _RESERVED_3 = 0x03,
2176 }
2177 impl Sadst {
2178 #[inline(always)]
2179 pub const fn from_bits(val: u8) -> Sadst {
2180 unsafe { core::mem::transmute(val & 0x03) }
2181 }
2182 #[inline(always)]
2183 pub const fn to_bits(self) -> u8 {
2184 unsafe { core::mem::transmute(self) }
2185 }
2186 }
2187 impl From<u8> for Sadst {
2188 #[inline(always)]
2189 fn from(val: u8) -> Sadst {
2190 Sadst::from_bits(val)
2191 }
2192 }
2193 impl From<Sadst> for u8 {
2194 #[inline(always)]
2195 fn from(val: Sadst) -> u8 {
2196 Sadst::to_bits(val)
2197 }
2198 }
2199 #[doc = "Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface."]
2200 #[repr(u8)]
2201 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2202 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2203 pub enum Scksrc {
2204 #[doc = "Serial clock source is CCK0."]
2205 CCK0 = 0x0,
2206 #[doc = "Serial clock source is CCK1."]
2207 CCK1 = 0x01,
2208 #[doc = "Serial clock source is CCI0."]
2209 CKI0 = 0x02,
2210 #[doc = "Serial clock source is CCI1."]
2211 CKI1 = 0x03,
2212 }
2213 impl Scksrc {
2214 #[inline(always)]
2215 pub const fn from_bits(val: u8) -> Scksrc {
2216 unsafe { core::mem::transmute(val & 0x03) }
2217 }
2218 #[inline(always)]
2219 pub const fn to_bits(self) -> u8 {
2220 unsafe { core::mem::transmute(self) }
2221 }
2222 }
2223 impl From<u8> for Scksrc {
2224 #[inline(always)]
2225 fn from(val: u8) -> Scksrc {
2226 Scksrc::from_bits(val)
2227 }
2228 }
2229 impl From<Scksrc> for u8 {
2230 #[inline(always)]
2231 fn from(val: Scksrc) -> u8 {
2232 Scksrc::to_bits(val)
2233 }
2234 }
2235 #[doc = "Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode."]
2236 #[repr(u8)]
2237 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2238 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2239 pub enum Sitfmod {
2240 #[doc = "LF_MASTER SPI mode."]
2241 MASTER_SPI = 0x0,
2242 #[doc = "Normal SPI mode."]
2243 NORMAL_SPI = 0x01,
2244 #[doc = "Manchester mode rising edge = logic 0, falling edge = logic 1."]
2245 MANCHESTER_FALLING = 0x02,
2246 #[doc = "Manchester mode rising edge = logic 1, falling edge = logic 0."]
2247 MANCHESTER_RISING = 0x03,
2248 }
2249 impl Sitfmod {
2250 #[inline(always)]
2251 pub const fn from_bits(val: u8) -> Sitfmod {
2252 unsafe { core::mem::transmute(val & 0x03) }
2253 }
2254 #[inline(always)]
2255 pub const fn to_bits(self) -> u8 {
2256 unsafe { core::mem::transmute(self) }
2257 }
2258 }
2259 impl From<u8> for Sitfmod {
2260 #[inline(always)]
2261 fn from(val: u8) -> Sitfmod {
2262 Sitfmod::from_bits(val)
2263 }
2264 }
2265 impl From<Sitfmod> for u8 {
2266 #[inline(always)]
2267 fn from(val: Sitfmod) -> u8 {
2268 Sitfmod::to_bits(val)
2269 }
2270 }
2271 #[doc = "SNTHR. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value."]
2272 #[repr(u8)]
2273 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2274 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2275 pub enum Snthr {
2276 #[doc = "Threshold is 3.5 dB higher than ANLVL"]
2277 NOISE_PLUS_3_5 = 0x0,
2278 #[doc = "Threshold is 6.0 dB higher than ANLVL"]
2279 NOISE_PLUS_6_0 = 0x01,
2280 #[doc = "Threshold is 9.5 dB higher than ANLVL"]
2281 NOISE_PLUS_9_5 = 0x02,
2282 #[doc = "Threshold is 12 dB higher than ANLVL"]
2283 NOISE_PLUS_12 = 0x03,
2284 #[doc = "Threshold is 15.6 dB higher than ANLVL"]
2285 NOISE_PLUS_15_6 = 0x04,
2286 #[doc = "Threshold is 18 dB higher than ANLVL"]
2287 NOISE_PLUS_18 = 0x05,
2288 #[doc = "Threshold is 21.6 dB higher than ANLVL"]
2289 NOISE_PLUS_21_6 = 0x06,
2290 #[doc = "Threshold is 24.1 dB higher than ANLVL"]
2291 NOISE_PLUS_24_1 = 0x07,
2292 #[doc = "Threshold is 27.6 dB higher than ANLVL"]
2293 NOISE_PLUS_27_6 = 0x08,
2294 #[doc = "Threshold is 30.1 dB higher than ANLVL"]
2295 NOISE_PLUS_30_1 = 0x09,
2296 _RESERVED_a = 0x0a,
2297 _RESERVED_b = 0x0b,
2298 _RESERVED_c = 0x0c,
2299 _RESERVED_d = 0x0d,
2300 _RESERVED_e = 0x0e,
2301 _RESERVED_f = 0x0f,
2302 }
2303 impl Snthr {
2304 #[inline(always)]
2305 pub const fn from_bits(val: u8) -> Snthr {
2306 unsafe { core::mem::transmute(val & 0x0f) }
2307 }
2308 #[inline(always)]
2309 pub const fn to_bits(self) -> u8 {
2310 unsafe { core::mem::transmute(self) }
2311 }
2312 }
2313 impl From<u8> for Snthr {
2314 #[inline(always)]
2315 fn from(val: u8) -> Snthr {
2316 Snthr::from_bits(val)
2317 }
2318 }
2319 impl From<Snthr> for u8 {
2320 #[inline(always)]
2321 fn from(val: Snthr) -> u8 {
2322 Snthr::to_bits(val)
2323 }
2324 }
2325 #[doc = "CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0."]
2326 #[repr(u8)]
2327 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2328 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2329 pub enum Trgsens {
2330 #[doc = "A rising edge event triggers the activation of CKGEN dividers."]
2331 RISING_EDGE = 0x0,
2332 #[doc = "A falling edge even triggers the activation of CKGEN dividers."]
2333 FALLING_EDGE = 0x01,
2334 }
2335 impl Trgsens {
2336 #[inline(always)]
2337 pub const fn from_bits(val: u8) -> Trgsens {
2338 unsafe { core::mem::transmute(val & 0x01) }
2339 }
2340 #[inline(always)]
2341 pub const fn to_bits(self) -> u8 {
2342 unsafe { core::mem::transmute(self) }
2343 }
2344 }
2345 impl From<u8> for Trgsens {
2346 #[inline(always)]
2347 fn from(val: u8) -> Trgsens {
2348 Trgsens::from_bits(val)
2349 }
2350 }
2351 impl From<Trgsens> for u8 {
2352 #[inline(always)]
2353 fn from(val: Trgsens) -> u8 {
2354 Trgsens::to_bits(val)
2355 }
2356 }
2357 #[doc = "Digital filter trigger signal selection."]
2358 #[repr(u8)]
2359 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2360 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2361 pub enum Trgsrc {
2362 #[doc = "TRGO Selected."]
2363 TRGO = 0x0,
2364 _RESERVED_1 = 0x01,
2365 #[doc = "adf_trg1 selected."]
2366 TRG1 = 0x02,
2367 _RESERVED_3 = 0x03,
2368 _RESERVED_4 = 0x04,
2369 _RESERVED_5 = 0x05,
2370 _RESERVED_6 = 0x06,
2371 _RESERVED_7 = 0x07,
2372 _RESERVED_8 = 0x08,
2373 _RESERVED_9 = 0x09,
2374 _RESERVED_a = 0x0a,
2375 _RESERVED_b = 0x0b,
2376 _RESERVED_c = 0x0c,
2377 _RESERVED_d = 0x0d,
2378 _RESERVED_e = 0x0e,
2379 _RESERVED_f = 0x0f,
2380 }
2381 impl Trgsrc {
2382 #[inline(always)]
2383 pub const fn from_bits(val: u8) -> Trgsrc {
2384 unsafe { core::mem::transmute(val & 0x0f) }
2385 }
2386 #[inline(always)]
2387 pub const fn to_bits(self) -> u8 {
2388 unsafe { core::mem::transmute(self) }
2389 }
2390 }
2391 impl From<u8> for Trgsrc {
2392 #[inline(always)]
2393 fn from(val: u8) -> Trgsrc {
2394 Trgsrc::from_bits(val)
2395 }
2396 }
2397 impl From<Trgsrc> for u8 {
2398 #[inline(always)]
2399 fn from(val: Trgsrc) -> u8 {
2400 Trgsrc::to_bits(val)
2401 }
2402 }
2403}
2404