1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Controller area network with flexible data rate (FD)"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Fdcan {
9 ptr: *mut u8,
10}
11unsafe impl Send for Fdcan {}
12unsafe impl Sync for Fdcan {}
13impl Fdcan {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "FDCAN core release register"]
23 #[inline(always)]
24 pub const fn crel(self) -> crate::common::Reg<regs::Crel, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "FDCAN endian register"]
28 #[inline(always)]
29 pub const fn endn(self) -> crate::common::Reg<regs::Endn, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "FDCAN data bit timing and prescaler register"]
33 #[inline(always)]
34 pub const fn dbtp(self) -> crate::common::Reg<regs::Dbtp, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
36 }
37 #[doc = "FDCAN test register"]
38 #[inline(always)]
39 pub const fn test(self) -> crate::common::Reg<regs::Test, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
41 }
42 #[doc = "FDCAN RAM watchdog register"]
43 #[inline(always)]
44 pub const fn rwd(self) -> crate::common::Reg<regs::Rwd, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
46 }
47 #[doc = "FDCAN CC control register"]
48 #[inline(always)]
49 pub const fn cccr(self) -> crate::common::Reg<regs::Cccr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
51 }
52 #[doc = "FDCAN nominal bit timing and prescaler register"]
53 #[inline(always)]
54 pub const fn nbtp(self) -> crate::common::Reg<regs::Nbtp, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
56 }
57 #[doc = "FDCAN timestamp counter configuration register"]
58 #[inline(always)]
59 pub const fn tscc(self) -> crate::common::Reg<regs::Tscc, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
61 }
62 #[doc = "FDCAN timestamp counter value register"]
63 #[inline(always)]
64 pub const fn tscv(self) -> crate::common::Reg<regs::Tscv, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
66 }
67 #[doc = "FDCAN timeout counter configuration register"]
68 #[inline(always)]
69 pub const fn tocc(self) -> crate::common::Reg<regs::Tocc, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
71 }
72 #[doc = "FDCAN timeout counter value register"]
73 #[inline(always)]
74 pub const fn tocv(self) -> crate::common::Reg<regs::Tocv, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
76 }
77 #[doc = "FDCAN error counter register"]
78 #[inline(always)]
79 pub const fn ecr(self) -> crate::common::Reg<regs::Ecr, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
81 }
82 #[doc = "FDCAN protocol status register"]
83 #[inline(always)]
84 pub const fn psr(self) -> crate::common::Reg<regs::Psr, crate::common::RW> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
86 }
87 #[doc = "FDCAN transmitter delay compensation register"]
88 #[inline(always)]
89 pub const fn tdcr(self) -> crate::common::Reg<regs::Tdcr, crate::common::RW> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
91 }
92 #[doc = "FDCAN interrupt register"]
93 #[inline(always)]
94 pub const fn ir(self) -> crate::common::Reg<regs::Ir, crate::common::RW> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
96 }
97 #[doc = "FDCAN interrupt enable register"]
98 #[inline(always)]
99 pub const fn ie(self) -> crate::common::Reg<regs::Ie, crate::common::RW> {
100 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
101 }
102 #[doc = "FDCAN interrupt line select register"]
103 #[inline(always)]
104 pub const fn ils(self) -> crate::common::Reg<regs::Ils, crate::common::RW> {
105 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
106 }
107 #[doc = "FDCAN interrupt line enable register"]
108 #[inline(always)]
109 pub const fn ile(self) -> crate::common::Reg<regs::Ile, crate::common::RW> {
110 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
111 }
112 #[doc = "FDCAN global filter configuration register"]
113 #[inline(always)]
114 pub const fn rxgfc(self) -> crate::common::Reg<regs::Rxgfc, crate::common::RW> {
115 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
116 }
117 #[doc = "FDCAN extended ID and mask register"]
118 #[inline(always)]
119 pub const fn xidam(self) -> crate::common::Reg<regs::Xidam, crate::common::RW> {
120 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
121 }
122 #[doc = "FDCAN high-priority message status register"]
123 #[inline(always)]
124 pub const fn hpms(self) -> crate::common::Reg<regs::Hpms, crate::common::RW> {
125 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
126 }
127 #[doc = "FDCAN Rx FIFO X status register"]
128 #[inline(always)]
129 pub const fn rxfs(self, n: usize) -> crate::common::Reg<regs::Rxfs, crate::common::RW> {
130 assert!(n < 2usize);
131 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize + ([0usize, 8usize][n] as usize)) as _) }
132 }
133 #[doc = "CAN Rx FIFO X acknowledge register"]
134 #[inline(always)]
135 pub const fn rxfa(self, n: usize) -> crate::common::Reg<regs::Rxfa, crate::common::RW> {
136 assert!(n < 2usize);
137 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize + ([0usize, 8usize][n] as usize)) as _) }
138 }
139 #[doc = "FDCAN Tx buffer configuration register"]
140 #[inline(always)]
141 pub const fn txbc(self) -> crate::common::Reg<regs::Txbc, crate::common::RW> {
142 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
143 }
144 #[doc = "FDCAN Tx FIFO/queue status register"]
145 #[inline(always)]
146 pub const fn txfqs(self) -> crate::common::Reg<regs::Txfqs, crate::common::RW> {
147 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
148 }
149 #[doc = "FDCAN Tx buffer request pending register"]
150 #[inline(always)]
151 pub const fn txbrp(self) -> crate::common::Reg<regs::Txbrp, crate::common::RW> {
152 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) }
153 }
154 #[doc = "FDCAN Tx buffer add request register"]
155 #[inline(always)]
156 pub const fn txbar(self) -> crate::common::Reg<regs::Txbar, crate::common::RW> {
157 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xccusize) as _) }
158 }
159 #[doc = "FDCAN Tx buffer cancellation request register"]
160 #[inline(always)]
161 pub const fn txbcr(self) -> crate::common::Reg<regs::Txbcr, crate::common::RW> {
162 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) }
163 }
164 #[doc = "FDCAN Tx buffer transmission occurred register"]
165 #[inline(always)]
166 pub const fn txbto(self) -> crate::common::Reg<regs::Txbto, crate::common::RW> {
167 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd4usize) as _) }
168 }
169 #[doc = "FDCAN Tx buffer cancellation finished register"]
170 #[inline(always)]
171 pub const fn txbcf(self) -> crate::common::Reg<regs::Txbcf, crate::common::RW> {
172 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) }
173 }
174 #[doc = "FDCAN Tx buffer transmission interrupt enable register"]
175 #[inline(always)]
176 pub const fn txbtie(self) -> crate::common::Reg<regs::Txbtie, crate::common::RW> {
177 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) }
178 }
179 #[doc = "FDCAN Tx buffer cancellation finished interrupt enable register"]
180 #[inline(always)]
181 pub const fn txbcie(self) -> crate::common::Reg<regs::Txbcie, crate::common::RW> {
182 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) }
183 }
184 #[doc = "FDCAN Tx event FIFO status register"]
185 #[inline(always)]
186 pub const fn txefs(self) -> crate::common::Reg<regs::Txefs, crate::common::RW> {
187 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) }
188 }
189 #[doc = "FDCAN Tx event FIFO acknowledge register"]
190 #[inline(always)]
191 pub const fn txefa(self) -> crate::common::Reg<regs::Txefa, crate::common::RW> {
192 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) }
193 }
194 #[doc = "FDCAN CFG clock divider register"]
195 #[inline(always)]
196 pub const fn ckdiv(self) -> crate::common::Reg<regs::Ckdiv, crate::common::RW> {
197 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) }
198 }
199}
200pub mod regs {
201 #[doc = "FDCAN CC control register"]
202 #[repr(transparent)]
203 #[derive(Copy, Clone, Eq, PartialEq)]
204 pub struct Cccr(pub u32);
205 impl Cccr {
206 #[doc = "Initialization"]
207 #[inline(always)]
208 pub const fn init(&self) -> bool {
209 let val = (self.0 >> 0usize) & 0x01;
210 val != 0
211 }
212 #[doc = "Initialization"]
213 #[inline(always)]
214 pub fn set_init(&mut self, val: bool) {
215 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
216 }
217 #[doc = "Configuration change enable"]
218 #[inline(always)]
219 pub const fn cce(&self) -> bool {
220 let val = (self.0 >> 1usize) & 0x01;
221 val != 0
222 }
223 #[doc = "Configuration change enable"]
224 #[inline(always)]
225 pub fn set_cce(&mut self, val: bool) {
226 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
227 }
228 #[doc = "ASM restricted operation mode. The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time"]
229 #[inline(always)]
230 pub const fn asm(&self) -> bool {
231 let val = (self.0 >> 2usize) & 0x01;
232 val != 0
233 }
234 #[doc = "ASM restricted operation mode. The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time"]
235 #[inline(always)]
236 pub fn set_asm(&mut self, val: bool) {
237 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
238 }
239 #[doc = "Clock stop acknowledge"]
240 #[inline(always)]
241 pub const fn csa(&self) -> bool {
242 let val = (self.0 >> 3usize) & 0x01;
243 val != 0
244 }
245 #[doc = "Clock stop acknowledge"]
246 #[inline(always)]
247 pub fn set_csa(&mut self, val: bool) {
248 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
249 }
250 #[doc = "Clock stop request"]
251 #[inline(always)]
252 pub const fn csr(&self) -> bool {
253 let val = (self.0 >> 4usize) & 0x01;
254 val != 0
255 }
256 #[doc = "Clock stop request"]
257 #[inline(always)]
258 pub fn set_csr(&mut self, val: bool) {
259 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
260 }
261 #[doc = "Bus monitoring mode. Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time"]
262 #[inline(always)]
263 pub const fn mon(&self) -> bool {
264 let val = (self.0 >> 5usize) & 0x01;
265 val != 0
266 }
267 #[doc = "Bus monitoring mode. Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time"]
268 #[inline(always)]
269 pub fn set_mon(&mut self, val: bool) {
270 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
271 }
272 #[doc = "Disable automatic retransmission"]
273 #[inline(always)]
274 pub const fn dar(&self) -> bool {
275 let val = (self.0 >> 6usize) & 0x01;
276 val != 0
277 }
278 #[doc = "Disable automatic retransmission"]
279 #[inline(always)]
280 pub fn set_dar(&mut self, val: bool) {
281 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
282 }
283 #[doc = "Test mode enable"]
284 #[inline(always)]
285 pub const fn test(&self) -> bool {
286 let val = (self.0 >> 7usize) & 0x01;
287 val != 0
288 }
289 #[doc = "Test mode enable"]
290 #[inline(always)]
291 pub fn set_test(&mut self, val: bool) {
292 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
293 }
294 #[doc = "FD operation enable"]
295 #[inline(always)]
296 pub const fn fdoe(&self) -> bool {
297 let val = (self.0 >> 8usize) & 0x01;
298 val != 0
299 }
300 #[doc = "FD operation enable"]
301 #[inline(always)]
302 pub fn set_fdoe(&mut self, val: bool) {
303 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
304 }
305 #[doc = "FDCAN bit rate switching"]
306 #[inline(always)]
307 pub const fn brse(&self) -> bool {
308 let val = (self.0 >> 9usize) & 0x01;
309 val != 0
310 }
311 #[doc = "FDCAN bit rate switching"]
312 #[inline(always)]
313 pub fn set_brse(&mut self, val: bool) {
314 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
315 }
316 #[doc = "Protocol exception handling disable"]
317 #[inline(always)]
318 pub const fn pxhd(&self) -> bool {
319 let val = (self.0 >> 12usize) & 0x01;
320 val != 0
321 }
322 #[doc = "Protocol exception handling disable"]
323 #[inline(always)]
324 pub fn set_pxhd(&mut self, val: bool) {
325 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
326 }
327 #[doc = "Edge filtering during bus integration"]
328 #[inline(always)]
329 pub const fn efbi(&self) -> bool {
330 let val = (self.0 >> 13usize) & 0x01;
331 val != 0
332 }
333 #[doc = "Edge filtering during bus integration"]
334 #[inline(always)]
335 pub fn set_efbi(&mut self, val: bool) {
336 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
337 }
338 #[doc = "If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame"]
339 #[inline(always)]
340 pub const fn txp(&self) -> bool {
341 let val = (self.0 >> 14usize) & 0x01;
342 val != 0
343 }
344 #[doc = "If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame"]
345 #[inline(always)]
346 pub fn set_txp(&mut self, val: bool) {
347 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
348 }
349 #[doc = "Non ISO operation. If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0"]
350 #[inline(always)]
351 pub const fn niso(&self) -> bool {
352 let val = (self.0 >> 15usize) & 0x01;
353 val != 0
354 }
355 #[doc = "Non ISO operation. If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0"]
356 #[inline(always)]
357 pub fn set_niso(&mut self, val: bool) {
358 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
359 }
360 }
361 impl Default for Cccr {
362 #[inline(always)]
363 fn default() -> Cccr {
364 Cccr(0)
365 }
366 }
367 impl core::fmt::Debug for Cccr {
368 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
369 f.debug_struct("Cccr")
370 .field("init", &self.init())
371 .field("cce", &self.cce())
372 .field("asm", &self.asm())
373 .field("csa", &self.csa())
374 .field("csr", &self.csr())
375 .field("mon", &self.mon())
376 .field("dar", &self.dar())
377 .field("test", &self.test())
378 .field("fdoe", &self.fdoe())
379 .field("brse", &self.brse())
380 .field("pxhd", &self.pxhd())
381 .field("efbi", &self.efbi())
382 .field("txp", &self.txp())
383 .field("niso", &self.niso())
384 .finish()
385 }
386 }
387 #[cfg(feature = "defmt")]
388 impl defmt::Format for Cccr {
389 fn format(&self, f: defmt::Formatter) {
390 #[derive(defmt :: Format)]
391 struct Cccr {
392 init: bool,
393 cce: bool,
394 asm: bool,
395 csa: bool,
396 csr: bool,
397 mon: bool,
398 dar: bool,
399 test: bool,
400 fdoe: bool,
401 brse: bool,
402 pxhd: bool,
403 efbi: bool,
404 txp: bool,
405 niso: bool,
406 }
407 let proxy = Cccr {
408 init: self.init(),
409 cce: self.cce(),
410 asm: self.asm(),
411 csa: self.csa(),
412 csr: self.csr(),
413 mon: self.mon(),
414 dar: self.dar(),
415 test: self.test(),
416 fdoe: self.fdoe(),
417 brse: self.brse(),
418 pxhd: self.pxhd(),
419 efbi: self.efbi(),
420 txp: self.txp(),
421 niso: self.niso(),
422 };
423 defmt::write!(f, "{}", proxy)
424 }
425 }
426 #[doc = "FDCAN CFG clock divider register"]
427 #[repr(transparent)]
428 #[derive(Copy, Clone, Eq, PartialEq)]
429 pub struct Ckdiv(pub u32);
430 impl Ckdiv {
431 #[doc = "input clock divider. The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
432and bit 0 \\[INIT\\]
433of CCCR register are set to 1"]
434 #[inline(always)]
435 pub const fn pdiv(&self) -> super::vals::Pdiv {
436 let val = (self.0 >> 0usize) & 0x0f;
437 super::vals::Pdiv::from_bits(val as u8)
438 }
439 #[doc = "input clock divider. The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
440and bit 0 \\[INIT\\]
441of CCCR register are set to 1"]
442 #[inline(always)]
443 pub fn set_pdiv(&mut self, val: super::vals::Pdiv) {
444 self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize);
445 }
446 }
447 impl Default for Ckdiv {
448 #[inline(always)]
449 fn default() -> Ckdiv {
450 Ckdiv(0)
451 }
452 }
453 impl core::fmt::Debug for Ckdiv {
454 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
455 f.debug_struct("Ckdiv").field("pdiv", &self.pdiv()).finish()
456 }
457 }
458 #[cfg(feature = "defmt")]
459 impl defmt::Format for Ckdiv {
460 fn format(&self, f: defmt::Formatter) {
461 #[derive(defmt :: Format)]
462 struct Ckdiv {
463 pdiv: super::vals::Pdiv,
464 }
465 let proxy = Ckdiv { pdiv: self.pdiv() };
466 defmt::write!(f, "{}", proxy)
467 }
468 }
469 #[doc = "FDCAN core release register"]
470 #[repr(transparent)]
471 #[derive(Copy, Clone, Eq, PartialEq)]
472 pub struct Crel(pub u32);
473 impl Crel {
474 #[doc = "DAY"]
475 #[inline(always)]
476 pub const fn day(&self) -> u8 {
477 let val = (self.0 >> 0usize) & 0xff;
478 val as u8
479 }
480 #[doc = "DAY"]
481 #[inline(always)]
482 pub fn set_day(&mut self, val: u8) {
483 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
484 }
485 #[doc = "MON"]
486 #[inline(always)]
487 pub const fn mon(&self) -> u8 {
488 let val = (self.0 >> 8usize) & 0xff;
489 val as u8
490 }
491 #[doc = "MON"]
492 #[inline(always)]
493 pub fn set_mon(&mut self, val: u8) {
494 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
495 }
496 #[doc = "YEAR"]
497 #[inline(always)]
498 pub const fn year(&self) -> u8 {
499 let val = (self.0 >> 16usize) & 0x0f;
500 val as u8
501 }
502 #[doc = "YEAR"]
503 #[inline(always)]
504 pub fn set_year(&mut self, val: u8) {
505 self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
506 }
507 #[doc = "SUBSTEP"]
508 #[inline(always)]
509 pub const fn substep(&self) -> u8 {
510 let val = (self.0 >> 20usize) & 0x0f;
511 val as u8
512 }
513 #[doc = "SUBSTEP"]
514 #[inline(always)]
515 pub fn set_substep(&mut self, val: u8) {
516 self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
517 }
518 #[doc = "STEP"]
519 #[inline(always)]
520 pub const fn step(&self) -> u8 {
521 let val = (self.0 >> 24usize) & 0x0f;
522 val as u8
523 }
524 #[doc = "STEP"]
525 #[inline(always)]
526 pub fn set_step(&mut self, val: u8) {
527 self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
528 }
529 #[doc = "REL"]
530 #[inline(always)]
531 pub const fn rel(&self) -> u8 {
532 let val = (self.0 >> 28usize) & 0x0f;
533 val as u8
534 }
535 #[doc = "REL"]
536 #[inline(always)]
537 pub fn set_rel(&mut self, val: u8) {
538 self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
539 }
540 }
541 impl Default for Crel {
542 #[inline(always)]
543 fn default() -> Crel {
544 Crel(0)
545 }
546 }
547 impl core::fmt::Debug for Crel {
548 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
549 f.debug_struct("Crel")
550 .field("day", &self.day())
551 .field("mon", &self.mon())
552 .field("year", &self.year())
553 .field("substep", &self.substep())
554 .field("step", &self.step())
555 .field("rel", &self.rel())
556 .finish()
557 }
558 }
559 #[cfg(feature = "defmt")]
560 impl defmt::Format for Crel {
561 fn format(&self, f: defmt::Formatter) {
562 #[derive(defmt :: Format)]
563 struct Crel {
564 day: u8,
565 mon: u8,
566 year: u8,
567 substep: u8,
568 step: u8,
569 rel: u8,
570 }
571 let proxy = Crel {
572 day: self.day(),
573 mon: self.mon(),
574 year: self.year(),
575 substep: self.substep(),
576 step: self.step(),
577 rel: self.rel(),
578 };
579 defmt::write!(f, "{}", proxy)
580 }
581 }
582 #[doc = "FDCAN data bit timing and prescaler register"]
583 #[repr(transparent)]
584 #[derive(Copy, Clone, Eq, PartialEq)]
585 pub struct Dbtp(pub u32);
586 impl Dbtp {
587 #[doc = "Synchronization jump width. Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq."]
588 #[inline(always)]
589 pub const fn dsjw(&self) -> u8 {
590 let val = (self.0 >> 0usize) & 0x0f;
591 val as u8
592 }
593 #[doc = "Synchronization jump width. Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq."]
594 #[inline(always)]
595 pub fn set_dsjw(&mut self, val: u8) {
596 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
597 }
598 #[doc = "Data time segment after sample point. Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq"]
599 #[inline(always)]
600 pub const fn dtseg2(&self) -> u8 {
601 let val = (self.0 >> 4usize) & 0x0f;
602 val as u8
603 }
604 #[doc = "Data time segment after sample point. Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq"]
605 #[inline(always)]
606 pub fn set_dtseg2(&mut self, val: u8) {
607 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
608 }
609 #[doc = "Data time segment before sample point. Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq"]
610 #[inline(always)]
611 pub const fn dtseg1(&self) -> u8 {
612 let val = (self.0 >> 8usize) & 0x1f;
613 val as u8
614 }
615 #[doc = "Data time segment before sample point. Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq"]
616 #[inline(always)]
617 pub fn set_dtseg1(&mut self, val: u8) {
618 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
619 }
620 #[doc = "Data bit rate prescaler. The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1"]
621 #[inline(always)]
622 pub const fn dbrp(&self) -> u8 {
623 let val = (self.0 >> 16usize) & 0x1f;
624 val as u8
625 }
626 #[doc = "Data bit rate prescaler. The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1"]
627 #[inline(always)]
628 pub fn set_dbrp(&mut self, val: u8) {
629 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
630 }
631 #[doc = "Transceiver delay compensation"]
632 #[inline(always)]
633 pub const fn tdc(&self) -> bool {
634 let val = (self.0 >> 23usize) & 0x01;
635 val != 0
636 }
637 #[doc = "Transceiver delay compensation"]
638 #[inline(always)]
639 pub fn set_tdc(&mut self, val: bool) {
640 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
641 }
642 }
643 impl Default for Dbtp {
644 #[inline(always)]
645 fn default() -> Dbtp {
646 Dbtp(0)
647 }
648 }
649 impl core::fmt::Debug for Dbtp {
650 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
651 f.debug_struct("Dbtp")
652 .field("dsjw", &self.dsjw())
653 .field("dtseg2", &self.dtseg2())
654 .field("dtseg1", &self.dtseg1())
655 .field("dbrp", &self.dbrp())
656 .field("tdc", &self.tdc())
657 .finish()
658 }
659 }
660 #[cfg(feature = "defmt")]
661 impl defmt::Format for Dbtp {
662 fn format(&self, f: defmt::Formatter) {
663 #[derive(defmt :: Format)]
664 struct Dbtp {
665 dsjw: u8,
666 dtseg2: u8,
667 dtseg1: u8,
668 dbrp: u8,
669 tdc: bool,
670 }
671 let proxy = Dbtp {
672 dsjw: self.dsjw(),
673 dtseg2: self.dtseg2(),
674 dtseg1: self.dtseg1(),
675 dbrp: self.dbrp(),
676 tdc: self.tdc(),
677 };
678 defmt::write!(f, "{}", proxy)
679 }
680 }
681 #[doc = "FDCAN error counter register"]
682 #[repr(transparent)]
683 #[derive(Copy, Clone, Eq, PartialEq)]
684 pub struct Ecr(pub u32);
685 impl Ecr {
686 #[doc = "Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented"]
687 #[inline(always)]
688 pub const fn tec(&self) -> u8 {
689 let val = (self.0 >> 0usize) & 0xff;
690 val as u8
691 }
692 #[doc = "Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented"]
693 #[inline(always)]
694 pub fn set_tec(&mut self, val: u8) {
695 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
696 }
697 #[doc = "Receive error counter. Actual state of the receive error counter, values between 0 and 127"]
698 #[inline(always)]
699 pub const fn rec(&self) -> u8 {
700 let val = (self.0 >> 8usize) & 0x7f;
701 val as u8
702 }
703 #[doc = "Receive error counter. Actual state of the receive error counter, values between 0 and 127"]
704 #[inline(always)]
705 pub fn set_rec(&mut self, val: u8) {
706 self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize);
707 }
708 #[doc = "Receive error passive"]
709 #[inline(always)]
710 pub const fn rp(&self) -> bool {
711 let val = (self.0 >> 15usize) & 0x01;
712 val != 0
713 }
714 #[doc = "Receive error passive"]
715 #[inline(always)]
716 pub fn set_rp(&mut self, val: bool) {
717 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
718 }
719 #[doc = "CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR\\[ELO\\]. Access type is RX: reset on read."]
720 #[inline(always)]
721 pub const fn cel(&self) -> u8 {
722 let val = (self.0 >> 16usize) & 0xff;
723 val as u8
724 }
725 #[doc = "CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR\\[ELO\\]. Access type is RX: reset on read."]
726 #[inline(always)]
727 pub fn set_cel(&mut self, val: u8) {
728 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
729 }
730 }
731 impl Default for Ecr {
732 #[inline(always)]
733 fn default() -> Ecr {
734 Ecr(0)
735 }
736 }
737 impl core::fmt::Debug for Ecr {
738 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
739 f.debug_struct("Ecr")
740 .field("tec", &self.tec())
741 .field("rec", &self.rec())
742 .field("rp", &self.rp())
743 .field("cel", &self.cel())
744 .finish()
745 }
746 }
747 #[cfg(feature = "defmt")]
748 impl defmt::Format for Ecr {
749 fn format(&self, f: defmt::Formatter) {
750 #[derive(defmt :: Format)]
751 struct Ecr {
752 tec: u8,
753 rec: u8,
754 rp: bool,
755 cel: u8,
756 }
757 let proxy = Ecr {
758 tec: self.tec(),
759 rec: self.rec(),
760 rp: self.rp(),
761 cel: self.cel(),
762 };
763 defmt::write!(f, "{}", proxy)
764 }
765 }
766 #[doc = "FDCAN endian register"]
767 #[repr(transparent)]
768 #[derive(Copy, Clone, Eq, PartialEq)]
769 pub struct Endn(pub u32);
770 impl Endn {
771 #[doc = "Endianness test value. The endianness test value is 0x8765 4321"]
772 #[inline(always)]
773 pub const fn etv(&self) -> u32 {
774 let val = (self.0 >> 0usize) & 0xffff_ffff;
775 val as u32
776 }
777 #[doc = "Endianness test value. The endianness test value is 0x8765 4321"]
778 #[inline(always)]
779 pub fn set_etv(&mut self, val: u32) {
780 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
781 }
782 }
783 impl Default for Endn {
784 #[inline(always)]
785 fn default() -> Endn {
786 Endn(0)
787 }
788 }
789 impl core::fmt::Debug for Endn {
790 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
791 f.debug_struct("Endn").field("etv", &self.etv()).finish()
792 }
793 }
794 #[cfg(feature = "defmt")]
795 impl defmt::Format for Endn {
796 fn format(&self, f: defmt::Formatter) {
797 #[derive(defmt :: Format)]
798 struct Endn {
799 etv: u32,
800 }
801 let proxy = Endn { etv: self.etv() };
802 defmt::write!(f, "{}", proxy)
803 }
804 }
805 #[doc = "FDCAN high-priority message status register"]
806 #[repr(transparent)]
807 #[derive(Copy, Clone, Eq, PartialEq)]
808 pub struct Hpms(pub u32);
809 impl Hpms {
810 #[doc = "Buffer index. Index of Rx FIFO element to which the message was stored. Only valid when MSI\\[1\\]
811= 1"]
812 #[inline(always)]
813 pub const fn bidx(&self) -> u8 {
814 let val = (self.0 >> 0usize) & 0x07;
815 val as u8
816 }
817 #[doc = "Buffer index. Index of Rx FIFO element to which the message was stored. Only valid when MSI\\[1\\]
818= 1"]
819 #[inline(always)]
820 pub fn set_bidx(&mut self, val: u8) {
821 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
822 }
823 #[doc = "Message storage indicator"]
824 #[inline(always)]
825 pub const fn msi(&self) -> super::vals::Msi {
826 let val = (self.0 >> 6usize) & 0x03;
827 super::vals::Msi::from_bits(val as u8)
828 }
829 #[doc = "Message storage indicator"]
830 #[inline(always)]
831 pub fn set_msi(&mut self, val: super::vals::Msi) {
832 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
833 }
834 #[doc = "Filter index. Index of matching filter element. Range is 0 to RXGFC\\[LSS\\]
835- 1 or RXGFC\\[LSE\\]
836- 1"]
837 #[inline(always)]
838 pub const fn fidx(&self) -> u8 {
839 let val = (self.0 >> 8usize) & 0x1f;
840 val as u8
841 }
842 #[doc = "Filter index. Index of matching filter element. Range is 0 to RXGFC\\[LSS\\]
843- 1 or RXGFC\\[LSE\\]
844- 1"]
845 #[inline(always)]
846 pub fn set_fidx(&mut self, val: u8) {
847 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
848 }
849 #[doc = "Filter list. Indicates the filter list of the matching filter element"]
850 #[inline(always)]
851 pub const fn flst(&self) -> bool {
852 let val = (self.0 >> 15usize) & 0x01;
853 val != 0
854 }
855 #[doc = "Filter list. Indicates the filter list of the matching filter element"]
856 #[inline(always)]
857 pub fn set_flst(&mut self, val: bool) {
858 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
859 }
860 }
861 impl Default for Hpms {
862 #[inline(always)]
863 fn default() -> Hpms {
864 Hpms(0)
865 }
866 }
867 impl core::fmt::Debug for Hpms {
868 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
869 f.debug_struct("Hpms")
870 .field("bidx", &self.bidx())
871 .field("msi", &self.msi())
872 .field("fidx", &self.fidx())
873 .field("flst", &self.flst())
874 .finish()
875 }
876 }
877 #[cfg(feature = "defmt")]
878 impl defmt::Format for Hpms {
879 fn format(&self, f: defmt::Formatter) {
880 #[derive(defmt :: Format)]
881 struct Hpms {
882 bidx: u8,
883 msi: super::vals::Msi,
884 fidx: u8,
885 flst: bool,
886 }
887 let proxy = Hpms {
888 bidx: self.bidx(),
889 msi: self.msi(),
890 fidx: self.fidx(),
891 flst: self.flst(),
892 };
893 defmt::write!(f, "{}", proxy)
894 }
895 }
896 #[doc = "FDCAN interrupt enable register"]
897 #[repr(transparent)]
898 #[derive(Copy, Clone, Eq, PartialEq)]
899 pub struct Ie(pub u32);
900 impl Ie {
901 #[doc = "Rx FIFO X new message interrupt enable"]
902 #[inline(always)]
903 pub const fn rfne(&self, n: usize) -> bool {
904 assert!(n < 2usize);
905 let offs = 0usize + ([0usize, 3usize][n] as usize);
906 let val = (self.0 >> offs) & 0x01;
907 val != 0
908 }
909 #[doc = "Rx FIFO X new message interrupt enable"]
910 #[inline(always)]
911 pub fn set_rfne(&mut self, n: usize, val: bool) {
912 assert!(n < 2usize);
913 let offs = 0usize + ([0usize, 3usize][n] as usize);
914 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
915 }
916 #[doc = "Rx FIFO X full interrupt enable"]
917 #[inline(always)]
918 pub const fn rffe(&self, n: usize) -> bool {
919 assert!(n < 2usize);
920 let offs = 1usize + ([0usize, 3usize][n] as usize);
921 let val = (self.0 >> offs) & 0x01;
922 val != 0
923 }
924 #[doc = "Rx FIFO X full interrupt enable"]
925 #[inline(always)]
926 pub fn set_rffe(&mut self, n: usize, val: bool) {
927 assert!(n < 2usize);
928 let offs = 1usize + ([0usize, 3usize][n] as usize);
929 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
930 }
931 #[doc = "Rx FIFO X message lost interrupt enable"]
932 #[inline(always)]
933 pub const fn rfle(&self, n: usize) -> bool {
934 assert!(n < 2usize);
935 let offs = 2usize + ([0usize, 3usize][n] as usize);
936 let val = (self.0 >> offs) & 0x01;
937 val != 0
938 }
939 #[doc = "Rx FIFO X message lost interrupt enable"]
940 #[inline(always)]
941 pub fn set_rfle(&mut self, n: usize, val: bool) {
942 assert!(n < 2usize);
943 let offs = 2usize + ([0usize, 3usize][n] as usize);
944 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
945 }
946 #[doc = "High-priority message interrupt enable"]
947 #[inline(always)]
948 pub const fn hpme(&self) -> bool {
949 let val = (self.0 >> 6usize) & 0x01;
950 val != 0
951 }
952 #[doc = "High-priority message interrupt enable"]
953 #[inline(always)]
954 pub fn set_hpme(&mut self, val: bool) {
955 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
956 }
957 #[doc = "Transmission completed interrupt enable"]
958 #[inline(always)]
959 pub const fn tce(&self) -> bool {
960 let val = (self.0 >> 7usize) & 0x01;
961 val != 0
962 }
963 #[doc = "Transmission completed interrupt enable"]
964 #[inline(always)]
965 pub fn set_tce(&mut self, val: bool) {
966 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
967 }
968 #[doc = "Transmission cancellation finished interrupt enable"]
969 #[inline(always)]
970 pub const fn tcfe(&self) -> bool {
971 let val = (self.0 >> 8usize) & 0x01;
972 val != 0
973 }
974 #[doc = "Transmission cancellation finished interrupt enable"]
975 #[inline(always)]
976 pub fn set_tcfe(&mut self, val: bool) {
977 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
978 }
979 #[doc = "Tx FIFO empty interrupt enable"]
980 #[inline(always)]
981 pub const fn tfee(&self) -> bool {
982 let val = (self.0 >> 9usize) & 0x01;
983 val != 0
984 }
985 #[doc = "Tx FIFO empty interrupt enable"]
986 #[inline(always)]
987 pub fn set_tfee(&mut self, val: bool) {
988 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
989 }
990 #[doc = "Tx event FIFO new entry interrupt enable"]
991 #[inline(always)]
992 pub const fn tefne(&self) -> bool {
993 let val = (self.0 >> 10usize) & 0x01;
994 val != 0
995 }
996 #[doc = "Tx event FIFO new entry interrupt enable"]
997 #[inline(always)]
998 pub fn set_tefne(&mut self, val: bool) {
999 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1000 }
1001 #[doc = "Tx event FIFO full interrupt enable"]
1002 #[inline(always)]
1003 pub const fn teffe(&self) -> bool {
1004 let val = (self.0 >> 11usize) & 0x01;
1005 val != 0
1006 }
1007 #[doc = "Tx event FIFO full interrupt enable"]
1008 #[inline(always)]
1009 pub fn set_teffe(&mut self, val: bool) {
1010 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1011 }
1012 #[doc = "Tx event FIFO element lost interrupt enable"]
1013 #[inline(always)]
1014 pub const fn tefle(&self) -> bool {
1015 let val = (self.0 >> 12usize) & 0x01;
1016 val != 0
1017 }
1018 #[doc = "Tx event FIFO element lost interrupt enable"]
1019 #[inline(always)]
1020 pub fn set_tefle(&mut self, val: bool) {
1021 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1022 }
1023 #[doc = "Timestamp wraparound interrupt enable"]
1024 #[inline(always)]
1025 pub const fn tswe(&self) -> bool {
1026 let val = (self.0 >> 13usize) & 0x01;
1027 val != 0
1028 }
1029 #[doc = "Timestamp wraparound interrupt enable"]
1030 #[inline(always)]
1031 pub fn set_tswe(&mut self, val: bool) {
1032 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1033 }
1034 #[doc = "Message RAM access failure interrupt enable"]
1035 #[inline(always)]
1036 pub const fn mrafe(&self) -> bool {
1037 let val = (self.0 >> 14usize) & 0x01;
1038 val != 0
1039 }
1040 #[doc = "Message RAM access failure interrupt enable"]
1041 #[inline(always)]
1042 pub fn set_mrafe(&mut self, val: bool) {
1043 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1044 }
1045 #[doc = "Timeout occurred interrupt enable"]
1046 #[inline(always)]
1047 pub const fn tooe(&self) -> bool {
1048 let val = (self.0 >> 15usize) & 0x01;
1049 val != 0
1050 }
1051 #[doc = "Timeout occurred interrupt enable"]
1052 #[inline(always)]
1053 pub fn set_tooe(&mut self, val: bool) {
1054 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1055 }
1056 #[doc = "Error logging overflow interrupt enable"]
1057 #[inline(always)]
1058 pub const fn eloe(&self) -> bool {
1059 let val = (self.0 >> 16usize) & 0x01;
1060 val != 0
1061 }
1062 #[doc = "Error logging overflow interrupt enable"]
1063 #[inline(always)]
1064 pub fn set_eloe(&mut self, val: bool) {
1065 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1066 }
1067 #[doc = "Error passive interrupt enable"]
1068 #[inline(always)]
1069 pub const fn epe(&self) -> bool {
1070 let val = (self.0 >> 17usize) & 0x01;
1071 val != 0
1072 }
1073 #[doc = "Error passive interrupt enable"]
1074 #[inline(always)]
1075 pub fn set_epe(&mut self, val: bool) {
1076 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1077 }
1078 #[doc = "Warning status interrupt enable"]
1079 #[inline(always)]
1080 pub const fn ewe(&self) -> bool {
1081 let val = (self.0 >> 18usize) & 0x01;
1082 val != 0
1083 }
1084 #[doc = "Warning status interrupt enable"]
1085 #[inline(always)]
1086 pub fn set_ewe(&mut self, val: bool) {
1087 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1088 }
1089 #[doc = "Bus_Off status enable"]
1090 #[inline(always)]
1091 pub const fn boe(&self) -> bool {
1092 let val = (self.0 >> 19usize) & 0x01;
1093 val != 0
1094 }
1095 #[doc = "Bus_Off status enable"]
1096 #[inline(always)]
1097 pub fn set_boe(&mut self, val: bool) {
1098 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1099 }
1100 #[doc = "Watchdog interrupt enable"]
1101 #[inline(always)]
1102 pub const fn wdie(&self) -> bool {
1103 let val = (self.0 >> 20usize) & 0x01;
1104 val != 0
1105 }
1106 #[doc = "Watchdog interrupt enable"]
1107 #[inline(always)]
1108 pub fn set_wdie(&mut self, val: bool) {
1109 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1110 }
1111 #[doc = "Protocol error in arbitration phase enable"]
1112 #[inline(always)]
1113 pub const fn peae(&self) -> bool {
1114 let val = (self.0 >> 21usize) & 0x01;
1115 val != 0
1116 }
1117 #[doc = "Protocol error in arbitration phase enable"]
1118 #[inline(always)]
1119 pub fn set_peae(&mut self, val: bool) {
1120 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1121 }
1122 #[doc = "Protocol error in data phase enable"]
1123 #[inline(always)]
1124 pub const fn pede(&self) -> bool {
1125 let val = (self.0 >> 22usize) & 0x01;
1126 val != 0
1127 }
1128 #[doc = "Protocol error in data phase enable"]
1129 #[inline(always)]
1130 pub fn set_pede(&mut self, val: bool) {
1131 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
1132 }
1133 #[doc = "Access to reserved address enable"]
1134 #[inline(always)]
1135 pub const fn arae(&self) -> bool {
1136 let val = (self.0 >> 23usize) & 0x01;
1137 val != 0
1138 }
1139 #[doc = "Access to reserved address enable"]
1140 #[inline(always)]
1141 pub fn set_arae(&mut self, val: bool) {
1142 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1143 }
1144 }
1145 impl Default for Ie {
1146 #[inline(always)]
1147 fn default() -> Ie {
1148 Ie(0)
1149 }
1150 }
1151 impl core::fmt::Debug for Ie {
1152 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1153 f.debug_struct("Ie")
1154 .field("rfne", &[self.rfne(0usize), self.rfne(1usize)])
1155 .field("rffe", &[self.rffe(0usize), self.rffe(1usize)])
1156 .field("rfle", &[self.rfle(0usize), self.rfle(1usize)])
1157 .field("hpme", &self.hpme())
1158 .field("tce", &self.tce())
1159 .field("tcfe", &self.tcfe())
1160 .field("tfee", &self.tfee())
1161 .field("tefne", &self.tefne())
1162 .field("teffe", &self.teffe())
1163 .field("tefle", &self.tefle())
1164 .field("tswe", &self.tswe())
1165 .field("mrafe", &self.mrafe())
1166 .field("tooe", &self.tooe())
1167 .field("eloe", &self.eloe())
1168 .field("epe", &self.epe())
1169 .field("ewe", &self.ewe())
1170 .field("boe", &self.boe())
1171 .field("wdie", &self.wdie())
1172 .field("peae", &self.peae())
1173 .field("pede", &self.pede())
1174 .field("arae", &self.arae())
1175 .finish()
1176 }
1177 }
1178 #[cfg(feature = "defmt")]
1179 impl defmt::Format for Ie {
1180 fn format(&self, f: defmt::Formatter) {
1181 #[derive(defmt :: Format)]
1182 struct Ie {
1183 rfne: [bool; 2usize],
1184 rffe: [bool; 2usize],
1185 rfle: [bool; 2usize],
1186 hpme: bool,
1187 tce: bool,
1188 tcfe: bool,
1189 tfee: bool,
1190 tefne: bool,
1191 teffe: bool,
1192 tefle: bool,
1193 tswe: bool,
1194 mrafe: bool,
1195 tooe: bool,
1196 eloe: bool,
1197 epe: bool,
1198 ewe: bool,
1199 boe: bool,
1200 wdie: bool,
1201 peae: bool,
1202 pede: bool,
1203 arae: bool,
1204 }
1205 let proxy = Ie {
1206 rfne: [self.rfne(0usize), self.rfne(1usize)],
1207 rffe: [self.rffe(0usize), self.rffe(1usize)],
1208 rfle: [self.rfle(0usize), self.rfle(1usize)],
1209 hpme: self.hpme(),
1210 tce: self.tce(),
1211 tcfe: self.tcfe(),
1212 tfee: self.tfee(),
1213 tefne: self.tefne(),
1214 teffe: self.teffe(),
1215 tefle: self.tefle(),
1216 tswe: self.tswe(),
1217 mrafe: self.mrafe(),
1218 tooe: self.tooe(),
1219 eloe: self.eloe(),
1220 epe: self.epe(),
1221 ewe: self.ewe(),
1222 boe: self.boe(),
1223 wdie: self.wdie(),
1224 peae: self.peae(),
1225 pede: self.pede(),
1226 arae: self.arae(),
1227 };
1228 defmt::write!(f, "{}", proxy)
1229 }
1230 }
1231 #[doc = "FDCAN interrupt line enable register"]
1232 #[repr(transparent)]
1233 #[derive(Copy, Clone, Eq, PartialEq)]
1234 pub struct Ile(pub u32);
1235 impl Ile {
1236 #[doc = "Enable interrupt line 0"]
1237 #[inline(always)]
1238 pub const fn eint0(&self) -> bool {
1239 let val = (self.0 >> 0usize) & 0x01;
1240 val != 0
1241 }
1242 #[doc = "Enable interrupt line 0"]
1243 #[inline(always)]
1244 pub fn set_eint0(&mut self, val: bool) {
1245 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1246 }
1247 #[doc = "Enable interrupt line 1"]
1248 #[inline(always)]
1249 pub const fn eint1(&self) -> bool {
1250 let val = (self.0 >> 1usize) & 0x01;
1251 val != 0
1252 }
1253 #[doc = "Enable interrupt line 1"]
1254 #[inline(always)]
1255 pub fn set_eint1(&mut self, val: bool) {
1256 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1257 }
1258 }
1259 impl Default for Ile {
1260 #[inline(always)]
1261 fn default() -> Ile {
1262 Ile(0)
1263 }
1264 }
1265 impl core::fmt::Debug for Ile {
1266 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1267 f.debug_struct("Ile")
1268 .field("eint0", &self.eint0())
1269 .field("eint1", &self.eint1())
1270 .finish()
1271 }
1272 }
1273 #[cfg(feature = "defmt")]
1274 impl defmt::Format for Ile {
1275 fn format(&self, f: defmt::Formatter) {
1276 #[derive(defmt :: Format)]
1277 struct Ile {
1278 eint0: bool,
1279 eint1: bool,
1280 }
1281 let proxy = Ile {
1282 eint0: self.eint0(),
1283 eint1: self.eint1(),
1284 };
1285 defmt::write!(f, "{}", proxy)
1286 }
1287 }
1288 #[doc = "FDCAN interrupt line select register"]
1289 #[repr(transparent)]
1290 #[derive(Copy, Clone, Eq, PartialEq)]
1291 pub struct Ils(pub u32);
1292 impl Ils {
1293 #[doc = "RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line."]
1294 #[inline(always)]
1295 pub const fn rxfifo(&self, n: usize) -> bool {
1296 assert!(n < 2usize);
1297 let offs = 0usize + n * 1usize;
1298 let val = (self.0 >> offs) & 0x01;
1299 val != 0
1300 }
1301 #[doc = "RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line."]
1302 #[inline(always)]
1303 pub fn set_rxfifo(&mut self, n: usize, val: bool) {
1304 assert!(n < 2usize);
1305 let offs = 0usize + n * 1usize;
1306 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1307 }
1308 #[doc = "Status message bit grouping the following interruption. TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line."]
1309 #[inline(always)]
1310 pub const fn smsg(&self) -> bool {
1311 let val = (self.0 >> 2usize) & 0x01;
1312 val != 0
1313 }
1314 #[doc = "Status message bit grouping the following interruption. TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line."]
1315 #[inline(always)]
1316 pub fn set_smsg(&mut self, val: bool) {
1317 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1318 }
1319 #[doc = "Tx FIFO ERROR grouping the following interruption. TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line."]
1320 #[inline(always)]
1321 pub const fn tferr(&self) -> bool {
1322 let val = (self.0 >> 3usize) & 0x01;
1323 val != 0
1324 }
1325 #[doc = "Tx FIFO ERROR grouping the following interruption. TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line."]
1326 #[inline(always)]
1327 pub fn set_tferr(&mut self, val: bool) {
1328 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1329 }
1330 #[doc = "Interrupt regrouping the following interruption. TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line."]
1331 #[inline(always)]
1332 pub const fn misc(&self) -> bool {
1333 let val = (self.0 >> 4usize) & 0x01;
1334 val != 0
1335 }
1336 #[doc = "Interrupt regrouping the following interruption. TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line."]
1337 #[inline(always)]
1338 pub fn set_misc(&mut self, val: bool) {
1339 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1340 }
1341 #[doc = "Bit and line error grouping the following interruption. EPL Error passive interrupt line ELOL: Error logging overflow interrupt line."]
1342 #[inline(always)]
1343 pub const fn berr(&self) -> bool {
1344 let val = (self.0 >> 5usize) & 0x01;
1345 val != 0
1346 }
1347 #[doc = "Bit and line error grouping the following interruption. EPL Error passive interrupt line ELOL: Error logging overflow interrupt line."]
1348 #[inline(always)]
1349 pub fn set_berr(&mut self, val: bool) {
1350 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1351 }
1352 #[doc = "Protocol error grouping the following interruption. ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line."]
1353 #[inline(always)]
1354 pub const fn perr(&self) -> bool {
1355 let val = (self.0 >> 6usize) & 0x01;
1356 val != 0
1357 }
1358 #[doc = "Protocol error grouping the following interruption. ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line."]
1359 #[inline(always)]
1360 pub fn set_perr(&mut self, val: bool) {
1361 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1362 }
1363 }
1364 impl Default for Ils {
1365 #[inline(always)]
1366 fn default() -> Ils {
1367 Ils(0)
1368 }
1369 }
1370 impl core::fmt::Debug for Ils {
1371 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1372 f.debug_struct("Ils")
1373 .field("rxfifo", &[self.rxfifo(0usize), self.rxfifo(1usize)])
1374 .field("smsg", &self.smsg())
1375 .field("tferr", &self.tferr())
1376 .field("misc", &self.misc())
1377 .field("berr", &self.berr())
1378 .field("perr", &self.perr())
1379 .finish()
1380 }
1381 }
1382 #[cfg(feature = "defmt")]
1383 impl defmt::Format for Ils {
1384 fn format(&self, f: defmt::Formatter) {
1385 #[derive(defmt :: Format)]
1386 struct Ils {
1387 rxfifo: [bool; 2usize],
1388 smsg: bool,
1389 tferr: bool,
1390 misc: bool,
1391 berr: bool,
1392 perr: bool,
1393 }
1394 let proxy = Ils {
1395 rxfifo: [self.rxfifo(0usize), self.rxfifo(1usize)],
1396 smsg: self.smsg(),
1397 tferr: self.tferr(),
1398 misc: self.misc(),
1399 berr: self.berr(),
1400 perr: self.perr(),
1401 };
1402 defmt::write!(f, "{}", proxy)
1403 }
1404 }
1405 #[doc = "FDCAN interrupt register"]
1406 #[repr(transparent)]
1407 #[derive(Copy, Clone, Eq, PartialEq)]
1408 pub struct Ir(pub u32);
1409 impl Ir {
1410 #[doc = "Rx FIFO X new message"]
1411 #[inline(always)]
1412 pub const fn rfn(&self, n: usize) -> bool {
1413 assert!(n < 2usize);
1414 let offs = 0usize + ([0usize, 3usize][n] as usize);
1415 let val = (self.0 >> offs) & 0x01;
1416 val != 0
1417 }
1418 #[doc = "Rx FIFO X new message"]
1419 #[inline(always)]
1420 pub fn set_rfn(&mut self, n: usize, val: bool) {
1421 assert!(n < 2usize);
1422 let offs = 0usize + ([0usize, 3usize][n] as usize);
1423 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1424 }
1425 #[doc = "Rx FIFO X full"]
1426 #[inline(always)]
1427 pub const fn rff(&self, n: usize) -> bool {
1428 assert!(n < 2usize);
1429 let offs = 1usize + ([0usize, 3usize][n] as usize);
1430 let val = (self.0 >> offs) & 0x01;
1431 val != 0
1432 }
1433 #[doc = "Rx FIFO X full"]
1434 #[inline(always)]
1435 pub fn set_rff(&mut self, n: usize, val: bool) {
1436 assert!(n < 2usize);
1437 let offs = 1usize + ([0usize, 3usize][n] as usize);
1438 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1439 }
1440 #[doc = "Rx FIFO X message lost"]
1441 #[inline(always)]
1442 pub const fn rfl(&self, n: usize) -> bool {
1443 assert!(n < 2usize);
1444 let offs = 2usize + ([0usize, 3usize][n] as usize);
1445 let val = (self.0 >> offs) & 0x01;
1446 val != 0
1447 }
1448 #[doc = "Rx FIFO X message lost"]
1449 #[inline(always)]
1450 pub fn set_rfl(&mut self, n: usize, val: bool) {
1451 assert!(n < 2usize);
1452 let offs = 2usize + ([0usize, 3usize][n] as usize);
1453 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1454 }
1455 #[doc = "High-priority message"]
1456 #[inline(always)]
1457 pub const fn hpm(&self) -> bool {
1458 let val = (self.0 >> 6usize) & 0x01;
1459 val != 0
1460 }
1461 #[doc = "High-priority message"]
1462 #[inline(always)]
1463 pub fn set_hpm(&mut self, val: bool) {
1464 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1465 }
1466 #[doc = "Transmission completed"]
1467 #[inline(always)]
1468 pub const fn tc(&self) -> bool {
1469 let val = (self.0 >> 7usize) & 0x01;
1470 val != 0
1471 }
1472 #[doc = "Transmission completed"]
1473 #[inline(always)]
1474 pub fn set_tc(&mut self, val: bool) {
1475 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1476 }
1477 #[doc = "Transmission cancellation finished"]
1478 #[inline(always)]
1479 pub const fn tcf(&self) -> bool {
1480 let val = (self.0 >> 8usize) & 0x01;
1481 val != 0
1482 }
1483 #[doc = "Transmission cancellation finished"]
1484 #[inline(always)]
1485 pub fn set_tcf(&mut self, val: bool) {
1486 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1487 }
1488 #[doc = "Tx FIFO empty"]
1489 #[inline(always)]
1490 pub const fn tfe(&self) -> bool {
1491 let val = (self.0 >> 9usize) & 0x01;
1492 val != 0
1493 }
1494 #[doc = "Tx FIFO empty"]
1495 #[inline(always)]
1496 pub fn set_tfe(&mut self, val: bool) {
1497 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1498 }
1499 #[doc = "Tx event FIFO New Entry"]
1500 #[inline(always)]
1501 pub const fn tefn(&self) -> bool {
1502 let val = (self.0 >> 10usize) & 0x01;
1503 val != 0
1504 }
1505 #[doc = "Tx event FIFO New Entry"]
1506 #[inline(always)]
1507 pub fn set_tefn(&mut self, val: bool) {
1508 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1509 }
1510 #[doc = "Tx event FIFO full"]
1511 #[inline(always)]
1512 pub const fn teff(&self) -> bool {
1513 let val = (self.0 >> 11usize) & 0x01;
1514 val != 0
1515 }
1516 #[doc = "Tx event FIFO full"]
1517 #[inline(always)]
1518 pub fn set_teff(&mut self, val: bool) {
1519 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1520 }
1521 #[doc = "Tx event FIFO element lost"]
1522 #[inline(always)]
1523 pub const fn tefl(&self) -> bool {
1524 let val = (self.0 >> 12usize) & 0x01;
1525 val != 0
1526 }
1527 #[doc = "Tx event FIFO element lost"]
1528 #[inline(always)]
1529 pub fn set_tefl(&mut self, val: bool) {
1530 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1531 }
1532 #[doc = "Timestamp wraparound"]
1533 #[inline(always)]
1534 pub const fn tsw(&self) -> bool {
1535 let val = (self.0 >> 13usize) & 0x01;
1536 val != 0
1537 }
1538 #[doc = "Timestamp wraparound"]
1539 #[inline(always)]
1540 pub fn set_tsw(&mut self, val: bool) {
1541 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1542 }
1543 #[doc = "Message RAM access failure. The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM."]
1544 #[inline(always)]
1545 pub const fn mraf(&self) -> bool {
1546 let val = (self.0 >> 14usize) & 0x01;
1547 val != 0
1548 }
1549 #[doc = "Message RAM access failure. The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM."]
1550 #[inline(always)]
1551 pub fn set_mraf(&mut self, val: bool) {
1552 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1553 }
1554 #[doc = "Timeout occurred"]
1555 #[inline(always)]
1556 pub const fn too(&self) -> bool {
1557 let val = (self.0 >> 15usize) & 0x01;
1558 val != 0
1559 }
1560 #[doc = "Timeout occurred"]
1561 #[inline(always)]
1562 pub fn set_too(&mut self, val: bool) {
1563 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1564 }
1565 #[doc = "Error logging overflow"]
1566 #[inline(always)]
1567 pub const fn elo(&self) -> bool {
1568 let val = (self.0 >> 16usize) & 0x01;
1569 val != 0
1570 }
1571 #[doc = "Error logging overflow"]
1572 #[inline(always)]
1573 pub fn set_elo(&mut self, val: bool) {
1574 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1575 }
1576 #[doc = "Error passive"]
1577 #[inline(always)]
1578 pub const fn ep(&self) -> bool {
1579 let val = (self.0 >> 17usize) & 0x01;
1580 val != 0
1581 }
1582 #[doc = "Error passive"]
1583 #[inline(always)]
1584 pub fn set_ep(&mut self, val: bool) {
1585 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1586 }
1587 #[doc = "Warning status"]
1588 #[inline(always)]
1589 pub const fn ew(&self) -> bool {
1590 let val = (self.0 >> 18usize) & 0x01;
1591 val != 0
1592 }
1593 #[doc = "Warning status"]
1594 #[inline(always)]
1595 pub fn set_ew(&mut self, val: bool) {
1596 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1597 }
1598 #[doc = "Bus_Off status"]
1599 #[inline(always)]
1600 pub const fn bo(&self) -> bool {
1601 let val = (self.0 >> 19usize) & 0x01;
1602 val != 0
1603 }
1604 #[doc = "Bus_Off status"]
1605 #[inline(always)]
1606 pub fn set_bo(&mut self, val: bool) {
1607 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1608 }
1609 #[doc = "Watchdog interrupt"]
1610 #[inline(always)]
1611 pub const fn wdi(&self) -> bool {
1612 let val = (self.0 >> 20usize) & 0x01;
1613 val != 0
1614 }
1615 #[doc = "Watchdog interrupt"]
1616 #[inline(always)]
1617 pub fn set_wdi(&mut self, val: bool) {
1618 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1619 }
1620 #[doc = "Protocol error in arbitration phase (nominal bit time is used)"]
1621 #[inline(always)]
1622 pub const fn pea(&self) -> bool {
1623 let val = (self.0 >> 21usize) & 0x01;
1624 val != 0
1625 }
1626 #[doc = "Protocol error in arbitration phase (nominal bit time is used)"]
1627 #[inline(always)]
1628 pub fn set_pea(&mut self, val: bool) {
1629 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1630 }
1631 #[doc = "Protocol error in data phase (data bit time is used)"]
1632 #[inline(always)]
1633 pub const fn ped(&self) -> bool {
1634 let val = (self.0 >> 22usize) & 0x01;
1635 val != 0
1636 }
1637 #[doc = "Protocol error in data phase (data bit time is used)"]
1638 #[inline(always)]
1639 pub fn set_ped(&mut self, val: bool) {
1640 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
1641 }
1642 #[doc = "Access to reserved address"]
1643 #[inline(always)]
1644 pub const fn ara(&self) -> bool {
1645 let val = (self.0 >> 23usize) & 0x01;
1646 val != 0
1647 }
1648 #[doc = "Access to reserved address"]
1649 #[inline(always)]
1650 pub fn set_ara(&mut self, val: bool) {
1651 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1652 }
1653 }
1654 impl Default for Ir {
1655 #[inline(always)]
1656 fn default() -> Ir {
1657 Ir(0)
1658 }
1659 }
1660 impl core::fmt::Debug for Ir {
1661 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1662 f.debug_struct("Ir")
1663 .field("rfn", &[self.rfn(0usize), self.rfn(1usize)])
1664 .field("rff", &[self.rff(0usize), self.rff(1usize)])
1665 .field("rfl", &[self.rfl(0usize), self.rfl(1usize)])
1666 .field("hpm", &self.hpm())
1667 .field("tc", &self.tc())
1668 .field("tcf", &self.tcf())
1669 .field("tfe", &self.tfe())
1670 .field("tefn", &self.tefn())
1671 .field("teff", &self.teff())
1672 .field("tefl", &self.tefl())
1673 .field("tsw", &self.tsw())
1674 .field("mraf", &self.mraf())
1675 .field("too", &self.too())
1676 .field("elo", &self.elo())
1677 .field("ep", &self.ep())
1678 .field("ew", &self.ew())
1679 .field("bo", &self.bo())
1680 .field("wdi", &self.wdi())
1681 .field("pea", &self.pea())
1682 .field("ped", &self.ped())
1683 .field("ara", &self.ara())
1684 .finish()
1685 }
1686 }
1687 #[cfg(feature = "defmt")]
1688 impl defmt::Format for Ir {
1689 fn format(&self, f: defmt::Formatter) {
1690 #[derive(defmt :: Format)]
1691 struct Ir {
1692 rfn: [bool; 2usize],
1693 rff: [bool; 2usize],
1694 rfl: [bool; 2usize],
1695 hpm: bool,
1696 tc: bool,
1697 tcf: bool,
1698 tfe: bool,
1699 tefn: bool,
1700 teff: bool,
1701 tefl: bool,
1702 tsw: bool,
1703 mraf: bool,
1704 too: bool,
1705 elo: bool,
1706 ep: bool,
1707 ew: bool,
1708 bo: bool,
1709 wdi: bool,
1710 pea: bool,
1711 ped: bool,
1712 ara: bool,
1713 }
1714 let proxy = Ir {
1715 rfn: [self.rfn(0usize), self.rfn(1usize)],
1716 rff: [self.rff(0usize), self.rff(1usize)],
1717 rfl: [self.rfl(0usize), self.rfl(1usize)],
1718 hpm: self.hpm(),
1719 tc: self.tc(),
1720 tcf: self.tcf(),
1721 tfe: self.tfe(),
1722 tefn: self.tefn(),
1723 teff: self.teff(),
1724 tefl: self.tefl(),
1725 tsw: self.tsw(),
1726 mraf: self.mraf(),
1727 too: self.too(),
1728 elo: self.elo(),
1729 ep: self.ep(),
1730 ew: self.ew(),
1731 bo: self.bo(),
1732 wdi: self.wdi(),
1733 pea: self.pea(),
1734 ped: self.ped(),
1735 ara: self.ara(),
1736 };
1737 defmt::write!(f, "{}", proxy)
1738 }
1739 }
1740 #[doc = "FDCAN nominal bit timing and prescaler register"]
1741 #[repr(transparent)]
1742 #[derive(Copy, Clone, Eq, PartialEq)]
1743 pub struct Nbtp(pub u32);
1744 impl Nbtp {
1745 #[doc = "Nominal time segment after sample point. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used"]
1746 #[inline(always)]
1747 pub const fn ntseg2(&self) -> u8 {
1748 let val = (self.0 >> 0usize) & 0x7f;
1749 val as u8
1750 }
1751 #[doc = "Nominal time segment after sample point. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used"]
1752 #[inline(always)]
1753 pub fn set_ntseg2(&mut self, val: u8) {
1754 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
1755 }
1756 #[doc = "Nominal time segment before sample point. Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
1757and bit 0 \\[INIT\\]
1758of CCCR register are set to 1"]
1759 #[inline(always)]
1760 pub const fn ntseg1(&self) -> u8 {
1761 let val = (self.0 >> 8usize) & 0xff;
1762 val as u8
1763 }
1764 #[doc = "Nominal time segment before sample point. Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
1765and bit 0 \\[INIT\\]
1766of CCCR register are set to 1"]
1767 #[inline(always)]
1768 pub fn set_ntseg1(&mut self, val: u8) {
1769 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
1770 }
1771 #[doc = "Bit rate prescaler. Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
1772and bit 0 \\[INIT\\]
1773of CCCR register are set to 1"]
1774 #[inline(always)]
1775 pub const fn nbrp(&self) -> u16 {
1776 let val = (self.0 >> 16usize) & 0x01ff;
1777 val as u16
1778 }
1779 #[doc = "Bit rate prescaler. Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
1780and bit 0 \\[INIT\\]
1781of CCCR register are set to 1"]
1782 #[inline(always)]
1783 pub fn set_nbrp(&mut self, val: u16) {
1784 self.0 = (self.0 & !(0x01ff << 16usize)) | (((val as u32) & 0x01ff) << 16usize);
1785 }
1786 #[doc = "Nominal (re)synchronization jump width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
1787and bit 0 \\[INIT\\]
1788of CCCR register are set to 1"]
1789 #[inline(always)]
1790 pub const fn nsjw(&self) -> u8 {
1791 let val = (self.0 >> 25usize) & 0x7f;
1792 val as u8
1793 }
1794 #[doc = "Nominal (re)synchronization jump width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
1795and bit 0 \\[INIT\\]
1796of CCCR register are set to 1"]
1797 #[inline(always)]
1798 pub fn set_nsjw(&mut self, val: u8) {
1799 self.0 = (self.0 & !(0x7f << 25usize)) | (((val as u32) & 0x7f) << 25usize);
1800 }
1801 }
1802 impl Default for Nbtp {
1803 #[inline(always)]
1804 fn default() -> Nbtp {
1805 Nbtp(0)
1806 }
1807 }
1808 impl core::fmt::Debug for Nbtp {
1809 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1810 f.debug_struct("Nbtp")
1811 .field("ntseg2", &self.ntseg2())
1812 .field("ntseg1", &self.ntseg1())
1813 .field("nbrp", &self.nbrp())
1814 .field("nsjw", &self.nsjw())
1815 .finish()
1816 }
1817 }
1818 #[cfg(feature = "defmt")]
1819 impl defmt::Format for Nbtp {
1820 fn format(&self, f: defmt::Formatter) {
1821 #[derive(defmt :: Format)]
1822 struct Nbtp {
1823 ntseg2: u8,
1824 ntseg1: u8,
1825 nbrp: u16,
1826 nsjw: u8,
1827 }
1828 let proxy = Nbtp {
1829 ntseg2: self.ntseg2(),
1830 ntseg1: self.ntseg1(),
1831 nbrp: self.nbrp(),
1832 nsjw: self.nsjw(),
1833 };
1834 defmt::write!(f, "{}", proxy)
1835 }
1836 }
1837 #[doc = "FDCAN protocol status register"]
1838 #[repr(transparent)]
1839 #[derive(Copy, Clone, Eq, PartialEq)]
1840 pub struct Psr(pub u32);
1841 impl Psr {
1842 #[doc = "Last error code. The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read."]
1843 #[inline(always)]
1844 pub const fn lec(&self) -> super::vals::Lec {
1845 let val = (self.0 >> 0usize) & 0x07;
1846 super::vals::Lec::from_bits(val as u8)
1847 }
1848 #[doc = "Last error code. The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read."]
1849 #[inline(always)]
1850 pub fn set_lec(&mut self, val: super::vals::Lec) {
1851 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
1852 }
1853 #[doc = "Activity. Monitors the module’s CAN communication state"]
1854 #[inline(always)]
1855 pub const fn act(&self) -> super::vals::Act {
1856 let val = (self.0 >> 3usize) & 0x03;
1857 super::vals::Act::from_bits(val as u8)
1858 }
1859 #[doc = "Activity. Monitors the module’s CAN communication state"]
1860 #[inline(always)]
1861 pub fn set_act(&mut self, val: super::vals::Act) {
1862 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
1863 }
1864 #[doc = "Error passive"]
1865 #[inline(always)]
1866 pub const fn ep(&self) -> bool {
1867 let val = (self.0 >> 5usize) & 0x01;
1868 val != 0
1869 }
1870 #[doc = "Error passive"]
1871 #[inline(always)]
1872 pub fn set_ep(&mut self, val: bool) {
1873 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1874 }
1875 #[doc = "Warning Sstatus"]
1876 #[inline(always)]
1877 pub const fn ew(&self) -> bool {
1878 let val = (self.0 >> 6usize) & 0x01;
1879 val != 0
1880 }
1881 #[doc = "Warning Sstatus"]
1882 #[inline(always)]
1883 pub fn set_ew(&mut self, val: bool) {
1884 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1885 }
1886 #[doc = "Bus_Off status"]
1887 #[inline(always)]
1888 pub const fn bo(&self) -> bool {
1889 let val = (self.0 >> 7usize) & 0x01;
1890 val != 0
1891 }
1892 #[doc = "Bus_Off status"]
1893 #[inline(always)]
1894 pub fn set_bo(&mut self, val: bool) {
1895 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1896 }
1897 #[doc = "Data last error code. Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read."]
1898 #[inline(always)]
1899 pub const fn dlec(&self) -> u8 {
1900 let val = (self.0 >> 8usize) & 0x07;
1901 val as u8
1902 }
1903 #[doc = "Data last error code. Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read."]
1904 #[inline(always)]
1905 pub fn set_dlec(&mut self, val: u8) {
1906 self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
1907 }
1908 #[doc = "ESI flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read."]
1909 #[inline(always)]
1910 pub const fn resi(&self) -> bool {
1911 let val = (self.0 >> 11usize) & 0x01;
1912 val != 0
1913 }
1914 #[doc = "ESI flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read."]
1915 #[inline(always)]
1916 pub fn set_resi(&mut self, val: bool) {
1917 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1918 }
1919 #[doc = "BRS flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read."]
1920 #[inline(always)]
1921 pub const fn rbrs(&self) -> bool {
1922 let val = (self.0 >> 12usize) & 0x01;
1923 val != 0
1924 }
1925 #[doc = "BRS flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read."]
1926 #[inline(always)]
1927 pub fn set_rbrs(&mut self, val: bool) {
1928 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1929 }
1930 #[doc = "Received FDCAN message. This bit is set independent of acceptance filtering. Access type is RX: reset on read."]
1931 #[inline(always)]
1932 pub const fn redl(&self) -> bool {
1933 let val = (self.0 >> 13usize) & 0x01;
1934 val != 0
1935 }
1936 #[doc = "Received FDCAN message. This bit is set independent of acceptance filtering. Access type is RX: reset on read."]
1937 #[inline(always)]
1938 pub fn set_redl(&mut self, val: bool) {
1939 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1940 }
1941 #[doc = "Protocol exception event"]
1942 #[inline(always)]
1943 pub const fn pxe(&self) -> bool {
1944 let val = (self.0 >> 14usize) & 0x01;
1945 val != 0
1946 }
1947 #[doc = "Protocol exception event"]
1948 #[inline(always)]
1949 pub fn set_pxe(&mut self, val: bool) {
1950 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1951 }
1952 #[doc = "Transmitter delay compensation value. Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq"]
1953 #[inline(always)]
1954 pub const fn tdcv(&self) -> u8 {
1955 let val = (self.0 >> 16usize) & 0x7f;
1956 val as u8
1957 }
1958 #[doc = "Transmitter delay compensation value. Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq"]
1959 #[inline(always)]
1960 pub fn set_tdcv(&mut self, val: u8) {
1961 self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
1962 }
1963 }
1964 impl Default for Psr {
1965 #[inline(always)]
1966 fn default() -> Psr {
1967 Psr(0)
1968 }
1969 }
1970 impl core::fmt::Debug for Psr {
1971 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1972 f.debug_struct("Psr")
1973 .field("lec", &self.lec())
1974 .field("act", &self.act())
1975 .field("ep", &self.ep())
1976 .field("ew", &self.ew())
1977 .field("bo", &self.bo())
1978 .field("dlec", &self.dlec())
1979 .field("resi", &self.resi())
1980 .field("rbrs", &self.rbrs())
1981 .field("redl", &self.redl())
1982 .field("pxe", &self.pxe())
1983 .field("tdcv", &self.tdcv())
1984 .finish()
1985 }
1986 }
1987 #[cfg(feature = "defmt")]
1988 impl defmt::Format for Psr {
1989 fn format(&self, f: defmt::Formatter) {
1990 #[derive(defmt :: Format)]
1991 struct Psr {
1992 lec: super::vals::Lec,
1993 act: super::vals::Act,
1994 ep: bool,
1995 ew: bool,
1996 bo: bool,
1997 dlec: u8,
1998 resi: bool,
1999 rbrs: bool,
2000 redl: bool,
2001 pxe: bool,
2002 tdcv: u8,
2003 }
2004 let proxy = Psr {
2005 lec: self.lec(),
2006 act: self.act(),
2007 ep: self.ep(),
2008 ew: self.ew(),
2009 bo: self.bo(),
2010 dlec: self.dlec(),
2011 resi: self.resi(),
2012 rbrs: self.rbrs(),
2013 redl: self.redl(),
2014 pxe: self.pxe(),
2015 tdcv: self.tdcv(),
2016 };
2017 defmt::write!(f, "{}", proxy)
2018 }
2019 }
2020 #[doc = "FDCAN RAM watchdog register"]
2021 #[repr(transparent)]
2022 #[derive(Copy, Clone, Eq, PartialEq)]
2023 pub struct Rwd(pub u32);
2024 impl Rwd {
2025 #[doc = "Watchdog configuration. Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2026and bit 0 \\[INIT\\]
2027of FDCAN_CCCR register are set to 1"]
2028 #[inline(always)]
2029 pub const fn wdc(&self) -> u8 {
2030 let val = (self.0 >> 0usize) & 0xff;
2031 val as u8
2032 }
2033 #[doc = "Watchdog configuration. Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2034and bit 0 \\[INIT\\]
2035of FDCAN_CCCR register are set to 1"]
2036 #[inline(always)]
2037 pub fn set_wdc(&mut self, val: u8) {
2038 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
2039 }
2040 #[doc = "Watchdog value. Actual message RAM watchdog counter value"]
2041 #[inline(always)]
2042 pub const fn wdv(&self) -> u8 {
2043 let val = (self.0 >> 8usize) & 0xff;
2044 val as u8
2045 }
2046 #[doc = "Watchdog value. Actual message RAM watchdog counter value"]
2047 #[inline(always)]
2048 pub fn set_wdv(&mut self, val: u8) {
2049 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
2050 }
2051 }
2052 impl Default for Rwd {
2053 #[inline(always)]
2054 fn default() -> Rwd {
2055 Rwd(0)
2056 }
2057 }
2058 impl core::fmt::Debug for Rwd {
2059 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2060 f.debug_struct("Rwd")
2061 .field("wdc", &self.wdc())
2062 .field("wdv", &self.wdv())
2063 .finish()
2064 }
2065 }
2066 #[cfg(feature = "defmt")]
2067 impl defmt::Format for Rwd {
2068 fn format(&self, f: defmt::Formatter) {
2069 #[derive(defmt :: Format)]
2070 struct Rwd {
2071 wdc: u8,
2072 wdv: u8,
2073 }
2074 let proxy = Rwd {
2075 wdc: self.wdc(),
2076 wdv: self.wdv(),
2077 };
2078 defmt::write!(f, "{}", proxy)
2079 }
2080 }
2081 #[doc = "CAN Rx FIFO X acknowledge register"]
2082 #[repr(transparent)]
2083 #[derive(Copy, Clone, Eq, PartialEq)]
2084 pub struct Rxfa(pub u32);
2085 impl Rxfa {
2086 #[doc = "Rx FIFO X acknowledge index. After the Host has read a message or a sequence of messages from Rx FIFO X it has to write the buffer index of the last element read from Rx FIFO X to FAI. This sets the Rx FIFO X get index RXFS\\[FGI\\]
2087to FAI + 1 and update the FIFO X fill level RXFS\\[FFL\\]"]
2088 #[inline(always)]
2089 pub const fn fai(&self) -> u8 {
2090 let val = (self.0 >> 0usize) & 0x07;
2091 val as u8
2092 }
2093 #[doc = "Rx FIFO X acknowledge index. After the Host has read a message or a sequence of messages from Rx FIFO X it has to write the buffer index of the last element read from Rx FIFO X to FAI. This sets the Rx FIFO X get index RXFS\\[FGI\\]
2094to FAI + 1 and update the FIFO X fill level RXFS\\[FFL\\]"]
2095 #[inline(always)]
2096 pub fn set_fai(&mut self, val: u8) {
2097 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
2098 }
2099 }
2100 impl Default for Rxfa {
2101 #[inline(always)]
2102 fn default() -> Rxfa {
2103 Rxfa(0)
2104 }
2105 }
2106 impl core::fmt::Debug for Rxfa {
2107 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2108 f.debug_struct("Rxfa").field("fai", &self.fai()).finish()
2109 }
2110 }
2111 #[cfg(feature = "defmt")]
2112 impl defmt::Format for Rxfa {
2113 fn format(&self, f: defmt::Formatter) {
2114 #[derive(defmt :: Format)]
2115 struct Rxfa {
2116 fai: u8,
2117 }
2118 let proxy = Rxfa { fai: self.fai() };
2119 defmt::write!(f, "{}", proxy)
2120 }
2121 }
2122 #[doc = "FDCAN Rx FIFO X status register"]
2123 #[repr(transparent)]
2124 #[derive(Copy, Clone, Eq, PartialEq)]
2125 pub struct Rxfs(pub u32);
2126 impl Rxfs {
2127 #[doc = "Rx FIFO X fill level. Number of elements stored in Rx FIFO X, range 0 to 3"]
2128 #[inline(always)]
2129 pub const fn ffl(&self) -> u8 {
2130 let val = (self.0 >> 0usize) & 0x0f;
2131 val as u8
2132 }
2133 #[doc = "Rx FIFO X fill level. Number of elements stored in Rx FIFO X, range 0 to 3"]
2134 #[inline(always)]
2135 pub fn set_ffl(&mut self, val: u8) {
2136 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
2137 }
2138 #[doc = "Rx FIFO X get index. Rx FIFO X read index pointer, range 0 to 2"]
2139 #[inline(always)]
2140 pub const fn fgi(&self) -> u8 {
2141 let val = (self.0 >> 8usize) & 0x03;
2142 val as u8
2143 }
2144 #[doc = "Rx FIFO X get index. Rx FIFO X read index pointer, range 0 to 2"]
2145 #[inline(always)]
2146 pub fn set_fgi(&mut self, val: u8) {
2147 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
2148 }
2149 #[doc = "Rx FIFO X put index. Rx FIFO X write index pointer, range 0 to 2"]
2150 #[inline(always)]
2151 pub const fn fpi(&self) -> u8 {
2152 let val = (self.0 >> 16usize) & 0x03;
2153 val as u8
2154 }
2155 #[doc = "Rx FIFO X put index. Rx FIFO X write index pointer, range 0 to 2"]
2156 #[inline(always)]
2157 pub fn set_fpi(&mut self, val: u8) {
2158 self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
2159 }
2160 #[doc = "Rx FIFO X full"]
2161 #[inline(always)]
2162 pub const fn ff(&self) -> bool {
2163 let val = (self.0 >> 24usize) & 0x01;
2164 val != 0
2165 }
2166 #[doc = "Rx FIFO X full"]
2167 #[inline(always)]
2168 pub fn set_ff(&mut self, val: bool) {
2169 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2170 }
2171 #[doc = "Rx FIFO X message lost. This bit is a copy of interrupt flag IR\\[RFL\\]. When IR\\[RFL\\]
2172is reset, this bit is also reset"]
2173 #[inline(always)]
2174 pub const fn rfl(&self) -> bool {
2175 let val = (self.0 >> 25usize) & 0x01;
2176 val != 0
2177 }
2178 #[doc = "Rx FIFO X message lost. This bit is a copy of interrupt flag IR\\[RFL\\]. When IR\\[RFL\\]
2179is reset, this bit is also reset"]
2180 #[inline(always)]
2181 pub fn set_rfl(&mut self, val: bool) {
2182 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
2183 }
2184 }
2185 impl Default for Rxfs {
2186 #[inline(always)]
2187 fn default() -> Rxfs {
2188 Rxfs(0)
2189 }
2190 }
2191 impl core::fmt::Debug for Rxfs {
2192 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2193 f.debug_struct("Rxfs")
2194 .field("ffl", &self.ffl())
2195 .field("fgi", &self.fgi())
2196 .field("fpi", &self.fpi())
2197 .field("ff", &self.ff())
2198 .field("rfl", &self.rfl())
2199 .finish()
2200 }
2201 }
2202 #[cfg(feature = "defmt")]
2203 impl defmt::Format for Rxfs {
2204 fn format(&self, f: defmt::Formatter) {
2205 #[derive(defmt :: Format)]
2206 struct Rxfs {
2207 ffl: u8,
2208 fgi: u8,
2209 fpi: u8,
2210 ff: bool,
2211 rfl: bool,
2212 }
2213 let proxy = Rxfs {
2214 ffl: self.ffl(),
2215 fgi: self.fgi(),
2216 fpi: self.fpi(),
2217 ff: self.ff(),
2218 rfl: self.rfl(),
2219 };
2220 defmt::write!(f, "{}", proxy)
2221 }
2222 }
2223 #[doc = "FDCAN global filter configuration register"]
2224 #[repr(transparent)]
2225 #[derive(Copy, Clone, Eq, PartialEq)]
2226 pub struct Rxgfc(pub u32);
2227 impl Rxgfc {
2228 #[doc = "Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2229and bit 0 \\[INIT\\]
2230of CCCR register are set to 1"]
2231 #[inline(always)]
2232 pub const fn rrfe(&self) -> bool {
2233 let val = (self.0 >> 0usize) & 0x01;
2234 val != 0
2235 }
2236 #[doc = "Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2237and bit 0 \\[INIT\\]
2238of CCCR register are set to 1"]
2239 #[inline(always)]
2240 pub fn set_rrfe(&mut self, val: bool) {
2241 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2242 }
2243 #[doc = "Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2244and bit 0 \\[INIT\\]
2245of CCCR register are set to 1"]
2246 #[inline(always)]
2247 pub const fn rrfs(&self) -> bool {
2248 let val = (self.0 >> 1usize) & 0x01;
2249 val != 0
2250 }
2251 #[doc = "Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2252and bit 0 \\[INIT\\]
2253of CCCR register are set to 1"]
2254 #[inline(always)]
2255 pub fn set_rrfs(&mut self, val: bool) {
2256 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2257 }
2258 #[doc = "Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2259and bit 0 \\[INIT\\]
2260of CCCR register are set to 1"]
2261 #[inline(always)]
2262 pub const fn anfe(&self) -> super::vals::Anfe {
2263 let val = (self.0 >> 2usize) & 0x03;
2264 super::vals::Anfe::from_bits(val as u8)
2265 }
2266 #[doc = "Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2267and bit 0 \\[INIT\\]
2268of CCCR register are set to 1"]
2269 #[inline(always)]
2270 pub fn set_anfe(&mut self, val: super::vals::Anfe) {
2271 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
2272 }
2273 #[doc = "Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2274and bit 0 \\[INIT\\]
2275of CCCR register are set to 1"]
2276 #[inline(always)]
2277 pub const fn anfs(&self) -> super::vals::Anfs {
2278 let val = (self.0 >> 4usize) & 0x03;
2279 super::vals::Anfs::from_bits(val as u8)
2280 }
2281 #[doc = "Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2282and bit 0 \\[INIT\\]
2283of CCCR register are set to 1"]
2284 #[inline(always)]
2285 pub fn set_anfs(&mut self, val: super::vals::Anfs) {
2286 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
2287 }
2288 #[doc = "FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2289and bit 0 \\[INIT\\]
2290of CCCR register are set to 1"]
2291 #[inline(always)]
2292 pub const fn f1om(&self) -> bool {
2293 let val = (self.0 >> 8usize) & 0x01;
2294 val != 0
2295 }
2296 #[doc = "FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2297and bit 0 \\[INIT\\]
2298of CCCR register are set to 1"]
2299 #[inline(always)]
2300 pub fn set_f1om(&mut self, val: bool) {
2301 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2302 }
2303 #[doc = "FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2304and bit 0 \\[INIT\\]
2305of CCCR register are set to 1"]
2306 #[inline(always)]
2307 pub const fn f0om(&self) -> bool {
2308 let val = (self.0 >> 9usize) & 0x01;
2309 val != 0
2310 }
2311 #[doc = "FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2312and bit 0 \\[INIT\\]
2313of CCCR register are set to 1"]
2314 #[inline(always)]
2315 pub fn set_f0om(&mut self, val: bool) {
2316 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2317 }
2318 #[doc = "List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2319and bit 0 \\[INIT\\]
2320of CCCR register are set to 1."]
2321 #[inline(always)]
2322 pub const fn lss(&self) -> u8 {
2323 let val = (self.0 >> 16usize) & 0x1f;
2324 val as u8
2325 }
2326 #[doc = "List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2327and bit 0 \\[INIT\\]
2328of CCCR register are set to 1."]
2329 #[inline(always)]
2330 pub fn set_lss(&mut self, val: u8) {
2331 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
2332 }
2333 #[doc = "List size extended. >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2334and bit 0 \\[INIT\\]
2335of CCCR register are set to 1."]
2336 #[inline(always)]
2337 pub const fn lse(&self) -> u8 {
2338 let val = (self.0 >> 24usize) & 0x0f;
2339 val as u8
2340 }
2341 #[doc = "List size extended. >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2342and bit 0 \\[INIT\\]
2343of CCCR register are set to 1."]
2344 #[inline(always)]
2345 pub fn set_lse(&mut self, val: u8) {
2346 self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
2347 }
2348 }
2349 impl Default for Rxgfc {
2350 #[inline(always)]
2351 fn default() -> Rxgfc {
2352 Rxgfc(0)
2353 }
2354 }
2355 impl core::fmt::Debug for Rxgfc {
2356 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2357 f.debug_struct("Rxgfc")
2358 .field("rrfe", &self.rrfe())
2359 .field("rrfs", &self.rrfs())
2360 .field("anfe", &self.anfe())
2361 .field("anfs", &self.anfs())
2362 .field("f1om", &self.f1om())
2363 .field("f0om", &self.f0om())
2364 .field("lss", &self.lss())
2365 .field("lse", &self.lse())
2366 .finish()
2367 }
2368 }
2369 #[cfg(feature = "defmt")]
2370 impl defmt::Format for Rxgfc {
2371 fn format(&self, f: defmt::Formatter) {
2372 #[derive(defmt :: Format)]
2373 struct Rxgfc {
2374 rrfe: bool,
2375 rrfs: bool,
2376 anfe: super::vals::Anfe,
2377 anfs: super::vals::Anfs,
2378 f1om: bool,
2379 f0om: bool,
2380 lss: u8,
2381 lse: u8,
2382 }
2383 let proxy = Rxgfc {
2384 rrfe: self.rrfe(),
2385 rrfs: self.rrfs(),
2386 anfe: self.anfe(),
2387 anfs: self.anfs(),
2388 f1om: self.f1om(),
2389 f0om: self.f0om(),
2390 lss: self.lss(),
2391 lse: self.lse(),
2392 };
2393 defmt::write!(f, "{}", proxy)
2394 }
2395 }
2396 #[doc = "FDCAN transmitter delay compensation register"]
2397 #[repr(transparent)]
2398 #[derive(Copy, Clone, Eq, PartialEq)]
2399 pub struct Tdcr(pub u32);
2400 impl Tdcr {
2401 #[doc = "Transmitter delay compensation filter window length. Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2402and bit 0 \\[INIT\\]
2403of CCCR register are set to 1"]
2404 #[inline(always)]
2405 pub const fn tdcf(&self) -> u8 {
2406 let val = (self.0 >> 0usize) & 0x7f;
2407 val as u8
2408 }
2409 #[doc = "Transmitter delay compensation filter window length. Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2410and bit 0 \\[INIT\\]
2411of CCCR register are set to 1"]
2412 #[inline(always)]
2413 pub fn set_tdcf(&mut self, val: u8) {
2414 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
2415 }
2416 #[doc = "Transmitter delay compensation offset. Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2417and bit 0 \\[INIT\\]
2418of CCCR register are set to 1"]
2419 #[inline(always)]
2420 pub const fn tdco(&self) -> u8 {
2421 let val = (self.0 >> 8usize) & 0x7f;
2422 val as u8
2423 }
2424 #[doc = "Transmitter delay compensation offset. Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2425and bit 0 \\[INIT\\]
2426of CCCR register are set to 1"]
2427 #[inline(always)]
2428 pub fn set_tdco(&mut self, val: u8) {
2429 self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize);
2430 }
2431 }
2432 impl Default for Tdcr {
2433 #[inline(always)]
2434 fn default() -> Tdcr {
2435 Tdcr(0)
2436 }
2437 }
2438 impl core::fmt::Debug for Tdcr {
2439 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2440 f.debug_struct("Tdcr")
2441 .field("tdcf", &self.tdcf())
2442 .field("tdco", &self.tdco())
2443 .finish()
2444 }
2445 }
2446 #[cfg(feature = "defmt")]
2447 impl defmt::Format for Tdcr {
2448 fn format(&self, f: defmt::Formatter) {
2449 #[derive(defmt :: Format)]
2450 struct Tdcr {
2451 tdcf: u8,
2452 tdco: u8,
2453 }
2454 let proxy = Tdcr {
2455 tdcf: self.tdcf(),
2456 tdco: self.tdco(),
2457 };
2458 defmt::write!(f, "{}", proxy)
2459 }
2460 }
2461 #[doc = "FDCAN test register"]
2462 #[repr(transparent)]
2463 #[derive(Copy, Clone, Eq, PartialEq)]
2464 pub struct Test(pub u32);
2465 impl Test {
2466 #[doc = "Loop back mode"]
2467 #[inline(always)]
2468 pub const fn lbck(&self) -> bool {
2469 let val = (self.0 >> 4usize) & 0x01;
2470 val != 0
2471 }
2472 #[doc = "Loop back mode"]
2473 #[inline(always)]
2474 pub fn set_lbck(&mut self, val: bool) {
2475 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2476 }
2477 #[doc = "Control of transmit pin"]
2478 #[inline(always)]
2479 pub const fn tx(&self) -> super::vals::Tx {
2480 let val = (self.0 >> 5usize) & 0x03;
2481 super::vals::Tx::from_bits(val as u8)
2482 }
2483 #[doc = "Control of transmit pin"]
2484 #[inline(always)]
2485 pub fn set_tx(&mut self, val: super::vals::Tx) {
2486 self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
2487 }
2488 #[doc = "Receive pin. Monitors the actual value of pin FDCANx_RX"]
2489 #[inline(always)]
2490 pub const fn rx(&self) -> bool {
2491 let val = (self.0 >> 7usize) & 0x01;
2492 val != 0
2493 }
2494 #[doc = "Receive pin. Monitors the actual value of pin FDCANx_RX"]
2495 #[inline(always)]
2496 pub fn set_rx(&mut self, val: bool) {
2497 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2498 }
2499 }
2500 impl Default for Test {
2501 #[inline(always)]
2502 fn default() -> Test {
2503 Test(0)
2504 }
2505 }
2506 impl core::fmt::Debug for Test {
2507 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2508 f.debug_struct("Test")
2509 .field("lbck", &self.lbck())
2510 .field("tx", &self.tx())
2511 .field("rx", &self.rx())
2512 .finish()
2513 }
2514 }
2515 #[cfg(feature = "defmt")]
2516 impl defmt::Format for Test {
2517 fn format(&self, f: defmt::Formatter) {
2518 #[derive(defmt :: Format)]
2519 struct Test {
2520 lbck: bool,
2521 tx: super::vals::Tx,
2522 rx: bool,
2523 }
2524 let proxy = Test {
2525 lbck: self.lbck(),
2526 tx: self.tx(),
2527 rx: self.rx(),
2528 };
2529 defmt::write!(f, "{}", proxy)
2530 }
2531 }
2532 #[doc = "FDCAN timeout counter configuration register"]
2533 #[repr(transparent)]
2534 #[derive(Copy, Clone, Eq, PartialEq)]
2535 pub struct Tocc(pub u32);
2536 impl Tocc {
2537 #[doc = "Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 \\[CCE\\]
2538and bit 0 \\[INIT\\]
2539of CCCR register are set to 1"]
2540 #[inline(always)]
2541 pub const fn etoc(&self) -> bool {
2542 let val = (self.0 >> 0usize) & 0x01;
2543 val != 0
2544 }
2545 #[doc = "Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 \\[CCE\\]
2546and bit 0 \\[INIT\\]
2547of CCCR register are set to 1"]
2548 #[inline(always)]
2549 pub fn set_etoc(&mut self, val: bool) {
2550 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2551 }
2552 #[doc = "Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC\\[TOP\\]
2553and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC\\[TOP\\]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2554and bit 0 \\[INIT\\]
2555of CCCR register are set to 1"]
2556 #[inline(always)]
2557 pub const fn tos(&self) -> super::vals::Tos {
2558 let val = (self.0 >> 1usize) & 0x03;
2559 super::vals::Tos::from_bits(val as u8)
2560 }
2561 #[doc = "Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC\\[TOP\\]
2562and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC\\[TOP\\]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2563and bit 0 \\[INIT\\]
2564of CCCR register are set to 1"]
2565 #[inline(always)]
2566 pub fn set_tos(&mut self, val: super::vals::Tos) {
2567 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
2568 }
2569 #[doc = "Timeout period. Start value of the timeout counter (down-counter). Configures the timeout period"]
2570 #[inline(always)]
2571 pub const fn top(&self) -> u16 {
2572 let val = (self.0 >> 16usize) & 0xffff;
2573 val as u16
2574 }
2575 #[doc = "Timeout period. Start value of the timeout counter (down-counter). Configures the timeout period"]
2576 #[inline(always)]
2577 pub fn set_top(&mut self, val: u16) {
2578 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
2579 }
2580 }
2581 impl Default for Tocc {
2582 #[inline(always)]
2583 fn default() -> Tocc {
2584 Tocc(0)
2585 }
2586 }
2587 impl core::fmt::Debug for Tocc {
2588 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2589 f.debug_struct("Tocc")
2590 .field("etoc", &self.etoc())
2591 .field("tos", &self.tos())
2592 .field("top", &self.top())
2593 .finish()
2594 }
2595 }
2596 #[cfg(feature = "defmt")]
2597 impl defmt::Format for Tocc {
2598 fn format(&self, f: defmt::Formatter) {
2599 #[derive(defmt :: Format)]
2600 struct Tocc {
2601 etoc: bool,
2602 tos: super::vals::Tos,
2603 top: u16,
2604 }
2605 let proxy = Tocc {
2606 etoc: self.etoc(),
2607 tos: self.tos(),
2608 top: self.top(),
2609 };
2610 defmt::write!(f, "{}", proxy)
2611 }
2612 }
2613 #[doc = "FDCAN timeout counter value register"]
2614 #[repr(transparent)]
2615 #[derive(Copy, Clone, Eq, PartialEq)]
2616 pub struct Tocv(pub u32);
2617 impl Tocv {
2618 #[doc = "Timeout counter. The timeout counter is decremented in multiples of CAN bit times \\[1 … 16\\]
2619depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS"]
2620 #[inline(always)]
2621 pub const fn toc(&self) -> u16 {
2622 let val = (self.0 >> 0usize) & 0xffff;
2623 val as u16
2624 }
2625 #[doc = "Timeout counter. The timeout counter is decremented in multiples of CAN bit times \\[1 … 16\\]
2626depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS"]
2627 #[inline(always)]
2628 pub fn set_toc(&mut self, val: u16) {
2629 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2630 }
2631 }
2632 impl Default for Tocv {
2633 #[inline(always)]
2634 fn default() -> Tocv {
2635 Tocv(0)
2636 }
2637 }
2638 impl core::fmt::Debug for Tocv {
2639 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2640 f.debug_struct("Tocv").field("toc", &self.toc()).finish()
2641 }
2642 }
2643 #[cfg(feature = "defmt")]
2644 impl defmt::Format for Tocv {
2645 fn format(&self, f: defmt::Formatter) {
2646 #[derive(defmt :: Format)]
2647 struct Tocv {
2648 toc: u16,
2649 }
2650 let proxy = Tocv { toc: self.toc() };
2651 defmt::write!(f, "{}", proxy)
2652 }
2653 }
2654 #[doc = "FDCAN timestamp counter configuration register"]
2655 #[repr(transparent)]
2656 #[derive(Copy, Clone, Eq, PartialEq)]
2657 pub struct Tscc(pub u32);
2658 impl Tscc {
2659 #[doc = "Timestamp select. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2660and bit 0 \\[INIT\\]
2661of CCCR register are set to 1"]
2662 #[inline(always)]
2663 pub const fn tss(&self) -> super::vals::Tss {
2664 let val = (self.0 >> 0usize) & 0x03;
2665 super::vals::Tss::from_bits(val as u8)
2666 }
2667 #[doc = "Timestamp select. These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2668and bit 0 \\[INIT\\]
2669of CCCR register are set to 1"]
2670 #[inline(always)]
2671 pub fn set_tss(&mut self, val: super::vals::Tss) {
2672 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
2673 }
2674 #[doc = "Timestamp counter prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times \\[1 … 16\\]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2675and bit 0 \\[INIT\\]
2676of CCCR register are set to 1"]
2677 #[inline(always)]
2678 pub const fn tcp(&self) -> u8 {
2679 let val = (self.0 >> 16usize) & 0x0f;
2680 val as u8
2681 }
2682 #[doc = "Timestamp counter prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times \\[1 … 16\\]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 \\[CCE\\]
2683and bit 0 \\[INIT\\]
2684of CCCR register are set to 1"]
2685 #[inline(always)]
2686 pub fn set_tcp(&mut self, val: u8) {
2687 self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
2688 }
2689 }
2690 impl Default for Tscc {
2691 #[inline(always)]
2692 fn default() -> Tscc {
2693 Tscc(0)
2694 }
2695 }
2696 impl core::fmt::Debug for Tscc {
2697 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2698 f.debug_struct("Tscc")
2699 .field("tss", &self.tss())
2700 .field("tcp", &self.tcp())
2701 .finish()
2702 }
2703 }
2704 #[cfg(feature = "defmt")]
2705 impl defmt::Format for Tscc {
2706 fn format(&self, f: defmt::Formatter) {
2707 #[derive(defmt :: Format)]
2708 struct Tscc {
2709 tss: super::vals::Tss,
2710 tcp: u8,
2711 }
2712 let proxy = Tscc {
2713 tss: self.tss(),
2714 tcp: self.tcp(),
2715 };
2716 defmt::write!(f, "{}", proxy)
2717 }
2718 }
2719 #[doc = "FDCAN timestamp counter value register"]
2720 #[repr(transparent)]
2721 #[derive(Copy, Clone, Eq, PartialEq)]
2722 pub struct Tscv(pub u32);
2723 impl Tscv {
2724 #[doc = "Timestamp counter. The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC\\[TSS\\]
2725= 01, the timestamp counter is incremented in multiples of CAN bit times \\[1 … 16\\]
2726depending on the configuration of TSCC\\[TCP\\]. A wrap around sets interrupt flag IR\\[TSW\\]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact"]
2727 #[inline(always)]
2728 pub const fn tsc(&self) -> u16 {
2729 let val = (self.0 >> 0usize) & 0xffff;
2730 val as u16
2731 }
2732 #[doc = "Timestamp counter. The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC\\[TSS\\]
2733= 01, the timestamp counter is incremented in multiples of CAN bit times \\[1 … 16\\]
2734depending on the configuration of TSCC\\[TCP\\]. A wrap around sets interrupt flag IR\\[TSW\\]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact"]
2735 #[inline(always)]
2736 pub fn set_tsc(&mut self, val: u16) {
2737 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2738 }
2739 }
2740 impl Default for Tscv {
2741 #[inline(always)]
2742 fn default() -> Tscv {
2743 Tscv(0)
2744 }
2745 }
2746 impl core::fmt::Debug for Tscv {
2747 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2748 f.debug_struct("Tscv").field("tsc", &self.tsc()).finish()
2749 }
2750 }
2751 #[cfg(feature = "defmt")]
2752 impl defmt::Format for Tscv {
2753 fn format(&self, f: defmt::Formatter) {
2754 #[derive(defmt :: Format)]
2755 struct Tscv {
2756 tsc: u16,
2757 }
2758 let proxy = Tscv { tsc: self.tsc() };
2759 defmt::write!(f, "{}", proxy)
2760 }
2761 }
2762 #[doc = "FDCAN Tx buffer add request register"]
2763 #[repr(transparent)]
2764 #[derive(Copy, Clone, Eq, PartialEq)]
2765 pub struct Txbar(pub u32);
2766 impl Txbar {
2767 #[doc = "Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed"]
2768 #[inline(always)]
2769 pub const fn ar(&self, n: usize) -> bool {
2770 assert!(n < 3usize);
2771 let offs = 0usize + n * 1usize;
2772 let val = (self.0 >> offs) & 0x01;
2773 val != 0
2774 }
2775 #[doc = "Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed"]
2776 #[inline(always)]
2777 pub fn set_ar(&mut self, n: usize, val: bool) {
2778 assert!(n < 3usize);
2779 let offs = 0usize + n * 1usize;
2780 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2781 }
2782 }
2783 impl Default for Txbar {
2784 #[inline(always)]
2785 fn default() -> Txbar {
2786 Txbar(0)
2787 }
2788 }
2789 impl core::fmt::Debug for Txbar {
2790 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2791 f.debug_struct("Txbar")
2792 .field("ar", &[self.ar(0usize), self.ar(1usize), self.ar(2usize)])
2793 .finish()
2794 }
2795 }
2796 #[cfg(feature = "defmt")]
2797 impl defmt::Format for Txbar {
2798 fn format(&self, f: defmt::Formatter) {
2799 #[derive(defmt :: Format)]
2800 struct Txbar {
2801 ar: [bool; 3usize],
2802 }
2803 let proxy = Txbar {
2804 ar: [self.ar(0usize), self.ar(1usize), self.ar(2usize)],
2805 };
2806 defmt::write!(f, "{}", proxy)
2807 }
2808 }
2809 #[doc = "FDCAN Tx buffer configuration register"]
2810 #[repr(transparent)]
2811 #[derive(Copy, Clone, Eq, PartialEq)]
2812 pub struct Txbc(pub u32);
2813 impl Txbc {
2814 #[doc = "Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2815and bit 0 \\[INIT\\]
2816of CCCR register are set to 1"]
2817 #[inline(always)]
2818 pub const fn tfqm(&self) -> super::vals::Tfqm {
2819 let val = (self.0 >> 24usize) & 0x01;
2820 super::vals::Tfqm::from_bits(val as u8)
2821 }
2822 #[doc = "Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
2823and bit 0 \\[INIT\\]
2824of CCCR register are set to 1"]
2825 #[inline(always)]
2826 pub fn set_tfqm(&mut self, val: super::vals::Tfqm) {
2827 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize);
2828 }
2829 }
2830 impl Default for Txbc {
2831 #[inline(always)]
2832 fn default() -> Txbc {
2833 Txbc(0)
2834 }
2835 }
2836 impl core::fmt::Debug for Txbc {
2837 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2838 f.debug_struct("Txbc").field("tfqm", &self.tfqm()).finish()
2839 }
2840 }
2841 #[cfg(feature = "defmt")]
2842 impl defmt::Format for Txbc {
2843 fn format(&self, f: defmt::Formatter) {
2844 #[derive(defmt :: Format)]
2845 struct Txbc {
2846 tfqm: super::vals::Tfqm,
2847 }
2848 let proxy = Txbc { tfqm: self.tfqm() };
2849 defmt::write!(f, "{}", proxy)
2850 }
2851 }
2852 #[doc = "FDCAN Tx buffer cancellation finished register"]
2853 #[repr(transparent)]
2854 #[derive(Copy, Clone, Eq, PartialEq)]
2855 pub struct Txbcf(pub u32);
2856 impl Txbcf {
2857 #[doc = "Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR"]
2858 #[inline(always)]
2859 pub const fn cf(&self, n: usize) -> bool {
2860 assert!(n < 3usize);
2861 let offs = 0usize + n * 1usize;
2862 let val = (self.0 >> offs) & 0x01;
2863 val != 0
2864 }
2865 #[doc = "Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR"]
2866 #[inline(always)]
2867 pub fn set_cf(&mut self, n: usize, val: bool) {
2868 assert!(n < 3usize);
2869 let offs = 0usize + n * 1usize;
2870 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2871 }
2872 }
2873 impl Default for Txbcf {
2874 #[inline(always)]
2875 fn default() -> Txbcf {
2876 Txbcf(0)
2877 }
2878 }
2879 impl core::fmt::Debug for Txbcf {
2880 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2881 f.debug_struct("Txbcf")
2882 .field("cf", &[self.cf(0usize), self.cf(1usize), self.cf(2usize)])
2883 .finish()
2884 }
2885 }
2886 #[cfg(feature = "defmt")]
2887 impl defmt::Format for Txbcf {
2888 fn format(&self, f: defmt::Formatter) {
2889 #[derive(defmt :: Format)]
2890 struct Txbcf {
2891 cf: [bool; 3usize],
2892 }
2893 let proxy = Txbcf {
2894 cf: [self.cf(0usize), self.cf(1usize), self.cf(2usize)],
2895 };
2896 defmt::write!(f, "{}", proxy)
2897 }
2898 }
2899 #[doc = "FDCAN Tx buffer cancellation finished interrupt enable register"]
2900 #[repr(transparent)]
2901 #[derive(Copy, Clone, Eq, PartialEq)]
2902 pub struct Txbcie(pub u32);
2903 impl Txbcie {
2904 #[doc = "Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit"]
2905 #[inline(always)]
2906 pub const fn cfie(&self, n: usize) -> bool {
2907 assert!(n < 3usize);
2908 let offs = 0usize + n * 1usize;
2909 let val = (self.0 >> offs) & 0x01;
2910 val != 0
2911 }
2912 #[doc = "Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit"]
2913 #[inline(always)]
2914 pub fn set_cfie(&mut self, n: usize, val: bool) {
2915 assert!(n < 3usize);
2916 let offs = 0usize + n * 1usize;
2917 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2918 }
2919 }
2920 impl Default for Txbcie {
2921 #[inline(always)]
2922 fn default() -> Txbcie {
2923 Txbcie(0)
2924 }
2925 }
2926 impl core::fmt::Debug for Txbcie {
2927 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2928 f.debug_struct("Txbcie")
2929 .field("cfie", &[self.cfie(0usize), self.cfie(1usize), self.cfie(2usize)])
2930 .finish()
2931 }
2932 }
2933 #[cfg(feature = "defmt")]
2934 impl defmt::Format for Txbcie {
2935 fn format(&self, f: defmt::Formatter) {
2936 #[derive(defmt :: Format)]
2937 struct Txbcie {
2938 cfie: [bool; 3usize],
2939 }
2940 let proxy = Txbcie {
2941 cfie: [self.cfie(0usize), self.cfie(1usize), self.cfie(2usize)],
2942 };
2943 defmt::write!(f, "{}", proxy)
2944 }
2945 }
2946 #[doc = "FDCAN Tx buffer cancellation request register"]
2947 #[repr(transparent)]
2948 #[derive(Copy, Clone, Eq, PartialEq)]
2949 pub struct Txbcr(pub u32);
2950 impl Txbcr {
2951 #[doc = "Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset"]
2952 #[inline(always)]
2953 pub const fn cr(&self, n: usize) -> bool {
2954 assert!(n < 3usize);
2955 let offs = 0usize + n * 1usize;
2956 let val = (self.0 >> offs) & 0x01;
2957 val != 0
2958 }
2959 #[doc = "Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset"]
2960 #[inline(always)]
2961 pub fn set_cr(&mut self, n: usize, val: bool) {
2962 assert!(n < 3usize);
2963 let offs = 0usize + n * 1usize;
2964 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2965 }
2966 }
2967 impl Default for Txbcr {
2968 #[inline(always)]
2969 fn default() -> Txbcr {
2970 Txbcr(0)
2971 }
2972 }
2973 impl core::fmt::Debug for Txbcr {
2974 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2975 f.debug_struct("Txbcr")
2976 .field("cr", &[self.cr(0usize), self.cr(1usize), self.cr(2usize)])
2977 .finish()
2978 }
2979 }
2980 #[cfg(feature = "defmt")]
2981 impl defmt::Format for Txbcr {
2982 fn format(&self, f: defmt::Formatter) {
2983 #[derive(defmt :: Format)]
2984 struct Txbcr {
2985 cr: [bool; 3usize],
2986 }
2987 let proxy = Txbcr {
2988 cr: [self.cr(0usize), self.cr(1usize), self.cr(2usize)],
2989 };
2990 defmt::write!(f, "{}", proxy)
2991 }
2992 }
2993 #[doc = "FDCAN Tx buffer request pending register"]
2994 #[repr(transparent)]
2995 #[derive(Copy, Clone, Eq, PartialEq)]
2996 pub struct Txbrp(pub u32);
2997 impl Txbrp {
2998 #[doc = "Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions"]
2999 #[inline(always)]
3000 pub const fn trp(&self, n: usize) -> bool {
3001 assert!(n < 3usize);
3002 let offs = 0usize + n * 1usize;
3003 let val = (self.0 >> offs) & 0x01;
3004 val != 0
3005 }
3006 #[doc = "Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions"]
3007 #[inline(always)]
3008 pub fn set_trp(&mut self, n: usize, val: bool) {
3009 assert!(n < 3usize);
3010 let offs = 0usize + n * 1usize;
3011 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3012 }
3013 }
3014 impl Default for Txbrp {
3015 #[inline(always)]
3016 fn default() -> Txbrp {
3017 Txbrp(0)
3018 }
3019 }
3020 impl core::fmt::Debug for Txbrp {
3021 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3022 f.debug_struct("Txbrp")
3023 .field("trp", &[self.trp(0usize), self.trp(1usize), self.trp(2usize)])
3024 .finish()
3025 }
3026 }
3027 #[cfg(feature = "defmt")]
3028 impl defmt::Format for Txbrp {
3029 fn format(&self, f: defmt::Formatter) {
3030 #[derive(defmt :: Format)]
3031 struct Txbrp {
3032 trp: [bool; 3usize],
3033 }
3034 let proxy = Txbrp {
3035 trp: [self.trp(0usize), self.trp(1usize), self.trp(2usize)],
3036 };
3037 defmt::write!(f, "{}", proxy)
3038 }
3039 }
3040 #[doc = "FDCAN Tx buffer transmission interrupt enable register"]
3041 #[repr(transparent)]
3042 #[derive(Copy, Clone, Eq, PartialEq)]
3043 pub struct Txbtie(pub u32);
3044 impl Txbtie {
3045 #[doc = "Transmission interrupt enable. Each Tx buffer has its own TIE bit"]
3046 #[inline(always)]
3047 pub const fn tie(&self, n: usize) -> bool {
3048 assert!(n < 3usize);
3049 let offs = 0usize + n * 1usize;
3050 let val = (self.0 >> offs) & 0x01;
3051 val != 0
3052 }
3053 #[doc = "Transmission interrupt enable. Each Tx buffer has its own TIE bit"]
3054 #[inline(always)]
3055 pub fn set_tie(&mut self, n: usize, val: bool) {
3056 assert!(n < 3usize);
3057 let offs = 0usize + n * 1usize;
3058 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3059 }
3060 }
3061 impl Default for Txbtie {
3062 #[inline(always)]
3063 fn default() -> Txbtie {
3064 Txbtie(0)
3065 }
3066 }
3067 impl core::fmt::Debug for Txbtie {
3068 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3069 f.debug_struct("Txbtie")
3070 .field("tie", &[self.tie(0usize), self.tie(1usize), self.tie(2usize)])
3071 .finish()
3072 }
3073 }
3074 #[cfg(feature = "defmt")]
3075 impl defmt::Format for Txbtie {
3076 fn format(&self, f: defmt::Formatter) {
3077 #[derive(defmt :: Format)]
3078 struct Txbtie {
3079 tie: [bool; 3usize],
3080 }
3081 let proxy = Txbtie {
3082 tie: [self.tie(0usize), self.tie(1usize), self.tie(2usize)],
3083 };
3084 defmt::write!(f, "{}", proxy)
3085 }
3086 }
3087 #[doc = "FDCAN Tx buffer transmission occurred register"]
3088 #[repr(transparent)]
3089 #[derive(Copy, Clone, Eq, PartialEq)]
3090 pub struct Txbto(pub u32);
3091 impl Txbto {
3092 #[doc = "Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR"]
3093 #[inline(always)]
3094 pub const fn to(&self, n: usize) -> bool {
3095 assert!(n < 3usize);
3096 let offs = 0usize + n * 1usize;
3097 let val = (self.0 >> offs) & 0x01;
3098 val != 0
3099 }
3100 #[doc = "Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR"]
3101 #[inline(always)]
3102 pub fn set_to(&mut self, n: usize, val: bool) {
3103 assert!(n < 3usize);
3104 let offs = 0usize + n * 1usize;
3105 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3106 }
3107 }
3108 impl Default for Txbto {
3109 #[inline(always)]
3110 fn default() -> Txbto {
3111 Txbto(0)
3112 }
3113 }
3114 impl core::fmt::Debug for Txbto {
3115 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3116 f.debug_struct("Txbto")
3117 .field("to", &[self.to(0usize), self.to(1usize), self.to(2usize)])
3118 .finish()
3119 }
3120 }
3121 #[cfg(feature = "defmt")]
3122 impl defmt::Format for Txbto {
3123 fn format(&self, f: defmt::Formatter) {
3124 #[derive(defmt :: Format)]
3125 struct Txbto {
3126 to: [bool; 3usize],
3127 }
3128 let proxy = Txbto {
3129 to: [self.to(0usize), self.to(1usize), self.to(2usize)],
3130 };
3131 defmt::write!(f, "{}", proxy)
3132 }
3133 }
3134 #[doc = "FDCAN Tx event FIFO acknowledge register"]
3135 #[repr(transparent)]
3136 #[derive(Copy, Clone, Eq, PartialEq)]
3137 pub struct Txefa(pub u32);
3138 impl Txefa {
3139 #[doc = "Event FIFO acknowledge index. After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS\\[EFGI\\]
3140to EFAI + 1 and updates the FIFO 0 fill level TXEFS\\[EFFL\\]"]
3141 #[inline(always)]
3142 pub const fn efai(&self) -> u8 {
3143 let val = (self.0 >> 0usize) & 0x03;
3144 val as u8
3145 }
3146 #[doc = "Event FIFO acknowledge index. After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS\\[EFGI\\]
3147to EFAI + 1 and updates the FIFO 0 fill level TXEFS\\[EFFL\\]"]
3148 #[inline(always)]
3149 pub fn set_efai(&mut self, val: u8) {
3150 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
3151 }
3152 }
3153 impl Default for Txefa {
3154 #[inline(always)]
3155 fn default() -> Txefa {
3156 Txefa(0)
3157 }
3158 }
3159 impl core::fmt::Debug for Txefa {
3160 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3161 f.debug_struct("Txefa").field("efai", &self.efai()).finish()
3162 }
3163 }
3164 #[cfg(feature = "defmt")]
3165 impl defmt::Format for Txefa {
3166 fn format(&self, f: defmt::Formatter) {
3167 #[derive(defmt :: Format)]
3168 struct Txefa {
3169 efai: u8,
3170 }
3171 let proxy = Txefa { efai: self.efai() };
3172 defmt::write!(f, "{}", proxy)
3173 }
3174 }
3175 #[doc = "FDCAN Tx event FIFO status register"]
3176 #[repr(transparent)]
3177 #[derive(Copy, Clone, Eq, PartialEq)]
3178 pub struct Txefs(pub u32);
3179 impl Txefs {
3180 #[doc = "Event FIFO fill level. Number of elements stored in Tx event FIFO, range 0 to 3"]
3181 #[inline(always)]
3182 pub const fn effl(&self) -> u8 {
3183 let val = (self.0 >> 0usize) & 0x07;
3184 val as u8
3185 }
3186 #[doc = "Event FIFO fill level. Number of elements stored in Tx event FIFO, range 0 to 3"]
3187 #[inline(always)]
3188 pub fn set_effl(&mut self, val: u8) {
3189 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
3190 }
3191 #[doc = "Event FIFO get index. Tx event FIFO read index pointer, range 0 to 3"]
3192 #[inline(always)]
3193 pub const fn efgi(&self) -> u8 {
3194 let val = (self.0 >> 8usize) & 0x03;
3195 val as u8
3196 }
3197 #[doc = "Event FIFO get index. Tx event FIFO read index pointer, range 0 to 3"]
3198 #[inline(always)]
3199 pub fn set_efgi(&mut self, val: u8) {
3200 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
3201 }
3202 #[doc = "Event FIFO put index. Tx event FIFO write index pointer, range 0 to 3"]
3203 #[inline(always)]
3204 pub const fn efpi(&self) -> u8 {
3205 let val = (self.0 >> 16usize) & 0x03;
3206 val as u8
3207 }
3208 #[doc = "Event FIFO put index. Tx event FIFO write index pointer, range 0 to 3"]
3209 #[inline(always)]
3210 pub fn set_efpi(&mut self, val: u8) {
3211 self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
3212 }
3213 #[doc = "Event FIFO full"]
3214 #[inline(always)]
3215 pub const fn eff(&self) -> bool {
3216 let val = (self.0 >> 24usize) & 0x01;
3217 val != 0
3218 }
3219 #[doc = "Event FIFO full"]
3220 #[inline(always)]
3221 pub fn set_eff(&mut self, val: bool) {
3222 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3223 }
3224 #[doc = "Tx event FIFO element lost. This bit is a copy of interrupt flag IR\\[TEFL\\]. When IR\\[TEFL\\]
3225is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0"]
3226 #[inline(always)]
3227 pub const fn tefl(&self) -> bool {
3228 let val = (self.0 >> 25usize) & 0x01;
3229 val != 0
3230 }
3231 #[doc = "Tx event FIFO element lost. This bit is a copy of interrupt flag IR\\[TEFL\\]. When IR\\[TEFL\\]
3232is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0"]
3233 #[inline(always)]
3234 pub fn set_tefl(&mut self, val: bool) {
3235 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
3236 }
3237 }
3238 impl Default for Txefs {
3239 #[inline(always)]
3240 fn default() -> Txefs {
3241 Txefs(0)
3242 }
3243 }
3244 impl core::fmt::Debug for Txefs {
3245 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3246 f.debug_struct("Txefs")
3247 .field("effl", &self.effl())
3248 .field("efgi", &self.efgi())
3249 .field("efpi", &self.efpi())
3250 .field("eff", &self.eff())
3251 .field("tefl", &self.tefl())
3252 .finish()
3253 }
3254 }
3255 #[cfg(feature = "defmt")]
3256 impl defmt::Format for Txefs {
3257 fn format(&self, f: defmt::Formatter) {
3258 #[derive(defmt :: Format)]
3259 struct Txefs {
3260 effl: u8,
3261 efgi: u8,
3262 efpi: u8,
3263 eff: bool,
3264 tefl: bool,
3265 }
3266 let proxy = Txefs {
3267 effl: self.effl(),
3268 efgi: self.efgi(),
3269 efpi: self.efpi(),
3270 eff: self.eff(),
3271 tefl: self.tefl(),
3272 };
3273 defmt::write!(f, "{}", proxy)
3274 }
3275 }
3276 #[doc = "FDCAN Tx FIFO/queue status register"]
3277 #[repr(transparent)]
3278 #[derive(Copy, Clone, Eq, PartialEq)]
3279 pub struct Txfqs(pub u32);
3280 impl Txfqs {
3281 #[doc = "Tx FIFO free level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC\\[TFQM\\]
3282= 1)"]
3283 #[inline(always)]
3284 pub const fn tffl(&self) -> u8 {
3285 let val = (self.0 >> 0usize) & 0x07;
3286 val as u8
3287 }
3288 #[doc = "Tx FIFO free level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC\\[TFQM\\]
3289= 1)"]
3290 #[inline(always)]
3291 pub fn set_tffl(&mut self, val: u8) {
3292 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
3293 }
3294 #[doc = "Tx FIFO get index. Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1)"]
3295 #[inline(always)]
3296 pub const fn tfgi(&self) -> u8 {
3297 let val = (self.0 >> 8usize) & 0x03;
3298 val as u8
3299 }
3300 #[doc = "Tx FIFO get index. Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1)"]
3301 #[inline(always)]
3302 pub fn set_tfgi(&mut self, val: u8) {
3303 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
3304 }
3305 #[doc = "Tx FIFO/queue put index. Tx FIFO/queue write index pointer, range 0 to 3"]
3306 #[inline(always)]
3307 pub const fn tfqpi(&self) -> u8 {
3308 let val = (self.0 >> 16usize) & 0x03;
3309 val as u8
3310 }
3311 #[doc = "Tx FIFO/queue put index. Tx FIFO/queue write index pointer, range 0 to 3"]
3312 #[inline(always)]
3313 pub fn set_tfqpi(&mut self, val: u8) {
3314 self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
3315 }
3316 #[doc = "Tx FIFO/queue full"]
3317 #[inline(always)]
3318 pub const fn tfqf(&self) -> bool {
3319 let val = (self.0 >> 21usize) & 0x01;
3320 val != 0
3321 }
3322 #[doc = "Tx FIFO/queue full"]
3323 #[inline(always)]
3324 pub fn set_tfqf(&mut self, val: bool) {
3325 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
3326 }
3327 }
3328 impl Default for Txfqs {
3329 #[inline(always)]
3330 fn default() -> Txfqs {
3331 Txfqs(0)
3332 }
3333 }
3334 impl core::fmt::Debug for Txfqs {
3335 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3336 f.debug_struct("Txfqs")
3337 .field("tffl", &self.tffl())
3338 .field("tfgi", &self.tfgi())
3339 .field("tfqpi", &self.tfqpi())
3340 .field("tfqf", &self.tfqf())
3341 .finish()
3342 }
3343 }
3344 #[cfg(feature = "defmt")]
3345 impl defmt::Format for Txfqs {
3346 fn format(&self, f: defmt::Formatter) {
3347 #[derive(defmt :: Format)]
3348 struct Txfqs {
3349 tffl: u8,
3350 tfgi: u8,
3351 tfqpi: u8,
3352 tfqf: bool,
3353 }
3354 let proxy = Txfqs {
3355 tffl: self.tffl(),
3356 tfgi: self.tfgi(),
3357 tfqpi: self.tfqpi(),
3358 tfqf: self.tfqf(),
3359 };
3360 defmt::write!(f, "{}", proxy)
3361 }
3362 }
3363 #[doc = "FDCAN extended ID and mask register"]
3364 #[repr(transparent)]
3365 #[derive(Copy, Clone, Eq, PartialEq)]
3366 pub struct Xidam(pub u32);
3367 impl Xidam {
3368 #[doc = "Extended ID mask. For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
3369and bit 0 \\[INIT\\]
3370of CCCR register are set to 1"]
3371 #[inline(always)]
3372 pub const fn eidm(&self) -> u32 {
3373 let val = (self.0 >> 0usize) & 0x1fff_ffff;
3374 val as u32
3375 }
3376 #[doc = "Extended ID mask. For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \\[CCE\\]
3377and bit 0 \\[INIT\\]
3378of CCCR register are set to 1"]
3379 #[inline(always)]
3380 pub fn set_eidm(&mut self, val: u32) {
3381 self.0 = (self.0 & !(0x1fff_ffff << 0usize)) | (((val as u32) & 0x1fff_ffff) << 0usize);
3382 }
3383 }
3384 impl Default for Xidam {
3385 #[inline(always)]
3386 fn default() -> Xidam {
3387 Xidam(0)
3388 }
3389 }
3390 impl core::fmt::Debug for Xidam {
3391 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3392 f.debug_struct("Xidam").field("eidm", &self.eidm()).finish()
3393 }
3394 }
3395 #[cfg(feature = "defmt")]
3396 impl defmt::Format for Xidam {
3397 fn format(&self, f: defmt::Formatter) {
3398 #[derive(defmt :: Format)]
3399 struct Xidam {
3400 eidm: u32,
3401 }
3402 let proxy = Xidam { eidm: self.eidm() };
3403 defmt::write!(f, "{}", proxy)
3404 }
3405 }
3406}
3407pub mod vals {
3408 #[repr(u8)]
3409 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3410 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3411 pub enum Act {
3412 #[doc = "Synchronizing: node is synchronizing on CAN communication."]
3413 SYNC = 0x0,
3414 #[doc = "Idle: node is neither receiver nor transmitter."]
3415 IDLE = 0x01,
3416 #[doc = "Receiver: node is operating as receiver."]
3417 RX = 0x02,
3418 #[doc = "Transmitter: node is operating as transmitter."]
3419 TX = 0x03,
3420 }
3421 impl Act {
3422 #[inline(always)]
3423 pub const fn from_bits(val: u8) -> Act {
3424 unsafe { core::mem::transmute(val & 0x03) }
3425 }
3426 #[inline(always)]
3427 pub const fn to_bits(self) -> u8 {
3428 unsafe { core::mem::transmute(self) }
3429 }
3430 }
3431 impl From<u8> for Act {
3432 #[inline(always)]
3433 fn from(val: u8) -> Act {
3434 Act::from_bits(val)
3435 }
3436 }
3437 impl From<Act> for u8 {
3438 #[inline(always)]
3439 fn from(val: Act) -> u8 {
3440 Act::to_bits(val)
3441 }
3442 }
3443 #[repr(u8)]
3444 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3445 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3446 pub enum Anfe {
3447 #[doc = "Accept in Rx FIFO 0"]
3448 ACCEPT_FIFO_0 = 0x0,
3449 #[doc = "Accept in Rx FIFO 1"]
3450 ACCEPT_FIFO_1 = 0x01,
3451 #[doc = "Reject"]
3452 REJECT = 0x02,
3453 _RESERVED_3 = 0x03,
3454 }
3455 impl Anfe {
3456 #[inline(always)]
3457 pub const fn from_bits(val: u8) -> Anfe {
3458 unsafe { core::mem::transmute(val & 0x03) }
3459 }
3460 #[inline(always)]
3461 pub const fn to_bits(self) -> u8 {
3462 unsafe { core::mem::transmute(self) }
3463 }
3464 }
3465 impl From<u8> for Anfe {
3466 #[inline(always)]
3467 fn from(val: u8) -> Anfe {
3468 Anfe::from_bits(val)
3469 }
3470 }
3471 impl From<Anfe> for u8 {
3472 #[inline(always)]
3473 fn from(val: Anfe) -> u8 {
3474 Anfe::to_bits(val)
3475 }
3476 }
3477 #[repr(u8)]
3478 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3479 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3480 pub enum Anfs {
3481 #[doc = "Accept in Rx FIFO 0"]
3482 ACCEPT_FIFO_0 = 0x0,
3483 #[doc = "Accept in Rx FIFO 1"]
3484 ACCEPT_FIFO_1 = 0x01,
3485 #[doc = "Reject"]
3486 REJECT = 0x02,
3487 _RESERVED_3 = 0x03,
3488 }
3489 impl Anfs {
3490 #[inline(always)]
3491 pub const fn from_bits(val: u8) -> Anfs {
3492 unsafe { core::mem::transmute(val & 0x03) }
3493 }
3494 #[inline(always)]
3495 pub const fn to_bits(self) -> u8 {
3496 unsafe { core::mem::transmute(self) }
3497 }
3498 }
3499 impl From<u8> for Anfs {
3500 #[inline(always)]
3501 fn from(val: u8) -> Anfs {
3502 Anfs::from_bits(val)
3503 }
3504 }
3505 impl From<Anfs> for u8 {
3506 #[inline(always)]
3507 fn from(val: Anfs) -> u8 {
3508 Anfs::to_bits(val)
3509 }
3510 }
3511 #[repr(u8)]
3512 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3513 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3514 pub enum Lec {
3515 #[doc = "No Error: No error occurred since LEC has been reset by successful reception or transmission."]
3516 NO_ERROR = 0x0,
3517 #[doc = "Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed."]
3518 STUFF = 0x01,
3519 #[doc = "Form Error: A fixed format part of a received frame has the wrong format."]
3520 FORM = 0x02,
3521 #[doc = "AckError: The message transmitted by the FDCAN was not acknowledged by another node."]
3522 ACK = 0x03,
3523 #[doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant."]
3524 BIT_1 = 0x04,
3525 #[doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)."]
3526 BIT_0 = 0x05,
3527 #[doc = "CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data."]
3528 CRC = 0x06,
3529 #[doc = "NoChange: Any read access to the Protocol status register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol status register."]
3530 NO_CHANGE = 0x07,
3531 }
3532 impl Lec {
3533 #[inline(always)]
3534 pub const fn from_bits(val: u8) -> Lec {
3535 unsafe { core::mem::transmute(val & 0x07) }
3536 }
3537 #[inline(always)]
3538 pub const fn to_bits(self) -> u8 {
3539 unsafe { core::mem::transmute(self) }
3540 }
3541 }
3542 impl From<u8> for Lec {
3543 #[inline(always)]
3544 fn from(val: u8) -> Lec {
3545 Lec::from_bits(val)
3546 }
3547 }
3548 impl From<Lec> for u8 {
3549 #[inline(always)]
3550 fn from(val: Lec) -> u8 {
3551 Lec::to_bits(val)
3552 }
3553 }
3554 #[repr(u8)]
3555 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3556 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3557 pub enum Msi {
3558 #[doc = "No FIFO selected"]
3559 NO_FIFO = 0x0,
3560 #[doc = "FIFO overrun"]
3561 OVERRUN = 0x01,
3562 #[doc = "Message stored in FIFO 0"]
3563 FIFO_0 = 0x02,
3564 #[doc = "Message stored in FIFO 1"]
3565 FIFO_1 = 0x03,
3566 }
3567 impl Msi {
3568 #[inline(always)]
3569 pub const fn from_bits(val: u8) -> Msi {
3570 unsafe { core::mem::transmute(val & 0x03) }
3571 }
3572 #[inline(always)]
3573 pub const fn to_bits(self) -> u8 {
3574 unsafe { core::mem::transmute(self) }
3575 }
3576 }
3577 impl From<u8> for Msi {
3578 #[inline(always)]
3579 fn from(val: u8) -> Msi {
3580 Msi::from_bits(val)
3581 }
3582 }
3583 impl From<Msi> for u8 {
3584 #[inline(always)]
3585 fn from(val: Msi) -> u8 {
3586 Msi::to_bits(val)
3587 }
3588 }
3589 #[repr(u8)]
3590 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3591 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3592 pub enum Pdiv {
3593 #[doc = "Divide by 1"]
3594 DIV_1 = 0x0,
3595 #[doc = "Divide by 2"]
3596 DIV_2 = 0x01,
3597 #[doc = "Divide by 4"]
3598 DIV_4 = 0x02,
3599 #[doc = "Divide by 6"]
3600 DIV_6 = 0x03,
3601 #[doc = "Divide by 8"]
3602 DIV_8 = 0x04,
3603 #[doc = "Divide by 10"]
3604 DIV_10 = 0x05,
3605 #[doc = "Divide by 12"]
3606 DIV_12 = 0x06,
3607 #[doc = "Divide by 14"]
3608 DIV_14 = 0x07,
3609 #[doc = "Divide by 16"]
3610 DIV_16 = 0x08,
3611 #[doc = "Divide by 18"]
3612 DIV_18 = 0x09,
3613 #[doc = "Divide by 20"]
3614 DIV_20 = 0x0a,
3615 #[doc = "Divide by 22"]
3616 DIV_22 = 0x0b,
3617 #[doc = "Divide by 24"]
3618 DIV_24 = 0x0c,
3619 #[doc = "Divide by 26"]
3620 DIV_26 = 0x0d,
3621 #[doc = "Divide by 28"]
3622 DIV_28 = 0x0e,
3623 #[doc = "Divide by 30"]
3624 DIV_30 = 0x0f,
3625 }
3626 impl Pdiv {
3627 #[inline(always)]
3628 pub const fn from_bits(val: u8) -> Pdiv {
3629 unsafe { core::mem::transmute(val & 0x0f) }
3630 }
3631 #[inline(always)]
3632 pub const fn to_bits(self) -> u8 {
3633 unsafe { core::mem::transmute(self) }
3634 }
3635 }
3636 impl From<u8> for Pdiv {
3637 #[inline(always)]
3638 fn from(val: u8) -> Pdiv {
3639 Pdiv::from_bits(val)
3640 }
3641 }
3642 impl From<Pdiv> for u8 {
3643 #[inline(always)]
3644 fn from(val: Pdiv) -> u8 {
3645 Pdiv::to_bits(val)
3646 }
3647 }
3648 #[repr(u8)]
3649 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3650 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3651 pub enum Tfqm {
3652 #[doc = "Tx FIFO operation"]
3653 FIFO = 0x0,
3654 #[doc = "Tx queue operation"]
3655 QUEUE = 0x01,
3656 }
3657 impl Tfqm {
3658 #[inline(always)]
3659 pub const fn from_bits(val: u8) -> Tfqm {
3660 unsafe { core::mem::transmute(val & 0x01) }
3661 }
3662 #[inline(always)]
3663 pub const fn to_bits(self) -> u8 {
3664 unsafe { core::mem::transmute(self) }
3665 }
3666 }
3667 impl From<u8> for Tfqm {
3668 #[inline(always)]
3669 fn from(val: u8) -> Tfqm {
3670 Tfqm::from_bits(val)
3671 }
3672 }
3673 impl From<Tfqm> for u8 {
3674 #[inline(always)]
3675 fn from(val: Tfqm) -> u8 {
3676 Tfqm::to_bits(val)
3677 }
3678 }
3679 #[repr(u8)]
3680 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3681 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3682 pub enum Tos {
3683 #[doc = "Continuous operation"]
3684 CONTINUOUS = 0x0,
3685 #[doc = "Timeout controlled by Tx event FIFO"]
3686 TX_EVENT_FIFO = 0x01,
3687 #[doc = "Timeout controlled by Rx FIFO 0"]
3688 RX_FIFO_0 = 0x02,
3689 #[doc = "Timeout controlled by Rx FIFO 1"]
3690 RX_FIFO_1 = 0x03,
3691 }
3692 impl Tos {
3693 #[inline(always)]
3694 pub const fn from_bits(val: u8) -> Tos {
3695 unsafe { core::mem::transmute(val & 0x03) }
3696 }
3697 #[inline(always)]
3698 pub const fn to_bits(self) -> u8 {
3699 unsafe { core::mem::transmute(self) }
3700 }
3701 }
3702 impl From<u8> for Tos {
3703 #[inline(always)]
3704 fn from(val: u8) -> Tos {
3705 Tos::from_bits(val)
3706 }
3707 }
3708 impl From<Tos> for u8 {
3709 #[inline(always)]
3710 fn from(val: Tos) -> u8 {
3711 Tos::to_bits(val)
3712 }
3713 }
3714 #[repr(u8)]
3715 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3716 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3717 pub enum Tss {
3718 #[doc = "Timestamp counter value always 0x0000"]
3719 ZERO = 0x0,
3720 #[doc = "Timestamp counter value incremented according to TCP"]
3721 INCREMENT = 0x01,
3722 #[doc = "External timestamp counter from TIM3 value (tim3_cnt\\[0:15\\])"]
3723 EXTERNAL = 0x02,
3724 _RESERVED_3 = 0x03,
3725 }
3726 impl Tss {
3727 #[inline(always)]
3728 pub const fn from_bits(val: u8) -> Tss {
3729 unsafe { core::mem::transmute(val & 0x03) }
3730 }
3731 #[inline(always)]
3732 pub const fn to_bits(self) -> u8 {
3733 unsafe { core::mem::transmute(self) }
3734 }
3735 }
3736 impl From<u8> for Tss {
3737 #[inline(always)]
3738 fn from(val: u8) -> Tss {
3739 Tss::from_bits(val)
3740 }
3741 }
3742 impl From<Tss> for u8 {
3743 #[inline(always)]
3744 fn from(val: Tss) -> u8 {
3745 Tss::to_bits(val)
3746 }
3747 }
3748 #[repr(u8)]
3749 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
3750 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
3751 pub enum Tx {
3752 #[doc = "Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time"]
3753 RESET = 0x0,
3754 #[doc = "Sample point can be monitored at pin FDCANx_TX"]
3755 SAMPLE_POINT = 0x01,
3756 #[doc = "Dominant (0) level at pin FDCANx_TX"]
3757 DOMINANT = 0x02,
3758 #[doc = "Recessive (1) at pin FDCANx_TX"]
3759 RECESSIVE = 0x03,
3760 }
3761 impl Tx {
3762 #[inline(always)]
3763 pub const fn from_bits(val: u8) -> Tx {
3764 unsafe { core::mem::transmute(val & 0x03) }
3765 }
3766 #[inline(always)]
3767 pub const fn to_bits(self) -> u8 {
3768 unsafe { core::mem::transmute(self) }
3769 }
3770 }
3771 impl From<u8> for Tx {
3772 #[inline(always)]
3773 fn from(val: u8) -> Tx {
3774 Tx::from_bits(val)
3775 }
3776 }
3777 impl From<Tx> for u8 {
3778 #[inline(always)]
3779 fn from(val: Tx) -> u8 {
3780 Tx::to_bits(val)
3781 }
3782 }
3783}
3784