1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Clock recovery system"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Crs {
9 ptr: *mut u8,
10}
11unsafe impl Send for Crs {}
12unsafe impl Sync for Crs {}
13impl Crs {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "control register"]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "configuration register"]
28 #[inline(always)]
29 pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "interrupt and status register"]
33 #[inline(always)]
34 pub const fn isr(self) -> crate::common::Reg<regs::Isr, crate::common::R> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "interrupt flag clear register"]
38 #[inline(always)]
39 pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42}
43pub mod regs {
44 #[doc = "configuration register"]
45 #[repr(transparent)]
46 #[derive(Copy, Clone, Eq, PartialEq)]
47 pub struct Cfgr(pub u32);
48 impl Cfgr {
49 #[doc = "Counter reload value"]
50 #[inline(always)]
51 pub const fn reload(&self) -> u16 {
52 let val = (self.0 >> 0usize) & 0xffff;
53 val as u16
54 }
55 #[doc = "Counter reload value"]
56 #[inline(always)]
57 pub fn set_reload(&mut self, val: u16) {
58 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
59 }
60 #[doc = "Frequency error limit"]
61 #[inline(always)]
62 pub const fn felim(&self) -> u8 {
63 let val = (self.0 >> 16usize) & 0xff;
64 val as u8
65 }
66 #[doc = "Frequency error limit"]
67 #[inline(always)]
68 pub fn set_felim(&mut self, val: u8) {
69 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
70 }
71 #[doc = "SYNC divider"]
72 #[inline(always)]
73 pub const fn syncdiv(&self) -> u8 {
74 let val = (self.0 >> 24usize) & 0x07;
75 val as u8
76 }
77 #[doc = "SYNC divider"]
78 #[inline(always)]
79 pub fn set_syncdiv(&mut self, val: u8) {
80 self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize);
81 }
82 #[doc = "SYNC signal source selection"]
83 #[inline(always)]
84 pub const fn syncsrc(&self) -> super::vals::Syncsrc {
85 let val = (self.0 >> 28usize) & 0x03;
86 super::vals::Syncsrc::from_bits(val as u8)
87 }
88 #[doc = "SYNC signal source selection"]
89 #[inline(always)]
90 pub fn set_syncsrc(&mut self, val: super::vals::Syncsrc) {
91 self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
92 }
93 #[doc = "SYNC polarity selection"]
94 #[inline(always)]
95 pub const fn syncpol(&self) -> bool {
96 let val = (self.0 >> 31usize) & 0x01;
97 val != 0
98 }
99 #[doc = "SYNC polarity selection"]
100 #[inline(always)]
101 pub fn set_syncpol(&mut self, val: bool) {
102 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
103 }
104 }
105 impl Default for Cfgr {
106 #[inline(always)]
107 fn default() -> Cfgr {
108 Cfgr(0)
109 }
110 }
111 impl core::fmt::Debug for Cfgr {
112 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
113 f.debug_struct("Cfgr")
114 .field("reload", &self.reload())
115 .field("felim", &self.felim())
116 .field("syncdiv", &self.syncdiv())
117 .field("syncsrc", &self.syncsrc())
118 .field("syncpol", &self.syncpol())
119 .finish()
120 }
121 }
122 #[cfg(feature = "defmt")]
123 impl defmt::Format for Cfgr {
124 fn format(&self, f: defmt::Formatter) {
125 #[derive(defmt :: Format)]
126 struct Cfgr {
127 reload: u16,
128 felim: u8,
129 syncdiv: u8,
130 syncsrc: super::vals::Syncsrc,
131 syncpol: bool,
132 }
133 let proxy = Cfgr {
134 reload: self.reload(),
135 felim: self.felim(),
136 syncdiv: self.syncdiv(),
137 syncsrc: self.syncsrc(),
138 syncpol: self.syncpol(),
139 };
140 defmt::write!(f, "{}", proxy)
141 }
142 }
143 #[doc = "control register"]
144 #[repr(transparent)]
145 #[derive(Copy, Clone, Eq, PartialEq)]
146 pub struct Cr(pub u32);
147 impl Cr {
148 #[doc = "SYNC event OK interrupt enable"]
149 #[inline(always)]
150 pub const fn syncokie(&self) -> bool {
151 let val = (self.0 >> 0usize) & 0x01;
152 val != 0
153 }
154 #[doc = "SYNC event OK interrupt enable"]
155 #[inline(always)]
156 pub fn set_syncokie(&mut self, val: bool) {
157 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
158 }
159 #[doc = "SYNC warning interrupt enable"]
160 #[inline(always)]
161 pub const fn syncwarnie(&self) -> bool {
162 let val = (self.0 >> 1usize) & 0x01;
163 val != 0
164 }
165 #[doc = "SYNC warning interrupt enable"]
166 #[inline(always)]
167 pub fn set_syncwarnie(&mut self, val: bool) {
168 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
169 }
170 #[doc = "Synchronization or trimming error interrupt enable"]
171 #[inline(always)]
172 pub const fn errie(&self) -> bool {
173 let val = (self.0 >> 2usize) & 0x01;
174 val != 0
175 }
176 #[doc = "Synchronization or trimming error interrupt enable"]
177 #[inline(always)]
178 pub fn set_errie(&mut self, val: bool) {
179 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
180 }
181 #[doc = "Expected SYNC interrupt enable"]
182 #[inline(always)]
183 pub const fn esyncie(&self) -> bool {
184 let val = (self.0 >> 3usize) & 0x01;
185 val != 0
186 }
187 #[doc = "Expected SYNC interrupt enable"]
188 #[inline(always)]
189 pub fn set_esyncie(&mut self, val: bool) {
190 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
191 }
192 #[doc = "Frequency error counter enable"]
193 #[inline(always)]
194 pub const fn cen(&self) -> bool {
195 let val = (self.0 >> 5usize) & 0x01;
196 val != 0
197 }
198 #[doc = "Frequency error counter enable"]
199 #[inline(always)]
200 pub fn set_cen(&mut self, val: bool) {
201 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
202 }
203 #[doc = "Automatic trimming enable"]
204 #[inline(always)]
205 pub const fn autotrimen(&self) -> bool {
206 let val = (self.0 >> 6usize) & 0x01;
207 val != 0
208 }
209 #[doc = "Automatic trimming enable"]
210 #[inline(always)]
211 pub fn set_autotrimen(&mut self, val: bool) {
212 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
213 }
214 #[doc = "Generate software SYNC event"]
215 #[inline(always)]
216 pub const fn swsync(&self) -> bool {
217 let val = (self.0 >> 7usize) & 0x01;
218 val != 0
219 }
220 #[doc = "Generate software SYNC event"]
221 #[inline(always)]
222 pub fn set_swsync(&mut self, val: bool) {
223 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
224 }
225 #[doc = "HSI48 oscillator smooth trimming"]
226 #[inline(always)]
227 pub const fn trim(&self) -> u8 {
228 let val = (self.0 >> 8usize) & 0x3f;
229 val as u8
230 }
231 #[doc = "HSI48 oscillator smooth trimming"]
232 #[inline(always)]
233 pub fn set_trim(&mut self, val: u8) {
234 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
235 }
236 }
237 impl Default for Cr {
238 #[inline(always)]
239 fn default() -> Cr {
240 Cr(0)
241 }
242 }
243 impl core::fmt::Debug for Cr {
244 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
245 f.debug_struct("Cr")
246 .field("syncokie", &self.syncokie())
247 .field("syncwarnie", &self.syncwarnie())
248 .field("errie", &self.errie())
249 .field("esyncie", &self.esyncie())
250 .field("cen", &self.cen())
251 .field("autotrimen", &self.autotrimen())
252 .field("swsync", &self.swsync())
253 .field("trim", &self.trim())
254 .finish()
255 }
256 }
257 #[cfg(feature = "defmt")]
258 impl defmt::Format for Cr {
259 fn format(&self, f: defmt::Formatter) {
260 #[derive(defmt :: Format)]
261 struct Cr {
262 syncokie: bool,
263 syncwarnie: bool,
264 errie: bool,
265 esyncie: bool,
266 cen: bool,
267 autotrimen: bool,
268 swsync: bool,
269 trim: u8,
270 }
271 let proxy = Cr {
272 syncokie: self.syncokie(),
273 syncwarnie: self.syncwarnie(),
274 errie: self.errie(),
275 esyncie: self.esyncie(),
276 cen: self.cen(),
277 autotrimen: self.autotrimen(),
278 swsync: self.swsync(),
279 trim: self.trim(),
280 };
281 defmt::write!(f, "{}", proxy)
282 }
283 }
284 #[doc = "interrupt flag clear register"]
285 #[repr(transparent)]
286 #[derive(Copy, Clone, Eq, PartialEq)]
287 pub struct Icr(pub u32);
288 impl Icr {
289 #[doc = "SYNC event OK clear flag"]
290 #[inline(always)]
291 pub const fn syncokc(&self) -> bool {
292 let val = (self.0 >> 0usize) & 0x01;
293 val != 0
294 }
295 #[doc = "SYNC event OK clear flag"]
296 #[inline(always)]
297 pub fn set_syncokc(&mut self, val: bool) {
298 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
299 }
300 #[doc = "SYNC warning clear flag"]
301 #[inline(always)]
302 pub const fn syncwarnc(&self) -> bool {
303 let val = (self.0 >> 1usize) & 0x01;
304 val != 0
305 }
306 #[doc = "SYNC warning clear flag"]
307 #[inline(always)]
308 pub fn set_syncwarnc(&mut self, val: bool) {
309 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
310 }
311 #[doc = "Error clear flag"]
312 #[inline(always)]
313 pub const fn errc(&self) -> bool {
314 let val = (self.0 >> 2usize) & 0x01;
315 val != 0
316 }
317 #[doc = "Error clear flag"]
318 #[inline(always)]
319 pub fn set_errc(&mut self, val: bool) {
320 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
321 }
322 #[doc = "Expected SYNC clear flag"]
323 #[inline(always)]
324 pub const fn esyncc(&self) -> bool {
325 let val = (self.0 >> 3usize) & 0x01;
326 val != 0
327 }
328 #[doc = "Expected SYNC clear flag"]
329 #[inline(always)]
330 pub fn set_esyncc(&mut self, val: bool) {
331 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
332 }
333 }
334 impl Default for Icr {
335 #[inline(always)]
336 fn default() -> Icr {
337 Icr(0)
338 }
339 }
340 impl core::fmt::Debug for Icr {
341 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
342 f.debug_struct("Icr")
343 .field("syncokc", &self.syncokc())
344 .field("syncwarnc", &self.syncwarnc())
345 .field("errc", &self.errc())
346 .field("esyncc", &self.esyncc())
347 .finish()
348 }
349 }
350 #[cfg(feature = "defmt")]
351 impl defmt::Format for Icr {
352 fn format(&self, f: defmt::Formatter) {
353 #[derive(defmt :: Format)]
354 struct Icr {
355 syncokc: bool,
356 syncwarnc: bool,
357 errc: bool,
358 esyncc: bool,
359 }
360 let proxy = Icr {
361 syncokc: self.syncokc(),
362 syncwarnc: self.syncwarnc(),
363 errc: self.errc(),
364 esyncc: self.esyncc(),
365 };
366 defmt::write!(f, "{}", proxy)
367 }
368 }
369 #[doc = "interrupt and status register"]
370 #[repr(transparent)]
371 #[derive(Copy, Clone, Eq, PartialEq)]
372 pub struct Isr(pub u32);
373 impl Isr {
374 #[doc = "SYNC event OK flag"]
375 #[inline(always)]
376 pub const fn syncokf(&self) -> bool {
377 let val = (self.0 >> 0usize) & 0x01;
378 val != 0
379 }
380 #[doc = "SYNC event OK flag"]
381 #[inline(always)]
382 pub fn set_syncokf(&mut self, val: bool) {
383 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
384 }
385 #[doc = "SYNC warning flag"]
386 #[inline(always)]
387 pub const fn syncwarnf(&self) -> bool {
388 let val = (self.0 >> 1usize) & 0x01;
389 val != 0
390 }
391 #[doc = "SYNC warning flag"]
392 #[inline(always)]
393 pub fn set_syncwarnf(&mut self, val: bool) {
394 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
395 }
396 #[doc = "Error flag"]
397 #[inline(always)]
398 pub const fn errf(&self) -> bool {
399 let val = (self.0 >> 2usize) & 0x01;
400 val != 0
401 }
402 #[doc = "Error flag"]
403 #[inline(always)]
404 pub fn set_errf(&mut self, val: bool) {
405 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
406 }
407 #[doc = "Expected SYNC flag"]
408 #[inline(always)]
409 pub const fn esyncf(&self) -> bool {
410 let val = (self.0 >> 3usize) & 0x01;
411 val != 0
412 }
413 #[doc = "Expected SYNC flag"]
414 #[inline(always)]
415 pub fn set_esyncf(&mut self, val: bool) {
416 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
417 }
418 #[doc = "SYNC error"]
419 #[inline(always)]
420 pub const fn syncerr(&self) -> bool {
421 let val = (self.0 >> 8usize) & 0x01;
422 val != 0
423 }
424 #[doc = "SYNC error"]
425 #[inline(always)]
426 pub fn set_syncerr(&mut self, val: bool) {
427 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
428 }
429 #[doc = "SYNC missed"]
430 #[inline(always)]
431 pub const fn syncmiss(&self) -> bool {
432 let val = (self.0 >> 9usize) & 0x01;
433 val != 0
434 }
435 #[doc = "SYNC missed"]
436 #[inline(always)]
437 pub fn set_syncmiss(&mut self, val: bool) {
438 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
439 }
440 #[doc = "Trimming overflow or underflow"]
441 #[inline(always)]
442 pub const fn trimovf(&self) -> bool {
443 let val = (self.0 >> 10usize) & 0x01;
444 val != 0
445 }
446 #[doc = "Trimming overflow or underflow"]
447 #[inline(always)]
448 pub fn set_trimovf(&mut self, val: bool) {
449 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
450 }
451 #[doc = "Frequency error direction"]
452 #[inline(always)]
453 pub const fn fedir(&self) -> bool {
454 let val = (self.0 >> 15usize) & 0x01;
455 val != 0
456 }
457 #[doc = "Frequency error direction"]
458 #[inline(always)]
459 pub fn set_fedir(&mut self, val: bool) {
460 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
461 }
462 #[doc = "Frequency error capture"]
463 #[inline(always)]
464 pub const fn fecap(&self) -> u16 {
465 let val = (self.0 >> 16usize) & 0xffff;
466 val as u16
467 }
468 #[doc = "Frequency error capture"]
469 #[inline(always)]
470 pub fn set_fecap(&mut self, val: u16) {
471 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
472 }
473 }
474 impl Default for Isr {
475 #[inline(always)]
476 fn default() -> Isr {
477 Isr(0)
478 }
479 }
480 impl core::fmt::Debug for Isr {
481 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
482 f.debug_struct("Isr")
483 .field("syncokf", &self.syncokf())
484 .field("syncwarnf", &self.syncwarnf())
485 .field("errf", &self.errf())
486 .field("esyncf", &self.esyncf())
487 .field("syncerr", &self.syncerr())
488 .field("syncmiss", &self.syncmiss())
489 .field("trimovf", &self.trimovf())
490 .field("fedir", &self.fedir())
491 .field("fecap", &self.fecap())
492 .finish()
493 }
494 }
495 #[cfg(feature = "defmt")]
496 impl defmt::Format for Isr {
497 fn format(&self, f: defmt::Formatter) {
498 #[derive(defmt :: Format)]
499 struct Isr {
500 syncokf: bool,
501 syncwarnf: bool,
502 errf: bool,
503 esyncf: bool,
504 syncerr: bool,
505 syncmiss: bool,
506 trimovf: bool,
507 fedir: bool,
508 fecap: u16,
509 }
510 let proxy = Isr {
511 syncokf: self.syncokf(),
512 syncwarnf: self.syncwarnf(),
513 errf: self.errf(),
514 esyncf: self.esyncf(),
515 syncerr: self.syncerr(),
516 syncmiss: self.syncmiss(),
517 trimovf: self.trimovf(),
518 fedir: self.fedir(),
519 fecap: self.fecap(),
520 };
521 defmt::write!(f, "{}", proxy)
522 }
523 }
524}
525pub mod vals {
526 #[repr(u8)]
527 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
528 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
529 pub enum Syncsrc {
530 #[doc = "GPIO selected as SYNC signal source"]
531 GPIO = 0x0,
532 #[doc = "LSE selected as SYNC signal source"]
533 LSE = 0x01,
534 #[doc = "USB SOF selected as SYNC signal source"]
535 USB = 0x02,
536 _RESERVED_3 = 0x03,
537 }
538 impl Syncsrc {
539 #[inline(always)]
540 pub const fn from_bits(val: u8) -> Syncsrc {
541 unsafe { core::mem::transmute(val & 0x03) }
542 }
543 #[inline(always)]
544 pub const fn to_bits(self) -> u8 {
545 unsafe { core::mem::transmute(self) }
546 }
547 }
548 impl From<u8> for Syncsrc {
549 #[inline(always)]
550 fn from(val: u8) -> Syncsrc {
551 Syncsrc::from_bits(val)
552 }
553 }
554 impl From<Syncsrc> for u8 {
555 #[inline(always)]
556 fn from(val: Syncsrc) -> u8 {
557 Syncsrc::to_bits(val)
558 }
559 }
560}
561