1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Digital-to-analog converter"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Dac {
9 ptr: *mut u8,
10}
11unsafe impl Send for Dac {}
12unsafe impl Sync for Dac {}
13impl Dac {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "control register"]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "software trigger register"]
28 #[inline(always)]
29 pub const fn swtrigr(self) -> crate::common::Reg<regs::Swtrigr, crate::common::W> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "channel 12-bit right-aligned data holding register"]
33 #[inline(always)]
34 pub const fn dhr12r(self, n: usize) -> crate::common::Reg<regs::Dhr12r, crate::common::RW> {
35 assert!(n < 2usize);
36 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 12usize) as _) }
37 }
38 #[doc = "channel 12-bit left-aligned data holding register"]
39 #[inline(always)]
40 pub const fn dhr12l(self, n: usize) -> crate::common::Reg<regs::Dhr12l, crate::common::RW> {
41 assert!(n < 2usize);
42 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize + n * 12usize) as _) }
43 }
44 #[doc = "channel 8-bit right-aligned data holding register"]
45 #[inline(always)]
46 pub const fn dhr8r(self, n: usize) -> crate::common::Reg<regs::Dhr8r, crate::common::RW> {
47 assert!(n < 2usize);
48 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 12usize) as _) }
49 }
50 #[doc = "dual 12-bit right-aligned data holding register"]
51 #[inline(always)]
52 pub const fn dhr12rd(self) -> crate::common::Reg<regs::Dhr12rd, crate::common::RW> {
53 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
54 }
55 #[doc = "dual 12-bit left aligned data holding register"]
56 #[inline(always)]
57 pub const fn dhr12ld(self) -> crate::common::Reg<regs::Dhr12ld, crate::common::RW> {
58 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
59 }
60 #[doc = "dual 8-bit right aligned data holding register"]
61 #[inline(always)]
62 pub const fn dhr8rd(self) -> crate::common::Reg<regs::Dhr8rd, crate::common::RW> {
63 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
64 }
65 #[doc = "channel data output register"]
66 #[inline(always)]
67 pub const fn dor(self, n: usize) -> crate::common::Reg<regs::Dor, crate::common::R> {
68 assert!(n < 2usize);
69 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize + n * 4usize) as _) }
70 }
71 #[doc = "status register"]
72 #[inline(always)]
73 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
74 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
75 }
76 #[doc = "calibration control register"]
77 #[inline(always)]
78 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
79 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
80 }
81 #[doc = "mode control register"]
82 #[inline(always)]
83 pub const fn mcr(self) -> crate::common::Reg<regs::Mcr, crate::common::RW> {
84 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
85 }
86 #[doc = "sample and hold sample time register"]
87 #[inline(always)]
88 pub const fn shsr(self, n: usize) -> crate::common::Reg<regs::Shsr, crate::common::RW> {
89 assert!(n < 2usize);
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize + n * 4usize) as _) }
91 }
92 #[doc = "sample and hold hold time register"]
93 #[inline(always)]
94 pub const fn shhr(self) -> crate::common::Reg<regs::Shhr, crate::common::RW> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
96 }
97 #[doc = "sample and hold refresh time register"]
98 #[inline(always)]
99 pub const fn shrr(self) -> crate::common::Reg<regs::Shrr, crate::common::RW> {
100 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
101 }
102}
103pub mod regs {
104 #[doc = "calibration control register"]
105 #[repr(transparent)]
106 #[derive(Copy, Clone, Eq, PartialEq)]
107 pub struct Ccr(pub u32);
108 impl Ccr {
109 #[doc = "channel offset trimming value"]
110 #[inline(always)]
111 pub const fn otrim(&self, n: usize) -> u8 {
112 assert!(n < 2usize);
113 let offs = 0usize + n * 16usize;
114 let val = (self.0 >> offs) & 0x1f;
115 val as u8
116 }
117 #[doc = "channel offset trimming value"]
118 #[inline(always)]
119 pub fn set_otrim(&mut self, n: usize, val: u8) {
120 assert!(n < 2usize);
121 let offs = 0usize + n * 16usize;
122 self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
123 }
124 }
125 impl Default for Ccr {
126 #[inline(always)]
127 fn default() -> Ccr {
128 Ccr(0)
129 }
130 }
131 impl core::fmt::Debug for Ccr {
132 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
133 f.debug_struct("Ccr")
134 .field("otrim", &[self.otrim(0usize), self.otrim(1usize)])
135 .finish()
136 }
137 }
138 #[cfg(feature = "defmt")]
139 impl defmt::Format for Ccr {
140 fn format(&self, f: defmt::Formatter) {
141 #[derive(defmt :: Format)]
142 struct Ccr {
143 otrim: [u8; 2usize],
144 }
145 let proxy = Ccr {
146 otrim: [self.otrim(0usize), self.otrim(1usize)],
147 };
148 defmt::write!(f, "{}", proxy)
149 }
150 }
151 #[doc = "control register"]
152 #[repr(transparent)]
153 #[derive(Copy, Clone, Eq, PartialEq)]
154 pub struct Cr(pub u32);
155 impl Cr {
156 #[doc = "channel enable"]
157 #[inline(always)]
158 pub const fn en(&self, n: usize) -> bool {
159 assert!(n < 2usize);
160 let offs = 0usize + n * 16usize;
161 let val = (self.0 >> offs) & 0x01;
162 val != 0
163 }
164 #[doc = "channel enable"]
165 #[inline(always)]
166 pub fn set_en(&mut self, n: usize, val: bool) {
167 assert!(n < 2usize);
168 let offs = 0usize + n * 16usize;
169 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
170 }
171 #[doc = "channel trigger enable"]
172 #[inline(always)]
173 pub const fn ten(&self, n: usize) -> bool {
174 assert!(n < 2usize);
175 let offs = 1usize + n * 16usize;
176 let val = (self.0 >> offs) & 0x01;
177 val != 0
178 }
179 #[doc = "channel trigger enable"]
180 #[inline(always)]
181 pub fn set_ten(&mut self, n: usize, val: bool) {
182 assert!(n < 2usize);
183 let offs = 1usize + n * 16usize;
184 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
185 }
186 #[doc = "channel trigger selection"]
187 #[inline(always)]
188 pub const fn tsel(&self, n: usize) -> u8 {
189 assert!(n < 2usize);
190 let offs = 2usize + n * 16usize;
191 let val = (self.0 >> offs) & 0x0f;
192 val as u8
193 }
194 #[doc = "channel trigger selection"]
195 #[inline(always)]
196 pub fn set_tsel(&mut self, n: usize, val: u8) {
197 assert!(n < 2usize);
198 let offs = 2usize + n * 16usize;
199 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
200 }
201 #[doc = "channel noise/triangle wave generation enable"]
202 #[inline(always)]
203 pub const fn wave(&self, n: usize) -> super::vals::Wave {
204 assert!(n < 2usize);
205 let offs = 6usize + n * 16usize;
206 let val = (self.0 >> offs) & 0x03;
207 super::vals::Wave::from_bits(val as u8)
208 }
209 #[doc = "channel noise/triangle wave generation enable"]
210 #[inline(always)]
211 pub fn set_wave(&mut self, n: usize, val: super::vals::Wave) {
212 assert!(n < 2usize);
213 let offs = 6usize + n * 16usize;
214 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
215 }
216 #[doc = "channel mask/amplitude selector"]
217 #[inline(always)]
218 pub const fn mamp(&self, n: usize) -> u8 {
219 assert!(n < 2usize);
220 let offs = 8usize + n * 16usize;
221 let val = (self.0 >> offs) & 0x0f;
222 val as u8
223 }
224 #[doc = "channel mask/amplitude selector"]
225 #[inline(always)]
226 pub fn set_mamp(&mut self, n: usize, val: u8) {
227 assert!(n < 2usize);
228 let offs = 8usize + n * 16usize;
229 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
230 }
231 #[doc = "channel DMA enable"]
232 #[inline(always)]
233 pub const fn dmaen(&self, n: usize) -> bool {
234 assert!(n < 2usize);
235 let offs = 12usize + n * 16usize;
236 let val = (self.0 >> offs) & 0x01;
237 val != 0
238 }
239 #[doc = "channel DMA enable"]
240 #[inline(always)]
241 pub fn set_dmaen(&mut self, n: usize, val: bool) {
242 assert!(n < 2usize);
243 let offs = 12usize + n * 16usize;
244 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
245 }
246 #[doc = "channel DMA Underrun Interrupt enable"]
247 #[inline(always)]
248 pub const fn dmaudrie(&self, n: usize) -> bool {
249 assert!(n < 2usize);
250 let offs = 13usize + n * 16usize;
251 let val = (self.0 >> offs) & 0x01;
252 val != 0
253 }
254 #[doc = "channel DMA Underrun Interrupt enable"]
255 #[inline(always)]
256 pub fn set_dmaudrie(&mut self, n: usize, val: bool) {
257 assert!(n < 2usize);
258 let offs = 13usize + n * 16usize;
259 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
260 }
261 #[doc = "DAC channel calibration enable"]
262 #[inline(always)]
263 pub const fn cen(&self, n: usize) -> bool {
264 assert!(n < 2usize);
265 let offs = 14usize + n * 16usize;
266 let val = (self.0 >> offs) & 0x01;
267 val != 0
268 }
269 #[doc = "DAC channel calibration enable"]
270 #[inline(always)]
271 pub fn set_cen(&mut self, n: usize, val: bool) {
272 assert!(n < 2usize);
273 let offs = 14usize + n * 16usize;
274 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
275 }
276 }
277 impl Default for Cr {
278 #[inline(always)]
279 fn default() -> Cr {
280 Cr(0)
281 }
282 }
283 impl core::fmt::Debug for Cr {
284 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
285 f.debug_struct("Cr")
286 .field("en", &[self.en(0usize), self.en(1usize)])
287 .field("ten", &[self.ten(0usize), self.ten(1usize)])
288 .field("tsel", &[self.tsel(0usize), self.tsel(1usize)])
289 .field("wave", &[self.wave(0usize), self.wave(1usize)])
290 .field("mamp", &[self.mamp(0usize), self.mamp(1usize)])
291 .field("dmaen", &[self.dmaen(0usize), self.dmaen(1usize)])
292 .field("dmaudrie", &[self.dmaudrie(0usize), self.dmaudrie(1usize)])
293 .field("cen", &[self.cen(0usize), self.cen(1usize)])
294 .finish()
295 }
296 }
297 #[cfg(feature = "defmt")]
298 impl defmt::Format for Cr {
299 fn format(&self, f: defmt::Formatter) {
300 #[derive(defmt :: Format)]
301 struct Cr {
302 en: [bool; 2usize],
303 ten: [bool; 2usize],
304 tsel: [u8; 2usize],
305 wave: [super::vals::Wave; 2usize],
306 mamp: [u8; 2usize],
307 dmaen: [bool; 2usize],
308 dmaudrie: [bool; 2usize],
309 cen: [bool; 2usize],
310 }
311 let proxy = Cr {
312 en: [self.en(0usize), self.en(1usize)],
313 ten: [self.ten(0usize), self.ten(1usize)],
314 tsel: [self.tsel(0usize), self.tsel(1usize)],
315 wave: [self.wave(0usize), self.wave(1usize)],
316 mamp: [self.mamp(0usize), self.mamp(1usize)],
317 dmaen: [self.dmaen(0usize), self.dmaen(1usize)],
318 dmaudrie: [self.dmaudrie(0usize), self.dmaudrie(1usize)],
319 cen: [self.cen(0usize), self.cen(1usize)],
320 };
321 defmt::write!(f, "{}", proxy)
322 }
323 }
324 #[doc = "channel 12-bit left-aligned data holding register"]
325 #[repr(transparent)]
326 #[derive(Copy, Clone, Eq, PartialEq)]
327 pub struct Dhr12l(pub u32);
328 impl Dhr12l {
329 #[doc = "channel 12-bit left-aligned data"]
330 #[inline(always)]
331 pub const fn dhr(&self) -> u16 {
332 let val = (self.0 >> 4usize) & 0x0fff;
333 val as u16
334 }
335 #[doc = "channel 12-bit left-aligned data"]
336 #[inline(always)]
337 pub fn set_dhr(&mut self, val: u16) {
338 self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
339 }
340 #[doc = "channel 12-bit left-aligned data B"]
341 #[inline(always)]
342 pub const fn dhrb(&self) -> u16 {
343 let val = (self.0 >> 20usize) & 0x0fff;
344 val as u16
345 }
346 #[doc = "channel 12-bit left-aligned data B"]
347 #[inline(always)]
348 pub fn set_dhrb(&mut self, val: u16) {
349 self.0 = (self.0 & !(0x0fff << 20usize)) | (((val as u32) & 0x0fff) << 20usize);
350 }
351 }
352 impl Default for Dhr12l {
353 #[inline(always)]
354 fn default() -> Dhr12l {
355 Dhr12l(0)
356 }
357 }
358 impl core::fmt::Debug for Dhr12l {
359 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
360 f.debug_struct("Dhr12l")
361 .field("dhr", &self.dhr())
362 .field("dhrb", &self.dhrb())
363 .finish()
364 }
365 }
366 #[cfg(feature = "defmt")]
367 impl defmt::Format for Dhr12l {
368 fn format(&self, f: defmt::Formatter) {
369 #[derive(defmt :: Format)]
370 struct Dhr12l {
371 dhr: u16,
372 dhrb: u16,
373 }
374 let proxy = Dhr12l {
375 dhr: self.dhr(),
376 dhrb: self.dhrb(),
377 };
378 defmt::write!(f, "{}", proxy)
379 }
380 }
381 #[doc = "dual 12-bit left aligned data holding register"]
382 #[repr(transparent)]
383 #[derive(Copy, Clone, Eq, PartialEq)]
384 pub struct Dhr12ld(pub u32);
385 impl Dhr12ld {
386 #[doc = "channel 12-bit left-aligned data"]
387 #[inline(always)]
388 pub const fn dhr(&self, n: usize) -> u16 {
389 assert!(n < 2usize);
390 let offs = 4usize + n * 16usize;
391 let val = (self.0 >> offs) & 0x0fff;
392 val as u16
393 }
394 #[doc = "channel 12-bit left-aligned data"]
395 #[inline(always)]
396 pub fn set_dhr(&mut self, n: usize, val: u16) {
397 assert!(n < 2usize);
398 let offs = 4usize + n * 16usize;
399 self.0 = (self.0 & !(0x0fff << offs)) | (((val as u32) & 0x0fff) << offs);
400 }
401 }
402 impl Default for Dhr12ld {
403 #[inline(always)]
404 fn default() -> Dhr12ld {
405 Dhr12ld(0)
406 }
407 }
408 impl core::fmt::Debug for Dhr12ld {
409 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
410 f.debug_struct("Dhr12ld")
411 .field("dhr", &[self.dhr(0usize), self.dhr(1usize)])
412 .finish()
413 }
414 }
415 #[cfg(feature = "defmt")]
416 impl defmt::Format for Dhr12ld {
417 fn format(&self, f: defmt::Formatter) {
418 #[derive(defmt :: Format)]
419 struct Dhr12ld {
420 dhr: [u16; 2usize],
421 }
422 let proxy = Dhr12ld {
423 dhr: [self.dhr(0usize), self.dhr(1usize)],
424 };
425 defmt::write!(f, "{}", proxy)
426 }
427 }
428 #[doc = "channel 12-bit right-aligned data holding register"]
429 #[repr(transparent)]
430 #[derive(Copy, Clone, Eq, PartialEq)]
431 pub struct Dhr12r(pub u32);
432 impl Dhr12r {
433 #[doc = "channel 12-bit right-aligned data"]
434 #[inline(always)]
435 pub const fn dhr(&self) -> u16 {
436 let val = (self.0 >> 0usize) & 0x0fff;
437 val as u16
438 }
439 #[doc = "channel 12-bit right-aligned data"]
440 #[inline(always)]
441 pub fn set_dhr(&mut self, val: u16) {
442 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
443 }
444 #[doc = "channel 12-bit right-aligned data B"]
445 #[inline(always)]
446 pub const fn dhrb(&self) -> u16 {
447 let val = (self.0 >> 16usize) & 0x0fff;
448 val as u16
449 }
450 #[doc = "channel 12-bit right-aligned data B"]
451 #[inline(always)]
452 pub fn set_dhrb(&mut self, val: u16) {
453 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
454 }
455 }
456 impl Default for Dhr12r {
457 #[inline(always)]
458 fn default() -> Dhr12r {
459 Dhr12r(0)
460 }
461 }
462 impl core::fmt::Debug for Dhr12r {
463 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
464 f.debug_struct("Dhr12r")
465 .field("dhr", &self.dhr())
466 .field("dhrb", &self.dhrb())
467 .finish()
468 }
469 }
470 #[cfg(feature = "defmt")]
471 impl defmt::Format for Dhr12r {
472 fn format(&self, f: defmt::Formatter) {
473 #[derive(defmt :: Format)]
474 struct Dhr12r {
475 dhr: u16,
476 dhrb: u16,
477 }
478 let proxy = Dhr12r {
479 dhr: self.dhr(),
480 dhrb: self.dhrb(),
481 };
482 defmt::write!(f, "{}", proxy)
483 }
484 }
485 #[doc = "dual 12-bit right-aligned data holding register"]
486 #[repr(transparent)]
487 #[derive(Copy, Clone, Eq, PartialEq)]
488 pub struct Dhr12rd(pub u32);
489 impl Dhr12rd {
490 #[doc = "channel 12-bit right-aligned data"]
491 #[inline(always)]
492 pub const fn dhr(&self, n: usize) -> u16 {
493 assert!(n < 2usize);
494 let offs = 0usize + n * 16usize;
495 let val = (self.0 >> offs) & 0x0fff;
496 val as u16
497 }
498 #[doc = "channel 12-bit right-aligned data"]
499 #[inline(always)]
500 pub fn set_dhr(&mut self, n: usize, val: u16) {
501 assert!(n < 2usize);
502 let offs = 0usize + n * 16usize;
503 self.0 = (self.0 & !(0x0fff << offs)) | (((val as u32) & 0x0fff) << offs);
504 }
505 }
506 impl Default for Dhr12rd {
507 #[inline(always)]
508 fn default() -> Dhr12rd {
509 Dhr12rd(0)
510 }
511 }
512 impl core::fmt::Debug for Dhr12rd {
513 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
514 f.debug_struct("Dhr12rd")
515 .field("dhr", &[self.dhr(0usize), self.dhr(1usize)])
516 .finish()
517 }
518 }
519 #[cfg(feature = "defmt")]
520 impl defmt::Format for Dhr12rd {
521 fn format(&self, f: defmt::Formatter) {
522 #[derive(defmt :: Format)]
523 struct Dhr12rd {
524 dhr: [u16; 2usize],
525 }
526 let proxy = Dhr12rd {
527 dhr: [self.dhr(0usize), self.dhr(1usize)],
528 };
529 defmt::write!(f, "{}", proxy)
530 }
531 }
532 #[doc = "channel 8-bit right-aligned data holding register"]
533 #[repr(transparent)]
534 #[derive(Copy, Clone, Eq, PartialEq)]
535 pub struct Dhr8r(pub u32);
536 impl Dhr8r {
537 #[doc = "channel 8-bit right-aligned data"]
538 #[inline(always)]
539 pub const fn dhr(&self) -> u8 {
540 let val = (self.0 >> 0usize) & 0xff;
541 val as u8
542 }
543 #[doc = "channel 8-bit right-aligned data"]
544 #[inline(always)]
545 pub fn set_dhr(&mut self, val: u8) {
546 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
547 }
548 #[doc = "channel 8-bit right-aligned data B"]
549 #[inline(always)]
550 pub const fn dhrb(&self) -> u8 {
551 let val = (self.0 >> 8usize) & 0xff;
552 val as u8
553 }
554 #[doc = "channel 8-bit right-aligned data B"]
555 #[inline(always)]
556 pub fn set_dhrb(&mut self, val: u8) {
557 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
558 }
559 }
560 impl Default for Dhr8r {
561 #[inline(always)]
562 fn default() -> Dhr8r {
563 Dhr8r(0)
564 }
565 }
566 impl core::fmt::Debug for Dhr8r {
567 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
568 f.debug_struct("Dhr8r")
569 .field("dhr", &self.dhr())
570 .field("dhrb", &self.dhrb())
571 .finish()
572 }
573 }
574 #[cfg(feature = "defmt")]
575 impl defmt::Format for Dhr8r {
576 fn format(&self, f: defmt::Formatter) {
577 #[derive(defmt :: Format)]
578 struct Dhr8r {
579 dhr: u8,
580 dhrb: u8,
581 }
582 let proxy = Dhr8r {
583 dhr: self.dhr(),
584 dhrb: self.dhrb(),
585 };
586 defmt::write!(f, "{}", proxy)
587 }
588 }
589 #[doc = "dual 8-bit right aligned data holding register"]
590 #[repr(transparent)]
591 #[derive(Copy, Clone, Eq, PartialEq)]
592 pub struct Dhr8rd(pub u32);
593 impl Dhr8rd {
594 #[doc = "channel 8-bit right-aligned data"]
595 #[inline(always)]
596 pub const fn dhr(&self, n: usize) -> u8 {
597 assert!(n < 2usize);
598 let offs = 0usize + n * 8usize;
599 let val = (self.0 >> offs) & 0xff;
600 val as u8
601 }
602 #[doc = "channel 8-bit right-aligned data"]
603 #[inline(always)]
604 pub fn set_dhr(&mut self, n: usize, val: u8) {
605 assert!(n < 2usize);
606 let offs = 0usize + n * 8usize;
607 self.0 = (self.0 & !(0xff << offs)) | (((val as u32) & 0xff) << offs);
608 }
609 }
610 impl Default for Dhr8rd {
611 #[inline(always)]
612 fn default() -> Dhr8rd {
613 Dhr8rd(0)
614 }
615 }
616 impl core::fmt::Debug for Dhr8rd {
617 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
618 f.debug_struct("Dhr8rd")
619 .field("dhr", &[self.dhr(0usize), self.dhr(1usize)])
620 .finish()
621 }
622 }
623 #[cfg(feature = "defmt")]
624 impl defmt::Format for Dhr8rd {
625 fn format(&self, f: defmt::Formatter) {
626 #[derive(defmt :: Format)]
627 struct Dhr8rd {
628 dhr: [u8; 2usize],
629 }
630 let proxy = Dhr8rd {
631 dhr: [self.dhr(0usize), self.dhr(1usize)],
632 };
633 defmt::write!(f, "{}", proxy)
634 }
635 }
636 #[doc = "channel data output register"]
637 #[repr(transparent)]
638 #[derive(Copy, Clone, Eq, PartialEq)]
639 pub struct Dor(pub u32);
640 impl Dor {
641 #[doc = "channel data output"]
642 #[inline(always)]
643 pub const fn dor(&self) -> u16 {
644 let val = (self.0 >> 0usize) & 0x0fff;
645 val as u16
646 }
647 #[doc = "channel data output"]
648 #[inline(always)]
649 pub fn set_dor(&mut self, val: u16) {
650 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
651 }
652 #[doc = "channel data output B"]
653 #[inline(always)]
654 pub const fn dorb(&self) -> u16 {
655 let val = (self.0 >> 16usize) & 0x0fff;
656 val as u16
657 }
658 #[doc = "channel data output B"]
659 #[inline(always)]
660 pub fn set_dorb(&mut self, val: u16) {
661 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
662 }
663 }
664 impl Default for Dor {
665 #[inline(always)]
666 fn default() -> Dor {
667 Dor(0)
668 }
669 }
670 impl core::fmt::Debug for Dor {
671 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
672 f.debug_struct("Dor")
673 .field("dor", &self.dor())
674 .field("dorb", &self.dorb())
675 .finish()
676 }
677 }
678 #[cfg(feature = "defmt")]
679 impl defmt::Format for Dor {
680 fn format(&self, f: defmt::Formatter) {
681 #[derive(defmt :: Format)]
682 struct Dor {
683 dor: u16,
684 dorb: u16,
685 }
686 let proxy = Dor {
687 dor: self.dor(),
688 dorb: self.dorb(),
689 };
690 defmt::write!(f, "{}", proxy)
691 }
692 }
693 #[doc = "mode control register"]
694 #[repr(transparent)]
695 #[derive(Copy, Clone, Eq, PartialEq)]
696 pub struct Mcr(pub u32);
697 impl Mcr {
698 #[doc = "DAC channel mode"]
699 #[inline(always)]
700 pub const fn mode(&self, n: usize) -> super::vals::Mode {
701 assert!(n < 2usize);
702 let offs = 0usize + n * 16usize;
703 let val = (self.0 >> offs) & 0x07;
704 super::vals::Mode::from_bits(val as u8)
705 }
706 #[doc = "DAC channel mode"]
707 #[inline(always)]
708 pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
709 assert!(n < 2usize);
710 let offs = 0usize + n * 16usize;
711 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32) & 0x07) << offs);
712 }
713 #[doc = "channel DMA double data mode."]
714 #[inline(always)]
715 pub const fn dmadouble(&self, n: usize) -> bool {
716 assert!(n < 2usize);
717 let offs = 8usize + n * 16usize;
718 let val = (self.0 >> offs) & 0x01;
719 val != 0
720 }
721 #[doc = "channel DMA double data mode."]
722 #[inline(always)]
723 pub fn set_dmadouble(&mut self, n: usize, val: bool) {
724 assert!(n < 2usize);
725 let offs = 8usize + n * 16usize;
726 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
727 }
728 #[doc = "enable signed format for DAC channel"]
729 #[inline(always)]
730 pub const fn sinformat(&self, n: usize) -> bool {
731 assert!(n < 2usize);
732 let offs = 9usize + n * 16usize;
733 let val = (self.0 >> offs) & 0x01;
734 val != 0
735 }
736 #[doc = "enable signed format for DAC channel"]
737 #[inline(always)]
738 pub fn set_sinformat(&mut self, n: usize, val: bool) {
739 assert!(n < 2usize);
740 let offs = 9usize + n * 16usize;
741 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
742 }
743 #[doc = "high frequency interface mode selection"]
744 #[inline(always)]
745 pub const fn hfsel(&self) -> u8 {
746 let val = (self.0 >> 14usize) & 0x03;
747 val as u8
748 }
749 #[doc = "high frequency interface mode selection"]
750 #[inline(always)]
751 pub fn set_hfsel(&mut self, val: u8) {
752 self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
753 }
754 }
755 impl Default for Mcr {
756 #[inline(always)]
757 fn default() -> Mcr {
758 Mcr(0)
759 }
760 }
761 impl core::fmt::Debug for Mcr {
762 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
763 f.debug_struct("Mcr")
764 .field("mode", &[self.mode(0usize), self.mode(1usize)])
765 .field("dmadouble", &[self.dmadouble(0usize), self.dmadouble(1usize)])
766 .field("sinformat", &[self.sinformat(0usize), self.sinformat(1usize)])
767 .field("hfsel", &self.hfsel())
768 .finish()
769 }
770 }
771 #[cfg(feature = "defmt")]
772 impl defmt::Format for Mcr {
773 fn format(&self, f: defmt::Formatter) {
774 #[derive(defmt :: Format)]
775 struct Mcr {
776 mode: [super::vals::Mode; 2usize],
777 dmadouble: [bool; 2usize],
778 sinformat: [bool; 2usize],
779 hfsel: u8,
780 }
781 let proxy = Mcr {
782 mode: [self.mode(0usize), self.mode(1usize)],
783 dmadouble: [self.dmadouble(0usize), self.dmadouble(1usize)],
784 sinformat: [self.sinformat(0usize), self.sinformat(1usize)],
785 hfsel: self.hfsel(),
786 };
787 defmt::write!(f, "{}", proxy)
788 }
789 }
790 #[doc = "sample and hold hold time register"]
791 #[repr(transparent)]
792 #[derive(Copy, Clone, Eq, PartialEq)]
793 pub struct Shhr(pub u32);
794 impl Shhr {
795 #[doc = "channel hold time"]
796 #[inline(always)]
797 pub const fn thold(&self, n: usize) -> u16 {
798 assert!(n < 2usize);
799 let offs = 0usize + n * 16usize;
800 let val = (self.0 >> offs) & 0x03ff;
801 val as u16
802 }
803 #[doc = "channel hold time"]
804 #[inline(always)]
805 pub fn set_thold(&mut self, n: usize, val: u16) {
806 assert!(n < 2usize);
807 let offs = 0usize + n * 16usize;
808 self.0 = (self.0 & !(0x03ff << offs)) | (((val as u32) & 0x03ff) << offs);
809 }
810 }
811 impl Default for Shhr {
812 #[inline(always)]
813 fn default() -> Shhr {
814 Shhr(0)
815 }
816 }
817 impl core::fmt::Debug for Shhr {
818 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
819 f.debug_struct("Shhr")
820 .field("thold", &[self.thold(0usize), self.thold(1usize)])
821 .finish()
822 }
823 }
824 #[cfg(feature = "defmt")]
825 impl defmt::Format for Shhr {
826 fn format(&self, f: defmt::Formatter) {
827 #[derive(defmt :: Format)]
828 struct Shhr {
829 thold: [u16; 2usize],
830 }
831 let proxy = Shhr {
832 thold: [self.thold(0usize), self.thold(1usize)],
833 };
834 defmt::write!(f, "{}", proxy)
835 }
836 }
837 #[doc = "sample and hold refresh time register"]
838 #[repr(transparent)]
839 #[derive(Copy, Clone, Eq, PartialEq)]
840 pub struct Shrr(pub u32);
841 impl Shrr {
842 #[doc = "channel refresh time"]
843 #[inline(always)]
844 pub const fn trefresh(&self, n: usize) -> u8 {
845 assert!(n < 2usize);
846 let offs = 0usize + n * 16usize;
847 let val = (self.0 >> offs) & 0xff;
848 val as u8
849 }
850 #[doc = "channel refresh time"]
851 #[inline(always)]
852 pub fn set_trefresh(&mut self, n: usize, val: u8) {
853 assert!(n < 2usize);
854 let offs = 0usize + n * 16usize;
855 self.0 = (self.0 & !(0xff << offs)) | (((val as u32) & 0xff) << offs);
856 }
857 }
858 impl Default for Shrr {
859 #[inline(always)]
860 fn default() -> Shrr {
861 Shrr(0)
862 }
863 }
864 impl core::fmt::Debug for Shrr {
865 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
866 f.debug_struct("Shrr")
867 .field("trefresh", &[self.trefresh(0usize), self.trefresh(1usize)])
868 .finish()
869 }
870 }
871 #[cfg(feature = "defmt")]
872 impl defmt::Format for Shrr {
873 fn format(&self, f: defmt::Formatter) {
874 #[derive(defmt :: Format)]
875 struct Shrr {
876 trefresh: [u8; 2usize],
877 }
878 let proxy = Shrr {
879 trefresh: [self.trefresh(0usize), self.trefresh(1usize)],
880 };
881 defmt::write!(f, "{}", proxy)
882 }
883 }
884 #[doc = "sample and hold sample time register"]
885 #[repr(transparent)]
886 #[derive(Copy, Clone, Eq, PartialEq)]
887 pub struct Shsr(pub u32);
888 impl Shsr {
889 #[doc = "channel sample time"]
890 #[inline(always)]
891 pub const fn tsample(&self) -> u16 {
892 let val = (self.0 >> 0usize) & 0x03ff;
893 val as u16
894 }
895 #[doc = "channel sample time"]
896 #[inline(always)]
897 pub fn set_tsample(&mut self, val: u16) {
898 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
899 }
900 }
901 impl Default for Shsr {
902 #[inline(always)]
903 fn default() -> Shsr {
904 Shsr(0)
905 }
906 }
907 impl core::fmt::Debug for Shsr {
908 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
909 f.debug_struct("Shsr").field("tsample", &self.tsample()).finish()
910 }
911 }
912 #[cfg(feature = "defmt")]
913 impl defmt::Format for Shsr {
914 fn format(&self, f: defmt::Formatter) {
915 #[derive(defmt :: Format)]
916 struct Shsr {
917 tsample: u16,
918 }
919 let proxy = Shsr {
920 tsample: self.tsample(),
921 };
922 defmt::write!(f, "{}", proxy)
923 }
924 }
925 #[doc = "status register"]
926 #[repr(transparent)]
927 #[derive(Copy, Clone, Eq, PartialEq)]
928 pub struct Sr(pub u32);
929 impl Sr {
930 #[doc = "channel ready status bit"]
931 #[inline(always)]
932 pub const fn dacrdy(&self, n: usize) -> bool {
933 assert!(n < 2usize);
934 let offs = 11usize + n * 16usize;
935 let val = (self.0 >> offs) & 0x01;
936 val != 0
937 }
938 #[doc = "channel ready status bit"]
939 #[inline(always)]
940 pub fn set_dacrdy(&mut self, n: usize, val: bool) {
941 assert!(n < 2usize);
942 let offs = 11usize + n * 16usize;
943 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
944 }
945 #[doc = "channel output register status bit"]
946 #[inline(always)]
947 pub const fn dorstat(&self, n: usize) -> bool {
948 assert!(n < 2usize);
949 let offs = 12usize + n * 16usize;
950 let val = (self.0 >> offs) & 0x01;
951 val != 0
952 }
953 #[doc = "channel output register status bit"]
954 #[inline(always)]
955 pub fn set_dorstat(&mut self, n: usize, val: bool) {
956 assert!(n < 2usize);
957 let offs = 12usize + n * 16usize;
958 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
959 }
960 #[doc = "channel DMA underrun flag"]
961 #[inline(always)]
962 pub const fn dmaudr(&self, n: usize) -> bool {
963 assert!(n < 2usize);
964 let offs = 13usize + n * 16usize;
965 let val = (self.0 >> offs) & 0x01;
966 val != 0
967 }
968 #[doc = "channel DMA underrun flag"]
969 #[inline(always)]
970 pub fn set_dmaudr(&mut self, n: usize, val: bool) {
971 assert!(n < 2usize);
972 let offs = 13usize + n * 16usize;
973 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
974 }
975 #[doc = "channel calibration offset status"]
976 #[inline(always)]
977 pub const fn cal_flag(&self, n: usize) -> bool {
978 assert!(n < 2usize);
979 let offs = 14usize + n * 16usize;
980 let val = (self.0 >> offs) & 0x01;
981 val != 0
982 }
983 #[doc = "channel calibration offset status"]
984 #[inline(always)]
985 pub fn set_cal_flag(&mut self, n: usize, val: bool) {
986 assert!(n < 2usize);
987 let offs = 14usize + n * 16usize;
988 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
989 }
990 #[doc = "channel busy writing sample time flag"]
991 #[inline(always)]
992 pub const fn bwst(&self, n: usize) -> bool {
993 assert!(n < 2usize);
994 let offs = 15usize + n * 16usize;
995 let val = (self.0 >> offs) & 0x01;
996 val != 0
997 }
998 #[doc = "channel busy writing sample time flag"]
999 #[inline(always)]
1000 pub fn set_bwst(&mut self, n: usize, val: bool) {
1001 assert!(n < 2usize);
1002 let offs = 15usize + n * 16usize;
1003 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1004 }
1005 }
1006 impl Default for Sr {
1007 #[inline(always)]
1008 fn default() -> Sr {
1009 Sr(0)
1010 }
1011 }
1012 impl core::fmt::Debug for Sr {
1013 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1014 f.debug_struct("Sr")
1015 .field("dacrdy", &[self.dacrdy(0usize), self.dacrdy(1usize)])
1016 .field("dorstat", &[self.dorstat(0usize), self.dorstat(1usize)])
1017 .field("dmaudr", &[self.dmaudr(0usize), self.dmaudr(1usize)])
1018 .field("cal_flag", &[self.cal_flag(0usize), self.cal_flag(1usize)])
1019 .field("bwst", &[self.bwst(0usize), self.bwst(1usize)])
1020 .finish()
1021 }
1022 }
1023 #[cfg(feature = "defmt")]
1024 impl defmt::Format for Sr {
1025 fn format(&self, f: defmt::Formatter) {
1026 #[derive(defmt :: Format)]
1027 struct Sr {
1028 dacrdy: [bool; 2usize],
1029 dorstat: [bool; 2usize],
1030 dmaudr: [bool; 2usize],
1031 cal_flag: [bool; 2usize],
1032 bwst: [bool; 2usize],
1033 }
1034 let proxy = Sr {
1035 dacrdy: [self.dacrdy(0usize), self.dacrdy(1usize)],
1036 dorstat: [self.dorstat(0usize), self.dorstat(1usize)],
1037 dmaudr: [self.dmaudr(0usize), self.dmaudr(1usize)],
1038 cal_flag: [self.cal_flag(0usize), self.cal_flag(1usize)],
1039 bwst: [self.bwst(0usize), self.bwst(1usize)],
1040 };
1041 defmt::write!(f, "{}", proxy)
1042 }
1043 }
1044 #[doc = "software trigger register"]
1045 #[repr(transparent)]
1046 #[derive(Copy, Clone, Eq, PartialEq)]
1047 pub struct Swtrigr(pub u32);
1048 impl Swtrigr {
1049 #[doc = "channel software trigger"]
1050 #[inline(always)]
1051 pub const fn swtrig(&self, n: usize) -> bool {
1052 assert!(n < 2usize);
1053 let offs = 0usize + n * 1usize;
1054 let val = (self.0 >> offs) & 0x01;
1055 val != 0
1056 }
1057 #[doc = "channel software trigger"]
1058 #[inline(always)]
1059 pub fn set_swtrig(&mut self, n: usize, val: bool) {
1060 assert!(n < 2usize);
1061 let offs = 0usize + n * 1usize;
1062 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1063 }
1064 #[doc = "channel software trigger B"]
1065 #[inline(always)]
1066 pub const fn swtrigb(&self, n: usize) -> bool {
1067 assert!(n < 2usize);
1068 let offs = 16usize + n * 1usize;
1069 let val = (self.0 >> offs) & 0x01;
1070 val != 0
1071 }
1072 #[doc = "channel software trigger B"]
1073 #[inline(always)]
1074 pub fn set_swtrigb(&mut self, n: usize, val: bool) {
1075 assert!(n < 2usize);
1076 let offs = 16usize + n * 1usize;
1077 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1078 }
1079 }
1080 impl Default for Swtrigr {
1081 #[inline(always)]
1082 fn default() -> Swtrigr {
1083 Swtrigr(0)
1084 }
1085 }
1086 impl core::fmt::Debug for Swtrigr {
1087 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1088 f.debug_struct("Swtrigr")
1089 .field("swtrig", &[self.swtrig(0usize), self.swtrig(1usize)])
1090 .field("swtrigb", &[self.swtrigb(0usize), self.swtrigb(1usize)])
1091 .finish()
1092 }
1093 }
1094 #[cfg(feature = "defmt")]
1095 impl defmt::Format for Swtrigr {
1096 fn format(&self, f: defmt::Formatter) {
1097 #[derive(defmt :: Format)]
1098 struct Swtrigr {
1099 swtrig: [bool; 2usize],
1100 swtrigb: [bool; 2usize],
1101 }
1102 let proxy = Swtrigr {
1103 swtrig: [self.swtrig(0usize), self.swtrig(1usize)],
1104 swtrigb: [self.swtrigb(0usize), self.swtrigb(1usize)],
1105 };
1106 defmt::write!(f, "{}", proxy)
1107 }
1108 }
1109}
1110pub mod vals {
1111 #[repr(u8)]
1112 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1113 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1114 pub enum Mode {
1115 #[doc = "Normal mode, external pin only, buffer enabled"]
1116 NORMAL_EXT_BUFEN = 0x0,
1117 #[doc = "Normal mode, external pin and internal peripherals, buffer enabled"]
1118 NORMAL_EXT_INT_BUFEN = 0x01,
1119 #[doc = "Normal mode, external pin only, buffer disabled"]
1120 NORMAL_EXT_BUFDIS = 0x02,
1121 #[doc = "Normal mode, internal peripherals only, buffer disabled"]
1122 NORMAL_INT_BUFDIS = 0x03,
1123 #[doc = "Sample and hold mode, external pin only, buffer enabled"]
1124 SAMPHOLD_EXT_BUFEN = 0x04,
1125 #[doc = "Sample and hold mode, external pin and internal peripherals, buffer enabled"]
1126 SAMPHOLD_EXT_INT_BUFEN = 0x05,
1127 #[doc = "Sample and hold mode, external pin and internal peripherals, buffer disabled"]
1128 SAMPHOLD_EXT_INT_BUFDIS = 0x06,
1129 #[doc = "Sample and hold mode, internal peripherals only, buffer disabled"]
1130 SAMPHOLD_INT_BUFDIS = 0x07,
1131 }
1132 impl Mode {
1133 #[inline(always)]
1134 pub const fn from_bits(val: u8) -> Mode {
1135 unsafe { core::mem::transmute(val & 0x07) }
1136 }
1137 #[inline(always)]
1138 pub const fn to_bits(self) -> u8 {
1139 unsafe { core::mem::transmute(self) }
1140 }
1141 }
1142 impl From<u8> for Mode {
1143 #[inline(always)]
1144 fn from(val: u8) -> Mode {
1145 Mode::from_bits(val)
1146 }
1147 }
1148 impl From<Mode> for u8 {
1149 #[inline(always)]
1150 fn from(val: Mode) -> u8 {
1151 Mode::to_bits(val)
1152 }
1153 }
1154 #[repr(u8)]
1155 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1156 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1157 pub enum Wave {
1158 #[doc = "Wave generation disabled"]
1159 DISABLED = 0x0,
1160 #[doc = "Noise wave generation enabled"]
1161 NOISE = 0x01,
1162 #[doc = "Triangle wave generation enabled"]
1163 TRIANGLE = 0x02,
1164 _RESERVED_3 = 0x03,
1165 }
1166 impl Wave {
1167 #[inline(always)]
1168 pub const fn from_bits(val: u8) -> Wave {
1169 unsafe { core::mem::transmute(val & 0x03) }
1170 }
1171 #[inline(always)]
1172 pub const fn to_bits(self) -> u8 {
1173 unsafe { core::mem::transmute(self) }
1174 }
1175 }
1176 impl From<u8> for Wave {
1177 #[inline(always)]
1178 fn from(val: u8) -> Wave {
1179 Wave::from_bits(val)
1180 }
1181 }
1182 impl From<Wave> for u8 {
1183 #[inline(always)]
1184 fn from(val: Wave) -> u8 {
1185 Wave::to_bits(val)
1186 }
1187 }
1188}
1189