1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Data cache."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Dcache {
9 ptr: *mut u8,
10}
11unsafe impl Send for Dcache {}
12unsafe impl Sync for Dcache {}
13impl Dcache {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "DCACHE control register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "DCACHE status register."]
28 #[inline(always)]
29 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "DCACHE interrupt enable register."]
33 #[inline(always)]
34 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "DCACHE flag clear register."]
38 #[inline(always)]
39 pub const fn fcr(self) -> crate::common::Reg<regs::Fcr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "DCACHE read-hit monitor register."]
43 #[inline(always)]
44 pub const fn rhmonr(self) -> crate::common::Reg<u32, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "DCACHE read-miss monitor register."]
48 #[inline(always)]
49 pub const fn rmmonr(self) -> crate::common::Reg<regs::Rmmonr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "DCACHE write-hit monitor register."]
53 #[inline(always)]
54 pub const fn whmonr(self) -> crate::common::Reg<u32, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
56 }
57 #[doc = "DCACHE write-miss monitor register."]
58 #[inline(always)]
59 pub const fn wmmonr(self) -> crate::common::Reg<regs::Wmmonr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
61 }
62 #[doc = "DCACHE command range start address register."]
63 #[inline(always)]
64 pub const fn cmdrsaddrr(self) -> crate::common::Reg<regs::Cmdrsaddrr, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
66 }
67 #[doc = "DCACHE command range end address register."]
68 #[inline(always)]
69 pub const fn cmdreaddrr(self) -> crate::common::Reg<regs::Cmdreaddrr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
71 }
72}
73pub mod regs {
74 #[doc = "DCACHE command range end address register."]
75 #[repr(transparent)]
76 #[derive(Copy, Clone, Eq, PartialEq)]
77 pub struct Cmdreaddrr(pub u32);
78 impl Cmdreaddrr {
79 #[doc = "end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written."]
80 #[inline(always)]
81 pub const fn cmdendaddr(&self) -> u32 {
82 let val = (self.0 >> 4usize) & 0x0fff_ffff;
83 val as u32
84 }
85 #[doc = "end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written."]
86 #[inline(always)]
87 pub fn set_cmdendaddr(&mut self, val: u32) {
88 self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
89 }
90 }
91 impl Default for Cmdreaddrr {
92 #[inline(always)]
93 fn default() -> Cmdreaddrr {
94 Cmdreaddrr(0)
95 }
96 }
97 impl core::fmt::Debug for Cmdreaddrr {
98 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99 f.debug_struct("Cmdreaddrr")
100 .field("cmdendaddr", &self.cmdendaddr())
101 .finish()
102 }
103 }
104 #[cfg(feature = "defmt")]
105 impl defmt::Format for Cmdreaddrr {
106 fn format(&self, f: defmt::Formatter) {
107 #[derive(defmt :: Format)]
108 struct Cmdreaddrr {
109 cmdendaddr: u32,
110 }
111 let proxy = Cmdreaddrr {
112 cmdendaddr: self.cmdendaddr(),
113 };
114 defmt::write!(f, "{}", proxy)
115 }
116 }
117 #[doc = "DCACHE command range start address register."]
118 #[repr(transparent)]
119 #[derive(Copy, Clone, Eq, PartialEq)]
120 pub struct Cmdrsaddrr(pub u32);
121 impl Cmdrsaddrr {
122 #[doc = "start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.."]
123 #[inline(always)]
124 pub const fn cmdstartaddr(&self) -> u32 {
125 let val = (self.0 >> 4usize) & 0x0fff_ffff;
126 val as u32
127 }
128 #[doc = "start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.."]
129 #[inline(always)]
130 pub fn set_cmdstartaddr(&mut self, val: u32) {
131 self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
132 }
133 }
134 impl Default for Cmdrsaddrr {
135 #[inline(always)]
136 fn default() -> Cmdrsaddrr {
137 Cmdrsaddrr(0)
138 }
139 }
140 impl core::fmt::Debug for Cmdrsaddrr {
141 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
142 f.debug_struct("Cmdrsaddrr")
143 .field("cmdstartaddr", &self.cmdstartaddr())
144 .finish()
145 }
146 }
147 #[cfg(feature = "defmt")]
148 impl defmt::Format for Cmdrsaddrr {
149 fn format(&self, f: defmt::Formatter) {
150 #[derive(defmt :: Format)]
151 struct Cmdrsaddrr {
152 cmdstartaddr: u32,
153 }
154 let proxy = Cmdrsaddrr {
155 cmdstartaddr: self.cmdstartaddr(),
156 };
157 defmt::write!(f, "{}", proxy)
158 }
159 }
160 #[doc = "DCACHE control register."]
161 #[repr(transparent)]
162 #[derive(Copy, Clone, Eq, PartialEq)]
163 pub struct Cr(pub u32);
164 impl Cr {
165 #[doc = "enable."]
166 #[inline(always)]
167 pub const fn en(&self) -> bool {
168 let val = (self.0 >> 0usize) & 0x01;
169 val != 0
170 }
171 #[doc = "enable."]
172 #[inline(always)]
173 pub fn set_en(&mut self, val: bool) {
174 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
175 }
176 #[doc = "full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect."]
177 #[inline(always)]
178 pub const fn cacheinv(&self) -> bool {
179 let val = (self.0 >> 1usize) & 0x01;
180 val != 0
181 }
182 #[doc = "full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect."]
183 #[inline(always)]
184 pub fn set_cacheinv(&mut self, val: bool) {
185 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
186 }
187 #[doc = "cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved."]
188 #[inline(always)]
189 pub const fn cachecmd(&self) -> u8 {
190 let val = (self.0 >> 8usize) & 0x07;
191 val as u8
192 }
193 #[doc = "cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved."]
194 #[inline(always)]
195 pub fn set_cachecmd(&mut self, val: u8) {
196 self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
197 }
198 #[doc = "starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect."]
199 #[inline(always)]
200 pub const fn startcmd(&self) -> bool {
201 let val = (self.0 >> 11usize) & 0x01;
202 val != 0
203 }
204 #[doc = "starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect."]
205 #[inline(always)]
206 pub fn set_startcmd(&mut self, val: bool) {
207 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
208 }
209 #[doc = "read-hit monitor enable."]
210 #[inline(always)]
211 pub const fn rhitmen(&self) -> bool {
212 let val = (self.0 >> 16usize) & 0x01;
213 val != 0
214 }
215 #[doc = "read-hit monitor enable."]
216 #[inline(always)]
217 pub fn set_rhitmen(&mut self, val: bool) {
218 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
219 }
220 #[doc = "read-miss monitor enable."]
221 #[inline(always)]
222 pub const fn rmissmen(&self) -> bool {
223 let val = (self.0 >> 17usize) & 0x01;
224 val != 0
225 }
226 #[doc = "read-miss monitor enable."]
227 #[inline(always)]
228 pub fn set_rmissmen(&mut self, val: bool) {
229 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
230 }
231 #[doc = "read-hit monitor reset."]
232 #[inline(always)]
233 pub const fn rhitmrst(&self) -> bool {
234 let val = (self.0 >> 18usize) & 0x01;
235 val != 0
236 }
237 #[doc = "read-hit monitor reset."]
238 #[inline(always)]
239 pub fn set_rhitmrst(&mut self, val: bool) {
240 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
241 }
242 #[doc = "read-miss monitor reset."]
243 #[inline(always)]
244 pub const fn rmissmrst(&self) -> bool {
245 let val = (self.0 >> 19usize) & 0x01;
246 val != 0
247 }
248 #[doc = "read-miss monitor reset."]
249 #[inline(always)]
250 pub fn set_rmissmrst(&mut self, val: bool) {
251 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
252 }
253 #[doc = "write-hit monitor enable."]
254 #[inline(always)]
255 pub const fn whitmen(&self) -> bool {
256 let val = (self.0 >> 20usize) & 0x01;
257 val != 0
258 }
259 #[doc = "write-hit monitor enable."]
260 #[inline(always)]
261 pub fn set_whitmen(&mut self, val: bool) {
262 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
263 }
264 #[doc = "write-miss monitor enable."]
265 #[inline(always)]
266 pub const fn wmissmen(&self) -> bool {
267 let val = (self.0 >> 21usize) & 0x01;
268 val != 0
269 }
270 #[doc = "write-miss monitor enable."]
271 #[inline(always)]
272 pub fn set_wmissmen(&mut self, val: bool) {
273 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
274 }
275 #[doc = "write-hit monitor reset."]
276 #[inline(always)]
277 pub const fn whitmrst(&self) -> bool {
278 let val = (self.0 >> 22usize) & 0x01;
279 val != 0
280 }
281 #[doc = "write-hit monitor reset."]
282 #[inline(always)]
283 pub fn set_whitmrst(&mut self, val: bool) {
284 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
285 }
286 #[doc = "write-miss monitor reset."]
287 #[inline(always)]
288 pub const fn wmissmrst(&self) -> bool {
289 let val = (self.0 >> 23usize) & 0x01;
290 val != 0
291 }
292 #[doc = "write-miss monitor reset."]
293 #[inline(always)]
294 pub fn set_wmissmrst(&mut self, val: bool) {
295 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
296 }
297 #[doc = "output burst type for cache master port read accesses Write access is always done in INCR burst type."]
298 #[inline(always)]
299 pub const fn hburst(&self) -> bool {
300 let val = (self.0 >> 31usize) & 0x01;
301 val != 0
302 }
303 #[doc = "output burst type for cache master port read accesses Write access is always done in INCR burst type."]
304 #[inline(always)]
305 pub fn set_hburst(&mut self, val: bool) {
306 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
307 }
308 }
309 impl Default for Cr {
310 #[inline(always)]
311 fn default() -> Cr {
312 Cr(0)
313 }
314 }
315 impl core::fmt::Debug for Cr {
316 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
317 f.debug_struct("Cr")
318 .field("en", &self.en())
319 .field("cacheinv", &self.cacheinv())
320 .field("cachecmd", &self.cachecmd())
321 .field("startcmd", &self.startcmd())
322 .field("rhitmen", &self.rhitmen())
323 .field("rmissmen", &self.rmissmen())
324 .field("rhitmrst", &self.rhitmrst())
325 .field("rmissmrst", &self.rmissmrst())
326 .field("whitmen", &self.whitmen())
327 .field("wmissmen", &self.wmissmen())
328 .field("whitmrst", &self.whitmrst())
329 .field("wmissmrst", &self.wmissmrst())
330 .field("hburst", &self.hburst())
331 .finish()
332 }
333 }
334 #[cfg(feature = "defmt")]
335 impl defmt::Format for Cr {
336 fn format(&self, f: defmt::Formatter) {
337 #[derive(defmt :: Format)]
338 struct Cr {
339 en: bool,
340 cacheinv: bool,
341 cachecmd: u8,
342 startcmd: bool,
343 rhitmen: bool,
344 rmissmen: bool,
345 rhitmrst: bool,
346 rmissmrst: bool,
347 whitmen: bool,
348 wmissmen: bool,
349 whitmrst: bool,
350 wmissmrst: bool,
351 hburst: bool,
352 }
353 let proxy = Cr {
354 en: self.en(),
355 cacheinv: self.cacheinv(),
356 cachecmd: self.cachecmd(),
357 startcmd: self.startcmd(),
358 rhitmen: self.rhitmen(),
359 rmissmen: self.rmissmen(),
360 rhitmrst: self.rhitmrst(),
361 rmissmrst: self.rmissmrst(),
362 whitmen: self.whitmen(),
363 wmissmen: self.wmissmen(),
364 whitmrst: self.whitmrst(),
365 wmissmrst: self.wmissmrst(),
366 hburst: self.hburst(),
367 };
368 defmt::write!(f, "{}", proxy)
369 }
370 }
371 #[doc = "DCACHE flag clear register."]
372 #[repr(transparent)]
373 #[derive(Copy, Clone, Eq, PartialEq)]
374 pub struct Fcr(pub u32);
375 impl Fcr {
376 #[doc = "clear full invalidate busy end flag Set by software."]
377 #[inline(always)]
378 pub const fn cbsyendf(&self) -> bool {
379 let val = (self.0 >> 1usize) & 0x01;
380 val != 0
381 }
382 #[doc = "clear full invalidate busy end flag Set by software."]
383 #[inline(always)]
384 pub fn set_cbsyendf(&mut self, val: bool) {
385 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
386 }
387 #[doc = "clear cache error flag Set by software."]
388 #[inline(always)]
389 pub const fn cerrf(&self) -> bool {
390 let val = (self.0 >> 2usize) & 0x01;
391 val != 0
392 }
393 #[doc = "clear cache error flag Set by software."]
394 #[inline(always)]
395 pub fn set_cerrf(&mut self, val: bool) {
396 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
397 }
398 #[doc = "clear command end flag Set by software."]
399 #[inline(always)]
400 pub const fn ccmdendf(&self) -> bool {
401 let val = (self.0 >> 4usize) & 0x01;
402 val != 0
403 }
404 #[doc = "clear command end flag Set by software."]
405 #[inline(always)]
406 pub fn set_ccmdendf(&mut self, val: bool) {
407 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
408 }
409 }
410 impl Default for Fcr {
411 #[inline(always)]
412 fn default() -> Fcr {
413 Fcr(0)
414 }
415 }
416 impl core::fmt::Debug for Fcr {
417 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
418 f.debug_struct("Fcr")
419 .field("cbsyendf", &self.cbsyendf())
420 .field("cerrf", &self.cerrf())
421 .field("ccmdendf", &self.ccmdendf())
422 .finish()
423 }
424 }
425 #[cfg(feature = "defmt")]
426 impl defmt::Format for Fcr {
427 fn format(&self, f: defmt::Formatter) {
428 #[derive(defmt :: Format)]
429 struct Fcr {
430 cbsyendf: bool,
431 cerrf: bool,
432 ccmdendf: bool,
433 }
434 let proxy = Fcr {
435 cbsyendf: self.cbsyendf(),
436 cerrf: self.cerrf(),
437 ccmdendf: self.ccmdendf(),
438 };
439 defmt::write!(f, "{}", proxy)
440 }
441 }
442 #[doc = "DCACHE interrupt enable register."]
443 #[repr(transparent)]
444 #[derive(Copy, Clone, Eq, PartialEq)]
445 pub struct Ier(pub u32);
446 impl Ier {
447 #[doc = "interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation."]
448 #[inline(always)]
449 pub const fn bsyendie(&self) -> bool {
450 let val = (self.0 >> 1usize) & 0x01;
451 val != 0
452 }
453 #[doc = "interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation."]
454 #[inline(always)]
455 pub fn set_bsyendie(&mut self, val: bool) {
456 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
457 }
458 #[doc = "interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error)."]
459 #[inline(always)]
460 pub const fn errie(&self) -> bool {
461 let val = (self.0 >> 2usize) & 0x01;
462 val != 0
463 }
464 #[doc = "interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error)."]
465 #[inline(always)]
466 pub fn set_errie(&mut self, val: bool) {
467 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
468 }
469 #[doc = "interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range)."]
470 #[inline(always)]
471 pub const fn cmdendie(&self) -> bool {
472 let val = (self.0 >> 4usize) & 0x01;
473 val != 0
474 }
475 #[doc = "interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range)."]
476 #[inline(always)]
477 pub fn set_cmdendie(&mut self, val: bool) {
478 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
479 }
480 }
481 impl Default for Ier {
482 #[inline(always)]
483 fn default() -> Ier {
484 Ier(0)
485 }
486 }
487 impl core::fmt::Debug for Ier {
488 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
489 f.debug_struct("Ier")
490 .field("bsyendie", &self.bsyendie())
491 .field("errie", &self.errie())
492 .field("cmdendie", &self.cmdendie())
493 .finish()
494 }
495 }
496 #[cfg(feature = "defmt")]
497 impl defmt::Format for Ier {
498 fn format(&self, f: defmt::Formatter) {
499 #[derive(defmt :: Format)]
500 struct Ier {
501 bsyendie: bool,
502 errie: bool,
503 cmdendie: bool,
504 }
505 let proxy = Ier {
506 bsyendie: self.bsyendie(),
507 errie: self.errie(),
508 cmdendie: self.cmdendie(),
509 };
510 defmt::write!(f, "{}", proxy)
511 }
512 }
513 #[doc = "DCACHE read-miss monitor register."]
514 #[repr(transparent)]
515 #[derive(Copy, Clone, Eq, PartialEq)]
516 pub struct Rmmonr(pub u32);
517 impl Rmmonr {
518 #[doc = "cache read-miss monitor counter."]
519 #[inline(always)]
520 pub const fn rmissmon(&self) -> u16 {
521 let val = (self.0 >> 0usize) & 0xffff;
522 val as u16
523 }
524 #[doc = "cache read-miss monitor counter."]
525 #[inline(always)]
526 pub fn set_rmissmon(&mut self, val: u16) {
527 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
528 }
529 }
530 impl Default for Rmmonr {
531 #[inline(always)]
532 fn default() -> Rmmonr {
533 Rmmonr(0)
534 }
535 }
536 impl core::fmt::Debug for Rmmonr {
537 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
538 f.debug_struct("Rmmonr").field("rmissmon", &self.rmissmon()).finish()
539 }
540 }
541 #[cfg(feature = "defmt")]
542 impl defmt::Format for Rmmonr {
543 fn format(&self, f: defmt::Formatter) {
544 #[derive(defmt :: Format)]
545 struct Rmmonr {
546 rmissmon: u16,
547 }
548 let proxy = Rmmonr {
549 rmissmon: self.rmissmon(),
550 };
551 defmt::write!(f, "{}", proxy)
552 }
553 }
554 #[doc = "DCACHE status register."]
555 #[repr(transparent)]
556 #[derive(Copy, Clone, Eq, PartialEq)]
557 pub struct Sr(pub u32);
558 impl Sr {
559 #[doc = "full invalidate busy flag."]
560 #[inline(always)]
561 pub const fn busyf(&self) -> bool {
562 let val = (self.0 >> 0usize) & 0x01;
563 val != 0
564 }
565 #[doc = "full invalidate busy flag."]
566 #[inline(always)]
567 pub fn set_busyf(&mut self, val: bool) {
568 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
569 }
570 #[doc = "full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1."]
571 #[inline(always)]
572 pub const fn bsyendf(&self) -> bool {
573 let val = (self.0 >> 1usize) & 0x01;
574 val != 0
575 }
576 #[doc = "full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1."]
577 #[inline(always)]
578 pub fn set_bsyendf(&mut self, val: bool) {
579 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
580 }
581 #[doc = "cache error flag Cleared by writing DCACHE_FCR.CERRF = 1."]
582 #[inline(always)]
583 pub const fn errf(&self) -> bool {
584 let val = (self.0 >> 2usize) & 0x01;
585 val != 0
586 }
587 #[doc = "cache error flag Cleared by writing DCACHE_FCR.CERRF = 1."]
588 #[inline(always)]
589 pub fn set_errf(&mut self, val: bool) {
590 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
591 }
592 #[doc = "command busy flag."]
593 #[inline(always)]
594 pub const fn busycmdf(&self) -> bool {
595 let val = (self.0 >> 3usize) & 0x01;
596 val != 0
597 }
598 #[doc = "command busy flag."]
599 #[inline(always)]
600 pub fn set_busycmdf(&mut self, val: bool) {
601 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
602 }
603 #[doc = "command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1."]
604 #[inline(always)]
605 pub const fn cmdendf(&self) -> bool {
606 let val = (self.0 >> 4usize) & 0x01;
607 val != 0
608 }
609 #[doc = "command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1."]
610 #[inline(always)]
611 pub fn set_cmdendf(&mut self, val: bool) {
612 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
613 }
614 }
615 impl Default for Sr {
616 #[inline(always)]
617 fn default() -> Sr {
618 Sr(0)
619 }
620 }
621 impl core::fmt::Debug for Sr {
622 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
623 f.debug_struct("Sr")
624 .field("busyf", &self.busyf())
625 .field("bsyendf", &self.bsyendf())
626 .field("errf", &self.errf())
627 .field("busycmdf", &self.busycmdf())
628 .field("cmdendf", &self.cmdendf())
629 .finish()
630 }
631 }
632 #[cfg(feature = "defmt")]
633 impl defmt::Format for Sr {
634 fn format(&self, f: defmt::Formatter) {
635 #[derive(defmt :: Format)]
636 struct Sr {
637 busyf: bool,
638 bsyendf: bool,
639 errf: bool,
640 busycmdf: bool,
641 cmdendf: bool,
642 }
643 let proxy = Sr {
644 busyf: self.busyf(),
645 bsyendf: self.bsyendf(),
646 errf: self.errf(),
647 busycmdf: self.busycmdf(),
648 cmdendf: self.cmdendf(),
649 };
650 defmt::write!(f, "{}", proxy)
651 }
652 }
653 #[doc = "DCACHE write-miss monitor register."]
654 #[repr(transparent)]
655 #[derive(Copy, Clone, Eq, PartialEq)]
656 pub struct Wmmonr(pub u32);
657 impl Wmmonr {
658 #[doc = "cache write-miss monitor counter."]
659 #[inline(always)]
660 pub const fn wmissmon(&self) -> u16 {
661 let val = (self.0 >> 0usize) & 0xffff;
662 val as u16
663 }
664 #[doc = "cache write-miss monitor counter."]
665 #[inline(always)]
666 pub fn set_wmissmon(&mut self, val: u16) {
667 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
668 }
669 }
670 impl Default for Wmmonr {
671 #[inline(always)]
672 fn default() -> Wmmonr {
673 Wmmonr(0)
674 }
675 }
676 impl core::fmt::Debug for Wmmonr {
677 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
678 f.debug_struct("Wmmonr").field("wmissmon", &self.wmissmon()).finish()
679 }
680 }
681 #[cfg(feature = "defmt")]
682 impl defmt::Format for Wmmonr {
683 fn format(&self, f: defmt::Formatter) {
684 #[derive(defmt :: Format)]
685 struct Wmmonr {
686 wmissmon: u16,
687 }
688 let proxy = Wmmonr {
689 wmissmon: self.wmissmon(),
690 };
691 defmt::write!(f, "{}", proxy)
692 }
693 }
694}
695