1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "DSI Host."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Dsihost {
9 ptr: *mut u8,
10}
11unsafe impl Send for Dsihost {}
12unsafe impl Sync for Dsihost {}
13impl Dsihost {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "DSI Host version register."]
23 #[inline(always)]
24 pub const fn vr(self) -> crate::common::Reg<regs::Vr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "DSI Host control register."]
28 #[inline(always)]
29 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "DSI Host clock control register."]
33 #[inline(always)]
34 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "DSI Host LTDC VCID register."]
38 #[inline(always)]
39 pub const fn lvcidr(self) -> crate::common::Reg<regs::Lvcidr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "DSI Host LTDC color coding register."]
43 #[inline(always)]
44 pub const fn lcolcr(self) -> crate::common::Reg<regs::Lcolcr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "DSI Host LTDC polarity configuration register."]
48 #[inline(always)]
49 pub const fn lpcr(self) -> crate::common::Reg<regs::Lpcr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "DSI Host low-power mode configuration register."]
53 #[inline(always)]
54 pub const fn lpmcr(self) -> crate::common::Reg<regs::Lpmcr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[doc = "DSI Host protocol configuration register."]
58 #[inline(always)]
59 pub const fn pcr(self) -> crate::common::Reg<regs::Pcr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
61 }
62 #[doc = "DSI Host generic VCID register."]
63 #[inline(always)]
64 pub const fn gvcidr(self) -> crate::common::Reg<regs::Gvcidr, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
66 }
67 #[doc = "DSI Host mode configuration register."]
68 #[inline(always)]
69 pub const fn mcr(self) -> crate::common::Reg<regs::Mcr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
71 }
72 #[doc = "DSI Host video mode configuration register."]
73 #[inline(always)]
74 pub const fn vmcr(self) -> crate::common::Reg<regs::Vmcr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
76 }
77 #[doc = "DSI Host video packet configuration register."]
78 #[inline(always)]
79 pub const fn vpcr(self) -> crate::common::Reg<regs::Vpcr, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
81 }
82 #[doc = "DSI Host video chunks configuration register."]
83 #[inline(always)]
84 pub const fn vccr(self) -> crate::common::Reg<regs::Vccr, crate::common::RW> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
86 }
87 #[doc = "DSI Host video null packet configuration register."]
88 #[inline(always)]
89 pub const fn vnpcr(self) -> crate::common::Reg<regs::Vnpcr, crate::common::RW> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
91 }
92 #[doc = "DSI Host video HSA configuration register."]
93 #[inline(always)]
94 pub const fn vhsacr(self) -> crate::common::Reg<regs::Vhsacr, crate::common::RW> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
96 }
97 #[doc = "DSI Host video HBP configuration register."]
98 #[inline(always)]
99 pub const fn vhbpcr(self) -> crate::common::Reg<regs::Vhbpcr, crate::common::RW> {
100 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
101 }
102 #[doc = "DSI Host video line configuration register."]
103 #[inline(always)]
104 pub const fn vlcr(self) -> crate::common::Reg<regs::Vlcr, crate::common::RW> {
105 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
106 }
107 #[doc = "DSI Host video VSA configuration register."]
108 #[inline(always)]
109 pub const fn vvsacr(self) -> crate::common::Reg<regs::Vvsacr, crate::common::RW> {
110 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
111 }
112 #[doc = "DSI Host video VBP configuration register."]
113 #[inline(always)]
114 pub const fn vvbpcr(self) -> crate::common::Reg<regs::Vvbpcr, crate::common::RW> {
115 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
116 }
117 #[doc = "DSI Host video VFP configuration register."]
118 #[inline(always)]
119 pub const fn vvfpcr(self) -> crate::common::Reg<regs::Vvfpcr, crate::common::RW> {
120 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
121 }
122 #[doc = "DSI Host video VA configuration register."]
123 #[inline(always)]
124 pub const fn vvacr(self) -> crate::common::Reg<regs::Vvacr, crate::common::RW> {
125 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
126 }
127 #[doc = "DSI Host LTDC command configuration register."]
128 #[inline(always)]
129 pub const fn lccr(self) -> crate::common::Reg<regs::Lccr, crate::common::RW> {
130 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
131 }
132 #[doc = "DSI Host command mode configuration register."]
133 #[inline(always)]
134 pub const fn cmcr(self) -> crate::common::Reg<regs::Cmcr, crate::common::RW> {
135 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
136 }
137 #[doc = "DSI Host generic header configuration register."]
138 #[inline(always)]
139 pub const fn ghcr(self) -> crate::common::Reg<regs::Ghcr, crate::common::RW> {
140 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) }
141 }
142 #[doc = "DSI Host generic payload data register."]
143 #[inline(always)]
144 pub const fn gpdr(self) -> crate::common::Reg<regs::Gpdr, crate::common::RW> {
145 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
146 }
147 #[doc = "DSI Host generic packet status register."]
148 #[inline(always)]
149 pub const fn gpsr(self) -> crate::common::Reg<regs::Gpsr, crate::common::RW> {
150 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
151 }
152 #[doc = "DSI Host timeout counter configuration register 0."]
153 #[inline(always)]
154 pub const fn tccr0(self) -> crate::common::Reg<regs::Tccr0, crate::common::RW> {
155 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
156 }
157 #[doc = "DSI Host timeout counter configuration register 1."]
158 #[inline(always)]
159 pub const fn tccr1(self) -> crate::common::Reg<regs::Tccr1, crate::common::RW> {
160 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
161 }
162 #[doc = "DSI Host timeout counter configuration register 2."]
163 #[inline(always)]
164 pub const fn tccr2(self) -> crate::common::Reg<regs::Tccr2, crate::common::RW> {
165 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
166 }
167 #[doc = "DSI Host timeout counter configuration register 3."]
168 #[inline(always)]
169 pub const fn tccr3(self) -> crate::common::Reg<regs::Tccr3, crate::common::RW> {
170 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
171 }
172 #[doc = "DSI Host timeout counter configuration register 4."]
173 #[inline(always)]
174 pub const fn tccr4(self) -> crate::common::Reg<regs::Tccr4, crate::common::RW> {
175 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
176 }
177 #[doc = "DSI Host timeout counter configuration register 5."]
178 #[inline(always)]
179 pub const fn tccr5(self) -> crate::common::Reg<regs::Tccr5, crate::common::RW> {
180 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) }
181 }
182 #[doc = "DSI Host clock lane configuration register."]
183 #[inline(always)]
184 pub const fn clcr(self) -> crate::common::Reg<regs::Clcr, crate::common::RW> {
185 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
186 }
187 #[doc = "DSI Host clock lane timer configuration register."]
188 #[inline(always)]
189 pub const fn cltcr(self) -> crate::common::Reg<regs::Cltcr, crate::common::RW> {
190 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) }
191 }
192 #[doc = "DSI Host data lane timer configuration register."]
193 #[inline(always)]
194 pub const fn dltcr(self) -> crate::common::Reg<regs::Dltcr, crate::common::RW> {
195 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) }
196 }
197 #[doc = "DSI Host PHY control register."]
198 #[inline(always)]
199 pub const fn pctlr(self) -> crate::common::Reg<regs::Pctlr, crate::common::RW> {
200 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
201 }
202 #[doc = "DSI Host PHY configuration register."]
203 #[inline(always)]
204 pub const fn pconfr(self) -> crate::common::Reg<regs::Pconfr, crate::common::RW> {
205 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
206 }
207 #[doc = "DSI Host PHY ULPS control register."]
208 #[inline(always)]
209 pub const fn pucr(self) -> crate::common::Reg<regs::Pucr, crate::common::RW> {
210 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) }
211 }
212 #[doc = "DSI Host PHY TX triggers configuration register."]
213 #[inline(always)]
214 pub const fn pttcr(self) -> crate::common::Reg<regs::Pttcr, crate::common::RW> {
215 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) }
216 }
217 #[doc = "DSI Host PHY status register."]
218 #[inline(always)]
219 pub const fn psr(self) -> crate::common::Reg<regs::Psr, crate::common::RW> {
220 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) }
221 }
222 #[doc = "DSI Host interrupt and status register 0."]
223 #[inline(always)]
224 pub const fn isr0(self) -> crate::common::Reg<regs::Isr0, crate::common::RW> {
225 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) }
226 }
227 #[doc = "DSI Host interrupt and status register 1."]
228 #[inline(always)]
229 pub const fn isr1(self) -> crate::common::Reg<regs::Isr1, crate::common::RW> {
230 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
231 }
232 #[doc = "DSI Host interrupt enable register 0."]
233 #[inline(always)]
234 pub const fn ier0(self) -> crate::common::Reg<regs::Ier0, crate::common::RW> {
235 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
236 }
237 #[doc = "DSI Host interrupt enable register 1."]
238 #[inline(always)]
239 pub const fn ier1(self) -> crate::common::Reg<regs::Ier1, crate::common::RW> {
240 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) }
241 }
242 #[doc = "DSI Host force interrupt register 0."]
243 #[inline(always)]
244 pub const fn fir0(self) -> crate::common::Reg<regs::Fir0, crate::common::RW> {
245 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) }
246 }
247 #[doc = "DSI Host force interrupt register 1."]
248 #[inline(always)]
249 pub const fn fir1(self) -> crate::common::Reg<regs::Fir1, crate::common::RW> {
250 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) }
251 }
252 #[doc = "DSI Host data lane timer read configuration register."]
253 #[inline(always)]
254 pub const fn dltrcr(self) -> crate::common::Reg<regs::Dltrcr, crate::common::RW> {
255 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) }
256 }
257 #[doc = "DSI Host video shadow control register."]
258 #[inline(always)]
259 pub const fn vscr(self) -> crate::common::Reg<regs::Vscr, crate::common::RW> {
260 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) }
261 }
262 #[doc = "DSI Host LTDC current VCID register."]
263 #[inline(always)]
264 pub const fn lcvcidr(self) -> crate::common::Reg<regs::Lcvcidr, crate::common::RW> {
265 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) }
266 }
267 #[doc = "DSI Host LTDC current color coding register."]
268 #[inline(always)]
269 pub const fn lcccr(self) -> crate::common::Reg<regs::Lcccr, crate::common::RW> {
270 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) }
271 }
272 #[doc = "DSI Host low-power mode current configuration register."]
273 #[inline(always)]
274 pub const fn lpmccr(self) -> crate::common::Reg<regs::Lpmccr, crate::common::RW> {
275 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0118usize) as _) }
276 }
277 #[doc = "DSI Host video mode current configuration register."]
278 #[inline(always)]
279 pub const fn vmccr(self) -> crate::common::Reg<regs::Vmccr, crate::common::RW> {
280 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) }
281 }
282 #[doc = "DSI Host video packet current configuration register."]
283 #[inline(always)]
284 pub const fn vpccr(self) -> crate::common::Reg<regs::Vpccr, crate::common::RW> {
285 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013cusize) as _) }
286 }
287 #[doc = "DSI Host video chunks current configuration register."]
288 #[inline(always)]
289 pub const fn vcccr(self) -> crate::common::Reg<regs::Vcccr, crate::common::RW> {
290 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) }
291 }
292 #[doc = "DSI Host video null packet current configuration register."]
293 #[inline(always)]
294 pub const fn vnpccr(self) -> crate::common::Reg<regs::Vnpccr, crate::common::RW> {
295 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0144usize) as _) }
296 }
297 #[doc = "DSI Host video HSA current configuration register."]
298 #[inline(always)]
299 pub const fn vhsaccr(self) -> crate::common::Reg<regs::Vhsaccr, crate::common::RW> {
300 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) }
301 }
302 #[doc = "DSI Host video HBP current configuration register."]
303 #[inline(always)]
304 pub const fn vhbpccr(self) -> crate::common::Reg<regs::Vhbpccr, crate::common::RW> {
305 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014cusize) as _) }
306 }
307 #[doc = "DSI Host video line current configuration register."]
308 #[inline(always)]
309 pub const fn vlccr(self) -> crate::common::Reg<regs::Vlccr, crate::common::RW> {
310 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) }
311 }
312 #[doc = "DSI Host video VSA current configuration register."]
313 #[inline(always)]
314 pub const fn vvsaccr(self) -> crate::common::Reg<regs::Vvsaccr, crate::common::RW> {
315 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0154usize) as _) }
316 }
317 #[doc = "DSI Host video VBP current configuration register."]
318 #[inline(always)]
319 pub const fn vvbpccr(self) -> crate::common::Reg<regs::Vvbpccr, crate::common::RW> {
320 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0158usize) as _) }
321 }
322 #[doc = "DSI Host video VFP current configuration register."]
323 #[inline(always)]
324 pub const fn vvfpccr(self) -> crate::common::Reg<regs::Vvfpccr, crate::common::RW> {
325 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) }
326 }
327 #[doc = "DSI Host video VA current configuration register."]
328 #[inline(always)]
329 pub const fn vvaccr(self) -> crate::common::Reg<regs::Vvaccr, crate::common::RW> {
330 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) }
331 }
332 #[doc = "DSI Host FIFO and buffer status register."]
333 #[inline(always)]
334 pub const fn fbsr(self) -> crate::common::Reg<regs::Fbsr, crate::common::RW> {
335 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) }
336 }
337 #[doc = "DSI Wrapper configuration register."]
338 #[inline(always)]
339 pub const fn wcfgr(self) -> crate::common::Reg<regs::Wcfgr, crate::common::RW> {
340 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) }
341 }
342 #[doc = "DSI Wrapper control register."]
343 #[inline(always)]
344 pub const fn wcr(self) -> crate::common::Reg<regs::Wcr, crate::common::RW> {
345 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0404usize) as _) }
346 }
347 #[doc = "DSI Wrapper interrupt enable register."]
348 #[inline(always)]
349 pub const fn wier(self) -> crate::common::Reg<regs::Wier, crate::common::RW> {
350 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0408usize) as _) }
351 }
352 #[doc = "DSI Wrapper interrupt and status register."]
353 #[inline(always)]
354 pub const fn wisr(self) -> crate::common::Reg<regs::Wisr, crate::common::RW> {
355 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x040cusize) as _) }
356 }
357 #[doc = "DSI Wrapper interrupt flag clear register."]
358 #[inline(always)]
359 pub const fn wifcr(self) -> crate::common::Reg<regs::Wifcr, crate::common::RW> {
360 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0410usize) as _) }
361 }
362 #[doc = "DSI Wrapper PHY configuration register 0."]
363 #[inline(always)]
364 pub const fn wpcr0(self) -> crate::common::Reg<regs::Wpcr0, crate::common::RW> {
365 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0418usize) as _) }
366 }
367 #[doc = "DSI Wrapper regulator and PLL control register."]
368 #[inline(always)]
369 pub const fn wrpcr(self) -> crate::common::Reg<regs::Wrpcr, crate::common::RW> {
370 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0430usize) as _) }
371 }
372 #[doc = "DSI bias configuration register."]
373 #[inline(always)]
374 pub const fn bcfgr(self) -> crate::common::Reg<regs::Bcfgr, crate::common::RW> {
375 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0808usize) as _) }
376 }
377 #[doc = "DSI D-PHY clock band control register."]
378 #[inline(always)]
379 pub const fn dpcbcr(self) -> crate::common::Reg<regs::Dpcbcr, crate::common::RW> {
380 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c04usize) as _) }
381 }
382 #[doc = "DSI D-PHY clock skew rate control register."]
383 #[inline(always)]
384 pub const fn dpcsrcr(self) -> crate::common::Reg<regs::Dpcsrcr, crate::common::RW> {
385 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c34usize) as _) }
386 }
387 #[doc = "DSI D-PHY data lane 0 band control register."]
388 #[inline(always)]
389 pub const fn dpdl0bcr(self) -> crate::common::Reg<regs::Dpdl0bcr, crate::common::RW> {
390 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c70usize) as _) }
391 }
392 #[doc = "DSI D-PHY data lane 0 skew rate control register."]
393 #[inline(always)]
394 pub const fn dpdl0srcr(self) -> crate::common::Reg<regs::Dpdl0srcr, crate::common::RW> {
395 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0ca0usize) as _) }
396 }
397 #[doc = "DSI D-PHY data lane 1 band control register."]
398 #[inline(always)]
399 pub const fn dpdl1bcr(self) -> crate::common::Reg<regs::Dpdl1bcr, crate::common::RW> {
400 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d08usize) as _) }
401 }
402 #[doc = "DSI D-PHY data lane 1 skew rate control register."]
403 #[inline(always)]
404 pub const fn dpdl1srcr(self) -> crate::common::Reg<regs::Dpdl1srcr, crate::common::RW> {
405 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d38usize) as _) }
406 }
407}
408pub mod regs {
409 #[doc = "DSI bias configuration register."]
410 #[repr(transparent)]
411 #[derive(Copy, Clone, Eq, PartialEq)]
412 pub struct Bcfgr(pub u32);
413 impl Bcfgr {
414 #[doc = "Power-up This bit powers-up the reference bias for the MIPI D-PHY."]
415 #[inline(always)]
416 pub const fn pwrup(&self) -> bool {
417 let val = (self.0 >> 6usize) & 0x01;
418 val != 0
419 }
420 #[doc = "Power-up This bit powers-up the reference bias for the MIPI D-PHY."]
421 #[inline(always)]
422 pub fn set_pwrup(&mut self, val: bool) {
423 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
424 }
425 }
426 impl Default for Bcfgr {
427 #[inline(always)]
428 fn default() -> Bcfgr {
429 Bcfgr(0)
430 }
431 }
432 impl core::fmt::Debug for Bcfgr {
433 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
434 f.debug_struct("Bcfgr").field("pwrup", &self.pwrup()).finish()
435 }
436 }
437 #[cfg(feature = "defmt")]
438 impl defmt::Format for Bcfgr {
439 fn format(&self, f: defmt::Formatter) {
440 #[derive(defmt :: Format)]
441 struct Bcfgr {
442 pwrup: bool,
443 }
444 let proxy = Bcfgr { pwrup: self.pwrup() };
445 defmt::write!(f, "{}", proxy)
446 }
447 }
448 #[doc = "DSI Host clock control register."]
449 #[repr(transparent)]
450 #[derive(Copy, Clone, Eq, PartialEq)]
451 pub struct Ccr(pub u32);
452 impl Ccr {
453 #[doc = "TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation."]
454 #[inline(always)]
455 pub const fn txeckdiv(&self) -> u8 {
456 let val = (self.0 >> 0usize) & 0xff;
457 val as u8
458 }
459 #[doc = "TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation."]
460 #[inline(always)]
461 pub fn set_txeckdiv(&mut self, val: u8) {
462 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
463 }
464 #[doc = "Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error."]
465 #[inline(always)]
466 pub const fn tockdiv(&self) -> u8 {
467 let val = (self.0 >> 8usize) & 0xff;
468 val as u8
469 }
470 #[doc = "Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error."]
471 #[inline(always)]
472 pub fn set_tockdiv(&mut self, val: u8) {
473 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
474 }
475 }
476 impl Default for Ccr {
477 #[inline(always)]
478 fn default() -> Ccr {
479 Ccr(0)
480 }
481 }
482 impl core::fmt::Debug for Ccr {
483 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
484 f.debug_struct("Ccr")
485 .field("txeckdiv", &self.txeckdiv())
486 .field("tockdiv", &self.tockdiv())
487 .finish()
488 }
489 }
490 #[cfg(feature = "defmt")]
491 impl defmt::Format for Ccr {
492 fn format(&self, f: defmt::Formatter) {
493 #[derive(defmt :: Format)]
494 struct Ccr {
495 txeckdiv: u8,
496 tockdiv: u8,
497 }
498 let proxy = Ccr {
499 txeckdiv: self.txeckdiv(),
500 tockdiv: self.tockdiv(),
501 };
502 defmt::write!(f, "{}", proxy)
503 }
504 }
505 #[doc = "DSI Host clock lane configuration register."]
506 #[repr(transparent)]
507 #[derive(Copy, Clone, Eq, PartialEq)]
508 pub struct Clcr(pub u32);
509 impl Clcr {
510 #[doc = "D-PHY clock control This bit controls the D-PHY clock state:."]
511 #[inline(always)]
512 pub const fn dpcc(&self) -> bool {
513 let val = (self.0 >> 0usize) & 0x01;
514 val != 0
515 }
516 #[doc = "D-PHY clock control This bit controls the D-PHY clock state:."]
517 #[inline(always)]
518 pub fn set_dpcc(&mut self, val: bool) {
519 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
520 }
521 #[doc = "Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows."]
522 #[inline(always)]
523 pub const fn acr(&self) -> bool {
524 let val = (self.0 >> 1usize) & 0x01;
525 val != 0
526 }
527 #[doc = "Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows."]
528 #[inline(always)]
529 pub fn set_acr(&mut self, val: bool) {
530 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
531 }
532 }
533 impl Default for Clcr {
534 #[inline(always)]
535 fn default() -> Clcr {
536 Clcr(0)
537 }
538 }
539 impl core::fmt::Debug for Clcr {
540 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
541 f.debug_struct("Clcr")
542 .field("dpcc", &self.dpcc())
543 .field("acr", &self.acr())
544 .finish()
545 }
546 }
547 #[cfg(feature = "defmt")]
548 impl defmt::Format for Clcr {
549 fn format(&self, f: defmt::Formatter) {
550 #[derive(defmt :: Format)]
551 struct Clcr {
552 dpcc: bool,
553 acr: bool,
554 }
555 let proxy = Clcr {
556 dpcc: self.dpcc(),
557 acr: self.acr(),
558 };
559 defmt::write!(f, "{}", proxy)
560 }
561 }
562 #[doc = "DSI Host clock lane timer configuration register."]
563 #[repr(transparent)]
564 #[derive(Copy, Clone, Eq, PartialEq)]
565 pub struct Cltcr(pub u32);
566 impl Cltcr {
567 #[doc = "Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâ\u{80}\u{91}power to high-speed transmission measured in lane byte clock cycles."]
568 #[inline(always)]
569 pub const fn lp2hs_time(&self) -> u16 {
570 let val = (self.0 >> 0usize) & 0x03ff;
571 val as u16
572 }
573 #[doc = "Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâ\u{80}\u{91}power to high-speed transmission measured in lane byte clock cycles."]
574 #[inline(always)]
575 pub fn set_lp2hs_time(&mut self, val: u16) {
576 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
577 }
578 #[doc = "High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâ\u{80}\u{91}speed to low-power transmission measured in lane byte clock cycles."]
579 #[inline(always)]
580 pub const fn hs2lp_time(&self) -> u16 {
581 let val = (self.0 >> 16usize) & 0x03ff;
582 val as u16
583 }
584 #[doc = "High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâ\u{80}\u{91}speed to low-power transmission measured in lane byte clock cycles."]
585 #[inline(always)]
586 pub fn set_hs2lp_time(&mut self, val: u16) {
587 self.0 = (self.0 & !(0x03ff << 16usize)) | (((val as u32) & 0x03ff) << 16usize);
588 }
589 }
590 impl Default for Cltcr {
591 #[inline(always)]
592 fn default() -> Cltcr {
593 Cltcr(0)
594 }
595 }
596 impl core::fmt::Debug for Cltcr {
597 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
598 f.debug_struct("Cltcr")
599 .field("lp2hs_time", &self.lp2hs_time())
600 .field("hs2lp_time", &self.hs2lp_time())
601 .finish()
602 }
603 }
604 #[cfg(feature = "defmt")]
605 impl defmt::Format for Cltcr {
606 fn format(&self, f: defmt::Formatter) {
607 #[derive(defmt :: Format)]
608 struct Cltcr {
609 lp2hs_time: u16,
610 hs2lp_time: u16,
611 }
612 let proxy = Cltcr {
613 lp2hs_time: self.lp2hs_time(),
614 hs2lp_time: self.hs2lp_time(),
615 };
616 defmt::write!(f, "{}", proxy)
617 }
618 }
619 #[doc = "DSI Host command mode configuration register."]
620 #[repr(transparent)]
621 #[derive(Copy, Clone, Eq, PartialEq)]
622 pub struct Cmcr(pub u32);
623 impl Cmcr {
624 #[doc = "Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:."]
625 #[inline(always)]
626 pub const fn teare(&self) -> bool {
627 let val = (self.0 >> 0usize) & 0x01;
628 val != 0
629 }
630 #[doc = "Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:."]
631 #[inline(always)]
632 pub fn set_teare(&mut self, val: bool) {
633 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
634 }
635 #[doc = "Acknowledge request enable This bit enables the acknowledge request after each packet transmission:."]
636 #[inline(always)]
637 pub const fn are(&self) -> bool {
638 let val = (self.0 >> 1usize) & 0x01;
639 val != 0
640 }
641 #[doc = "Acknowledge request enable This bit enables the acknowledge request after each packet transmission:."]
642 #[inline(always)]
643 pub fn set_are(&mut self, val: bool) {
644 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
645 }
646 #[doc = "Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:."]
647 #[inline(always)]
648 pub const fn gsw0tx(&self) -> bool {
649 let val = (self.0 >> 8usize) & 0x01;
650 val != 0
651 }
652 #[doc = "Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:."]
653 #[inline(always)]
654 pub fn set_gsw0tx(&mut self, val: bool) {
655 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
656 }
657 #[doc = "Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:."]
658 #[inline(always)]
659 pub const fn gsw1tx(&self) -> bool {
660 let val = (self.0 >> 9usize) & 0x01;
661 val != 0
662 }
663 #[doc = "Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:."]
664 #[inline(always)]
665 pub fn set_gsw1tx(&mut self, val: bool) {
666 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
667 }
668 #[doc = "Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:."]
669 #[inline(always)]
670 pub const fn gsw2tx(&self) -> bool {
671 let val = (self.0 >> 10usize) & 0x01;
672 val != 0
673 }
674 #[doc = "Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:."]
675 #[inline(always)]
676 pub fn set_gsw2tx(&mut self, val: bool) {
677 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
678 }
679 #[doc = "Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:."]
680 #[inline(always)]
681 pub const fn gsr0tx(&self) -> bool {
682 let val = (self.0 >> 11usize) & 0x01;
683 val != 0
684 }
685 #[doc = "Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:."]
686 #[inline(always)]
687 pub fn set_gsr0tx(&mut self, val: bool) {
688 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
689 }
690 #[doc = "Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:."]
691 #[inline(always)]
692 pub const fn gsr1tx(&self) -> bool {
693 let val = (self.0 >> 12usize) & 0x01;
694 val != 0
695 }
696 #[doc = "Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:."]
697 #[inline(always)]
698 pub fn set_gsr1tx(&mut self, val: bool) {
699 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
700 }
701 #[doc = "Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:."]
702 #[inline(always)]
703 pub const fn gsr2tx(&self) -> bool {
704 let val = (self.0 >> 13usize) & 0x01;
705 val != 0
706 }
707 #[doc = "Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:."]
708 #[inline(always)]
709 pub fn set_gsr2tx(&mut self, val: bool) {
710 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
711 }
712 #[doc = "Generic long write transmission This bit configures the generic long write packet command transmission type :."]
713 #[inline(always)]
714 pub const fn glwtx(&self) -> bool {
715 let val = (self.0 >> 14usize) & 0x01;
716 val != 0
717 }
718 #[doc = "Generic long write transmission This bit configures the generic long write packet command transmission type :."]
719 #[inline(always)]
720 pub fn set_glwtx(&mut self, val: bool) {
721 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
722 }
723 #[doc = "DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:."]
724 #[inline(always)]
725 pub const fn dsw0tx(&self) -> bool {
726 let val = (self.0 >> 16usize) & 0x01;
727 val != 0
728 }
729 #[doc = "DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:."]
730 #[inline(always)]
731 pub fn set_dsw0tx(&mut self, val: bool) {
732 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
733 }
734 #[doc = "DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:."]
735 #[inline(always)]
736 pub const fn dsw1tx(&self) -> bool {
737 let val = (self.0 >> 17usize) & 0x01;
738 val != 0
739 }
740 #[doc = "DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:."]
741 #[inline(always)]
742 pub fn set_dsw1tx(&mut self, val: bool) {
743 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
744 }
745 #[doc = "DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:."]
746 #[inline(always)]
747 pub const fn dsr0tx(&self) -> bool {
748 let val = (self.0 >> 18usize) & 0x01;
749 val != 0
750 }
751 #[doc = "DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:."]
752 #[inline(always)]
753 pub fn set_dsr0tx(&mut self, val: bool) {
754 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
755 }
756 #[doc = "DCS long write transmission This bit configures the DCS long write packet command transmission type:."]
757 #[inline(always)]
758 pub const fn dlwtx(&self) -> bool {
759 let val = (self.0 >> 19usize) & 0x01;
760 val != 0
761 }
762 #[doc = "DCS long write transmission This bit configures the DCS long write packet command transmission type:."]
763 #[inline(always)]
764 pub fn set_dlwtx(&mut self, val: bool) {
765 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
766 }
767 #[doc = "Maximum read packet size This bit configures the maximum read packet size command transmission type:."]
768 #[inline(always)]
769 pub const fn mrdps(&self) -> bool {
770 let val = (self.0 >> 24usize) & 0x01;
771 val != 0
772 }
773 #[doc = "Maximum read packet size This bit configures the maximum read packet size command transmission type:."]
774 #[inline(always)]
775 pub fn set_mrdps(&mut self, val: bool) {
776 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
777 }
778 }
779 impl Default for Cmcr {
780 #[inline(always)]
781 fn default() -> Cmcr {
782 Cmcr(0)
783 }
784 }
785 impl core::fmt::Debug for Cmcr {
786 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
787 f.debug_struct("Cmcr")
788 .field("teare", &self.teare())
789 .field("are", &self.are())
790 .field("gsw0tx", &self.gsw0tx())
791 .field("gsw1tx", &self.gsw1tx())
792 .field("gsw2tx", &self.gsw2tx())
793 .field("gsr0tx", &self.gsr0tx())
794 .field("gsr1tx", &self.gsr1tx())
795 .field("gsr2tx", &self.gsr2tx())
796 .field("glwtx", &self.glwtx())
797 .field("dsw0tx", &self.dsw0tx())
798 .field("dsw1tx", &self.dsw1tx())
799 .field("dsr0tx", &self.dsr0tx())
800 .field("dlwtx", &self.dlwtx())
801 .field("mrdps", &self.mrdps())
802 .finish()
803 }
804 }
805 #[cfg(feature = "defmt")]
806 impl defmt::Format for Cmcr {
807 fn format(&self, f: defmt::Formatter) {
808 #[derive(defmt :: Format)]
809 struct Cmcr {
810 teare: bool,
811 are: bool,
812 gsw0tx: bool,
813 gsw1tx: bool,
814 gsw2tx: bool,
815 gsr0tx: bool,
816 gsr1tx: bool,
817 gsr2tx: bool,
818 glwtx: bool,
819 dsw0tx: bool,
820 dsw1tx: bool,
821 dsr0tx: bool,
822 dlwtx: bool,
823 mrdps: bool,
824 }
825 let proxy = Cmcr {
826 teare: self.teare(),
827 are: self.are(),
828 gsw0tx: self.gsw0tx(),
829 gsw1tx: self.gsw1tx(),
830 gsw2tx: self.gsw2tx(),
831 gsr0tx: self.gsr0tx(),
832 gsr1tx: self.gsr1tx(),
833 gsr2tx: self.gsr2tx(),
834 glwtx: self.glwtx(),
835 dsw0tx: self.dsw0tx(),
836 dsw1tx: self.dsw1tx(),
837 dsr0tx: self.dsr0tx(),
838 dlwtx: self.dlwtx(),
839 mrdps: self.mrdps(),
840 };
841 defmt::write!(f, "{}", proxy)
842 }
843 }
844 #[doc = "DSI Host control register."]
845 #[repr(transparent)]
846 #[derive(Copy, Clone, Eq, PartialEq)]
847 pub struct Cr(pub u32);
848 impl Cr {
849 #[doc = "Enable This bit configures the DSI Host in either power-up mode or to reset."]
850 #[inline(always)]
851 pub const fn en(&self) -> bool {
852 let val = (self.0 >> 0usize) & 0x01;
853 val != 0
854 }
855 #[doc = "Enable This bit configures the DSI Host in either power-up mode or to reset."]
856 #[inline(always)]
857 pub fn set_en(&mut self, val: bool) {
858 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
859 }
860 }
861 impl Default for Cr {
862 #[inline(always)]
863 fn default() -> Cr {
864 Cr(0)
865 }
866 }
867 impl core::fmt::Debug for Cr {
868 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
869 f.debug_struct("Cr").field("en", &self.en()).finish()
870 }
871 }
872 #[cfg(feature = "defmt")]
873 impl defmt::Format for Cr {
874 fn format(&self, f: defmt::Formatter) {
875 #[derive(defmt :: Format)]
876 struct Cr {
877 en: bool,
878 }
879 let proxy = Cr { en: self.en() };
880 defmt::write!(f, "{}", proxy)
881 }
882 }
883 #[doc = "DSI Host data lane timer configuration register."]
884 #[repr(transparent)]
885 #[derive(Copy, Clone, Eq, PartialEq)]
886 pub struct Dltcr(pub u32);
887 impl Dltcr {
888 #[doc = "Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles."]
889 #[inline(always)]
890 pub const fn lp2hs_time(&self) -> u16 {
891 let val = (self.0 >> 0usize) & 0x03ff;
892 val as u16
893 }
894 #[doc = "Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles."]
895 #[inline(always)]
896 pub fn set_lp2hs_time(&mut self, val: u16) {
897 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
898 }
899 #[doc = "High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles."]
900 #[inline(always)]
901 pub const fn hs2lp_time(&self) -> u16 {
902 let val = (self.0 >> 16usize) & 0x03ff;
903 val as u16
904 }
905 #[doc = "High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles."]
906 #[inline(always)]
907 pub fn set_hs2lp_time(&mut self, val: u16) {
908 self.0 = (self.0 & !(0x03ff << 16usize)) | (((val as u32) & 0x03ff) << 16usize);
909 }
910 }
911 impl Default for Dltcr {
912 #[inline(always)]
913 fn default() -> Dltcr {
914 Dltcr(0)
915 }
916 }
917 impl core::fmt::Debug for Dltcr {
918 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
919 f.debug_struct("Dltcr")
920 .field("lp2hs_time", &self.lp2hs_time())
921 .field("hs2lp_time", &self.hs2lp_time())
922 .finish()
923 }
924 }
925 #[cfg(feature = "defmt")]
926 impl defmt::Format for Dltcr {
927 fn format(&self, f: defmt::Formatter) {
928 #[derive(defmt :: Format)]
929 struct Dltcr {
930 lp2hs_time: u16,
931 hs2lp_time: u16,
932 }
933 let proxy = Dltcr {
934 lp2hs_time: self.lp2hs_time(),
935 hs2lp_time: self.hs2lp_time(),
936 };
937 defmt::write!(f, "{}", proxy)
938 }
939 }
940 #[doc = "DSI Host data lane timer read configuration register."]
941 #[repr(transparent)]
942 #[derive(Copy, Clone, Eq, PartialEq)]
943 pub struct Dltrcr(pub u32);
944 impl Dltrcr {
945 #[doc = "Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress."]
946 #[inline(always)]
947 pub const fn mrd_time(&self) -> u16 {
948 let val = (self.0 >> 0usize) & 0x7fff;
949 val as u16
950 }
951 #[doc = "Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress."]
952 #[inline(always)]
953 pub fn set_mrd_time(&mut self, val: u16) {
954 self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize);
955 }
956 }
957 impl Default for Dltrcr {
958 #[inline(always)]
959 fn default() -> Dltrcr {
960 Dltrcr(0)
961 }
962 }
963 impl core::fmt::Debug for Dltrcr {
964 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
965 f.debug_struct("Dltrcr").field("mrd_time", &self.mrd_time()).finish()
966 }
967 }
968 #[cfg(feature = "defmt")]
969 impl defmt::Format for Dltrcr {
970 fn format(&self, f: defmt::Formatter) {
971 #[derive(defmt :: Format)]
972 struct Dltrcr {
973 mrd_time: u16,
974 }
975 let proxy = Dltrcr {
976 mrd_time: self.mrd_time(),
977 };
978 defmt::write!(f, "{}", proxy)
979 }
980 }
981 #[doc = "DSI D-PHY clock band control register."]
982 #[repr(transparent)]
983 #[derive(Copy, Clone, Eq, PartialEq)]
984 pub struct Dpcbcr(pub u32);
985 impl Dpcbcr {
986 #[doc = "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."]
987 #[inline(always)]
988 pub const fn bc(&self) -> u8 {
989 let val = (self.0 >> 3usize) & 0x1f;
990 val as u8
991 }
992 #[doc = "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."]
993 #[inline(always)]
994 pub fn set_bc(&mut self, val: u8) {
995 self.0 = (self.0 & !(0x1f << 3usize)) | (((val as u32) & 0x1f) << 3usize);
996 }
997 }
998 impl Default for Dpcbcr {
999 #[inline(always)]
1000 fn default() -> Dpcbcr {
1001 Dpcbcr(0)
1002 }
1003 }
1004 impl core::fmt::Debug for Dpcbcr {
1005 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1006 f.debug_struct("Dpcbcr").field("bc", &self.bc()).finish()
1007 }
1008 }
1009 #[cfg(feature = "defmt")]
1010 impl defmt::Format for Dpcbcr {
1011 fn format(&self, f: defmt::Formatter) {
1012 #[derive(defmt :: Format)]
1013 struct Dpcbcr {
1014 bc: u8,
1015 }
1016 let proxy = Dpcbcr { bc: self.bc() };
1017 defmt::write!(f, "{}", proxy)
1018 }
1019 }
1020 #[doc = "DSI D-PHY clock skew rate control register."]
1021 #[repr(transparent)]
1022 #[derive(Copy, Clone, Eq, PartialEq)]
1023 pub struct Dpcsrcr(pub u32);
1024 impl Dpcsrcr {
1025 #[doc = "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."]
1026 #[inline(always)]
1027 pub const fn src(&self) -> u8 {
1028 let val = (self.0 >> 0usize) & 0xff;
1029 val as u8
1030 }
1031 #[doc = "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."]
1032 #[inline(always)]
1033 pub fn set_src(&mut self, val: u8) {
1034 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1035 }
1036 }
1037 impl Default for Dpcsrcr {
1038 #[inline(always)]
1039 fn default() -> Dpcsrcr {
1040 Dpcsrcr(0)
1041 }
1042 }
1043 impl core::fmt::Debug for Dpcsrcr {
1044 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1045 f.debug_struct("Dpcsrcr").field("src", &self.src()).finish()
1046 }
1047 }
1048 #[cfg(feature = "defmt")]
1049 impl defmt::Format for Dpcsrcr {
1050 fn format(&self, f: defmt::Formatter) {
1051 #[derive(defmt :: Format)]
1052 struct Dpcsrcr {
1053 src: u8,
1054 }
1055 let proxy = Dpcsrcr { src: self.src() };
1056 defmt::write!(f, "{}", proxy)
1057 }
1058 }
1059 #[doc = "DSI D-PHY data lane 0 band control register."]
1060 #[repr(transparent)]
1061 #[derive(Copy, Clone, Eq, PartialEq)]
1062 pub struct Dpdl0bcr(pub u32);
1063 impl Dpdl0bcr {
1064 #[doc = "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."]
1065 #[inline(always)]
1066 pub const fn bc(&self) -> u8 {
1067 let val = (self.0 >> 0usize) & 0x1f;
1068 val as u8
1069 }
1070 #[doc = "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."]
1071 #[inline(always)]
1072 pub fn set_bc(&mut self, val: u8) {
1073 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
1074 }
1075 }
1076 impl Default for Dpdl0bcr {
1077 #[inline(always)]
1078 fn default() -> Dpdl0bcr {
1079 Dpdl0bcr(0)
1080 }
1081 }
1082 impl core::fmt::Debug for Dpdl0bcr {
1083 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1084 f.debug_struct("Dpdl0bcr").field("bc", &self.bc()).finish()
1085 }
1086 }
1087 #[cfg(feature = "defmt")]
1088 impl defmt::Format for Dpdl0bcr {
1089 fn format(&self, f: defmt::Formatter) {
1090 #[derive(defmt :: Format)]
1091 struct Dpdl0bcr {
1092 bc: u8,
1093 }
1094 let proxy = Dpdl0bcr { bc: self.bc() };
1095 defmt::write!(f, "{}", proxy)
1096 }
1097 }
1098 #[doc = "DSI D-PHY data lane 0 skew rate control register."]
1099 #[repr(transparent)]
1100 #[derive(Copy, Clone, Eq, PartialEq)]
1101 pub struct Dpdl0srcr(pub u32);
1102 impl Dpdl0srcr {
1103 #[doc = "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."]
1104 #[inline(always)]
1105 pub const fn src(&self) -> u8 {
1106 let val = (self.0 >> 0usize) & 0xff;
1107 val as u8
1108 }
1109 #[doc = "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."]
1110 #[inline(always)]
1111 pub fn set_src(&mut self, val: u8) {
1112 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1113 }
1114 }
1115 impl Default for Dpdl0srcr {
1116 #[inline(always)]
1117 fn default() -> Dpdl0srcr {
1118 Dpdl0srcr(0)
1119 }
1120 }
1121 impl core::fmt::Debug for Dpdl0srcr {
1122 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1123 f.debug_struct("Dpdl0srcr").field("src", &self.src()).finish()
1124 }
1125 }
1126 #[cfg(feature = "defmt")]
1127 impl defmt::Format for Dpdl0srcr {
1128 fn format(&self, f: defmt::Formatter) {
1129 #[derive(defmt :: Format)]
1130 struct Dpdl0srcr {
1131 src: u8,
1132 }
1133 let proxy = Dpdl0srcr { src: self.src() };
1134 defmt::write!(f, "{}", proxy)
1135 }
1136 }
1137 #[doc = "DSI D-PHY data lane 1 band control register."]
1138 #[repr(transparent)]
1139 #[derive(Copy, Clone, Eq, PartialEq)]
1140 pub struct Dpdl1bcr(pub u32);
1141 impl Dpdl1bcr {
1142 #[doc = "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."]
1143 #[inline(always)]
1144 pub const fn bc(&self) -> u8 {
1145 let val = (self.0 >> 0usize) & 0x1f;
1146 val as u8
1147 }
1148 #[doc = "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."]
1149 #[inline(always)]
1150 pub fn set_bc(&mut self, val: u8) {
1151 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
1152 }
1153 }
1154 impl Default for Dpdl1bcr {
1155 #[inline(always)]
1156 fn default() -> Dpdl1bcr {
1157 Dpdl1bcr(0)
1158 }
1159 }
1160 impl core::fmt::Debug for Dpdl1bcr {
1161 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1162 f.debug_struct("Dpdl1bcr").field("bc", &self.bc()).finish()
1163 }
1164 }
1165 #[cfg(feature = "defmt")]
1166 impl defmt::Format for Dpdl1bcr {
1167 fn format(&self, f: defmt::Formatter) {
1168 #[derive(defmt :: Format)]
1169 struct Dpdl1bcr {
1170 bc: u8,
1171 }
1172 let proxy = Dpdl1bcr { bc: self.bc() };
1173 defmt::write!(f, "{}", proxy)
1174 }
1175 }
1176 #[doc = "DSI D-PHY data lane 1 skew rate control register."]
1177 #[repr(transparent)]
1178 #[derive(Copy, Clone, Eq, PartialEq)]
1179 pub struct Dpdl1srcr(pub u32);
1180 impl Dpdl1srcr {
1181 #[doc = "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."]
1182 #[inline(always)]
1183 pub const fn src(&self) -> u8 {
1184 let val = (self.0 >> 0usize) & 0xff;
1185 val as u8
1186 }
1187 #[doc = "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."]
1188 #[inline(always)]
1189 pub fn set_src(&mut self, val: u8) {
1190 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1191 }
1192 }
1193 impl Default for Dpdl1srcr {
1194 #[inline(always)]
1195 fn default() -> Dpdl1srcr {
1196 Dpdl1srcr(0)
1197 }
1198 }
1199 impl core::fmt::Debug for Dpdl1srcr {
1200 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1201 f.debug_struct("Dpdl1srcr").field("src", &self.src()).finish()
1202 }
1203 }
1204 #[cfg(feature = "defmt")]
1205 impl defmt::Format for Dpdl1srcr {
1206 fn format(&self, f: defmt::Formatter) {
1207 #[derive(defmt :: Format)]
1208 struct Dpdl1srcr {
1209 src: u8,
1210 }
1211 let proxy = Dpdl1srcr { src: self.src() };
1212 defmt::write!(f, "{}", proxy)
1213 }
1214 }
1215 #[doc = "DSI Host FIFO and buffer status register."]
1216 #[repr(transparent)]
1217 #[derive(Copy, Clone, Eq, PartialEq)]
1218 pub struct Fbsr(pub u32);
1219 impl Fbsr {
1220 #[doc = "Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:."]
1221 #[inline(always)]
1222 pub const fn vcwfe(&self) -> bool {
1223 let val = (self.0 >> 0usize) & 0x01;
1224 val != 0
1225 }
1226 #[doc = "Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:."]
1227 #[inline(always)]
1228 pub fn set_vcwfe(&mut self, val: bool) {
1229 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1230 }
1231 #[doc = "Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:."]
1232 #[inline(always)]
1233 pub const fn vcwff(&self) -> bool {
1234 let val = (self.0 >> 1usize) & 0x01;
1235 val != 0
1236 }
1237 #[doc = "Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:."]
1238 #[inline(always)]
1239 pub fn set_vcwff(&mut self, val: bool) {
1240 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1241 }
1242 #[doc = "Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:."]
1243 #[inline(always)]
1244 pub const fn vpwfe(&self) -> bool {
1245 let val = (self.0 >> 2usize) & 0x01;
1246 val != 0
1247 }
1248 #[doc = "Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:."]
1249 #[inline(always)]
1250 pub fn set_vpwfe(&mut self, val: bool) {
1251 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1252 }
1253 #[doc = "Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:."]
1254 #[inline(always)]
1255 pub const fn vpwff(&self) -> bool {
1256 let val = (self.0 >> 3usize) & 0x01;
1257 val != 0
1258 }
1259 #[doc = "Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:."]
1260 #[inline(always)]
1261 pub fn set_vpwff(&mut self, val: bool) {
1262 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1263 }
1264 #[doc = "Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:."]
1265 #[inline(always)]
1266 pub const fn acwfe(&self) -> bool {
1267 let val = (self.0 >> 4usize) & 0x01;
1268 val != 0
1269 }
1270 #[doc = "Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:."]
1271 #[inline(always)]
1272 pub fn set_acwfe(&mut self, val: bool) {
1273 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1274 }
1275 #[doc = "Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:."]
1276 #[inline(always)]
1277 pub const fn acwff(&self) -> bool {
1278 let val = (self.0 >> 5usize) & 0x01;
1279 val != 0
1280 }
1281 #[doc = "Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:."]
1282 #[inline(always)]
1283 pub fn set_acwff(&mut self, val: bool) {
1284 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1285 }
1286 #[doc = "Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:."]
1287 #[inline(always)]
1288 pub const fn apwfe(&self) -> bool {
1289 let val = (self.0 >> 6usize) & 0x01;
1290 val != 0
1291 }
1292 #[doc = "Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:."]
1293 #[inline(always)]
1294 pub fn set_apwfe(&mut self, val: bool) {
1295 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1296 }
1297 #[doc = "Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:."]
1298 #[inline(always)]
1299 pub const fn apwff(&self) -> bool {
1300 let val = (self.0 >> 7usize) & 0x01;
1301 val != 0
1302 }
1303 #[doc = "Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:."]
1304 #[inline(always)]
1305 pub fn set_apwff(&mut self, val: bool) {
1306 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1307 }
1308 #[doc = "Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:."]
1309 #[inline(always)]
1310 pub const fn vpbe(&self) -> bool {
1311 let val = (self.0 >> 16usize) & 0x01;
1312 val != 0
1313 }
1314 #[doc = "Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:."]
1315 #[inline(always)]
1316 pub fn set_vpbe(&mut self, val: bool) {
1317 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1318 }
1319 #[doc = "Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:."]
1320 #[inline(always)]
1321 pub const fn vpbf(&self) -> bool {
1322 let val = (self.0 >> 17usize) & 0x01;
1323 val != 0
1324 }
1325 #[doc = "Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:."]
1326 #[inline(always)]
1327 pub fn set_vpbf(&mut self, val: bool) {
1328 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1329 }
1330 #[doc = "Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:."]
1331 #[inline(always)]
1332 pub const fn acbe(&self) -> bool {
1333 let val = (self.0 >> 20usize) & 0x01;
1334 val != 0
1335 }
1336 #[doc = "Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:."]
1337 #[inline(always)]
1338 pub fn set_acbe(&mut self, val: bool) {
1339 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1340 }
1341 #[doc = "Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:."]
1342 #[inline(always)]
1343 pub const fn acbf(&self) -> bool {
1344 let val = (self.0 >> 21usize) & 0x01;
1345 val != 0
1346 }
1347 #[doc = "Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:."]
1348 #[inline(always)]
1349 pub fn set_acbf(&mut self, val: bool) {
1350 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1351 }
1352 #[doc = "Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:."]
1353 #[inline(always)]
1354 pub const fn apbe(&self) -> bool {
1355 let val = (self.0 >> 22usize) & 0x01;
1356 val != 0
1357 }
1358 #[doc = "Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:."]
1359 #[inline(always)]
1360 pub fn set_apbe(&mut self, val: bool) {
1361 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
1362 }
1363 #[doc = "Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:."]
1364 #[inline(always)]
1365 pub const fn apbf(&self) -> bool {
1366 let val = (self.0 >> 23usize) & 0x01;
1367 val != 0
1368 }
1369 #[doc = "Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:."]
1370 #[inline(always)]
1371 pub fn set_apbf(&mut self, val: bool) {
1372 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1373 }
1374 }
1375 impl Default for Fbsr {
1376 #[inline(always)]
1377 fn default() -> Fbsr {
1378 Fbsr(0)
1379 }
1380 }
1381 impl core::fmt::Debug for Fbsr {
1382 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1383 f.debug_struct("Fbsr")
1384 .field("vcwfe", &self.vcwfe())
1385 .field("vcwff", &self.vcwff())
1386 .field("vpwfe", &self.vpwfe())
1387 .field("vpwff", &self.vpwff())
1388 .field("acwfe", &self.acwfe())
1389 .field("acwff", &self.acwff())
1390 .field("apwfe", &self.apwfe())
1391 .field("apwff", &self.apwff())
1392 .field("vpbe", &self.vpbe())
1393 .field("vpbf", &self.vpbf())
1394 .field("acbe", &self.acbe())
1395 .field("acbf", &self.acbf())
1396 .field("apbe", &self.apbe())
1397 .field("apbf", &self.apbf())
1398 .finish()
1399 }
1400 }
1401 #[cfg(feature = "defmt")]
1402 impl defmt::Format for Fbsr {
1403 fn format(&self, f: defmt::Formatter) {
1404 #[derive(defmt :: Format)]
1405 struct Fbsr {
1406 vcwfe: bool,
1407 vcwff: bool,
1408 vpwfe: bool,
1409 vpwff: bool,
1410 acwfe: bool,
1411 acwff: bool,
1412 apwfe: bool,
1413 apwff: bool,
1414 vpbe: bool,
1415 vpbf: bool,
1416 acbe: bool,
1417 acbf: bool,
1418 apbe: bool,
1419 apbf: bool,
1420 }
1421 let proxy = Fbsr {
1422 vcwfe: self.vcwfe(),
1423 vcwff: self.vcwff(),
1424 vpwfe: self.vpwfe(),
1425 vpwff: self.vpwff(),
1426 acwfe: self.acwfe(),
1427 acwff: self.acwff(),
1428 apwfe: self.apwfe(),
1429 apwff: self.apwff(),
1430 vpbe: self.vpbe(),
1431 vpbf: self.vpbf(),
1432 acbe: self.acbe(),
1433 acbf: self.acbf(),
1434 apbe: self.apbe(),
1435 apbf: self.apbf(),
1436 };
1437 defmt::write!(f, "{}", proxy)
1438 }
1439 }
1440 #[doc = "DSI Host force interrupt register 0."]
1441 #[repr(transparent)]
1442 #[derive(Copy, Clone, Eq, PartialEq)]
1443 pub struct Fir0(pub u32);
1444 impl Fir0 {
1445 #[doc = "Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0."]
1446 #[inline(always)]
1447 pub const fn fae0(&self) -> bool {
1448 let val = (self.0 >> 0usize) & 0x01;
1449 val != 0
1450 }
1451 #[doc = "Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0."]
1452 #[inline(always)]
1453 pub fn set_fae0(&mut self, val: bool) {
1454 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1455 }
1456 #[doc = "Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1."]
1457 #[inline(always)]
1458 pub const fn fae1(&self) -> bool {
1459 let val = (self.0 >> 1usize) & 0x01;
1460 val != 0
1461 }
1462 #[doc = "Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1."]
1463 #[inline(always)]
1464 pub fn set_fae1(&mut self, val: bool) {
1465 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1466 }
1467 #[doc = "Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2."]
1468 #[inline(always)]
1469 pub const fn fae2(&self) -> bool {
1470 let val = (self.0 >> 2usize) & 0x01;
1471 val != 0
1472 }
1473 #[doc = "Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2."]
1474 #[inline(always)]
1475 pub fn set_fae2(&mut self, val: bool) {
1476 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1477 }
1478 #[doc = "Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3."]
1479 #[inline(always)]
1480 pub const fn fae3(&self) -> bool {
1481 let val = (self.0 >> 3usize) & 0x01;
1482 val != 0
1483 }
1484 #[doc = "Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3."]
1485 #[inline(always)]
1486 pub fn set_fae3(&mut self, val: bool) {
1487 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1488 }
1489 #[doc = "Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4."]
1490 #[inline(always)]
1491 pub const fn fae4(&self) -> bool {
1492 let val = (self.0 >> 4usize) & 0x01;
1493 val != 0
1494 }
1495 #[doc = "Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4."]
1496 #[inline(always)]
1497 pub fn set_fae4(&mut self, val: bool) {
1498 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1499 }
1500 #[doc = "Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5."]
1501 #[inline(always)]
1502 pub const fn fae5(&self) -> bool {
1503 let val = (self.0 >> 5usize) & 0x01;
1504 val != 0
1505 }
1506 #[doc = "Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5."]
1507 #[inline(always)]
1508 pub fn set_fae5(&mut self, val: bool) {
1509 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1510 }
1511 #[doc = "Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6."]
1512 #[inline(always)]
1513 pub const fn fae6(&self) -> bool {
1514 let val = (self.0 >> 6usize) & 0x01;
1515 val != 0
1516 }
1517 #[doc = "Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6."]
1518 #[inline(always)]
1519 pub fn set_fae6(&mut self, val: bool) {
1520 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1521 }
1522 #[doc = "Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7."]
1523 #[inline(always)]
1524 pub const fn fae7(&self) -> bool {
1525 let val = (self.0 >> 7usize) & 0x01;
1526 val != 0
1527 }
1528 #[doc = "Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7."]
1529 #[inline(always)]
1530 pub fn set_fae7(&mut self, val: bool) {
1531 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1532 }
1533 #[doc = "Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8."]
1534 #[inline(always)]
1535 pub const fn fae8(&self) -> bool {
1536 let val = (self.0 >> 8usize) & 0x01;
1537 val != 0
1538 }
1539 #[doc = "Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8."]
1540 #[inline(always)]
1541 pub fn set_fae8(&mut self, val: bool) {
1542 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1543 }
1544 #[doc = "Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9."]
1545 #[inline(always)]
1546 pub const fn fae9(&self) -> bool {
1547 let val = (self.0 >> 9usize) & 0x01;
1548 val != 0
1549 }
1550 #[doc = "Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9."]
1551 #[inline(always)]
1552 pub fn set_fae9(&mut self, val: bool) {
1553 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1554 }
1555 #[doc = "Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10."]
1556 #[inline(always)]
1557 pub const fn fae10(&self) -> bool {
1558 let val = (self.0 >> 10usize) & 0x01;
1559 val != 0
1560 }
1561 #[doc = "Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10."]
1562 #[inline(always)]
1563 pub fn set_fae10(&mut self, val: bool) {
1564 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1565 }
1566 #[doc = "Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11."]
1567 #[inline(always)]
1568 pub const fn fae11(&self) -> bool {
1569 let val = (self.0 >> 11usize) & 0x01;
1570 val != 0
1571 }
1572 #[doc = "Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11."]
1573 #[inline(always)]
1574 pub fn set_fae11(&mut self, val: bool) {
1575 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1576 }
1577 #[doc = "Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12."]
1578 #[inline(always)]
1579 pub const fn fae12(&self) -> bool {
1580 let val = (self.0 >> 12usize) & 0x01;
1581 val != 0
1582 }
1583 #[doc = "Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12."]
1584 #[inline(always)]
1585 pub fn set_fae12(&mut self, val: bool) {
1586 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1587 }
1588 #[doc = "Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13."]
1589 #[inline(always)]
1590 pub const fn fae13(&self) -> bool {
1591 let val = (self.0 >> 13usize) & 0x01;
1592 val != 0
1593 }
1594 #[doc = "Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13."]
1595 #[inline(always)]
1596 pub fn set_fae13(&mut self, val: bool) {
1597 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1598 }
1599 #[doc = "Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14."]
1600 #[inline(always)]
1601 pub const fn fae14(&self) -> bool {
1602 let val = (self.0 >> 14usize) & 0x01;
1603 val != 0
1604 }
1605 #[doc = "Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14."]
1606 #[inline(always)]
1607 pub fn set_fae14(&mut self, val: bool) {
1608 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1609 }
1610 #[doc = "Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15."]
1611 #[inline(always)]
1612 pub const fn fae15(&self) -> bool {
1613 let val = (self.0 >> 15usize) & 0x01;
1614 val != 0
1615 }
1616 #[doc = "Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15."]
1617 #[inline(always)]
1618 pub fn set_fae15(&mut self, val: bool) {
1619 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1620 }
1621 #[doc = "Force PHY error 0 Writing one to this bit forces a PHY error 0."]
1622 #[inline(always)]
1623 pub const fn fpe0(&self) -> bool {
1624 let val = (self.0 >> 16usize) & 0x01;
1625 val != 0
1626 }
1627 #[doc = "Force PHY error 0 Writing one to this bit forces a PHY error 0."]
1628 #[inline(always)]
1629 pub fn set_fpe0(&mut self, val: bool) {
1630 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1631 }
1632 #[doc = "Force PHY error 1 Writing one to this bit forces a PHY error 1."]
1633 #[inline(always)]
1634 pub const fn fpe1(&self) -> bool {
1635 let val = (self.0 >> 17usize) & 0x01;
1636 val != 0
1637 }
1638 #[doc = "Force PHY error 1 Writing one to this bit forces a PHY error 1."]
1639 #[inline(always)]
1640 pub fn set_fpe1(&mut self, val: bool) {
1641 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1642 }
1643 #[doc = "Force PHY error 2 Writing one to this bit forces a PHY error 2."]
1644 #[inline(always)]
1645 pub const fn fpe2(&self) -> bool {
1646 let val = (self.0 >> 18usize) & 0x01;
1647 val != 0
1648 }
1649 #[doc = "Force PHY error 2 Writing one to this bit forces a PHY error 2."]
1650 #[inline(always)]
1651 pub fn set_fpe2(&mut self, val: bool) {
1652 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1653 }
1654 #[doc = "Force PHY error 3 Writing one to this bit forces a PHY error 3."]
1655 #[inline(always)]
1656 pub const fn fpe3(&self) -> bool {
1657 let val = (self.0 >> 19usize) & 0x01;
1658 val != 0
1659 }
1660 #[doc = "Force PHY error 3 Writing one to this bit forces a PHY error 3."]
1661 #[inline(always)]
1662 pub fn set_fpe3(&mut self, val: bool) {
1663 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1664 }
1665 #[doc = "Force PHY error 4 Writing one to this bit forces a PHY error 4."]
1666 #[inline(always)]
1667 pub const fn fpe4(&self) -> bool {
1668 let val = (self.0 >> 20usize) & 0x01;
1669 val != 0
1670 }
1671 #[doc = "Force PHY error 4 Writing one to this bit forces a PHY error 4."]
1672 #[inline(always)]
1673 pub fn set_fpe4(&mut self, val: bool) {
1674 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1675 }
1676 }
1677 impl Default for Fir0 {
1678 #[inline(always)]
1679 fn default() -> Fir0 {
1680 Fir0(0)
1681 }
1682 }
1683 impl core::fmt::Debug for Fir0 {
1684 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1685 f.debug_struct("Fir0")
1686 .field("fae0", &self.fae0())
1687 .field("fae1", &self.fae1())
1688 .field("fae2", &self.fae2())
1689 .field("fae3", &self.fae3())
1690 .field("fae4", &self.fae4())
1691 .field("fae5", &self.fae5())
1692 .field("fae6", &self.fae6())
1693 .field("fae7", &self.fae7())
1694 .field("fae8", &self.fae8())
1695 .field("fae9", &self.fae9())
1696 .field("fae10", &self.fae10())
1697 .field("fae11", &self.fae11())
1698 .field("fae12", &self.fae12())
1699 .field("fae13", &self.fae13())
1700 .field("fae14", &self.fae14())
1701 .field("fae15", &self.fae15())
1702 .field("fpe0", &self.fpe0())
1703 .field("fpe1", &self.fpe1())
1704 .field("fpe2", &self.fpe2())
1705 .field("fpe3", &self.fpe3())
1706 .field("fpe4", &self.fpe4())
1707 .finish()
1708 }
1709 }
1710 #[cfg(feature = "defmt")]
1711 impl defmt::Format for Fir0 {
1712 fn format(&self, f: defmt::Formatter) {
1713 #[derive(defmt :: Format)]
1714 struct Fir0 {
1715 fae0: bool,
1716 fae1: bool,
1717 fae2: bool,
1718 fae3: bool,
1719 fae4: bool,
1720 fae5: bool,
1721 fae6: bool,
1722 fae7: bool,
1723 fae8: bool,
1724 fae9: bool,
1725 fae10: bool,
1726 fae11: bool,
1727 fae12: bool,
1728 fae13: bool,
1729 fae14: bool,
1730 fae15: bool,
1731 fpe0: bool,
1732 fpe1: bool,
1733 fpe2: bool,
1734 fpe3: bool,
1735 fpe4: bool,
1736 }
1737 let proxy = Fir0 {
1738 fae0: self.fae0(),
1739 fae1: self.fae1(),
1740 fae2: self.fae2(),
1741 fae3: self.fae3(),
1742 fae4: self.fae4(),
1743 fae5: self.fae5(),
1744 fae6: self.fae6(),
1745 fae7: self.fae7(),
1746 fae8: self.fae8(),
1747 fae9: self.fae9(),
1748 fae10: self.fae10(),
1749 fae11: self.fae11(),
1750 fae12: self.fae12(),
1751 fae13: self.fae13(),
1752 fae14: self.fae14(),
1753 fae15: self.fae15(),
1754 fpe0: self.fpe0(),
1755 fpe1: self.fpe1(),
1756 fpe2: self.fpe2(),
1757 fpe3: self.fpe3(),
1758 fpe4: self.fpe4(),
1759 };
1760 defmt::write!(f, "{}", proxy)
1761 }
1762 }
1763 #[doc = "DSI Host force interrupt register 1."]
1764 #[repr(transparent)]
1765 #[derive(Copy, Clone, Eq, PartialEq)]
1766 pub struct Fir1(pub u32);
1767 impl Fir1 {
1768 #[doc = "Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission."]
1769 #[inline(always)]
1770 pub const fn ftohstx(&self) -> bool {
1771 let val = (self.0 >> 0usize) & 0x01;
1772 val != 0
1773 }
1774 #[doc = "Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission."]
1775 #[inline(always)]
1776 pub fn set_ftohstx(&mut self, val: bool) {
1777 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1778 }
1779 #[doc = "Force timeout low-power reception Writing one to this bit forces a timeout low-power reception."]
1780 #[inline(always)]
1781 pub const fn ftolprx(&self) -> bool {
1782 let val = (self.0 >> 1usize) & 0x01;
1783 val != 0
1784 }
1785 #[doc = "Force timeout low-power reception Writing one to this bit forces a timeout low-power reception."]
1786 #[inline(always)]
1787 pub fn set_ftolprx(&mut self, val: bool) {
1788 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1789 }
1790 #[doc = "Force ECC single-bit error Writing one to this bit forces a ECC single-bit error."]
1791 #[inline(always)]
1792 pub const fn feccse(&self) -> bool {
1793 let val = (self.0 >> 2usize) & 0x01;
1794 val != 0
1795 }
1796 #[doc = "Force ECC single-bit error Writing one to this bit forces a ECC single-bit error."]
1797 #[inline(always)]
1798 pub fn set_feccse(&mut self, val: bool) {
1799 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1800 }
1801 #[doc = "Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error."]
1802 #[inline(always)]
1803 pub const fn feccme(&self) -> bool {
1804 let val = (self.0 >> 3usize) & 0x01;
1805 val != 0
1806 }
1807 #[doc = "Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error."]
1808 #[inline(always)]
1809 pub fn set_feccme(&mut self, val: bool) {
1810 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1811 }
1812 #[doc = "Force CRC error Writing one to this bit forces a CRC error."]
1813 #[inline(always)]
1814 pub const fn fcrce(&self) -> bool {
1815 let val = (self.0 >> 4usize) & 0x01;
1816 val != 0
1817 }
1818 #[doc = "Force CRC error Writing one to this bit forces a CRC error."]
1819 #[inline(always)]
1820 pub fn set_fcrce(&mut self, val: bool) {
1821 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1822 }
1823 #[doc = "Force packet size error Writing one to this bit forces a packet size error."]
1824 #[inline(always)]
1825 pub const fn fpse(&self) -> bool {
1826 let val = (self.0 >> 5usize) & 0x01;
1827 val != 0
1828 }
1829 #[doc = "Force packet size error Writing one to this bit forces a packet size error."]
1830 #[inline(always)]
1831 pub fn set_fpse(&mut self, val: bool) {
1832 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1833 }
1834 #[doc = "Force EoTp error Writing one to this bit forces a EoTp error."]
1835 #[inline(always)]
1836 pub const fn feotpe(&self) -> bool {
1837 let val = (self.0 >> 6usize) & 0x01;
1838 val != 0
1839 }
1840 #[doc = "Force EoTp error Writing one to this bit forces a EoTp error."]
1841 #[inline(always)]
1842 pub fn set_feotpe(&mut self, val: bool) {
1843 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1844 }
1845 #[doc = "Force LTDC payload write error Writing one to this bit forces a LTDC payload write error."]
1846 #[inline(always)]
1847 pub const fn flpwre(&self) -> bool {
1848 let val = (self.0 >> 7usize) & 0x01;
1849 val != 0
1850 }
1851 #[doc = "Force LTDC payload write error Writing one to this bit forces a LTDC payload write error."]
1852 #[inline(always)]
1853 pub fn set_flpwre(&mut self, val: bool) {
1854 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1855 }
1856 #[doc = "Force generic command write error Writing one to this bit forces a generic command write error."]
1857 #[inline(always)]
1858 pub const fn fgcwre(&self) -> bool {
1859 let val = (self.0 >> 8usize) & 0x01;
1860 val != 0
1861 }
1862 #[doc = "Force generic command write error Writing one to this bit forces a generic command write error."]
1863 #[inline(always)]
1864 pub fn set_fgcwre(&mut self, val: bool) {
1865 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1866 }
1867 #[doc = "Force generic payload write error Writing one to this bit forces a generic payload write error."]
1868 #[inline(always)]
1869 pub const fn fgpwre(&self) -> bool {
1870 let val = (self.0 >> 9usize) & 0x01;
1871 val != 0
1872 }
1873 #[doc = "Force generic payload write error Writing one to this bit forces a generic payload write error."]
1874 #[inline(always)]
1875 pub fn set_fgpwre(&mut self, val: bool) {
1876 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1877 }
1878 #[doc = "Force generic payload transmit error Writing one to this bit forces a generic payload transmit error."]
1879 #[inline(always)]
1880 pub const fn fgptxe(&self) -> bool {
1881 let val = (self.0 >> 10usize) & 0x01;
1882 val != 0
1883 }
1884 #[doc = "Force generic payload transmit error Writing one to this bit forces a generic payload transmit error."]
1885 #[inline(always)]
1886 pub fn set_fgptxe(&mut self, val: bool) {
1887 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1888 }
1889 #[doc = "Force generic payload read error Writing one to this bit forces a generic payload read error."]
1890 #[inline(always)]
1891 pub const fn fgprde(&self) -> bool {
1892 let val = (self.0 >> 11usize) & 0x01;
1893 val != 0
1894 }
1895 #[doc = "Force generic payload read error Writing one to this bit forces a generic payload read error."]
1896 #[inline(always)]
1897 pub fn set_fgprde(&mut self, val: bool) {
1898 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1899 }
1900 #[doc = "Force generic payload receive error Writing one to this bit forces a generic payload receive error."]
1901 #[inline(always)]
1902 pub const fn fgprxe(&self) -> bool {
1903 let val = (self.0 >> 12usize) & 0x01;
1904 val != 0
1905 }
1906 #[doc = "Force generic payload receive error Writing one to this bit forces a generic payload receive error."]
1907 #[inline(always)]
1908 pub fn set_fgprxe(&mut self, val: bool) {
1909 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1910 }
1911 #[doc = "Force payload buffer underflow error Writing one to this bit forces a payload undrflow error."]
1912 #[inline(always)]
1913 pub const fn fpbue(&self) -> bool {
1914 let val = (self.0 >> 19usize) & 0x01;
1915 val != 0
1916 }
1917 #[doc = "Force payload buffer underflow error Writing one to this bit forces a payload undrflow error."]
1918 #[inline(always)]
1919 pub fn set_fpbue(&mut self, val: bool) {
1920 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1921 }
1922 }
1923 impl Default for Fir1 {
1924 #[inline(always)]
1925 fn default() -> Fir1 {
1926 Fir1(0)
1927 }
1928 }
1929 impl core::fmt::Debug for Fir1 {
1930 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1931 f.debug_struct("Fir1")
1932 .field("ftohstx", &self.ftohstx())
1933 .field("ftolprx", &self.ftolprx())
1934 .field("feccse", &self.feccse())
1935 .field("feccme", &self.feccme())
1936 .field("fcrce", &self.fcrce())
1937 .field("fpse", &self.fpse())
1938 .field("feotpe", &self.feotpe())
1939 .field("flpwre", &self.flpwre())
1940 .field("fgcwre", &self.fgcwre())
1941 .field("fgpwre", &self.fgpwre())
1942 .field("fgptxe", &self.fgptxe())
1943 .field("fgprde", &self.fgprde())
1944 .field("fgprxe", &self.fgprxe())
1945 .field("fpbue", &self.fpbue())
1946 .finish()
1947 }
1948 }
1949 #[cfg(feature = "defmt")]
1950 impl defmt::Format for Fir1 {
1951 fn format(&self, f: defmt::Formatter) {
1952 #[derive(defmt :: Format)]
1953 struct Fir1 {
1954 ftohstx: bool,
1955 ftolprx: bool,
1956 feccse: bool,
1957 feccme: bool,
1958 fcrce: bool,
1959 fpse: bool,
1960 feotpe: bool,
1961 flpwre: bool,
1962 fgcwre: bool,
1963 fgpwre: bool,
1964 fgptxe: bool,
1965 fgprde: bool,
1966 fgprxe: bool,
1967 fpbue: bool,
1968 }
1969 let proxy = Fir1 {
1970 ftohstx: self.ftohstx(),
1971 ftolprx: self.ftolprx(),
1972 feccse: self.feccse(),
1973 feccme: self.feccme(),
1974 fcrce: self.fcrce(),
1975 fpse: self.fpse(),
1976 feotpe: self.feotpe(),
1977 flpwre: self.flpwre(),
1978 fgcwre: self.fgcwre(),
1979 fgpwre: self.fgpwre(),
1980 fgptxe: self.fgptxe(),
1981 fgprde: self.fgprde(),
1982 fgprxe: self.fgprxe(),
1983 fpbue: self.fpbue(),
1984 };
1985 defmt::write!(f, "{}", proxy)
1986 }
1987 }
1988 #[doc = "DSI Host generic header configuration register."]
1989 #[repr(transparent)]
1990 #[derive(Copy, Clone, Eq, PartialEq)]
1991 pub struct Ghcr(pub u32);
1992 impl Ghcr {
1993 #[doc = "Type This field configures the packet data type of the header packet."]
1994 #[inline(always)]
1995 pub const fn dt(&self) -> u8 {
1996 let val = (self.0 >> 0usize) & 0x3f;
1997 val as u8
1998 }
1999 #[doc = "Type This field configures the packet data type of the header packet."]
2000 #[inline(always)]
2001 pub fn set_dt(&mut self, val: u8) {
2002 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
2003 }
2004 #[doc = "Channel This field configures the virtual channel ID of the header packet."]
2005 #[inline(always)]
2006 pub const fn vcid(&self) -> u8 {
2007 let val = (self.0 >> 6usize) & 0x03;
2008 val as u8
2009 }
2010 #[doc = "Channel This field configures the virtual channel ID of the header packet."]
2011 #[inline(always)]
2012 pub fn set_vcid(&mut self, val: u8) {
2013 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
2014 }
2015 #[doc = "WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets."]
2016 #[inline(always)]
2017 pub const fn wclsb(&self) -> u8 {
2018 let val = (self.0 >> 8usize) & 0xff;
2019 val as u8
2020 }
2021 #[doc = "WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets."]
2022 #[inline(always)]
2023 pub fn set_wclsb(&mut self, val: u8) {
2024 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
2025 }
2026 #[doc = "WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets."]
2027 #[inline(always)]
2028 pub const fn wcmsb(&self) -> u8 {
2029 let val = (self.0 >> 16usize) & 0xff;
2030 val as u8
2031 }
2032 #[doc = "WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets."]
2033 #[inline(always)]
2034 pub fn set_wcmsb(&mut self, val: u8) {
2035 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
2036 }
2037 }
2038 impl Default for Ghcr {
2039 #[inline(always)]
2040 fn default() -> Ghcr {
2041 Ghcr(0)
2042 }
2043 }
2044 impl core::fmt::Debug for Ghcr {
2045 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2046 f.debug_struct("Ghcr")
2047 .field("dt", &self.dt())
2048 .field("vcid", &self.vcid())
2049 .field("wclsb", &self.wclsb())
2050 .field("wcmsb", &self.wcmsb())
2051 .finish()
2052 }
2053 }
2054 #[cfg(feature = "defmt")]
2055 impl defmt::Format for Ghcr {
2056 fn format(&self, f: defmt::Formatter) {
2057 #[derive(defmt :: Format)]
2058 struct Ghcr {
2059 dt: u8,
2060 vcid: u8,
2061 wclsb: u8,
2062 wcmsb: u8,
2063 }
2064 let proxy = Ghcr {
2065 dt: self.dt(),
2066 vcid: self.vcid(),
2067 wclsb: self.wclsb(),
2068 wcmsb: self.wcmsb(),
2069 };
2070 defmt::write!(f, "{}", proxy)
2071 }
2072 }
2073 #[doc = "DSI Host generic payload data register."]
2074 #[repr(transparent)]
2075 #[derive(Copy, Clone, Eq, PartialEq)]
2076 pub struct Gpdr(pub u32);
2077 impl Gpdr {
2078 #[doc = "Payload byte 1 This field indicates the byte 1 of the packet payload."]
2079 #[inline(always)]
2080 pub const fn data1(&self) -> u8 {
2081 let val = (self.0 >> 0usize) & 0xff;
2082 val as u8
2083 }
2084 #[doc = "Payload byte 1 This field indicates the byte 1 of the packet payload."]
2085 #[inline(always)]
2086 pub fn set_data1(&mut self, val: u8) {
2087 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
2088 }
2089 #[doc = "Payload byte 2 This field indicates the byte 2 of the packet payload."]
2090 #[inline(always)]
2091 pub const fn data2(&self) -> u8 {
2092 let val = (self.0 >> 8usize) & 0xff;
2093 val as u8
2094 }
2095 #[doc = "Payload byte 2 This field indicates the byte 2 of the packet payload."]
2096 #[inline(always)]
2097 pub fn set_data2(&mut self, val: u8) {
2098 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
2099 }
2100 #[doc = "Payload byte 3 This field indicates the byte 3 of the packet payload."]
2101 #[inline(always)]
2102 pub const fn data3(&self) -> u8 {
2103 let val = (self.0 >> 16usize) & 0xff;
2104 val as u8
2105 }
2106 #[doc = "Payload byte 3 This field indicates the byte 3 of the packet payload."]
2107 #[inline(always)]
2108 pub fn set_data3(&mut self, val: u8) {
2109 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
2110 }
2111 #[doc = "Payload byte 4 This field indicates the byte 4 of the packet payload."]
2112 #[inline(always)]
2113 pub const fn data4(&self) -> u8 {
2114 let val = (self.0 >> 24usize) & 0xff;
2115 val as u8
2116 }
2117 #[doc = "Payload byte 4 This field indicates the byte 4 of the packet payload."]
2118 #[inline(always)]
2119 pub fn set_data4(&mut self, val: u8) {
2120 self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
2121 }
2122 }
2123 impl Default for Gpdr {
2124 #[inline(always)]
2125 fn default() -> Gpdr {
2126 Gpdr(0)
2127 }
2128 }
2129 impl core::fmt::Debug for Gpdr {
2130 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2131 f.debug_struct("Gpdr")
2132 .field("data1", &self.data1())
2133 .field("data2", &self.data2())
2134 .field("data3", &self.data3())
2135 .field("data4", &self.data4())
2136 .finish()
2137 }
2138 }
2139 #[cfg(feature = "defmt")]
2140 impl defmt::Format for Gpdr {
2141 fn format(&self, f: defmt::Formatter) {
2142 #[derive(defmt :: Format)]
2143 struct Gpdr {
2144 data1: u8,
2145 data2: u8,
2146 data3: u8,
2147 data4: u8,
2148 }
2149 let proxy = Gpdr {
2150 data1: self.data1(),
2151 data2: self.data2(),
2152 data3: self.data3(),
2153 data4: self.data4(),
2154 };
2155 defmt::write!(f, "{}", proxy)
2156 }
2157 }
2158 #[doc = "DSI Host generic packet status register."]
2159 #[repr(transparent)]
2160 #[derive(Copy, Clone, Eq, PartialEq)]
2161 pub struct Gpsr(pub u32);
2162 impl Gpsr {
2163 #[doc = "Command FIFO empty This bit indicates the empty status of the generic command FIFO:."]
2164 #[inline(always)]
2165 pub const fn cmdfe(&self) -> bool {
2166 let val = (self.0 >> 0usize) & 0x01;
2167 val != 0
2168 }
2169 #[doc = "Command FIFO empty This bit indicates the empty status of the generic command FIFO:."]
2170 #[inline(always)]
2171 pub fn set_cmdfe(&mut self, val: bool) {
2172 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2173 }
2174 #[doc = "Command FIFO full This bit indicates the full status of the generic command FIFO:."]
2175 #[inline(always)]
2176 pub const fn cmdff(&self) -> bool {
2177 let val = (self.0 >> 1usize) & 0x01;
2178 val != 0
2179 }
2180 #[doc = "Command FIFO full This bit indicates the full status of the generic command FIFO:."]
2181 #[inline(always)]
2182 pub fn set_cmdff(&mut self, val: bool) {
2183 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2184 }
2185 #[doc = "Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:."]
2186 #[inline(always)]
2187 pub const fn pwrfe(&self) -> bool {
2188 let val = (self.0 >> 2usize) & 0x01;
2189 val != 0
2190 }
2191 #[doc = "Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:."]
2192 #[inline(always)]
2193 pub fn set_pwrfe(&mut self, val: bool) {
2194 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2195 }
2196 #[doc = "Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:."]
2197 #[inline(always)]
2198 pub const fn pwrff(&self) -> bool {
2199 let val = (self.0 >> 3usize) & 0x01;
2200 val != 0
2201 }
2202 #[doc = "Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:."]
2203 #[inline(always)]
2204 pub fn set_pwrff(&mut self, val: bool) {
2205 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2206 }
2207 #[doc = "Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:."]
2208 #[inline(always)]
2209 pub const fn prdfe(&self) -> bool {
2210 let val = (self.0 >> 4usize) & 0x01;
2211 val != 0
2212 }
2213 #[doc = "Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:."]
2214 #[inline(always)]
2215 pub fn set_prdfe(&mut self, val: bool) {
2216 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2217 }
2218 #[doc = "Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:."]
2219 #[inline(always)]
2220 pub const fn prdff(&self) -> bool {
2221 let val = (self.0 >> 5usize) & 0x01;
2222 val != 0
2223 }
2224 #[doc = "Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:."]
2225 #[inline(always)]
2226 pub fn set_prdff(&mut self, val: bool) {
2227 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2228 }
2229 #[doc = "Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:."]
2230 #[inline(always)]
2231 pub const fn rcb(&self) -> bool {
2232 let val = (self.0 >> 6usize) & 0x01;
2233 val != 0
2234 }
2235 #[doc = "Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:."]
2236 #[inline(always)]
2237 pub fn set_rcb(&mut self, val: bool) {
2238 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2239 }
2240 #[doc = "Command buffer empty This bit indicates the empty status of the generic payload internal buffer:."]
2241 #[inline(always)]
2242 pub const fn cmdbe(&self) -> bool {
2243 let val = (self.0 >> 16usize) & 0x01;
2244 val != 0
2245 }
2246 #[doc = "Command buffer empty This bit indicates the empty status of the generic payload internal buffer:."]
2247 #[inline(always)]
2248 pub fn set_cmdbe(&mut self, val: bool) {
2249 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2250 }
2251 #[doc = "Command buffer full This bit indicates the full status of the generic command internal buffer:."]
2252 #[inline(always)]
2253 pub const fn cmdbf(&self) -> bool {
2254 let val = (self.0 >> 17usize) & 0x01;
2255 val != 0
2256 }
2257 #[doc = "Command buffer full This bit indicates the full status of the generic command internal buffer:."]
2258 #[inline(always)]
2259 pub fn set_cmdbf(&mut self, val: bool) {
2260 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2261 }
2262 #[doc = "Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:."]
2263 #[inline(always)]
2264 pub const fn pbe(&self) -> bool {
2265 let val = (self.0 >> 18usize) & 0x01;
2266 val != 0
2267 }
2268 #[doc = "Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:."]
2269 #[inline(always)]
2270 pub fn set_pbe(&mut self, val: bool) {
2271 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2272 }
2273 #[doc = "Payload buffer full This bit indicates the full status of the generic payload internal buffer:."]
2274 #[inline(always)]
2275 pub const fn pbf(&self) -> bool {
2276 let val = (self.0 >> 19usize) & 0x01;
2277 val != 0
2278 }
2279 #[doc = "Payload buffer full This bit indicates the full status of the generic payload internal buffer:."]
2280 #[inline(always)]
2281 pub fn set_pbf(&mut self, val: bool) {
2282 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2283 }
2284 }
2285 impl Default for Gpsr {
2286 #[inline(always)]
2287 fn default() -> Gpsr {
2288 Gpsr(0)
2289 }
2290 }
2291 impl core::fmt::Debug for Gpsr {
2292 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2293 f.debug_struct("Gpsr")
2294 .field("cmdfe", &self.cmdfe())
2295 .field("cmdff", &self.cmdff())
2296 .field("pwrfe", &self.pwrfe())
2297 .field("pwrff", &self.pwrff())
2298 .field("prdfe", &self.prdfe())
2299 .field("prdff", &self.prdff())
2300 .field("rcb", &self.rcb())
2301 .field("cmdbe", &self.cmdbe())
2302 .field("cmdbf", &self.cmdbf())
2303 .field("pbe", &self.pbe())
2304 .field("pbf", &self.pbf())
2305 .finish()
2306 }
2307 }
2308 #[cfg(feature = "defmt")]
2309 impl defmt::Format for Gpsr {
2310 fn format(&self, f: defmt::Formatter) {
2311 #[derive(defmt :: Format)]
2312 struct Gpsr {
2313 cmdfe: bool,
2314 cmdff: bool,
2315 pwrfe: bool,
2316 pwrff: bool,
2317 prdfe: bool,
2318 prdff: bool,
2319 rcb: bool,
2320 cmdbe: bool,
2321 cmdbf: bool,
2322 pbe: bool,
2323 pbf: bool,
2324 }
2325 let proxy = Gpsr {
2326 cmdfe: self.cmdfe(),
2327 cmdff: self.cmdff(),
2328 pwrfe: self.pwrfe(),
2329 pwrff: self.pwrff(),
2330 prdfe: self.prdfe(),
2331 prdff: self.prdff(),
2332 rcb: self.rcb(),
2333 cmdbe: self.cmdbe(),
2334 cmdbf: self.cmdbf(),
2335 pbe: self.pbe(),
2336 pbf: self.pbf(),
2337 };
2338 defmt::write!(f, "{}", proxy)
2339 }
2340 }
2341 #[doc = "DSI Host generic VCID register."]
2342 #[repr(transparent)]
2343 #[derive(Copy, Clone, Eq, PartialEq)]
2344 pub struct Gvcidr(pub u32);
2345 impl Gvcidr {
2346 #[doc = "Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification."]
2347 #[inline(always)]
2348 pub const fn vcidrx(&self) -> u8 {
2349 let val = (self.0 >> 0usize) & 0x03;
2350 val as u8
2351 }
2352 #[doc = "Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification."]
2353 #[inline(always)]
2354 pub fn set_vcidrx(&mut self, val: u8) {
2355 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
2356 }
2357 #[doc = "Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted."]
2358 #[inline(always)]
2359 pub const fn vcidtx(&self) -> u8 {
2360 let val = (self.0 >> 16usize) & 0x03;
2361 val as u8
2362 }
2363 #[doc = "Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted."]
2364 #[inline(always)]
2365 pub fn set_vcidtx(&mut self, val: u8) {
2366 self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
2367 }
2368 }
2369 impl Default for Gvcidr {
2370 #[inline(always)]
2371 fn default() -> Gvcidr {
2372 Gvcidr(0)
2373 }
2374 }
2375 impl core::fmt::Debug for Gvcidr {
2376 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2377 f.debug_struct("Gvcidr")
2378 .field("vcidrx", &self.vcidrx())
2379 .field("vcidtx", &self.vcidtx())
2380 .finish()
2381 }
2382 }
2383 #[cfg(feature = "defmt")]
2384 impl defmt::Format for Gvcidr {
2385 fn format(&self, f: defmt::Formatter) {
2386 #[derive(defmt :: Format)]
2387 struct Gvcidr {
2388 vcidrx: u8,
2389 vcidtx: u8,
2390 }
2391 let proxy = Gvcidr {
2392 vcidrx: self.vcidrx(),
2393 vcidtx: self.vcidtx(),
2394 };
2395 defmt::write!(f, "{}", proxy)
2396 }
2397 }
2398 #[doc = "DSI Host interrupt enable register 0."]
2399 #[repr(transparent)]
2400 #[derive(Copy, Clone, Eq, PartialEq)]
2401 pub struct Ier0(pub u32);
2402 impl Ier0 {
2403 #[doc = "Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0."]
2404 #[inline(always)]
2405 pub const fn ae0ie(&self) -> bool {
2406 let val = (self.0 >> 0usize) & 0x01;
2407 val != 0
2408 }
2409 #[doc = "Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0."]
2410 #[inline(always)]
2411 pub fn set_ae0ie(&mut self, val: bool) {
2412 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2413 }
2414 #[doc = "Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1."]
2415 #[inline(always)]
2416 pub const fn ae1ie(&self) -> bool {
2417 let val = (self.0 >> 1usize) & 0x01;
2418 val != 0
2419 }
2420 #[doc = "Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1."]
2421 #[inline(always)]
2422 pub fn set_ae1ie(&mut self, val: bool) {
2423 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2424 }
2425 #[doc = "Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2."]
2426 #[inline(always)]
2427 pub const fn ae2ie(&self) -> bool {
2428 let val = (self.0 >> 2usize) & 0x01;
2429 val != 0
2430 }
2431 #[doc = "Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2."]
2432 #[inline(always)]
2433 pub fn set_ae2ie(&mut self, val: bool) {
2434 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2435 }
2436 #[doc = "Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3."]
2437 #[inline(always)]
2438 pub const fn ae3ie(&self) -> bool {
2439 let val = (self.0 >> 3usize) & 0x01;
2440 val != 0
2441 }
2442 #[doc = "Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3."]
2443 #[inline(always)]
2444 pub fn set_ae3ie(&mut self, val: bool) {
2445 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2446 }
2447 #[doc = "Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4."]
2448 #[inline(always)]
2449 pub const fn ae4ie(&self) -> bool {
2450 let val = (self.0 >> 4usize) & 0x01;
2451 val != 0
2452 }
2453 #[doc = "Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4."]
2454 #[inline(always)]
2455 pub fn set_ae4ie(&mut self, val: bool) {
2456 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2457 }
2458 #[doc = "Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5."]
2459 #[inline(always)]
2460 pub const fn ae5ie(&self) -> bool {
2461 let val = (self.0 >> 5usize) & 0x01;
2462 val != 0
2463 }
2464 #[doc = "Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5."]
2465 #[inline(always)]
2466 pub fn set_ae5ie(&mut self, val: bool) {
2467 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2468 }
2469 #[doc = "Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6."]
2470 #[inline(always)]
2471 pub const fn ae6ie(&self) -> bool {
2472 let val = (self.0 >> 6usize) & 0x01;
2473 val != 0
2474 }
2475 #[doc = "Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6."]
2476 #[inline(always)]
2477 pub fn set_ae6ie(&mut self, val: bool) {
2478 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2479 }
2480 #[doc = "Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7."]
2481 #[inline(always)]
2482 pub const fn ae7ie(&self) -> bool {
2483 let val = (self.0 >> 7usize) & 0x01;
2484 val != 0
2485 }
2486 #[doc = "Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7."]
2487 #[inline(always)]
2488 pub fn set_ae7ie(&mut self, val: bool) {
2489 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2490 }
2491 #[doc = "Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8."]
2492 #[inline(always)]
2493 pub const fn ae8ie(&self) -> bool {
2494 let val = (self.0 >> 8usize) & 0x01;
2495 val != 0
2496 }
2497 #[doc = "Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8."]
2498 #[inline(always)]
2499 pub fn set_ae8ie(&mut self, val: bool) {
2500 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2501 }
2502 #[doc = "Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9."]
2503 #[inline(always)]
2504 pub const fn ae9ie(&self) -> bool {
2505 let val = (self.0 >> 9usize) & 0x01;
2506 val != 0
2507 }
2508 #[doc = "Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9."]
2509 #[inline(always)]
2510 pub fn set_ae9ie(&mut self, val: bool) {
2511 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2512 }
2513 #[doc = "Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10."]
2514 #[inline(always)]
2515 pub const fn ae10ie(&self) -> bool {
2516 let val = (self.0 >> 10usize) & 0x01;
2517 val != 0
2518 }
2519 #[doc = "Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10."]
2520 #[inline(always)]
2521 pub fn set_ae10ie(&mut self, val: bool) {
2522 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2523 }
2524 #[doc = "Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11."]
2525 #[inline(always)]
2526 pub const fn ae11ie(&self) -> bool {
2527 let val = (self.0 >> 11usize) & 0x01;
2528 val != 0
2529 }
2530 #[doc = "Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11."]
2531 #[inline(always)]
2532 pub fn set_ae11ie(&mut self, val: bool) {
2533 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2534 }
2535 #[doc = "Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12."]
2536 #[inline(always)]
2537 pub const fn ae12ie(&self) -> bool {
2538 let val = (self.0 >> 12usize) & 0x01;
2539 val != 0
2540 }
2541 #[doc = "Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12."]
2542 #[inline(always)]
2543 pub fn set_ae12ie(&mut self, val: bool) {
2544 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2545 }
2546 #[doc = "Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13."]
2547 #[inline(always)]
2548 pub const fn ae13ie(&self) -> bool {
2549 let val = (self.0 >> 13usize) & 0x01;
2550 val != 0
2551 }
2552 #[doc = "Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13."]
2553 #[inline(always)]
2554 pub fn set_ae13ie(&mut self, val: bool) {
2555 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2556 }
2557 #[doc = "Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14."]
2558 #[inline(always)]
2559 pub const fn ae14ie(&self) -> bool {
2560 let val = (self.0 >> 14usize) & 0x01;
2561 val != 0
2562 }
2563 #[doc = "Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14."]
2564 #[inline(always)]
2565 pub fn set_ae14ie(&mut self, val: bool) {
2566 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2567 }
2568 #[doc = "Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15."]
2569 #[inline(always)]
2570 pub const fn ae15ie(&self) -> bool {
2571 let val = (self.0 >> 15usize) & 0x01;
2572 val != 0
2573 }
2574 #[doc = "Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15."]
2575 #[inline(always)]
2576 pub fn set_ae15ie(&mut self, val: bool) {
2577 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2578 }
2579 #[doc = "PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0."]
2580 #[inline(always)]
2581 pub const fn pe0ie(&self) -> bool {
2582 let val = (self.0 >> 16usize) & 0x01;
2583 val != 0
2584 }
2585 #[doc = "PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0."]
2586 #[inline(always)]
2587 pub fn set_pe0ie(&mut self, val: bool) {
2588 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2589 }
2590 #[doc = "PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1."]
2591 #[inline(always)]
2592 pub const fn pe1ie(&self) -> bool {
2593 let val = (self.0 >> 17usize) & 0x01;
2594 val != 0
2595 }
2596 #[doc = "PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1."]
2597 #[inline(always)]
2598 pub fn set_pe1ie(&mut self, val: bool) {
2599 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2600 }
2601 #[doc = "PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2."]
2602 #[inline(always)]
2603 pub const fn pe2ie(&self) -> bool {
2604 let val = (self.0 >> 18usize) & 0x01;
2605 val != 0
2606 }
2607 #[doc = "PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2."]
2608 #[inline(always)]
2609 pub fn set_pe2ie(&mut self, val: bool) {
2610 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2611 }
2612 #[doc = "PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4."]
2613 #[inline(always)]
2614 pub const fn pe3ie(&self) -> bool {
2615 let val = (self.0 >> 19usize) & 0x01;
2616 val != 0
2617 }
2618 #[doc = "PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4."]
2619 #[inline(always)]
2620 pub fn set_pe3ie(&mut self, val: bool) {
2621 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2622 }
2623 #[doc = "PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4."]
2624 #[inline(always)]
2625 pub const fn pe4ie(&self) -> bool {
2626 let val = (self.0 >> 20usize) & 0x01;
2627 val != 0
2628 }
2629 #[doc = "PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4."]
2630 #[inline(always)]
2631 pub fn set_pe4ie(&mut self, val: bool) {
2632 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
2633 }
2634 }
2635 impl Default for Ier0 {
2636 #[inline(always)]
2637 fn default() -> Ier0 {
2638 Ier0(0)
2639 }
2640 }
2641 impl core::fmt::Debug for Ier0 {
2642 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2643 f.debug_struct("Ier0")
2644 .field("ae0ie", &self.ae0ie())
2645 .field("ae1ie", &self.ae1ie())
2646 .field("ae2ie", &self.ae2ie())
2647 .field("ae3ie", &self.ae3ie())
2648 .field("ae4ie", &self.ae4ie())
2649 .field("ae5ie", &self.ae5ie())
2650 .field("ae6ie", &self.ae6ie())
2651 .field("ae7ie", &self.ae7ie())
2652 .field("ae8ie", &self.ae8ie())
2653 .field("ae9ie", &self.ae9ie())
2654 .field("ae10ie", &self.ae10ie())
2655 .field("ae11ie", &self.ae11ie())
2656 .field("ae12ie", &self.ae12ie())
2657 .field("ae13ie", &self.ae13ie())
2658 .field("ae14ie", &self.ae14ie())
2659 .field("ae15ie", &self.ae15ie())
2660 .field("pe0ie", &self.pe0ie())
2661 .field("pe1ie", &self.pe1ie())
2662 .field("pe2ie", &self.pe2ie())
2663 .field("pe3ie", &self.pe3ie())
2664 .field("pe4ie", &self.pe4ie())
2665 .finish()
2666 }
2667 }
2668 #[cfg(feature = "defmt")]
2669 impl defmt::Format for Ier0 {
2670 fn format(&self, f: defmt::Formatter) {
2671 #[derive(defmt :: Format)]
2672 struct Ier0 {
2673 ae0ie: bool,
2674 ae1ie: bool,
2675 ae2ie: bool,
2676 ae3ie: bool,
2677 ae4ie: bool,
2678 ae5ie: bool,
2679 ae6ie: bool,
2680 ae7ie: bool,
2681 ae8ie: bool,
2682 ae9ie: bool,
2683 ae10ie: bool,
2684 ae11ie: bool,
2685 ae12ie: bool,
2686 ae13ie: bool,
2687 ae14ie: bool,
2688 ae15ie: bool,
2689 pe0ie: bool,
2690 pe1ie: bool,
2691 pe2ie: bool,
2692 pe3ie: bool,
2693 pe4ie: bool,
2694 }
2695 let proxy = Ier0 {
2696 ae0ie: self.ae0ie(),
2697 ae1ie: self.ae1ie(),
2698 ae2ie: self.ae2ie(),
2699 ae3ie: self.ae3ie(),
2700 ae4ie: self.ae4ie(),
2701 ae5ie: self.ae5ie(),
2702 ae6ie: self.ae6ie(),
2703 ae7ie: self.ae7ie(),
2704 ae8ie: self.ae8ie(),
2705 ae9ie: self.ae9ie(),
2706 ae10ie: self.ae10ie(),
2707 ae11ie: self.ae11ie(),
2708 ae12ie: self.ae12ie(),
2709 ae13ie: self.ae13ie(),
2710 ae14ie: self.ae14ie(),
2711 ae15ie: self.ae15ie(),
2712 pe0ie: self.pe0ie(),
2713 pe1ie: self.pe1ie(),
2714 pe2ie: self.pe2ie(),
2715 pe3ie: self.pe3ie(),
2716 pe4ie: self.pe4ie(),
2717 };
2718 defmt::write!(f, "{}", proxy)
2719 }
2720 }
2721 #[doc = "DSI Host interrupt enable register 1."]
2722 #[repr(transparent)]
2723 #[derive(Copy, Clone, Eq, PartialEq)]
2724 pub struct Ier1(pub u32);
2725 impl Ier1 {
2726 #[doc = "Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission."]
2727 #[inline(always)]
2728 pub const fn tohstxie(&self) -> bool {
2729 let val = (self.0 >> 0usize) & 0x01;
2730 val != 0
2731 }
2732 #[doc = "Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission."]
2733 #[inline(always)]
2734 pub fn set_tohstxie(&mut self, val: bool) {
2735 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2736 }
2737 #[doc = "Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception."]
2738 #[inline(always)]
2739 pub const fn tolprxie(&self) -> bool {
2740 let val = (self.0 >> 1usize) & 0x01;
2741 val != 0
2742 }
2743 #[doc = "Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception."]
2744 #[inline(always)]
2745 pub fn set_tolprxie(&mut self, val: bool) {
2746 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2747 }
2748 #[doc = "ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error."]
2749 #[inline(always)]
2750 pub const fn eccseie(&self) -> bool {
2751 let val = (self.0 >> 2usize) & 0x01;
2752 val != 0
2753 }
2754 #[doc = "ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error."]
2755 #[inline(always)]
2756 pub fn set_eccseie(&mut self, val: bool) {
2757 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2758 }
2759 #[doc = "ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error."]
2760 #[inline(always)]
2761 pub const fn eccmeie(&self) -> bool {
2762 let val = (self.0 >> 3usize) & 0x01;
2763 val != 0
2764 }
2765 #[doc = "ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error."]
2766 #[inline(always)]
2767 pub fn set_eccmeie(&mut self, val: bool) {
2768 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2769 }
2770 #[doc = "CRC error interrupt enable This bit enables the interrupt generation on CRC error."]
2771 #[inline(always)]
2772 pub const fn crceie(&self) -> bool {
2773 let val = (self.0 >> 4usize) & 0x01;
2774 val != 0
2775 }
2776 #[doc = "CRC error interrupt enable This bit enables the interrupt generation on CRC error."]
2777 #[inline(always)]
2778 pub fn set_crceie(&mut self, val: bool) {
2779 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2780 }
2781 #[doc = "Packet size error interrupt enable This bit enables the interrupt generation on packet size error."]
2782 #[inline(always)]
2783 pub const fn pseie(&self) -> bool {
2784 let val = (self.0 >> 5usize) & 0x01;
2785 val != 0
2786 }
2787 #[doc = "Packet size error interrupt enable This bit enables the interrupt generation on packet size error."]
2788 #[inline(always)]
2789 pub fn set_pseie(&mut self, val: bool) {
2790 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2791 }
2792 #[doc = "EoTp error interrupt enable This bit enables the interrupt generation on EoTp error."]
2793 #[inline(always)]
2794 pub const fn eotpeie(&self) -> bool {
2795 let val = (self.0 >> 6usize) & 0x01;
2796 val != 0
2797 }
2798 #[doc = "EoTp error interrupt enable This bit enables the interrupt generation on EoTp error."]
2799 #[inline(always)]
2800 pub fn set_eotpeie(&mut self, val: bool) {
2801 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2802 }
2803 #[doc = "LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error."]
2804 #[inline(always)]
2805 pub const fn lpwreie(&self) -> bool {
2806 let val = (self.0 >> 7usize) & 0x01;
2807 val != 0
2808 }
2809 #[doc = "LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error."]
2810 #[inline(always)]
2811 pub fn set_lpwreie(&mut self, val: bool) {
2812 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2813 }
2814 #[doc = "Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error."]
2815 #[inline(always)]
2816 pub const fn gcwreie(&self) -> bool {
2817 let val = (self.0 >> 8usize) & 0x01;
2818 val != 0
2819 }
2820 #[doc = "Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error."]
2821 #[inline(always)]
2822 pub fn set_gcwreie(&mut self, val: bool) {
2823 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2824 }
2825 #[doc = "Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error."]
2826 #[inline(always)]
2827 pub const fn gpwreie(&self) -> bool {
2828 let val = (self.0 >> 9usize) & 0x01;
2829 val != 0
2830 }
2831 #[doc = "Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error."]
2832 #[inline(always)]
2833 pub fn set_gpwreie(&mut self, val: bool) {
2834 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2835 }
2836 #[doc = "Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error."]
2837 #[inline(always)]
2838 pub const fn gptxeie(&self) -> bool {
2839 let val = (self.0 >> 10usize) & 0x01;
2840 val != 0
2841 }
2842 #[doc = "Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error."]
2843 #[inline(always)]
2844 pub fn set_gptxeie(&mut self, val: bool) {
2845 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2846 }
2847 #[doc = "Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error."]
2848 #[inline(always)]
2849 pub const fn gprdeie(&self) -> bool {
2850 let val = (self.0 >> 11usize) & 0x01;
2851 val != 0
2852 }
2853 #[doc = "Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error."]
2854 #[inline(always)]
2855 pub fn set_gprdeie(&mut self, val: bool) {
2856 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2857 }
2858 #[doc = "Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error."]
2859 #[inline(always)]
2860 pub const fn gprxeie(&self) -> bool {
2861 let val = (self.0 >> 12usize) & 0x01;
2862 val != 0
2863 }
2864 #[doc = "Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error."]
2865 #[inline(always)]
2866 pub fn set_gprxeie(&mut self, val: bool) {
2867 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2868 }
2869 #[doc = "Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error."]
2870 #[inline(always)]
2871 pub const fn pbueie(&self) -> bool {
2872 let val = (self.0 >> 19usize) & 0x01;
2873 val != 0
2874 }
2875 #[doc = "Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error."]
2876 #[inline(always)]
2877 pub fn set_pbueie(&mut self, val: bool) {
2878 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2879 }
2880 }
2881 impl Default for Ier1 {
2882 #[inline(always)]
2883 fn default() -> Ier1 {
2884 Ier1(0)
2885 }
2886 }
2887 impl core::fmt::Debug for Ier1 {
2888 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2889 f.debug_struct("Ier1")
2890 .field("tohstxie", &self.tohstxie())
2891 .field("tolprxie", &self.tolprxie())
2892 .field("eccseie", &self.eccseie())
2893 .field("eccmeie", &self.eccmeie())
2894 .field("crceie", &self.crceie())
2895 .field("pseie", &self.pseie())
2896 .field("eotpeie", &self.eotpeie())
2897 .field("lpwreie", &self.lpwreie())
2898 .field("gcwreie", &self.gcwreie())
2899 .field("gpwreie", &self.gpwreie())
2900 .field("gptxeie", &self.gptxeie())
2901 .field("gprdeie", &self.gprdeie())
2902 .field("gprxeie", &self.gprxeie())
2903 .field("pbueie", &self.pbueie())
2904 .finish()
2905 }
2906 }
2907 #[cfg(feature = "defmt")]
2908 impl defmt::Format for Ier1 {
2909 fn format(&self, f: defmt::Formatter) {
2910 #[derive(defmt :: Format)]
2911 struct Ier1 {
2912 tohstxie: bool,
2913 tolprxie: bool,
2914 eccseie: bool,
2915 eccmeie: bool,
2916 crceie: bool,
2917 pseie: bool,
2918 eotpeie: bool,
2919 lpwreie: bool,
2920 gcwreie: bool,
2921 gpwreie: bool,
2922 gptxeie: bool,
2923 gprdeie: bool,
2924 gprxeie: bool,
2925 pbueie: bool,
2926 }
2927 let proxy = Ier1 {
2928 tohstxie: self.tohstxie(),
2929 tolprxie: self.tolprxie(),
2930 eccseie: self.eccseie(),
2931 eccmeie: self.eccmeie(),
2932 crceie: self.crceie(),
2933 pseie: self.pseie(),
2934 eotpeie: self.eotpeie(),
2935 lpwreie: self.lpwreie(),
2936 gcwreie: self.gcwreie(),
2937 gpwreie: self.gpwreie(),
2938 gptxeie: self.gptxeie(),
2939 gprdeie: self.gprdeie(),
2940 gprxeie: self.gprxeie(),
2941 pbueie: self.pbueie(),
2942 };
2943 defmt::write!(f, "{}", proxy)
2944 }
2945 }
2946 #[doc = "DSI Host interrupt and status register 0."]
2947 #[repr(transparent)]
2948 #[derive(Copy, Clone, Eq, PartialEq)]
2949 pub struct Isr0(pub u32);
2950 impl Isr0 {
2951 #[doc = "Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report."]
2952 #[inline(always)]
2953 pub const fn ae0(&self) -> bool {
2954 let val = (self.0 >> 0usize) & 0x01;
2955 val != 0
2956 }
2957 #[doc = "Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report."]
2958 #[inline(always)]
2959 pub fn set_ae0(&mut self, val: bool) {
2960 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2961 }
2962 #[doc = "Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report."]
2963 #[inline(always)]
2964 pub const fn ae1(&self) -> bool {
2965 let val = (self.0 >> 1usize) & 0x01;
2966 val != 0
2967 }
2968 #[doc = "Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report."]
2969 #[inline(always)]
2970 pub fn set_ae1(&mut self, val: bool) {
2971 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2972 }
2973 #[doc = "Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report."]
2974 #[inline(always)]
2975 pub const fn ae2(&self) -> bool {
2976 let val = (self.0 >> 2usize) & 0x01;
2977 val != 0
2978 }
2979 #[doc = "Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report."]
2980 #[inline(always)]
2981 pub fn set_ae2(&mut self, val: bool) {
2982 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2983 }
2984 #[doc = "Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report."]
2985 #[inline(always)]
2986 pub const fn ae3(&self) -> bool {
2987 let val = (self.0 >> 3usize) & 0x01;
2988 val != 0
2989 }
2990 #[doc = "Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report."]
2991 #[inline(always)]
2992 pub fn set_ae3(&mut self, val: bool) {
2993 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2994 }
2995 #[doc = "Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report."]
2996 #[inline(always)]
2997 pub const fn ae4(&self) -> bool {
2998 let val = (self.0 >> 4usize) & 0x01;
2999 val != 0
3000 }
3001 #[doc = "Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report."]
3002 #[inline(always)]
3003 pub fn set_ae4(&mut self, val: bool) {
3004 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3005 }
3006 #[doc = "Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report."]
3007 #[inline(always)]
3008 pub const fn ae5(&self) -> bool {
3009 let val = (self.0 >> 5usize) & 0x01;
3010 val != 0
3011 }
3012 #[doc = "Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report."]
3013 #[inline(always)]
3014 pub fn set_ae5(&mut self, val: bool) {
3015 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3016 }
3017 #[doc = "Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report."]
3018 #[inline(always)]
3019 pub const fn ae6(&self) -> bool {
3020 let val = (self.0 >> 6usize) & 0x01;
3021 val != 0
3022 }
3023 #[doc = "Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report."]
3024 #[inline(always)]
3025 pub fn set_ae6(&mut self, val: bool) {
3026 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3027 }
3028 #[doc = "Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report."]
3029 #[inline(always)]
3030 pub const fn ae7(&self) -> bool {
3031 let val = (self.0 >> 7usize) & 0x01;
3032 val != 0
3033 }
3034 #[doc = "Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report."]
3035 #[inline(always)]
3036 pub fn set_ae7(&mut self, val: bool) {
3037 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3038 }
3039 #[doc = "Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report."]
3040 #[inline(always)]
3041 pub const fn ae8(&self) -> bool {
3042 let val = (self.0 >> 8usize) & 0x01;
3043 val != 0
3044 }
3045 #[doc = "Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report."]
3046 #[inline(always)]
3047 pub fn set_ae8(&mut self, val: bool) {
3048 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3049 }
3050 #[doc = "Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report."]
3051 #[inline(always)]
3052 pub const fn ae9(&self) -> bool {
3053 let val = (self.0 >> 9usize) & 0x01;
3054 val != 0
3055 }
3056 #[doc = "Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report."]
3057 #[inline(always)]
3058 pub fn set_ae9(&mut self, val: bool) {
3059 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3060 }
3061 #[doc = "Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report."]
3062 #[inline(always)]
3063 pub const fn ae10(&self) -> bool {
3064 let val = (self.0 >> 10usize) & 0x01;
3065 val != 0
3066 }
3067 #[doc = "Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report."]
3068 #[inline(always)]
3069 pub fn set_ae10(&mut self, val: bool) {
3070 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
3071 }
3072 #[doc = "Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report."]
3073 #[inline(always)]
3074 pub const fn ae11(&self) -> bool {
3075 let val = (self.0 >> 11usize) & 0x01;
3076 val != 0
3077 }
3078 #[doc = "Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report."]
3079 #[inline(always)]
3080 pub fn set_ae11(&mut self, val: bool) {
3081 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
3082 }
3083 #[doc = "Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report."]
3084 #[inline(always)]
3085 pub const fn ae12(&self) -> bool {
3086 let val = (self.0 >> 12usize) & 0x01;
3087 val != 0
3088 }
3089 #[doc = "Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report."]
3090 #[inline(always)]
3091 pub fn set_ae12(&mut self, val: bool) {
3092 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
3093 }
3094 #[doc = "Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report."]
3095 #[inline(always)]
3096 pub const fn ae13(&self) -> bool {
3097 let val = (self.0 >> 13usize) & 0x01;
3098 val != 0
3099 }
3100 #[doc = "Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report."]
3101 #[inline(always)]
3102 pub fn set_ae13(&mut self, val: bool) {
3103 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
3104 }
3105 #[doc = "Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report."]
3106 #[inline(always)]
3107 pub const fn ae14(&self) -> bool {
3108 let val = (self.0 >> 14usize) & 0x01;
3109 val != 0
3110 }
3111 #[doc = "Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report."]
3112 #[inline(always)]
3113 pub fn set_ae14(&mut self, val: bool) {
3114 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
3115 }
3116 #[doc = "Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report."]
3117 #[inline(always)]
3118 pub const fn ae15(&self) -> bool {
3119 let val = (self.0 >> 15usize) & 0x01;
3120 val != 0
3121 }
3122 #[doc = "Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report."]
3123 #[inline(always)]
3124 pub fn set_ae15(&mut self, val: bool) {
3125 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
3126 }
3127 #[doc = "PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0."]
3128 #[inline(always)]
3129 pub const fn pe0(&self) -> bool {
3130 let val = (self.0 >> 16usize) & 0x01;
3131 val != 0
3132 }
3133 #[doc = "PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0."]
3134 #[inline(always)]
3135 pub fn set_pe0(&mut self, val: bool) {
3136 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
3137 }
3138 #[doc = "PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0."]
3139 #[inline(always)]
3140 pub const fn pe1(&self) -> bool {
3141 let val = (self.0 >> 17usize) & 0x01;
3142 val != 0
3143 }
3144 #[doc = "PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0."]
3145 #[inline(always)]
3146 pub fn set_pe1(&mut self, val: bool) {
3147 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3148 }
3149 #[doc = "PHY error 2 This bit indicates the ErrControl error from lane 0."]
3150 #[inline(always)]
3151 pub const fn pe2(&self) -> bool {
3152 let val = (self.0 >> 18usize) & 0x01;
3153 val != 0
3154 }
3155 #[doc = "PHY error 2 This bit indicates the ErrControl error from lane 0."]
3156 #[inline(always)]
3157 pub fn set_pe2(&mut self, val: bool) {
3158 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3159 }
3160 #[doc = "PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0."]
3161 #[inline(always)]
3162 pub const fn pe3(&self) -> bool {
3163 let val = (self.0 >> 19usize) & 0x01;
3164 val != 0
3165 }
3166 #[doc = "PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0."]
3167 #[inline(always)]
3168 pub fn set_pe3(&mut self, val: bool) {
3169 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3170 }
3171 #[doc = "PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0."]
3172 #[inline(always)]
3173 pub const fn pe4(&self) -> bool {
3174 let val = (self.0 >> 20usize) & 0x01;
3175 val != 0
3176 }
3177 #[doc = "PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0."]
3178 #[inline(always)]
3179 pub fn set_pe4(&mut self, val: bool) {
3180 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3181 }
3182 }
3183 impl Default for Isr0 {
3184 #[inline(always)]
3185 fn default() -> Isr0 {
3186 Isr0(0)
3187 }
3188 }
3189 impl core::fmt::Debug for Isr0 {
3190 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3191 f.debug_struct("Isr0")
3192 .field("ae0", &self.ae0())
3193 .field("ae1", &self.ae1())
3194 .field("ae2", &self.ae2())
3195 .field("ae3", &self.ae3())
3196 .field("ae4", &self.ae4())
3197 .field("ae5", &self.ae5())
3198 .field("ae6", &self.ae6())
3199 .field("ae7", &self.ae7())
3200 .field("ae8", &self.ae8())
3201 .field("ae9", &self.ae9())
3202 .field("ae10", &self.ae10())
3203 .field("ae11", &self.ae11())
3204 .field("ae12", &self.ae12())
3205 .field("ae13", &self.ae13())
3206 .field("ae14", &self.ae14())
3207 .field("ae15", &self.ae15())
3208 .field("pe0", &self.pe0())
3209 .field("pe1", &self.pe1())
3210 .field("pe2", &self.pe2())
3211 .field("pe3", &self.pe3())
3212 .field("pe4", &self.pe4())
3213 .finish()
3214 }
3215 }
3216 #[cfg(feature = "defmt")]
3217 impl defmt::Format for Isr0 {
3218 fn format(&self, f: defmt::Formatter) {
3219 #[derive(defmt :: Format)]
3220 struct Isr0 {
3221 ae0: bool,
3222 ae1: bool,
3223 ae2: bool,
3224 ae3: bool,
3225 ae4: bool,
3226 ae5: bool,
3227 ae6: bool,
3228 ae7: bool,
3229 ae8: bool,
3230 ae9: bool,
3231 ae10: bool,
3232 ae11: bool,
3233 ae12: bool,
3234 ae13: bool,
3235 ae14: bool,
3236 ae15: bool,
3237 pe0: bool,
3238 pe1: bool,
3239 pe2: bool,
3240 pe3: bool,
3241 pe4: bool,
3242 }
3243 let proxy = Isr0 {
3244 ae0: self.ae0(),
3245 ae1: self.ae1(),
3246 ae2: self.ae2(),
3247 ae3: self.ae3(),
3248 ae4: self.ae4(),
3249 ae5: self.ae5(),
3250 ae6: self.ae6(),
3251 ae7: self.ae7(),
3252 ae8: self.ae8(),
3253 ae9: self.ae9(),
3254 ae10: self.ae10(),
3255 ae11: self.ae11(),
3256 ae12: self.ae12(),
3257 ae13: self.ae13(),
3258 ae14: self.ae14(),
3259 ae15: self.ae15(),
3260 pe0: self.pe0(),
3261 pe1: self.pe1(),
3262 pe2: self.pe2(),
3263 pe3: self.pe3(),
3264 pe4: self.pe4(),
3265 };
3266 defmt::write!(f, "{}", proxy)
3267 }
3268 }
3269 #[doc = "DSI Host interrupt and status register 1."]
3270 #[repr(transparent)]
3271 #[derive(Copy, Clone, Eq, PartialEq)]
3272 pub struct Isr1(pub u32);
3273 impl Isr1 {
3274 #[doc = "Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected."]
3275 #[inline(always)]
3276 pub const fn tohstx(&self) -> bool {
3277 let val = (self.0 >> 0usize) & 0x01;
3278 val != 0
3279 }
3280 #[doc = "Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected."]
3281 #[inline(always)]
3282 pub fn set_tohstx(&mut self, val: bool) {
3283 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3284 }
3285 #[doc = "Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected."]
3286 #[inline(always)]
3287 pub const fn tolprx(&self) -> bool {
3288 let val = (self.0 >> 1usize) & 0x01;
3289 val != 0
3290 }
3291 #[doc = "Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected."]
3292 #[inline(always)]
3293 pub fn set_tolprx(&mut self, val: bool) {
3294 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3295 }
3296 #[doc = "ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet."]
3297 #[inline(always)]
3298 pub const fn eccse(&self) -> bool {
3299 let val = (self.0 >> 2usize) & 0x01;
3300 val != 0
3301 }
3302 #[doc = "ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet."]
3303 #[inline(always)]
3304 pub fn set_eccse(&mut self, val: bool) {
3305 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3306 }
3307 #[doc = "ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet."]
3308 #[inline(always)]
3309 pub const fn eccme(&self) -> bool {
3310 let val = (self.0 >> 3usize) & 0x01;
3311 val != 0
3312 }
3313 #[doc = "ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet."]
3314 #[inline(always)]
3315 pub fn set_eccme(&mut self, val: bool) {
3316 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3317 }
3318 #[doc = "CRC error This bit indicates that the CRC error is detected in the received packet payload."]
3319 #[inline(always)]
3320 pub const fn crce(&self) -> bool {
3321 let val = (self.0 >> 4usize) & 0x01;
3322 val != 0
3323 }
3324 #[doc = "CRC error This bit indicates that the CRC error is detected in the received packet payload."]
3325 #[inline(always)]
3326 pub fn set_crce(&mut self, val: bool) {
3327 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3328 }
3329 #[doc = "Packet size error This bit indicates that the packet size error is detected during the packet reception."]
3330 #[inline(always)]
3331 pub const fn pse(&self) -> bool {
3332 let val = (self.0 >> 5usize) & 0x01;
3333 val != 0
3334 }
3335 #[doc = "Packet size error This bit indicates that the packet size error is detected during the packet reception."]
3336 #[inline(always)]
3337 pub fn set_pse(&mut self, val: bool) {
3338 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3339 }
3340 #[doc = "EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission."]
3341 #[inline(always)]
3342 pub const fn eotpe(&self) -> bool {
3343 let val = (self.0 >> 6usize) & 0x01;
3344 val != 0
3345 }
3346 #[doc = "EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission."]
3347 #[inline(always)]
3348 pub fn set_eotpe(&mut self, val: bool) {
3349 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3350 }
3351 #[doc = "LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted."]
3352 #[inline(always)]
3353 pub const fn lpwre(&self) -> bool {
3354 let val = (self.0 >> 7usize) & 0x01;
3355 val != 0
3356 }
3357 #[doc = "LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted."]
3358 #[inline(always)]
3359 pub fn set_lpwre(&mut self, val: bool) {
3360 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3361 }
3362 #[doc = "Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written."]
3363 #[inline(always)]
3364 pub const fn gcwre(&self) -> bool {
3365 let val = (self.0 >> 8usize) & 0x01;
3366 val != 0
3367 }
3368 #[doc = "Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written."]
3369 #[inline(always)]
3370 pub fn set_gcwre(&mut self, val: bool) {
3371 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3372 }
3373 #[doc = "Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written."]
3374 #[inline(always)]
3375 pub const fn gpwre(&self) -> bool {
3376 let val = (self.0 >> 9usize) & 0x01;
3377 val != 0
3378 }
3379 #[doc = "Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written."]
3380 #[inline(always)]
3381 pub fn set_gpwre(&mut self, val: bool) {
3382 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3383 }
3384 #[doc = "Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent."]
3385 #[inline(always)]
3386 pub const fn gptxe(&self) -> bool {
3387 let val = (self.0 >> 10usize) & 0x01;
3388 val != 0
3389 }
3390 #[doc = "Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent."]
3391 #[inline(always)]
3392 pub fn set_gptxe(&mut self, val: bool) {
3393 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
3394 }
3395 #[doc = "Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted."]
3396 #[inline(always)]
3397 pub const fn gprde(&self) -> bool {
3398 let val = (self.0 >> 11usize) & 0x01;
3399 val != 0
3400 }
3401 #[doc = "Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted."]
3402 #[inline(always)]
3403 pub fn set_gprde(&mut self, val: bool) {
3404 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
3405 }
3406 #[doc = "Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted."]
3407 #[inline(always)]
3408 pub const fn gprxe(&self) -> bool {
3409 let val = (self.0 >> 12usize) & 0x01;
3410 val != 0
3411 }
3412 #[doc = "Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted."]
3413 #[inline(always)]
3414 pub fn set_gprxe(&mut self, val: bool) {
3415 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
3416 }
3417 #[doc = "Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode."]
3418 #[inline(always)]
3419 pub const fn pbue(&self) -> bool {
3420 let val = (self.0 >> 19usize) & 0x01;
3421 val != 0
3422 }
3423 #[doc = "Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode."]
3424 #[inline(always)]
3425 pub fn set_pbue(&mut self, val: bool) {
3426 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3427 }
3428 }
3429 impl Default for Isr1 {
3430 #[inline(always)]
3431 fn default() -> Isr1 {
3432 Isr1(0)
3433 }
3434 }
3435 impl core::fmt::Debug for Isr1 {
3436 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3437 f.debug_struct("Isr1")
3438 .field("tohstx", &self.tohstx())
3439 .field("tolprx", &self.tolprx())
3440 .field("eccse", &self.eccse())
3441 .field("eccme", &self.eccme())
3442 .field("crce", &self.crce())
3443 .field("pse", &self.pse())
3444 .field("eotpe", &self.eotpe())
3445 .field("lpwre", &self.lpwre())
3446 .field("gcwre", &self.gcwre())
3447 .field("gpwre", &self.gpwre())
3448 .field("gptxe", &self.gptxe())
3449 .field("gprde", &self.gprde())
3450 .field("gprxe", &self.gprxe())
3451 .field("pbue", &self.pbue())
3452 .finish()
3453 }
3454 }
3455 #[cfg(feature = "defmt")]
3456 impl defmt::Format for Isr1 {
3457 fn format(&self, f: defmt::Formatter) {
3458 #[derive(defmt :: Format)]
3459 struct Isr1 {
3460 tohstx: bool,
3461 tolprx: bool,
3462 eccse: bool,
3463 eccme: bool,
3464 crce: bool,
3465 pse: bool,
3466 eotpe: bool,
3467 lpwre: bool,
3468 gcwre: bool,
3469 gpwre: bool,
3470 gptxe: bool,
3471 gprde: bool,
3472 gprxe: bool,
3473 pbue: bool,
3474 }
3475 let proxy = Isr1 {
3476 tohstx: self.tohstx(),
3477 tolprx: self.tolprx(),
3478 eccse: self.eccse(),
3479 eccme: self.eccme(),
3480 crce: self.crce(),
3481 pse: self.pse(),
3482 eotpe: self.eotpe(),
3483 lpwre: self.lpwre(),
3484 gcwre: self.gcwre(),
3485 gpwre: self.gpwre(),
3486 gptxe: self.gptxe(),
3487 gprde: self.gprde(),
3488 gprxe: self.gprxe(),
3489 pbue: self.pbue(),
3490 };
3491 defmt::write!(f, "{}", proxy)
3492 }
3493 }
3494 #[doc = "DSI Host LTDC current color coding register."]
3495 #[repr(transparent)]
3496 #[derive(Copy, Clone, Eq, PartialEq)]
3497 pub struct Lcccr(pub u32);
3498 impl Lcccr {
3499 #[doc = "Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit."]
3500 #[inline(always)]
3501 pub const fn colc(&self) -> u8 {
3502 let val = (self.0 >> 0usize) & 0x0f;
3503 val as u8
3504 }
3505 #[doc = "Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit."]
3506 #[inline(always)]
3507 pub fn set_colc(&mut self, val: u8) {
3508 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3509 }
3510 #[doc = "Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations."]
3511 #[inline(always)]
3512 pub const fn lpe(&self) -> bool {
3513 let val = (self.0 >> 8usize) & 0x01;
3514 val != 0
3515 }
3516 #[doc = "Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations."]
3517 #[inline(always)]
3518 pub fn set_lpe(&mut self, val: bool) {
3519 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3520 }
3521 }
3522 impl Default for Lcccr {
3523 #[inline(always)]
3524 fn default() -> Lcccr {
3525 Lcccr(0)
3526 }
3527 }
3528 impl core::fmt::Debug for Lcccr {
3529 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3530 f.debug_struct("Lcccr")
3531 .field("colc", &self.colc())
3532 .field("lpe", &self.lpe())
3533 .finish()
3534 }
3535 }
3536 #[cfg(feature = "defmt")]
3537 impl defmt::Format for Lcccr {
3538 fn format(&self, f: defmt::Formatter) {
3539 #[derive(defmt :: Format)]
3540 struct Lcccr {
3541 colc: u8,
3542 lpe: bool,
3543 }
3544 let proxy = Lcccr {
3545 colc: self.colc(),
3546 lpe: self.lpe(),
3547 };
3548 defmt::write!(f, "{}", proxy)
3549 }
3550 }
3551 #[doc = "DSI Host LTDC command configuration register."]
3552 #[repr(transparent)]
3553 #[derive(Copy, Clone, Eq, PartialEq)]
3554 pub struct Lccr(pub u32);
3555 impl Lccr {
3556 #[doc = "Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled."]
3557 #[inline(always)]
3558 pub const fn cmdsize(&self) -> u16 {
3559 let val = (self.0 >> 0usize) & 0xffff;
3560 val as u16
3561 }
3562 #[doc = "Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled."]
3563 #[inline(always)]
3564 pub fn set_cmdsize(&mut self, val: u16) {
3565 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3566 }
3567 }
3568 impl Default for Lccr {
3569 #[inline(always)]
3570 fn default() -> Lccr {
3571 Lccr(0)
3572 }
3573 }
3574 impl core::fmt::Debug for Lccr {
3575 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3576 f.debug_struct("Lccr").field("cmdsize", &self.cmdsize()).finish()
3577 }
3578 }
3579 #[cfg(feature = "defmt")]
3580 impl defmt::Format for Lccr {
3581 fn format(&self, f: defmt::Formatter) {
3582 #[derive(defmt :: Format)]
3583 struct Lccr {
3584 cmdsize: u16,
3585 }
3586 let proxy = Lccr {
3587 cmdsize: self.cmdsize(),
3588 };
3589 defmt::write!(f, "{}", proxy)
3590 }
3591 }
3592 #[doc = "DSI Host LTDC color coding register."]
3593 #[repr(transparent)]
3594 #[derive(Copy, Clone, Eq, PartialEq)]
3595 pub struct Lcolcr(pub u32);
3596 impl Lcolcr {
3597 #[doc = "Color coding This field configures the DPI color coding. Others: Reserved."]
3598 #[inline(always)]
3599 pub const fn colc(&self) -> u8 {
3600 let val = (self.0 >> 0usize) & 0x0f;
3601 val as u8
3602 }
3603 #[doc = "Color coding This field configures the DPI color coding. Others: Reserved."]
3604 #[inline(always)]
3605 pub fn set_colc(&mut self, val: u8) {
3606 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3607 }
3608 #[doc = "Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration."]
3609 #[inline(always)]
3610 pub const fn lpe(&self) -> bool {
3611 let val = (self.0 >> 8usize) & 0x01;
3612 val != 0
3613 }
3614 #[doc = "Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration."]
3615 #[inline(always)]
3616 pub fn set_lpe(&mut self, val: bool) {
3617 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3618 }
3619 }
3620 impl Default for Lcolcr {
3621 #[inline(always)]
3622 fn default() -> Lcolcr {
3623 Lcolcr(0)
3624 }
3625 }
3626 impl core::fmt::Debug for Lcolcr {
3627 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3628 f.debug_struct("Lcolcr")
3629 .field("colc", &self.colc())
3630 .field("lpe", &self.lpe())
3631 .finish()
3632 }
3633 }
3634 #[cfg(feature = "defmt")]
3635 impl defmt::Format for Lcolcr {
3636 fn format(&self, f: defmt::Formatter) {
3637 #[derive(defmt :: Format)]
3638 struct Lcolcr {
3639 colc: u8,
3640 lpe: bool,
3641 }
3642 let proxy = Lcolcr {
3643 colc: self.colc(),
3644 lpe: self.lpe(),
3645 };
3646 defmt::write!(f, "{}", proxy)
3647 }
3648 }
3649 #[doc = "DSI Host LTDC current VCID register."]
3650 #[repr(transparent)]
3651 #[derive(Copy, Clone, Eq, PartialEq)]
3652 pub struct Lcvcidr(pub u32);
3653 impl Lcvcidr {
3654 #[doc = "Virtual channel ID This field returns the virtual channel ID for the LTDC interface."]
3655 #[inline(always)]
3656 pub const fn vcid(&self) -> u8 {
3657 let val = (self.0 >> 0usize) & 0x03;
3658 val as u8
3659 }
3660 #[doc = "Virtual channel ID This field returns the virtual channel ID for the LTDC interface."]
3661 #[inline(always)]
3662 pub fn set_vcid(&mut self, val: u8) {
3663 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
3664 }
3665 }
3666 impl Default for Lcvcidr {
3667 #[inline(always)]
3668 fn default() -> Lcvcidr {
3669 Lcvcidr(0)
3670 }
3671 }
3672 impl core::fmt::Debug for Lcvcidr {
3673 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3674 f.debug_struct("Lcvcidr").field("vcid", &self.vcid()).finish()
3675 }
3676 }
3677 #[cfg(feature = "defmt")]
3678 impl defmt::Format for Lcvcidr {
3679 fn format(&self, f: defmt::Formatter) {
3680 #[derive(defmt :: Format)]
3681 struct Lcvcidr {
3682 vcid: u8,
3683 }
3684 let proxy = Lcvcidr { vcid: self.vcid() };
3685 defmt::write!(f, "{}", proxy)
3686 }
3687 }
3688 #[doc = "DSI Host LTDC polarity configuration register."]
3689 #[repr(transparent)]
3690 #[derive(Copy, Clone, Eq, PartialEq)]
3691 pub struct Lpcr(pub u32);
3692 impl Lpcr {
3693 #[doc = "Data enable polarity This bit configures the polarity of data enable pin."]
3694 #[inline(always)]
3695 pub const fn dep(&self) -> bool {
3696 let val = (self.0 >> 0usize) & 0x01;
3697 val != 0
3698 }
3699 #[doc = "Data enable polarity This bit configures the polarity of data enable pin."]
3700 #[inline(always)]
3701 pub fn set_dep(&mut self, val: bool) {
3702 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3703 }
3704 #[doc = "VSYNC polarity This bit configures the polarity of VSYNC pin."]
3705 #[inline(always)]
3706 pub const fn vsp(&self) -> bool {
3707 let val = (self.0 >> 1usize) & 0x01;
3708 val != 0
3709 }
3710 #[doc = "VSYNC polarity This bit configures the polarity of VSYNC pin."]
3711 #[inline(always)]
3712 pub fn set_vsp(&mut self, val: bool) {
3713 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3714 }
3715 #[doc = "HSYNC polarity This bit configures the polarity of HSYNC pin."]
3716 #[inline(always)]
3717 pub const fn hsp(&self) -> bool {
3718 let val = (self.0 >> 2usize) & 0x01;
3719 val != 0
3720 }
3721 #[doc = "HSYNC polarity This bit configures the polarity of HSYNC pin."]
3722 #[inline(always)]
3723 pub fn set_hsp(&mut self, val: bool) {
3724 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3725 }
3726 }
3727 impl Default for Lpcr {
3728 #[inline(always)]
3729 fn default() -> Lpcr {
3730 Lpcr(0)
3731 }
3732 }
3733 impl core::fmt::Debug for Lpcr {
3734 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3735 f.debug_struct("Lpcr")
3736 .field("dep", &self.dep())
3737 .field("vsp", &self.vsp())
3738 .field("hsp", &self.hsp())
3739 .finish()
3740 }
3741 }
3742 #[cfg(feature = "defmt")]
3743 impl defmt::Format for Lpcr {
3744 fn format(&self, f: defmt::Formatter) {
3745 #[derive(defmt :: Format)]
3746 struct Lpcr {
3747 dep: bool,
3748 vsp: bool,
3749 hsp: bool,
3750 }
3751 let proxy = Lpcr {
3752 dep: self.dep(),
3753 vsp: self.vsp(),
3754 hsp: self.hsp(),
3755 };
3756 defmt::write!(f, "{}", proxy)
3757 }
3758 }
3759 #[doc = "DSI Host low-power mode current configuration register."]
3760 #[repr(transparent)]
3761 #[derive(Copy, Clone, Eq, PartialEq)]
3762 pub struct Lpmccr(pub u32);
3763 impl Lpmccr {
3764 #[doc = "VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode."]
3765 #[inline(always)]
3766 pub const fn vlpsize(&self) -> u8 {
3767 let val = (self.0 >> 0usize) & 0xff;
3768 val as u8
3769 }
3770 #[doc = "VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode."]
3771 #[inline(always)]
3772 pub fn set_vlpsize(&mut self, val: u8) {
3773 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
3774 }
3775 #[doc = "Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode."]
3776 #[inline(always)]
3777 pub const fn lpsize(&self) -> u8 {
3778 let val = (self.0 >> 16usize) & 0xff;
3779 val as u8
3780 }
3781 #[doc = "Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode."]
3782 #[inline(always)]
3783 pub fn set_lpsize(&mut self, val: u8) {
3784 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
3785 }
3786 }
3787 impl Default for Lpmccr {
3788 #[inline(always)]
3789 fn default() -> Lpmccr {
3790 Lpmccr(0)
3791 }
3792 }
3793 impl core::fmt::Debug for Lpmccr {
3794 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3795 f.debug_struct("Lpmccr")
3796 .field("vlpsize", &self.vlpsize())
3797 .field("lpsize", &self.lpsize())
3798 .finish()
3799 }
3800 }
3801 #[cfg(feature = "defmt")]
3802 impl defmt::Format for Lpmccr {
3803 fn format(&self, f: defmt::Formatter) {
3804 #[derive(defmt :: Format)]
3805 struct Lpmccr {
3806 vlpsize: u8,
3807 lpsize: u8,
3808 }
3809 let proxy = Lpmccr {
3810 vlpsize: self.vlpsize(),
3811 lpsize: self.lpsize(),
3812 };
3813 defmt::write!(f, "{}", proxy)
3814 }
3815 }
3816 #[doc = "DSI Host low-power mode configuration register."]
3817 #[repr(transparent)]
3818 #[derive(Copy, Clone, Eq, PartialEq)]
3819 pub struct Lpmcr(pub u32);
3820 impl Lpmcr {
3821 #[doc = "VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions."]
3822 #[inline(always)]
3823 pub const fn vlpsize(&self) -> u8 {
3824 let val = (self.0 >> 0usize) & 0xff;
3825 val as u8
3826 }
3827 #[doc = "VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions."]
3828 #[inline(always)]
3829 pub fn set_vlpsize(&mut self, val: u8) {
3830 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
3831 }
3832 #[doc = "Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions."]
3833 #[inline(always)]
3834 pub const fn lpsize(&self) -> u8 {
3835 let val = (self.0 >> 16usize) & 0xff;
3836 val as u8
3837 }
3838 #[doc = "Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions."]
3839 #[inline(always)]
3840 pub fn set_lpsize(&mut self, val: u8) {
3841 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
3842 }
3843 }
3844 impl Default for Lpmcr {
3845 #[inline(always)]
3846 fn default() -> Lpmcr {
3847 Lpmcr(0)
3848 }
3849 }
3850 impl core::fmt::Debug for Lpmcr {
3851 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3852 f.debug_struct("Lpmcr")
3853 .field("vlpsize", &self.vlpsize())
3854 .field("lpsize", &self.lpsize())
3855 .finish()
3856 }
3857 }
3858 #[cfg(feature = "defmt")]
3859 impl defmt::Format for Lpmcr {
3860 fn format(&self, f: defmt::Formatter) {
3861 #[derive(defmt :: Format)]
3862 struct Lpmcr {
3863 vlpsize: u8,
3864 lpsize: u8,
3865 }
3866 let proxy = Lpmcr {
3867 vlpsize: self.vlpsize(),
3868 lpsize: self.lpsize(),
3869 };
3870 defmt::write!(f, "{}", proxy)
3871 }
3872 }
3873 #[doc = "DSI Host LTDC VCID register."]
3874 #[repr(transparent)]
3875 #[derive(Copy, Clone, Eq, PartialEq)]
3876 pub struct Lvcidr(pub u32);
3877 impl Lvcidr {
3878 #[doc = "Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic."]
3879 #[inline(always)]
3880 pub const fn vcid(&self) -> u8 {
3881 let val = (self.0 >> 0usize) & 0x03;
3882 val as u8
3883 }
3884 #[doc = "Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic."]
3885 #[inline(always)]
3886 pub fn set_vcid(&mut self, val: u8) {
3887 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
3888 }
3889 }
3890 impl Default for Lvcidr {
3891 #[inline(always)]
3892 fn default() -> Lvcidr {
3893 Lvcidr(0)
3894 }
3895 }
3896 impl core::fmt::Debug for Lvcidr {
3897 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3898 f.debug_struct("Lvcidr").field("vcid", &self.vcid()).finish()
3899 }
3900 }
3901 #[cfg(feature = "defmt")]
3902 impl defmt::Format for Lvcidr {
3903 fn format(&self, f: defmt::Formatter) {
3904 #[derive(defmt :: Format)]
3905 struct Lvcidr {
3906 vcid: u8,
3907 }
3908 let proxy = Lvcidr { vcid: self.vcid() };
3909 defmt::write!(f, "{}", proxy)
3910 }
3911 }
3912 #[doc = "DSI Host mode configuration register."]
3913 #[repr(transparent)]
3914 #[derive(Copy, Clone, Eq, PartialEq)]
3915 pub struct Mcr(pub u32);
3916 impl Mcr {
3917 #[doc = "Command mode This bit configures the DSI Host in either video or command mode."]
3918 #[inline(always)]
3919 pub const fn cmdm(&self) -> bool {
3920 let val = (self.0 >> 0usize) & 0x01;
3921 val != 0
3922 }
3923 #[doc = "Command mode This bit configures the DSI Host in either video or command mode."]
3924 #[inline(always)]
3925 pub fn set_cmdm(&mut self, val: bool) {
3926 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3927 }
3928 }
3929 impl Default for Mcr {
3930 #[inline(always)]
3931 fn default() -> Mcr {
3932 Mcr(0)
3933 }
3934 }
3935 impl core::fmt::Debug for Mcr {
3936 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3937 f.debug_struct("Mcr").field("cmdm", &self.cmdm()).finish()
3938 }
3939 }
3940 #[cfg(feature = "defmt")]
3941 impl defmt::Format for Mcr {
3942 fn format(&self, f: defmt::Formatter) {
3943 #[derive(defmt :: Format)]
3944 struct Mcr {
3945 cmdm: bool,
3946 }
3947 let proxy = Mcr { cmdm: self.cmdm() };
3948 defmt::write!(f, "{}", proxy)
3949 }
3950 }
3951 #[doc = "DSI Host PHY configuration register."]
3952 #[repr(transparent)]
3953 #[derive(Copy, Clone, Eq, PartialEq)]
3954 pub struct Pconfr(pub u32);
3955 impl Pconfr {
3956 #[doc = "Number of lanes This field configures the number of active data lanes: Others: Reserved."]
3957 #[inline(always)]
3958 pub const fn nl(&self) -> u8 {
3959 let val = (self.0 >> 0usize) & 0x03;
3960 val as u8
3961 }
3962 #[doc = "Number of lanes This field configures the number of active data lanes: Others: Reserved."]
3963 #[inline(always)]
3964 pub fn set_nl(&mut self, val: u8) {
3965 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
3966 }
3967 #[doc = "Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state."]
3968 #[inline(always)]
3969 pub const fn sw_time(&self) -> u8 {
3970 let val = (self.0 >> 8usize) & 0xff;
3971 val as u8
3972 }
3973 #[doc = "Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state."]
3974 #[inline(always)]
3975 pub fn set_sw_time(&mut self, val: u8) {
3976 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
3977 }
3978 }
3979 impl Default for Pconfr {
3980 #[inline(always)]
3981 fn default() -> Pconfr {
3982 Pconfr(0)
3983 }
3984 }
3985 impl core::fmt::Debug for Pconfr {
3986 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3987 f.debug_struct("Pconfr")
3988 .field("nl", &self.nl())
3989 .field("sw_time", &self.sw_time())
3990 .finish()
3991 }
3992 }
3993 #[cfg(feature = "defmt")]
3994 impl defmt::Format for Pconfr {
3995 fn format(&self, f: defmt::Formatter) {
3996 #[derive(defmt :: Format)]
3997 struct Pconfr {
3998 nl: u8,
3999 sw_time: u8,
4000 }
4001 let proxy = Pconfr {
4002 nl: self.nl(),
4003 sw_time: self.sw_time(),
4004 };
4005 defmt::write!(f, "{}", proxy)
4006 }
4007 }
4008 #[doc = "DSI Host protocol configuration register."]
4009 #[repr(transparent)]
4010 #[derive(Copy, Clone, Eq, PartialEq)]
4011 pub struct Pcr(pub u32);
4012 impl Pcr {
4013 #[doc = "EoTp transmission enable This bit enables the EoTP transmission."]
4014 #[inline(always)]
4015 pub const fn ettxe(&self) -> bool {
4016 let val = (self.0 >> 0usize) & 0x01;
4017 val != 0
4018 }
4019 #[doc = "EoTp transmission enable This bit enables the EoTP transmission."]
4020 #[inline(always)]
4021 pub fn set_ettxe(&mut self, val: bool) {
4022 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4023 }
4024 #[doc = "EoTp reception enable This bit enables the EoTp reception."]
4025 #[inline(always)]
4026 pub const fn etrxe(&self) -> bool {
4027 let val = (self.0 >> 1usize) & 0x01;
4028 val != 0
4029 }
4030 #[doc = "EoTp reception enable This bit enables the EoTp reception."]
4031 #[inline(always)]
4032 pub fn set_etrxe(&mut self, val: bool) {
4033 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4034 }
4035 #[doc = "Bus-turn-around enable This bit enables the bus-turn-around (BTA) request."]
4036 #[inline(always)]
4037 pub const fn btae(&self) -> bool {
4038 let val = (self.0 >> 2usize) & 0x01;
4039 val != 0
4040 }
4041 #[doc = "Bus-turn-around enable This bit enables the bus-turn-around (BTA) request."]
4042 #[inline(always)]
4043 pub fn set_btae(&mut self, val: bool) {
4044 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4045 }
4046 #[doc = "ECC reception enable This bit enables the ECC reception, error correction and reporting."]
4047 #[inline(always)]
4048 pub const fn eccrxe(&self) -> bool {
4049 let val = (self.0 >> 3usize) & 0x01;
4050 val != 0
4051 }
4052 #[doc = "ECC reception enable This bit enables the ECC reception, error correction and reporting."]
4053 #[inline(always)]
4054 pub fn set_eccrxe(&mut self, val: bool) {
4055 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4056 }
4057 #[doc = "CRC reception enable This bit enables the CRC reception and error reporting."]
4058 #[inline(always)]
4059 pub const fn crcrxe(&self) -> bool {
4060 let val = (self.0 >> 4usize) & 0x01;
4061 val != 0
4062 }
4063 #[doc = "CRC reception enable This bit enables the CRC reception and error reporting."]
4064 #[inline(always)]
4065 pub fn set_crcrxe(&mut self, val: bool) {
4066 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4067 }
4068 #[doc = "EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power."]
4069 #[inline(always)]
4070 pub const fn ettxlpe(&self) -> bool {
4071 let val = (self.0 >> 5usize) & 0x01;
4072 val != 0
4073 }
4074 #[doc = "EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power."]
4075 #[inline(always)]
4076 pub fn set_ettxlpe(&mut self, val: bool) {
4077 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4078 }
4079 }
4080 impl Default for Pcr {
4081 #[inline(always)]
4082 fn default() -> Pcr {
4083 Pcr(0)
4084 }
4085 }
4086 impl core::fmt::Debug for Pcr {
4087 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4088 f.debug_struct("Pcr")
4089 .field("ettxe", &self.ettxe())
4090 .field("etrxe", &self.etrxe())
4091 .field("btae", &self.btae())
4092 .field("eccrxe", &self.eccrxe())
4093 .field("crcrxe", &self.crcrxe())
4094 .field("ettxlpe", &self.ettxlpe())
4095 .finish()
4096 }
4097 }
4098 #[cfg(feature = "defmt")]
4099 impl defmt::Format for Pcr {
4100 fn format(&self, f: defmt::Formatter) {
4101 #[derive(defmt :: Format)]
4102 struct Pcr {
4103 ettxe: bool,
4104 etrxe: bool,
4105 btae: bool,
4106 eccrxe: bool,
4107 crcrxe: bool,
4108 ettxlpe: bool,
4109 }
4110 let proxy = Pcr {
4111 ettxe: self.ettxe(),
4112 etrxe: self.etrxe(),
4113 btae: self.btae(),
4114 eccrxe: self.eccrxe(),
4115 crcrxe: self.crcrxe(),
4116 ettxlpe: self.ettxlpe(),
4117 };
4118 defmt::write!(f, "{}", proxy)
4119 }
4120 }
4121 #[doc = "DSI Host PHY control register."]
4122 #[repr(transparent)]
4123 #[derive(Copy, Clone, Eq, PartialEq)]
4124 pub struct Pctlr(pub u32);
4125 impl Pctlr {
4126 #[doc = "Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state."]
4127 #[inline(always)]
4128 pub const fn den(&self) -> bool {
4129 let val = (self.0 >> 1usize) & 0x01;
4130 val != 0
4131 }
4132 #[doc = "Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state."]
4133 #[inline(always)]
4134 pub fn set_den(&mut self, val: bool) {
4135 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4136 }
4137 #[doc = "Clock enable This bit enables the D-PHY clock lane module:."]
4138 #[inline(always)]
4139 pub const fn cke(&self) -> bool {
4140 let val = (self.0 >> 2usize) & 0x01;
4141 val != 0
4142 }
4143 #[doc = "Clock enable This bit enables the D-PHY clock lane module:."]
4144 #[inline(always)]
4145 pub fn set_cke(&mut self, val: bool) {
4146 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4147 }
4148 }
4149 impl Default for Pctlr {
4150 #[inline(always)]
4151 fn default() -> Pctlr {
4152 Pctlr(0)
4153 }
4154 }
4155 impl core::fmt::Debug for Pctlr {
4156 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4157 f.debug_struct("Pctlr")
4158 .field("den", &self.den())
4159 .field("cke", &self.cke())
4160 .finish()
4161 }
4162 }
4163 #[cfg(feature = "defmt")]
4164 impl defmt::Format for Pctlr {
4165 fn format(&self, f: defmt::Formatter) {
4166 #[derive(defmt :: Format)]
4167 struct Pctlr {
4168 den: bool,
4169 cke: bool,
4170 }
4171 let proxy = Pctlr {
4172 den: self.den(),
4173 cke: self.cke(),
4174 };
4175 defmt::write!(f, "{}", proxy)
4176 }
4177 }
4178 #[doc = "DSI Host PHY status register."]
4179 #[repr(transparent)]
4180 #[derive(Copy, Clone, Eq, PartialEq)]
4181 pub struct Psr(pub u32);
4182 impl Psr {
4183 #[doc = "PHY direction This bit indicates the status of phydirection D-PHY signal."]
4184 #[inline(always)]
4185 pub const fn pd(&self) -> bool {
4186 let val = (self.0 >> 1usize) & 0x01;
4187 val != 0
4188 }
4189 #[doc = "PHY direction This bit indicates the status of phydirection D-PHY signal."]
4190 #[inline(always)]
4191 pub fn set_pd(&mut self, val: bool) {
4192 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4193 }
4194 #[doc = "PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal."]
4195 #[inline(always)]
4196 pub const fn pssc(&self) -> bool {
4197 let val = (self.0 >> 2usize) & 0x01;
4198 val != 0
4199 }
4200 #[doc = "PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal."]
4201 #[inline(always)]
4202 pub fn set_pssc(&mut self, val: bool) {
4203 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4204 }
4205 #[doc = "ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal."]
4206 #[inline(always)]
4207 pub const fn uanc(&self) -> bool {
4208 let val = (self.0 >> 3usize) & 0x01;
4209 val != 0
4210 }
4211 #[doc = "ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal."]
4212 #[inline(always)]
4213 pub fn set_uanc(&mut self, val: bool) {
4214 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4215 }
4216 #[doc = "PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal."]
4217 #[inline(always)]
4218 pub const fn pss0(&self) -> bool {
4219 let val = (self.0 >> 4usize) & 0x01;
4220 val != 0
4221 }
4222 #[doc = "PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal."]
4223 #[inline(always)]
4224 pub fn set_pss0(&mut self, val: bool) {
4225 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4226 }
4227 #[doc = "ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal."]
4228 #[inline(always)]
4229 pub const fn uan0(&self) -> bool {
4230 let val = (self.0 >> 5usize) & 0x01;
4231 val != 0
4232 }
4233 #[doc = "ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal."]
4234 #[inline(always)]
4235 pub fn set_uan0(&mut self, val: bool) {
4236 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4237 }
4238 #[doc = "RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal."]
4239 #[inline(always)]
4240 pub const fn rue0(&self) -> bool {
4241 let val = (self.0 >> 6usize) & 0x01;
4242 val != 0
4243 }
4244 #[doc = "RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal."]
4245 #[inline(always)]
4246 pub fn set_rue0(&mut self, val: bool) {
4247 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4248 }
4249 #[doc = "PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal."]
4250 #[inline(always)]
4251 pub const fn pss1(&self) -> bool {
4252 let val = (self.0 >> 7usize) & 0x01;
4253 val != 0
4254 }
4255 #[doc = "PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal."]
4256 #[inline(always)]
4257 pub fn set_pss1(&mut self, val: bool) {
4258 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
4259 }
4260 #[doc = "ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal."]
4261 #[inline(always)]
4262 pub const fn uan1(&self) -> bool {
4263 let val = (self.0 >> 8usize) & 0x01;
4264 val != 0
4265 }
4266 #[doc = "ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal."]
4267 #[inline(always)]
4268 pub fn set_uan1(&mut self, val: bool) {
4269 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4270 }
4271 }
4272 impl Default for Psr {
4273 #[inline(always)]
4274 fn default() -> Psr {
4275 Psr(0)
4276 }
4277 }
4278 impl core::fmt::Debug for Psr {
4279 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4280 f.debug_struct("Psr")
4281 .field("pd", &self.pd())
4282 .field("pssc", &self.pssc())
4283 .field("uanc", &self.uanc())
4284 .field("pss0", &self.pss0())
4285 .field("uan0", &self.uan0())
4286 .field("rue0", &self.rue0())
4287 .field("pss1", &self.pss1())
4288 .field("uan1", &self.uan1())
4289 .finish()
4290 }
4291 }
4292 #[cfg(feature = "defmt")]
4293 impl defmt::Format for Psr {
4294 fn format(&self, f: defmt::Formatter) {
4295 #[derive(defmt :: Format)]
4296 struct Psr {
4297 pd: bool,
4298 pssc: bool,
4299 uanc: bool,
4300 pss0: bool,
4301 uan0: bool,
4302 rue0: bool,
4303 pss1: bool,
4304 uan1: bool,
4305 }
4306 let proxy = Psr {
4307 pd: self.pd(),
4308 pssc: self.pssc(),
4309 uanc: self.uanc(),
4310 pss0: self.pss0(),
4311 uan0: self.uan0(),
4312 rue0: self.rue0(),
4313 pss1: self.pss1(),
4314 uan1: self.uan1(),
4315 };
4316 defmt::write!(f, "{}", proxy)
4317 }
4318 }
4319 #[doc = "DSI Host PHY TX triggers configuration register."]
4320 #[repr(transparent)]
4321 #[derive(Copy, Clone, Eq, PartialEq)]
4322 pub struct Pttcr(pub u32);
4323 impl Pttcr {
4324 #[doc = "Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time."]
4325 #[inline(always)]
4326 pub const fn tx_trig(&self) -> u8 {
4327 let val = (self.0 >> 0usize) & 0x0f;
4328 val as u8
4329 }
4330 #[doc = "Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time."]
4331 #[inline(always)]
4332 pub fn set_tx_trig(&mut self, val: u8) {
4333 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
4334 }
4335 }
4336 impl Default for Pttcr {
4337 #[inline(always)]
4338 fn default() -> Pttcr {
4339 Pttcr(0)
4340 }
4341 }
4342 impl core::fmt::Debug for Pttcr {
4343 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4344 f.debug_struct("Pttcr").field("tx_trig", &self.tx_trig()).finish()
4345 }
4346 }
4347 #[cfg(feature = "defmt")]
4348 impl defmt::Format for Pttcr {
4349 fn format(&self, f: defmt::Formatter) {
4350 #[derive(defmt :: Format)]
4351 struct Pttcr {
4352 tx_trig: u8,
4353 }
4354 let proxy = Pttcr {
4355 tx_trig: self.tx_trig(),
4356 };
4357 defmt::write!(f, "{}", proxy)
4358 }
4359 }
4360 #[doc = "DSI Host PHY ULPS control register."]
4361 #[repr(transparent)]
4362 #[derive(Copy, Clone, Eq, PartialEq)]
4363 pub struct Pucr(pub u32);
4364 impl Pucr {
4365 #[doc = "ULPS request on clock lane ULPS mode request on clock lane."]
4366 #[inline(always)]
4367 pub const fn urcl(&self) -> bool {
4368 let val = (self.0 >> 0usize) & 0x01;
4369 val != 0
4370 }
4371 #[doc = "ULPS request on clock lane ULPS mode request on clock lane."]
4372 #[inline(always)]
4373 pub fn set_urcl(&mut self, val: bool) {
4374 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4375 }
4376 #[doc = "ULPS exit on clock lane ULPS mode exit on clock lane."]
4377 #[inline(always)]
4378 pub const fn uecl(&self) -> bool {
4379 let val = (self.0 >> 1usize) & 0x01;
4380 val != 0
4381 }
4382 #[doc = "ULPS exit on clock lane ULPS mode exit on clock lane."]
4383 #[inline(always)]
4384 pub fn set_uecl(&mut self, val: bool) {
4385 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4386 }
4387 #[doc = "ULPS request on data lane ULPS mode request on all active data lanes."]
4388 #[inline(always)]
4389 pub const fn urdl(&self) -> bool {
4390 let val = (self.0 >> 2usize) & 0x01;
4391 val != 0
4392 }
4393 #[doc = "ULPS request on data lane ULPS mode request on all active data lanes."]
4394 #[inline(always)]
4395 pub fn set_urdl(&mut self, val: bool) {
4396 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4397 }
4398 #[doc = "ULPS exit on data lane ULPS mode exit on all active data lanes."]
4399 #[inline(always)]
4400 pub const fn uedl(&self) -> bool {
4401 let val = (self.0 >> 3usize) & 0x01;
4402 val != 0
4403 }
4404 #[doc = "ULPS exit on data lane ULPS mode exit on all active data lanes."]
4405 #[inline(always)]
4406 pub fn set_uedl(&mut self, val: bool) {
4407 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4408 }
4409 }
4410 impl Default for Pucr {
4411 #[inline(always)]
4412 fn default() -> Pucr {
4413 Pucr(0)
4414 }
4415 }
4416 impl core::fmt::Debug for Pucr {
4417 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4418 f.debug_struct("Pucr")
4419 .field("urcl", &self.urcl())
4420 .field("uecl", &self.uecl())
4421 .field("urdl", &self.urdl())
4422 .field("uedl", &self.uedl())
4423 .finish()
4424 }
4425 }
4426 #[cfg(feature = "defmt")]
4427 impl defmt::Format for Pucr {
4428 fn format(&self, f: defmt::Formatter) {
4429 #[derive(defmt :: Format)]
4430 struct Pucr {
4431 urcl: bool,
4432 uecl: bool,
4433 urdl: bool,
4434 uedl: bool,
4435 }
4436 let proxy = Pucr {
4437 urcl: self.urcl(),
4438 uecl: self.uecl(),
4439 urdl: self.urdl(),
4440 uedl: self.uedl(),
4441 };
4442 defmt::write!(f, "{}", proxy)
4443 }
4444 }
4445 #[doc = "DSI Host timeout counter configuration register 0."]
4446 #[repr(transparent)]
4447 #[derive(Copy, Clone, Eq, PartialEq)]
4448 pub struct Tccr0(pub u32);
4449 impl Tccr0 {
4450 #[doc = "Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles)."]
4451 #[inline(always)]
4452 pub const fn lprx_tocnt(&self) -> u16 {
4453 let val = (self.0 >> 0usize) & 0xffff;
4454 val as u16
4455 }
4456 #[doc = "Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles)."]
4457 #[inline(always)]
4458 pub fn set_lprx_tocnt(&mut self, val: u16) {
4459 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4460 }
4461 #[doc = "High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\u{89}¥ the time of one FRAME data transmission *Â (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\u{89}¥ the time of one LINE data transmission *Â (1Â +Â 10%)."]
4462 #[inline(always)]
4463 pub const fn hstx_tocnt(&self) -> u16 {
4464 let val = (self.0 >> 16usize) & 0xffff;
4465 val as u16
4466 }
4467 #[doc = "High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\u{89}¥ the time of one FRAME data transmission *Â (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\u{89}¥ the time of one LINE data transmission *Â (1Â +Â 10%)."]
4468 #[inline(always)]
4469 pub fn set_hstx_tocnt(&mut self, val: u16) {
4470 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
4471 }
4472 }
4473 impl Default for Tccr0 {
4474 #[inline(always)]
4475 fn default() -> Tccr0 {
4476 Tccr0(0)
4477 }
4478 }
4479 impl core::fmt::Debug for Tccr0 {
4480 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4481 f.debug_struct("Tccr0")
4482 .field("lprx_tocnt", &self.lprx_tocnt())
4483 .field("hstx_tocnt", &self.hstx_tocnt())
4484 .finish()
4485 }
4486 }
4487 #[cfg(feature = "defmt")]
4488 impl defmt::Format for Tccr0 {
4489 fn format(&self, f: defmt::Formatter) {
4490 #[derive(defmt :: Format)]
4491 struct Tccr0 {
4492 lprx_tocnt: u16,
4493 hstx_tocnt: u16,
4494 }
4495 let proxy = Tccr0 {
4496 lprx_tocnt: self.lprx_tocnt(),
4497 hstx_tocnt: self.hstx_tocnt(),
4498 };
4499 defmt::write!(f, "{}", proxy)
4500 }
4501 }
4502 #[doc = "DSI Host timeout counter configuration register 1."]
4503 #[repr(transparent)]
4504 #[derive(Copy, Clone, Eq, PartialEq)]
4505 pub struct Tccr1(pub u32);
4506 impl Tccr1 {
4507 #[doc = "High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4508 #[inline(always)]
4509 pub const fn hsrd_tocnt(&self) -> u16 {
4510 let val = (self.0 >> 0usize) & 0xffff;
4511 val as u16
4512 }
4513 #[doc = "High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4514 #[inline(always)]
4515 pub fn set_hsrd_tocnt(&mut self, val: u16) {
4516 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4517 }
4518 }
4519 impl Default for Tccr1 {
4520 #[inline(always)]
4521 fn default() -> Tccr1 {
4522 Tccr1(0)
4523 }
4524 }
4525 impl core::fmt::Debug for Tccr1 {
4526 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4527 f.debug_struct("Tccr1").field("hsrd_tocnt", &self.hsrd_tocnt()).finish()
4528 }
4529 }
4530 #[cfg(feature = "defmt")]
4531 impl defmt::Format for Tccr1 {
4532 fn format(&self, f: defmt::Formatter) {
4533 #[derive(defmt :: Format)]
4534 struct Tccr1 {
4535 hsrd_tocnt: u16,
4536 }
4537 let proxy = Tccr1 {
4538 hsrd_tocnt: self.hsrd_tocnt(),
4539 };
4540 defmt::write!(f, "{}", proxy)
4541 }
4542 }
4543 #[doc = "DSI Host timeout counter configuration register 2."]
4544 #[repr(transparent)]
4545 #[derive(Copy, Clone, Eq, PartialEq)]
4546 pub struct Tccr2(pub u32);
4547 impl Tccr2 {
4548 #[doc = "Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4549 #[inline(always)]
4550 pub const fn lprd_tocnt(&self) -> u16 {
4551 let val = (self.0 >> 0usize) & 0xffff;
4552 val as u16
4553 }
4554 #[doc = "Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4555 #[inline(always)]
4556 pub fn set_lprd_tocnt(&mut self, val: u16) {
4557 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4558 }
4559 }
4560 impl Default for Tccr2 {
4561 #[inline(always)]
4562 fn default() -> Tccr2 {
4563 Tccr2(0)
4564 }
4565 }
4566 impl core::fmt::Debug for Tccr2 {
4567 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4568 f.debug_struct("Tccr2").field("lprd_tocnt", &self.lprd_tocnt()).finish()
4569 }
4570 }
4571 #[cfg(feature = "defmt")]
4572 impl defmt::Format for Tccr2 {
4573 fn format(&self, f: defmt::Formatter) {
4574 #[derive(defmt :: Format)]
4575 struct Tccr2 {
4576 lprd_tocnt: u16,
4577 }
4578 let proxy = Tccr2 {
4579 lprd_tocnt: self.lprd_tocnt(),
4580 };
4581 defmt::write!(f, "{}", proxy)
4582 }
4583 }
4584 #[doc = "DSI Host timeout counter configuration register 3."]
4585 #[repr(transparent)]
4586 #[derive(Copy, Clone, Eq, PartialEq)]
4587 pub struct Tccr3(pub u32);
4588 impl Tccr3 {
4589 #[doc = "High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4590 #[inline(always)]
4591 pub const fn hswr_tocnt(&self) -> u16 {
4592 let val = (self.0 >> 0usize) & 0xffff;
4593 val as u16
4594 }
4595 #[doc = "High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4596 #[inline(always)]
4597 pub fn set_hswr_tocnt(&mut self, val: u16) {
4598 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4599 }
4600 #[doc = "Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready."]
4601 #[inline(always)]
4602 pub const fn pm(&self) -> bool {
4603 let val = (self.0 >> 24usize) & 0x01;
4604 val != 0
4605 }
4606 #[doc = "Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready."]
4607 #[inline(always)]
4608 pub fn set_pm(&mut self, val: bool) {
4609 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
4610 }
4611 }
4612 impl Default for Tccr3 {
4613 #[inline(always)]
4614 fn default() -> Tccr3 {
4615 Tccr3(0)
4616 }
4617 }
4618 impl core::fmt::Debug for Tccr3 {
4619 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4620 f.debug_struct("Tccr3")
4621 .field("hswr_tocnt", &self.hswr_tocnt())
4622 .field("pm", &self.pm())
4623 .finish()
4624 }
4625 }
4626 #[cfg(feature = "defmt")]
4627 impl defmt::Format for Tccr3 {
4628 fn format(&self, f: defmt::Formatter) {
4629 #[derive(defmt :: Format)]
4630 struct Tccr3 {
4631 hswr_tocnt: u16,
4632 pm: bool,
4633 }
4634 let proxy = Tccr3 {
4635 hswr_tocnt: self.hswr_tocnt(),
4636 pm: self.pm(),
4637 };
4638 defmt::write!(f, "{}", proxy)
4639 }
4640 }
4641 #[doc = "DSI Host timeout counter configuration register 4."]
4642 #[repr(transparent)]
4643 #[derive(Copy, Clone, Eq, PartialEq)]
4644 pub struct Tccr4(pub u32);
4645 impl Tccr4 {
4646 #[doc = "Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4647 #[inline(always)]
4648 pub const fn lpwr_tocnt(&self) -> u16 {
4649 let val = (self.0 >> 0usize) & 0xffff;
4650 val as u16
4651 }
4652 #[doc = "Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts."]
4653 #[inline(always)]
4654 pub fn set_lpwr_tocnt(&mut self, val: u16) {
4655 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4656 }
4657 }
4658 impl Default for Tccr4 {
4659 #[inline(always)]
4660 fn default() -> Tccr4 {
4661 Tccr4(0)
4662 }
4663 }
4664 impl core::fmt::Debug for Tccr4 {
4665 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4666 f.debug_struct("Tccr4").field("lpwr_tocnt", &self.lpwr_tocnt()).finish()
4667 }
4668 }
4669 #[cfg(feature = "defmt")]
4670 impl defmt::Format for Tccr4 {
4671 fn format(&self, f: defmt::Formatter) {
4672 #[derive(defmt :: Format)]
4673 struct Tccr4 {
4674 lpwr_tocnt: u16,
4675 }
4676 let proxy = Tccr4 {
4677 lpwr_tocnt: self.lpwr_tocnt(),
4678 };
4679 defmt::write!(f, "{}", proxy)
4680 }
4681 }
4682 #[doc = "DSI Host timeout counter configuration register 5."]
4683 #[repr(transparent)]
4684 #[derive(Copy, Clone, Eq, PartialEq)]
4685 pub struct Tccr5(pub u32);
4686 impl Tccr5 {
4687 #[doc = "Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the Dâ\u{80}\u{91}PHY enters the Stop state and causes no interrupts."]
4688 #[inline(always)]
4689 pub const fn bta_tocnt(&self) -> u16 {
4690 let val = (self.0 >> 0usize) & 0xffff;
4691 val as u16
4692 }
4693 #[doc = "Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the Dâ\u{80}\u{91}PHY enters the Stop state and causes no interrupts."]
4694 #[inline(always)]
4695 pub fn set_bta_tocnt(&mut self, val: u16) {
4696 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4697 }
4698 }
4699 impl Default for Tccr5 {
4700 #[inline(always)]
4701 fn default() -> Tccr5 {
4702 Tccr5(0)
4703 }
4704 }
4705 impl core::fmt::Debug for Tccr5 {
4706 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4707 f.debug_struct("Tccr5").field("bta_tocnt", &self.bta_tocnt()).finish()
4708 }
4709 }
4710 #[cfg(feature = "defmt")]
4711 impl defmt::Format for Tccr5 {
4712 fn format(&self, f: defmt::Formatter) {
4713 #[derive(defmt :: Format)]
4714 struct Tccr5 {
4715 bta_tocnt: u16,
4716 }
4717 let proxy = Tccr5 {
4718 bta_tocnt: self.bta_tocnt(),
4719 };
4720 defmt::write!(f, "{}", proxy)
4721 }
4722 }
4723 #[doc = "DSI Host video chunks current configuration register."]
4724 #[repr(transparent)]
4725 #[derive(Copy, Clone, Eq, PartialEq)]
4726 pub struct Vcccr(pub u32);
4727 impl Vcccr {
4728 #[doc = "Number of chunks This field returns the number of chunks being transmitted during a line period."]
4729 #[inline(always)]
4730 pub const fn numc(&self) -> u16 {
4731 let val = (self.0 >> 0usize) & 0x1fff;
4732 val as u16
4733 }
4734 #[doc = "Number of chunks This field returns the number of chunks being transmitted during a line period."]
4735 #[inline(always)]
4736 pub fn set_numc(&mut self, val: u16) {
4737 self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize);
4738 }
4739 }
4740 impl Default for Vcccr {
4741 #[inline(always)]
4742 fn default() -> Vcccr {
4743 Vcccr(0)
4744 }
4745 }
4746 impl core::fmt::Debug for Vcccr {
4747 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4748 f.debug_struct("Vcccr").field("numc", &self.numc()).finish()
4749 }
4750 }
4751 #[cfg(feature = "defmt")]
4752 impl defmt::Format for Vcccr {
4753 fn format(&self, f: defmt::Formatter) {
4754 #[derive(defmt :: Format)]
4755 struct Vcccr {
4756 numc: u16,
4757 }
4758 let proxy = Vcccr { numc: self.numc() };
4759 defmt::write!(f, "{}", proxy)
4760 }
4761 }
4762 #[doc = "DSI Host video chunks configuration register."]
4763 #[repr(transparent)]
4764 #[derive(Copy, Clone, Eq, PartialEq)]
4765 pub struct Vccr(pub u32);
4766 impl Vccr {
4767 #[doc = "Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line."]
4768 #[inline(always)]
4769 pub const fn numc(&self) -> u16 {
4770 let val = (self.0 >> 0usize) & 0x1fff;
4771 val as u16
4772 }
4773 #[doc = "Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line."]
4774 #[inline(always)]
4775 pub fn set_numc(&mut self, val: u16) {
4776 self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize);
4777 }
4778 }
4779 impl Default for Vccr {
4780 #[inline(always)]
4781 fn default() -> Vccr {
4782 Vccr(0)
4783 }
4784 }
4785 impl core::fmt::Debug for Vccr {
4786 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4787 f.debug_struct("Vccr").field("numc", &self.numc()).finish()
4788 }
4789 }
4790 #[cfg(feature = "defmt")]
4791 impl defmt::Format for Vccr {
4792 fn format(&self, f: defmt::Formatter) {
4793 #[derive(defmt :: Format)]
4794 struct Vccr {
4795 numc: u16,
4796 }
4797 let proxy = Vccr { numc: self.numc() };
4798 defmt::write!(f, "{}", proxy)
4799 }
4800 }
4801 #[doc = "DSI Host video HBP current configuration register."]
4802 #[repr(transparent)]
4803 #[derive(Copy, Clone, Eq, PartialEq)]
4804 pub struct Vhbpccr(pub u32);
4805 impl Vhbpccr {
4806 #[doc = "Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles."]
4807 #[inline(always)]
4808 pub const fn hbp(&self) -> u16 {
4809 let val = (self.0 >> 0usize) & 0x0fff;
4810 val as u16
4811 }
4812 #[doc = "Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles."]
4813 #[inline(always)]
4814 pub fn set_hbp(&mut self, val: u16) {
4815 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
4816 }
4817 }
4818 impl Default for Vhbpccr {
4819 #[inline(always)]
4820 fn default() -> Vhbpccr {
4821 Vhbpccr(0)
4822 }
4823 }
4824 impl core::fmt::Debug for Vhbpccr {
4825 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4826 f.debug_struct("Vhbpccr").field("hbp", &self.hbp()).finish()
4827 }
4828 }
4829 #[cfg(feature = "defmt")]
4830 impl defmt::Format for Vhbpccr {
4831 fn format(&self, f: defmt::Formatter) {
4832 #[derive(defmt :: Format)]
4833 struct Vhbpccr {
4834 hbp: u16,
4835 }
4836 let proxy = Vhbpccr { hbp: self.hbp() };
4837 defmt::write!(f, "{}", proxy)
4838 }
4839 }
4840 #[doc = "DSI Host video HBP configuration register."]
4841 #[repr(transparent)]
4842 #[derive(Copy, Clone, Eq, PartialEq)]
4843 pub struct Vhbpcr(pub u32);
4844 impl Vhbpcr {
4845 #[doc = "Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles."]
4846 #[inline(always)]
4847 pub const fn hbp(&self) -> u16 {
4848 let val = (self.0 >> 0usize) & 0x0fff;
4849 val as u16
4850 }
4851 #[doc = "Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles."]
4852 #[inline(always)]
4853 pub fn set_hbp(&mut self, val: u16) {
4854 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
4855 }
4856 }
4857 impl Default for Vhbpcr {
4858 #[inline(always)]
4859 fn default() -> Vhbpcr {
4860 Vhbpcr(0)
4861 }
4862 }
4863 impl core::fmt::Debug for Vhbpcr {
4864 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4865 f.debug_struct("Vhbpcr").field("hbp", &self.hbp()).finish()
4866 }
4867 }
4868 #[cfg(feature = "defmt")]
4869 impl defmt::Format for Vhbpcr {
4870 fn format(&self, f: defmt::Formatter) {
4871 #[derive(defmt :: Format)]
4872 struct Vhbpcr {
4873 hbp: u16,
4874 }
4875 let proxy = Vhbpcr { hbp: self.hbp() };
4876 defmt::write!(f, "{}", proxy)
4877 }
4878 }
4879 #[doc = "DSI Host video HSA current configuration register."]
4880 #[repr(transparent)]
4881 #[derive(Copy, Clone, Eq, PartialEq)]
4882 pub struct Vhsaccr(pub u32);
4883 impl Vhsaccr {
4884 #[doc = "Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles."]
4885 #[inline(always)]
4886 pub const fn hsa(&self) -> u16 {
4887 let val = (self.0 >> 0usize) & 0x0fff;
4888 val as u16
4889 }
4890 #[doc = "Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles."]
4891 #[inline(always)]
4892 pub fn set_hsa(&mut self, val: u16) {
4893 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
4894 }
4895 }
4896 impl Default for Vhsaccr {
4897 #[inline(always)]
4898 fn default() -> Vhsaccr {
4899 Vhsaccr(0)
4900 }
4901 }
4902 impl core::fmt::Debug for Vhsaccr {
4903 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4904 f.debug_struct("Vhsaccr").field("hsa", &self.hsa()).finish()
4905 }
4906 }
4907 #[cfg(feature = "defmt")]
4908 impl defmt::Format for Vhsaccr {
4909 fn format(&self, f: defmt::Formatter) {
4910 #[derive(defmt :: Format)]
4911 struct Vhsaccr {
4912 hsa: u16,
4913 }
4914 let proxy = Vhsaccr { hsa: self.hsa() };
4915 defmt::write!(f, "{}", proxy)
4916 }
4917 }
4918 #[doc = "DSI Host video HSA configuration register."]
4919 #[repr(transparent)]
4920 #[derive(Copy, Clone, Eq, PartialEq)]
4921 pub struct Vhsacr(pub u32);
4922 impl Vhsacr {
4923 #[doc = "Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles."]
4924 #[inline(always)]
4925 pub const fn hsa(&self) -> u16 {
4926 let val = (self.0 >> 0usize) & 0x0fff;
4927 val as u16
4928 }
4929 #[doc = "Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles."]
4930 #[inline(always)]
4931 pub fn set_hsa(&mut self, val: u16) {
4932 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
4933 }
4934 }
4935 impl Default for Vhsacr {
4936 #[inline(always)]
4937 fn default() -> Vhsacr {
4938 Vhsacr(0)
4939 }
4940 }
4941 impl core::fmt::Debug for Vhsacr {
4942 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4943 f.debug_struct("Vhsacr").field("hsa", &self.hsa()).finish()
4944 }
4945 }
4946 #[cfg(feature = "defmt")]
4947 impl defmt::Format for Vhsacr {
4948 fn format(&self, f: defmt::Formatter) {
4949 #[derive(defmt :: Format)]
4950 struct Vhsacr {
4951 hsa: u16,
4952 }
4953 let proxy = Vhsacr { hsa: self.hsa() };
4954 defmt::write!(f, "{}", proxy)
4955 }
4956 }
4957 #[doc = "DSI Host video line current configuration register."]
4958 #[repr(transparent)]
4959 #[derive(Copy, Clone, Eq, PartialEq)]
4960 pub struct Vlccr(pub u32);
4961 impl Vlccr {
4962 #[doc = "Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles."]
4963 #[inline(always)]
4964 pub const fn hline(&self) -> u16 {
4965 let val = (self.0 >> 0usize) & 0x7fff;
4966 val as u16
4967 }
4968 #[doc = "Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles."]
4969 #[inline(always)]
4970 pub fn set_hline(&mut self, val: u16) {
4971 self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize);
4972 }
4973 }
4974 impl Default for Vlccr {
4975 #[inline(always)]
4976 fn default() -> Vlccr {
4977 Vlccr(0)
4978 }
4979 }
4980 impl core::fmt::Debug for Vlccr {
4981 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4982 f.debug_struct("Vlccr").field("hline", &self.hline()).finish()
4983 }
4984 }
4985 #[cfg(feature = "defmt")]
4986 impl defmt::Format for Vlccr {
4987 fn format(&self, f: defmt::Formatter) {
4988 #[derive(defmt :: Format)]
4989 struct Vlccr {
4990 hline: u16,
4991 }
4992 let proxy = Vlccr { hline: self.hline() };
4993 defmt::write!(f, "{}", proxy)
4994 }
4995 }
4996 #[doc = "DSI Host video line configuration register."]
4997 #[repr(transparent)]
4998 #[derive(Copy, Clone, Eq, PartialEq)]
4999 pub struct Vlcr(pub u32);
5000 impl Vlcr {
5001 #[doc = "Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles."]
5002 #[inline(always)]
5003 pub const fn hline(&self) -> u16 {
5004 let val = (self.0 >> 0usize) & 0x7fff;
5005 val as u16
5006 }
5007 #[doc = "Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles."]
5008 #[inline(always)]
5009 pub fn set_hline(&mut self, val: u16) {
5010 self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize);
5011 }
5012 }
5013 impl Default for Vlcr {
5014 #[inline(always)]
5015 fn default() -> Vlcr {
5016 Vlcr(0)
5017 }
5018 }
5019 impl core::fmt::Debug for Vlcr {
5020 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5021 f.debug_struct("Vlcr").field("hline", &self.hline()).finish()
5022 }
5023 }
5024 #[cfg(feature = "defmt")]
5025 impl defmt::Format for Vlcr {
5026 fn format(&self, f: defmt::Formatter) {
5027 #[derive(defmt :: Format)]
5028 struct Vlcr {
5029 hline: u16,
5030 }
5031 let proxy = Vlcr { hline: self.hline() };
5032 defmt::write!(f, "{}", proxy)
5033 }
5034 }
5035 #[doc = "DSI Host video mode current configuration register."]
5036 #[repr(transparent)]
5037 #[derive(Copy, Clone, Eq, PartialEq)]
5038 pub struct Vmccr(pub u32);
5039 impl Vmccr {
5040 #[doc = "Video mode type This field returns the current video mode transmission type: 1x: Burst mode."]
5041 #[inline(always)]
5042 pub const fn vmt(&self) -> u8 {
5043 let val = (self.0 >> 0usize) & 0x03;
5044 val as u8
5045 }
5046 #[doc = "Video mode type This field returns the current video mode transmission type: 1x: Burst mode."]
5047 #[inline(always)]
5048 pub fn set_vmt(&mut self, val: u8) {
5049 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
5050 }
5051 #[doc = "Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows."]
5052 #[inline(always)]
5053 pub const fn lpvsae(&self) -> bool {
5054 let val = (self.0 >> 2usize) & 0x01;
5055 val != 0
5056 }
5057 #[doc = "Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows."]
5058 #[inline(always)]
5059 pub fn set_lpvsae(&mut self, val: bool) {
5060 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
5061 }
5062 #[doc = "Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows."]
5063 #[inline(always)]
5064 pub const fn lpvbpe(&self) -> bool {
5065 let val = (self.0 >> 3usize) & 0x01;
5066 val != 0
5067 }
5068 #[doc = "Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows."]
5069 #[inline(always)]
5070 pub fn set_lpvbpe(&mut self, val: bool) {
5071 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
5072 }
5073 #[doc = "Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows."]
5074 #[inline(always)]
5075 pub const fn lpvfpe(&self) -> bool {
5076 let val = (self.0 >> 4usize) & 0x01;
5077 val != 0
5078 }
5079 #[doc = "Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows."]
5080 #[inline(always)]
5081 pub fn set_lpvfpe(&mut self, val: bool) {
5082 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
5083 }
5084 #[doc = "Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows."]
5085 #[inline(always)]
5086 pub const fn lpvae(&self) -> bool {
5087 let val = (self.0 >> 5usize) & 0x01;
5088 val != 0
5089 }
5090 #[doc = "Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows."]
5091 #[inline(always)]
5092 pub fn set_lpvae(&mut self, val: bool) {
5093 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
5094 }
5095 #[doc = "Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows."]
5096 #[inline(always)]
5097 pub const fn lphbpe(&self) -> bool {
5098 let val = (self.0 >> 6usize) & 0x01;
5099 val != 0
5100 }
5101 #[doc = "Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows."]
5102 #[inline(always)]
5103 pub fn set_lphbpe(&mut self, val: bool) {
5104 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5105 }
5106 #[doc = "Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows."]
5107 #[inline(always)]
5108 pub const fn lphfe(&self) -> bool {
5109 let val = (self.0 >> 7usize) & 0x01;
5110 val != 0
5111 }
5112 #[doc = "Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows."]
5113 #[inline(always)]
5114 pub fn set_lphfe(&mut self, val: bool) {
5115 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5116 }
5117 #[doc = "Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame."]
5118 #[inline(always)]
5119 pub const fn fbtaae(&self) -> bool {
5120 let val = (self.0 >> 8usize) & 0x01;
5121 val != 0
5122 }
5123 #[doc = "Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame."]
5124 #[inline(always)]
5125 pub fn set_fbtaae(&mut self, val: bool) {
5126 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5127 }
5128 #[doc = "Low-power command enable This bit returns the current command transmission state in low-power mode."]
5129 #[inline(always)]
5130 pub const fn lpce(&self) -> bool {
5131 let val = (self.0 >> 9usize) & 0x01;
5132 val != 0
5133 }
5134 #[doc = "Low-power command enable This bit returns the current command transmission state in low-power mode."]
5135 #[inline(always)]
5136 pub fn set_lpce(&mut self, val: bool) {
5137 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
5138 }
5139 }
5140 impl Default for Vmccr {
5141 #[inline(always)]
5142 fn default() -> Vmccr {
5143 Vmccr(0)
5144 }
5145 }
5146 impl core::fmt::Debug for Vmccr {
5147 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5148 f.debug_struct("Vmccr")
5149 .field("vmt", &self.vmt())
5150 .field("lpvsae", &self.lpvsae())
5151 .field("lpvbpe", &self.lpvbpe())
5152 .field("lpvfpe", &self.lpvfpe())
5153 .field("lpvae", &self.lpvae())
5154 .field("lphbpe", &self.lphbpe())
5155 .field("lphfe", &self.lphfe())
5156 .field("fbtaae", &self.fbtaae())
5157 .field("lpce", &self.lpce())
5158 .finish()
5159 }
5160 }
5161 #[cfg(feature = "defmt")]
5162 impl defmt::Format for Vmccr {
5163 fn format(&self, f: defmt::Formatter) {
5164 #[derive(defmt :: Format)]
5165 struct Vmccr {
5166 vmt: u8,
5167 lpvsae: bool,
5168 lpvbpe: bool,
5169 lpvfpe: bool,
5170 lpvae: bool,
5171 lphbpe: bool,
5172 lphfe: bool,
5173 fbtaae: bool,
5174 lpce: bool,
5175 }
5176 let proxy = Vmccr {
5177 vmt: self.vmt(),
5178 lpvsae: self.lpvsae(),
5179 lpvbpe: self.lpvbpe(),
5180 lpvfpe: self.lpvfpe(),
5181 lpvae: self.lpvae(),
5182 lphbpe: self.lphbpe(),
5183 lphfe: self.lphfe(),
5184 fbtaae: self.fbtaae(),
5185 lpce: self.lpce(),
5186 };
5187 defmt::write!(f, "{}", proxy)
5188 }
5189 }
5190 #[doc = "DSI Host video mode configuration register."]
5191 #[repr(transparent)]
5192 #[derive(Copy, Clone, Eq, PartialEq)]
5193 pub struct Vmcr(pub u32);
5194 impl Vmcr {
5195 #[doc = "Video mode type This field configures the video mode transmission type : 1x: Burst mode."]
5196 #[inline(always)]
5197 pub const fn vmt(&self) -> u8 {
5198 let val = (self.0 >> 0usize) & 0x03;
5199 val as u8
5200 }
5201 #[doc = "Video mode type This field configures the video mode transmission type : 1x: Burst mode."]
5202 #[inline(always)]
5203 pub fn set_vmt(&mut self, val: u8) {
5204 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
5205 }
5206 #[doc = "Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows."]
5207 #[inline(always)]
5208 pub const fn lpvsae(&self) -> bool {
5209 let val = (self.0 >> 8usize) & 0x01;
5210 val != 0
5211 }
5212 #[doc = "Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows."]
5213 #[inline(always)]
5214 pub fn set_lpvsae(&mut self, val: bool) {
5215 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5216 }
5217 #[doc = "Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows."]
5218 #[inline(always)]
5219 pub const fn lpvbpe(&self) -> bool {
5220 let val = (self.0 >> 9usize) & 0x01;
5221 val != 0
5222 }
5223 #[doc = "Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows."]
5224 #[inline(always)]
5225 pub fn set_lpvbpe(&mut self, val: bool) {
5226 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
5227 }
5228 #[doc = "Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows."]
5229 #[inline(always)]
5230 pub const fn lpvfpe(&self) -> bool {
5231 let val = (self.0 >> 10usize) & 0x01;
5232 val != 0
5233 }
5234 #[doc = "Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows."]
5235 #[inline(always)]
5236 pub fn set_lpvfpe(&mut self, val: bool) {
5237 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
5238 }
5239 #[doc = "Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows."]
5240 #[inline(always)]
5241 pub const fn lpvae(&self) -> bool {
5242 let val = (self.0 >> 11usize) & 0x01;
5243 val != 0
5244 }
5245 #[doc = "Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows."]
5246 #[inline(always)]
5247 pub fn set_lpvae(&mut self, val: bool) {
5248 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
5249 }
5250 #[doc = "Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows."]
5251 #[inline(always)]
5252 pub const fn lphbpe(&self) -> bool {
5253 let val = (self.0 >> 12usize) & 0x01;
5254 val != 0
5255 }
5256 #[doc = "Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows."]
5257 #[inline(always)]
5258 pub fn set_lphbpe(&mut self, val: bool) {
5259 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
5260 }
5261 #[doc = "Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows."]
5262 #[inline(always)]
5263 pub const fn lphfpe(&self) -> bool {
5264 let val = (self.0 >> 13usize) & 0x01;
5265 val != 0
5266 }
5267 #[doc = "Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows."]
5268 #[inline(always)]
5269 pub fn set_lphfpe(&mut self, val: bool) {
5270 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
5271 }
5272 #[doc = "Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame."]
5273 #[inline(always)]
5274 pub const fn fbtaae(&self) -> bool {
5275 let val = (self.0 >> 14usize) & 0x01;
5276 val != 0
5277 }
5278 #[doc = "Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame."]
5279 #[inline(always)]
5280 pub fn set_fbtaae(&mut self, val: bool) {
5281 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
5282 }
5283 #[doc = "Low-power command enable This bit enables the command transmission only in low-power mode."]
5284 #[inline(always)]
5285 pub const fn lpce(&self) -> bool {
5286 let val = (self.0 >> 15usize) & 0x01;
5287 val != 0
5288 }
5289 #[doc = "Low-power command enable This bit enables the command transmission only in low-power mode."]
5290 #[inline(always)]
5291 pub fn set_lpce(&mut self, val: bool) {
5292 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
5293 }
5294 #[doc = "Pattern generator enable This bit enables the video mode pattern generator."]
5295 #[inline(always)]
5296 pub const fn pge(&self) -> bool {
5297 let val = (self.0 >> 16usize) & 0x01;
5298 val != 0
5299 }
5300 #[doc = "Pattern generator enable This bit enables the video mode pattern generator."]
5301 #[inline(always)]
5302 pub fn set_pge(&mut self, val: bool) {
5303 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
5304 }
5305 #[doc = "Pattern generator mode This bit configures the pattern generator mode."]
5306 #[inline(always)]
5307 pub const fn pgm(&self) -> bool {
5308 let val = (self.0 >> 20usize) & 0x01;
5309 val != 0
5310 }
5311 #[doc = "Pattern generator mode This bit configures the pattern generator mode."]
5312 #[inline(always)]
5313 pub fn set_pgm(&mut self, val: bool) {
5314 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
5315 }
5316 #[doc = "Pattern generator orientation This bit configures the color bar orientation."]
5317 #[inline(always)]
5318 pub const fn pgo(&self) -> bool {
5319 let val = (self.0 >> 24usize) & 0x01;
5320 val != 0
5321 }
5322 #[doc = "Pattern generator orientation This bit configures the color bar orientation."]
5323 #[inline(always)]
5324 pub fn set_pgo(&mut self, val: bool) {
5325 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
5326 }
5327 }
5328 impl Default for Vmcr {
5329 #[inline(always)]
5330 fn default() -> Vmcr {
5331 Vmcr(0)
5332 }
5333 }
5334 impl core::fmt::Debug for Vmcr {
5335 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5336 f.debug_struct("Vmcr")
5337 .field("vmt", &self.vmt())
5338 .field("lpvsae", &self.lpvsae())
5339 .field("lpvbpe", &self.lpvbpe())
5340 .field("lpvfpe", &self.lpvfpe())
5341 .field("lpvae", &self.lpvae())
5342 .field("lphbpe", &self.lphbpe())
5343 .field("lphfpe", &self.lphfpe())
5344 .field("fbtaae", &self.fbtaae())
5345 .field("lpce", &self.lpce())
5346 .field("pge", &self.pge())
5347 .field("pgm", &self.pgm())
5348 .field("pgo", &self.pgo())
5349 .finish()
5350 }
5351 }
5352 #[cfg(feature = "defmt")]
5353 impl defmt::Format for Vmcr {
5354 fn format(&self, f: defmt::Formatter) {
5355 #[derive(defmt :: Format)]
5356 struct Vmcr {
5357 vmt: u8,
5358 lpvsae: bool,
5359 lpvbpe: bool,
5360 lpvfpe: bool,
5361 lpvae: bool,
5362 lphbpe: bool,
5363 lphfpe: bool,
5364 fbtaae: bool,
5365 lpce: bool,
5366 pge: bool,
5367 pgm: bool,
5368 pgo: bool,
5369 }
5370 let proxy = Vmcr {
5371 vmt: self.vmt(),
5372 lpvsae: self.lpvsae(),
5373 lpvbpe: self.lpvbpe(),
5374 lpvfpe: self.lpvfpe(),
5375 lpvae: self.lpvae(),
5376 lphbpe: self.lphbpe(),
5377 lphfpe: self.lphfpe(),
5378 fbtaae: self.fbtaae(),
5379 lpce: self.lpce(),
5380 pge: self.pge(),
5381 pgm: self.pgm(),
5382 pgo: self.pgo(),
5383 };
5384 defmt::write!(f, "{}", proxy)
5385 }
5386 }
5387 #[doc = "DSI Host video null packet current configuration register."]
5388 #[repr(transparent)]
5389 #[derive(Copy, Clone, Eq, PartialEq)]
5390 pub struct Vnpccr(pub u32);
5391 impl Vnpccr {
5392 #[doc = "Null packet size This field returns the number of bytes inside a null packet."]
5393 #[inline(always)]
5394 pub const fn npsize(&self) -> u16 {
5395 let val = (self.0 >> 0usize) & 0x1fff;
5396 val as u16
5397 }
5398 #[doc = "Null packet size This field returns the number of bytes inside a null packet."]
5399 #[inline(always)]
5400 pub fn set_npsize(&mut self, val: u16) {
5401 self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize);
5402 }
5403 }
5404 impl Default for Vnpccr {
5405 #[inline(always)]
5406 fn default() -> Vnpccr {
5407 Vnpccr(0)
5408 }
5409 }
5410 impl core::fmt::Debug for Vnpccr {
5411 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5412 f.debug_struct("Vnpccr").field("npsize", &self.npsize()).finish()
5413 }
5414 }
5415 #[cfg(feature = "defmt")]
5416 impl defmt::Format for Vnpccr {
5417 fn format(&self, f: defmt::Formatter) {
5418 #[derive(defmt :: Format)]
5419 struct Vnpccr {
5420 npsize: u16,
5421 }
5422 let proxy = Vnpccr { npsize: self.npsize() };
5423 defmt::write!(f, "{}", proxy)
5424 }
5425 }
5426 #[doc = "DSI Host video null packet configuration register."]
5427 #[repr(transparent)]
5428 #[derive(Copy, Clone, Eq, PartialEq)]
5429 pub struct Vnpcr(pub u32);
5430 impl Vnpcr {
5431 #[doc = "Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets."]
5432 #[inline(always)]
5433 pub const fn npsize(&self) -> u16 {
5434 let val = (self.0 >> 0usize) & 0x1fff;
5435 val as u16
5436 }
5437 #[doc = "Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets."]
5438 #[inline(always)]
5439 pub fn set_npsize(&mut self, val: u16) {
5440 self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize);
5441 }
5442 }
5443 impl Default for Vnpcr {
5444 #[inline(always)]
5445 fn default() -> Vnpcr {
5446 Vnpcr(0)
5447 }
5448 }
5449 impl core::fmt::Debug for Vnpcr {
5450 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5451 f.debug_struct("Vnpcr").field("npsize", &self.npsize()).finish()
5452 }
5453 }
5454 #[cfg(feature = "defmt")]
5455 impl defmt::Format for Vnpcr {
5456 fn format(&self, f: defmt::Formatter) {
5457 #[derive(defmt :: Format)]
5458 struct Vnpcr {
5459 npsize: u16,
5460 }
5461 let proxy = Vnpcr { npsize: self.npsize() };
5462 defmt::write!(f, "{}", proxy)
5463 }
5464 }
5465 #[doc = "DSI Host video packet current configuration register."]
5466 #[repr(transparent)]
5467 #[derive(Copy, Clone, Eq, PartialEq)]
5468 pub struct Vpccr(pub u32);
5469 impl Vpccr {
5470 #[doc = "Video packet size This field returns the number of pixels in a single video packet."]
5471 #[inline(always)]
5472 pub const fn vpsize(&self) -> u16 {
5473 let val = (self.0 >> 0usize) & 0x3fff;
5474 val as u16
5475 }
5476 #[doc = "Video packet size This field returns the number of pixels in a single video packet."]
5477 #[inline(always)]
5478 pub fn set_vpsize(&mut self, val: u16) {
5479 self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
5480 }
5481 }
5482 impl Default for Vpccr {
5483 #[inline(always)]
5484 fn default() -> Vpccr {
5485 Vpccr(0)
5486 }
5487 }
5488 impl core::fmt::Debug for Vpccr {
5489 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5490 f.debug_struct("Vpccr").field("vpsize", &self.vpsize()).finish()
5491 }
5492 }
5493 #[cfg(feature = "defmt")]
5494 impl defmt::Format for Vpccr {
5495 fn format(&self, f: defmt::Formatter) {
5496 #[derive(defmt :: Format)]
5497 struct Vpccr {
5498 vpsize: u16,
5499 }
5500 let proxy = Vpccr { vpsize: self.vpsize() };
5501 defmt::write!(f, "{}", proxy)
5502 }
5503 }
5504 #[doc = "DSI Host video packet configuration register."]
5505 #[repr(transparent)]
5506 #[derive(Copy, Clone, Eq, PartialEq)]
5507 pub struct Vpcr(pub u32);
5508 impl Vpcr {
5509 #[doc = "Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification."]
5510 #[inline(always)]
5511 pub const fn vpsize(&self) -> u16 {
5512 let val = (self.0 >> 0usize) & 0x3fff;
5513 val as u16
5514 }
5515 #[doc = "Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification."]
5516 #[inline(always)]
5517 pub fn set_vpsize(&mut self, val: u16) {
5518 self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
5519 }
5520 }
5521 impl Default for Vpcr {
5522 #[inline(always)]
5523 fn default() -> Vpcr {
5524 Vpcr(0)
5525 }
5526 }
5527 impl core::fmt::Debug for Vpcr {
5528 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5529 f.debug_struct("Vpcr").field("vpsize", &self.vpsize()).finish()
5530 }
5531 }
5532 #[cfg(feature = "defmt")]
5533 impl defmt::Format for Vpcr {
5534 fn format(&self, f: defmt::Formatter) {
5535 #[derive(defmt :: Format)]
5536 struct Vpcr {
5537 vpsize: u16,
5538 }
5539 let proxy = Vpcr { vpsize: self.vpsize() };
5540 defmt::write!(f, "{}", proxy)
5541 }
5542 }
5543 #[doc = "DSI Host version register."]
5544 #[repr(transparent)]
5545 #[derive(Copy, Clone, Eq, PartialEq)]
5546 pub struct Vr(pub u32);
5547 impl Vr {
5548 #[doc = "Version of the DSI Host This read-only register contains the version of the DSI Host."]
5549 #[inline(always)]
5550 pub const fn version(&self) -> u32 {
5551 let val = (self.0 >> 0usize) & 0xffff_ffff;
5552 val as u32
5553 }
5554 #[doc = "Version of the DSI Host This read-only register contains the version of the DSI Host."]
5555 #[inline(always)]
5556 pub fn set_version(&mut self, val: u32) {
5557 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
5558 }
5559 }
5560 impl Default for Vr {
5561 #[inline(always)]
5562 fn default() -> Vr {
5563 Vr(0)
5564 }
5565 }
5566 impl core::fmt::Debug for Vr {
5567 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5568 f.debug_struct("Vr").field("version", &self.version()).finish()
5569 }
5570 }
5571 #[cfg(feature = "defmt")]
5572 impl defmt::Format for Vr {
5573 fn format(&self, f: defmt::Formatter) {
5574 #[derive(defmt :: Format)]
5575 struct Vr {
5576 version: u32,
5577 }
5578 let proxy = Vr {
5579 version: self.version(),
5580 };
5581 defmt::write!(f, "{}", proxy)
5582 }
5583 }
5584 #[doc = "DSI Host video shadow control register."]
5585 #[repr(transparent)]
5586 #[derive(Copy, Clone, Eq, PartialEq)]
5587 pub struct Vscr(pub u32);
5588 impl Vscr {
5589 #[doc = "Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated."]
5590 #[inline(always)]
5591 pub const fn en(&self) -> bool {
5592 let val = (self.0 >> 0usize) & 0x01;
5593 val != 0
5594 }
5595 #[doc = "Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated."]
5596 #[inline(always)]
5597 pub fn set_en(&mut self, val: bool) {
5598 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5599 }
5600 #[doc = "Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared."]
5601 #[inline(always)]
5602 pub const fn ur(&self) -> bool {
5603 let val = (self.0 >> 8usize) & 0x01;
5604 val != 0
5605 }
5606 #[doc = "Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared."]
5607 #[inline(always)]
5608 pub fn set_ur(&mut self, val: bool) {
5609 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5610 }
5611 }
5612 impl Default for Vscr {
5613 #[inline(always)]
5614 fn default() -> Vscr {
5615 Vscr(0)
5616 }
5617 }
5618 impl core::fmt::Debug for Vscr {
5619 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5620 f.debug_struct("Vscr")
5621 .field("en", &self.en())
5622 .field("ur", &self.ur())
5623 .finish()
5624 }
5625 }
5626 #[cfg(feature = "defmt")]
5627 impl defmt::Format for Vscr {
5628 fn format(&self, f: defmt::Formatter) {
5629 #[derive(defmt :: Format)]
5630 struct Vscr {
5631 en: bool,
5632 ur: bool,
5633 }
5634 let proxy = Vscr {
5635 en: self.en(),
5636 ur: self.ur(),
5637 };
5638 defmt::write!(f, "{}", proxy)
5639 }
5640 }
5641 #[doc = "DSI Host video VA current configuration register."]
5642 #[repr(transparent)]
5643 #[derive(Copy, Clone, Eq, PartialEq)]
5644 pub struct Vvaccr(pub u32);
5645 impl Vvaccr {
5646 #[doc = "Vertical active duration This field returns the current vertical active period measured in number of horizontal lines."]
5647 #[inline(always)]
5648 pub const fn va(&self) -> u16 {
5649 let val = (self.0 >> 0usize) & 0x3fff;
5650 val as u16
5651 }
5652 #[doc = "Vertical active duration This field returns the current vertical active period measured in number of horizontal lines."]
5653 #[inline(always)]
5654 pub fn set_va(&mut self, val: u16) {
5655 self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
5656 }
5657 }
5658 impl Default for Vvaccr {
5659 #[inline(always)]
5660 fn default() -> Vvaccr {
5661 Vvaccr(0)
5662 }
5663 }
5664 impl core::fmt::Debug for Vvaccr {
5665 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5666 f.debug_struct("Vvaccr").field("va", &self.va()).finish()
5667 }
5668 }
5669 #[cfg(feature = "defmt")]
5670 impl defmt::Format for Vvaccr {
5671 fn format(&self, f: defmt::Formatter) {
5672 #[derive(defmt :: Format)]
5673 struct Vvaccr {
5674 va: u16,
5675 }
5676 let proxy = Vvaccr { va: self.va() };
5677 defmt::write!(f, "{}", proxy)
5678 }
5679 }
5680 #[doc = "DSI Host video VA configuration register."]
5681 #[repr(transparent)]
5682 #[derive(Copy, Clone, Eq, PartialEq)]
5683 pub struct Vvacr(pub u32);
5684 impl Vvacr {
5685 #[doc = "Vertical active duration This fields configures the vertical active period measured in number of horizontal lines."]
5686 #[inline(always)]
5687 pub const fn va(&self) -> u16 {
5688 let val = (self.0 >> 0usize) & 0x3fff;
5689 val as u16
5690 }
5691 #[doc = "Vertical active duration This fields configures the vertical active period measured in number of horizontal lines."]
5692 #[inline(always)]
5693 pub fn set_va(&mut self, val: u16) {
5694 self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize);
5695 }
5696 }
5697 impl Default for Vvacr {
5698 #[inline(always)]
5699 fn default() -> Vvacr {
5700 Vvacr(0)
5701 }
5702 }
5703 impl core::fmt::Debug for Vvacr {
5704 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5705 f.debug_struct("Vvacr").field("va", &self.va()).finish()
5706 }
5707 }
5708 #[cfg(feature = "defmt")]
5709 impl defmt::Format for Vvacr {
5710 fn format(&self, f: defmt::Formatter) {
5711 #[derive(defmt :: Format)]
5712 struct Vvacr {
5713 va: u16,
5714 }
5715 let proxy = Vvacr { va: self.va() };
5716 defmt::write!(f, "{}", proxy)
5717 }
5718 }
5719 #[doc = "DSI Host video VBP current configuration register."]
5720 #[repr(transparent)]
5721 #[derive(Copy, Clone, Eq, PartialEq)]
5722 pub struct Vvbpccr(pub u32);
5723 impl Vvbpccr {
5724 #[doc = "Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines."]
5725 #[inline(always)]
5726 pub const fn vbp(&self) -> u16 {
5727 let val = (self.0 >> 0usize) & 0x03ff;
5728 val as u16
5729 }
5730 #[doc = "Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines."]
5731 #[inline(always)]
5732 pub fn set_vbp(&mut self, val: u16) {
5733 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
5734 }
5735 }
5736 impl Default for Vvbpccr {
5737 #[inline(always)]
5738 fn default() -> Vvbpccr {
5739 Vvbpccr(0)
5740 }
5741 }
5742 impl core::fmt::Debug for Vvbpccr {
5743 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5744 f.debug_struct("Vvbpccr").field("vbp", &self.vbp()).finish()
5745 }
5746 }
5747 #[cfg(feature = "defmt")]
5748 impl defmt::Format for Vvbpccr {
5749 fn format(&self, f: defmt::Formatter) {
5750 #[derive(defmt :: Format)]
5751 struct Vvbpccr {
5752 vbp: u16,
5753 }
5754 let proxy = Vvbpccr { vbp: self.vbp() };
5755 defmt::write!(f, "{}", proxy)
5756 }
5757 }
5758 #[doc = "DSI Host video VBP configuration register."]
5759 #[repr(transparent)]
5760 #[derive(Copy, Clone, Eq, PartialEq)]
5761 pub struct Vvbpcr(pub u32);
5762 impl Vvbpcr {
5763 #[doc = "Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines."]
5764 #[inline(always)]
5765 pub const fn vbp(&self) -> u16 {
5766 let val = (self.0 >> 0usize) & 0x03ff;
5767 val as u16
5768 }
5769 #[doc = "Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines."]
5770 #[inline(always)]
5771 pub fn set_vbp(&mut self, val: u16) {
5772 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
5773 }
5774 }
5775 impl Default for Vvbpcr {
5776 #[inline(always)]
5777 fn default() -> Vvbpcr {
5778 Vvbpcr(0)
5779 }
5780 }
5781 impl core::fmt::Debug for Vvbpcr {
5782 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5783 f.debug_struct("Vvbpcr").field("vbp", &self.vbp()).finish()
5784 }
5785 }
5786 #[cfg(feature = "defmt")]
5787 impl defmt::Format for Vvbpcr {
5788 fn format(&self, f: defmt::Formatter) {
5789 #[derive(defmt :: Format)]
5790 struct Vvbpcr {
5791 vbp: u16,
5792 }
5793 let proxy = Vvbpcr { vbp: self.vbp() };
5794 defmt::write!(f, "{}", proxy)
5795 }
5796 }
5797 #[doc = "DSI Host video VFP current configuration register."]
5798 #[repr(transparent)]
5799 #[derive(Copy, Clone, Eq, PartialEq)]
5800 pub struct Vvfpccr(pub u32);
5801 impl Vvfpccr {
5802 #[doc = "Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines."]
5803 #[inline(always)]
5804 pub const fn vfp(&self) -> u16 {
5805 let val = (self.0 >> 0usize) & 0x03ff;
5806 val as u16
5807 }
5808 #[doc = "Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines."]
5809 #[inline(always)]
5810 pub fn set_vfp(&mut self, val: u16) {
5811 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
5812 }
5813 }
5814 impl Default for Vvfpccr {
5815 #[inline(always)]
5816 fn default() -> Vvfpccr {
5817 Vvfpccr(0)
5818 }
5819 }
5820 impl core::fmt::Debug for Vvfpccr {
5821 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5822 f.debug_struct("Vvfpccr").field("vfp", &self.vfp()).finish()
5823 }
5824 }
5825 #[cfg(feature = "defmt")]
5826 impl defmt::Format for Vvfpccr {
5827 fn format(&self, f: defmt::Formatter) {
5828 #[derive(defmt :: Format)]
5829 struct Vvfpccr {
5830 vfp: u16,
5831 }
5832 let proxy = Vvfpccr { vfp: self.vfp() };
5833 defmt::write!(f, "{}", proxy)
5834 }
5835 }
5836 #[doc = "DSI Host video VFP configuration register."]
5837 #[repr(transparent)]
5838 #[derive(Copy, Clone, Eq, PartialEq)]
5839 pub struct Vvfpcr(pub u32);
5840 impl Vvfpcr {
5841 #[doc = "Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines."]
5842 #[inline(always)]
5843 pub const fn vfp(&self) -> u16 {
5844 let val = (self.0 >> 0usize) & 0x03ff;
5845 val as u16
5846 }
5847 #[doc = "Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines."]
5848 #[inline(always)]
5849 pub fn set_vfp(&mut self, val: u16) {
5850 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
5851 }
5852 }
5853 impl Default for Vvfpcr {
5854 #[inline(always)]
5855 fn default() -> Vvfpcr {
5856 Vvfpcr(0)
5857 }
5858 }
5859 impl core::fmt::Debug for Vvfpcr {
5860 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5861 f.debug_struct("Vvfpcr").field("vfp", &self.vfp()).finish()
5862 }
5863 }
5864 #[cfg(feature = "defmt")]
5865 impl defmt::Format for Vvfpcr {
5866 fn format(&self, f: defmt::Formatter) {
5867 #[derive(defmt :: Format)]
5868 struct Vvfpcr {
5869 vfp: u16,
5870 }
5871 let proxy = Vvfpcr { vfp: self.vfp() };
5872 defmt::write!(f, "{}", proxy)
5873 }
5874 }
5875 #[doc = "DSI Host video VSA current configuration register."]
5876 #[repr(transparent)]
5877 #[derive(Copy, Clone, Eq, PartialEq)]
5878 pub struct Vvsaccr(pub u32);
5879 impl Vvsaccr {
5880 #[doc = "Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines."]
5881 #[inline(always)]
5882 pub const fn vsa(&self) -> u16 {
5883 let val = (self.0 >> 0usize) & 0x03ff;
5884 val as u16
5885 }
5886 #[doc = "Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines."]
5887 #[inline(always)]
5888 pub fn set_vsa(&mut self, val: u16) {
5889 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
5890 }
5891 }
5892 impl Default for Vvsaccr {
5893 #[inline(always)]
5894 fn default() -> Vvsaccr {
5895 Vvsaccr(0)
5896 }
5897 }
5898 impl core::fmt::Debug for Vvsaccr {
5899 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5900 f.debug_struct("Vvsaccr").field("vsa", &self.vsa()).finish()
5901 }
5902 }
5903 #[cfg(feature = "defmt")]
5904 impl defmt::Format for Vvsaccr {
5905 fn format(&self, f: defmt::Formatter) {
5906 #[derive(defmt :: Format)]
5907 struct Vvsaccr {
5908 vsa: u16,
5909 }
5910 let proxy = Vvsaccr { vsa: self.vsa() };
5911 defmt::write!(f, "{}", proxy)
5912 }
5913 }
5914 #[doc = "DSI Host video VSA configuration register."]
5915 #[repr(transparent)]
5916 #[derive(Copy, Clone, Eq, PartialEq)]
5917 pub struct Vvsacr(pub u32);
5918 impl Vvsacr {
5919 #[doc = "Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines."]
5920 #[inline(always)]
5921 pub const fn vsa(&self) -> u16 {
5922 let val = (self.0 >> 0usize) & 0x03ff;
5923 val as u16
5924 }
5925 #[doc = "Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines."]
5926 #[inline(always)]
5927 pub fn set_vsa(&mut self, val: u16) {
5928 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
5929 }
5930 }
5931 impl Default for Vvsacr {
5932 #[inline(always)]
5933 fn default() -> Vvsacr {
5934 Vvsacr(0)
5935 }
5936 }
5937 impl core::fmt::Debug for Vvsacr {
5938 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5939 f.debug_struct("Vvsacr").field("vsa", &self.vsa()).finish()
5940 }
5941 }
5942 #[cfg(feature = "defmt")]
5943 impl defmt::Format for Vvsacr {
5944 fn format(&self, f: defmt::Formatter) {
5945 #[derive(defmt :: Format)]
5946 struct Vvsacr {
5947 vsa: u16,
5948 }
5949 let proxy = Vvsacr { vsa: self.vsa() };
5950 defmt::write!(f, "{}", proxy)
5951 }
5952 }
5953 #[doc = "DSI Wrapper configuration register."]
5954 #[repr(transparent)]
5955 #[derive(Copy, Clone, Eq, PartialEq)]
5956 pub struct Wcfgr(pub u32);
5957 impl Wcfgr {
5958 #[doc = "DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
5959 #[inline(always)]
5960 pub const fn dsim(&self) -> bool {
5961 let val = (self.0 >> 0usize) & 0x01;
5962 val != 0
5963 }
5964 #[doc = "DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
5965 #[inline(always)]
5966 pub fn set_dsim(&mut self, val: bool) {
5967 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5968 }
5969 #[doc = "Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.ENÂ =Â 0)."]
5970 #[inline(always)]
5971 pub const fn colmux(&self) -> u8 {
5972 let val = (self.0 >> 1usize) & 0x07;
5973 val as u8
5974 }
5975 #[doc = "Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.ENÂ =Â 0)."]
5976 #[inline(always)]
5977 pub fn set_colmux(&mut self, val: u8) {
5978 self.0 = (self.0 & !(0x07 << 1usize)) | (((val as u32) & 0x07) << 1usize);
5979 }
5980 #[doc = "TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
5981 #[inline(always)]
5982 pub const fn tesrc(&self) -> bool {
5983 let val = (self.0 >> 4usize) & 0x01;
5984 val != 0
5985 }
5986 #[doc = "TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
5987 #[inline(always)]
5988 pub fn set_tesrc(&mut self, val: bool) {
5989 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
5990 }
5991 #[doc = "TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
5992 #[inline(always)]
5993 pub const fn tepol(&self) -> bool {
5994 let val = (self.0 >> 5usize) & 0x01;
5995 val != 0
5996 }
5997 #[doc = "TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
5998 #[inline(always)]
5999 pub fn set_tepol(&mut self, val: bool) {
6000 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6001 }
6002 #[doc = "Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
6003 #[inline(always)]
6004 pub const fn ar(&self) -> bool {
6005 let val = (self.0 >> 6usize) & 0x01;
6006 val != 0
6007 }
6008 #[doc = "Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0)."]
6009 #[inline(always)]
6010 pub fn set_ar(&mut self, val: bool) {
6011 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
6012 }
6013 #[doc = "VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.ENÂ =Â 0)."]
6014 #[inline(always)]
6015 pub const fn vspol(&self) -> bool {
6016 let val = (self.0 >> 7usize) & 0x01;
6017 val != 0
6018 }
6019 #[doc = "VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.ENÂ =Â 0)."]
6020 #[inline(always)]
6021 pub fn set_vspol(&mut self, val: bool) {
6022 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
6023 }
6024 }
6025 impl Default for Wcfgr {
6026 #[inline(always)]
6027 fn default() -> Wcfgr {
6028 Wcfgr(0)
6029 }
6030 }
6031 impl core::fmt::Debug for Wcfgr {
6032 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6033 f.debug_struct("Wcfgr")
6034 .field("dsim", &self.dsim())
6035 .field("colmux", &self.colmux())
6036 .field("tesrc", &self.tesrc())
6037 .field("tepol", &self.tepol())
6038 .field("ar", &self.ar())
6039 .field("vspol", &self.vspol())
6040 .finish()
6041 }
6042 }
6043 #[cfg(feature = "defmt")]
6044 impl defmt::Format for Wcfgr {
6045 fn format(&self, f: defmt::Formatter) {
6046 #[derive(defmt :: Format)]
6047 struct Wcfgr {
6048 dsim: bool,
6049 colmux: u8,
6050 tesrc: bool,
6051 tepol: bool,
6052 ar: bool,
6053 vspol: bool,
6054 }
6055 let proxy = Wcfgr {
6056 dsim: self.dsim(),
6057 colmux: self.colmux(),
6058 tesrc: self.tesrc(),
6059 tepol: self.tepol(),
6060 ar: self.ar(),
6061 vspol: self.vspol(),
6062 };
6063 defmt::write!(f, "{}", proxy)
6064 }
6065 }
6066 #[doc = "DSI Wrapper control register."]
6067 #[repr(transparent)]
6068 #[derive(Copy, Clone, Eq, PartialEq)]
6069 pub struct Wcr(pub u32);
6070 impl Wcr {
6071 #[doc = "Color mode This bit controls the display color mode in video mode."]
6072 #[inline(always)]
6073 pub const fn colm(&self) -> bool {
6074 let val = (self.0 >> 0usize) & 0x01;
6075 val != 0
6076 }
6077 #[doc = "Color mode This bit controls the display color mode in video mode."]
6078 #[inline(always)]
6079 pub fn set_colm(&mut self, val: bool) {
6080 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6081 }
6082 #[doc = "Shutdown This bit controls the display shutdown in video mode."]
6083 #[inline(always)]
6084 pub const fn shtdn(&self) -> bool {
6085 let val = (self.0 >> 1usize) & 0x01;
6086 val != 0
6087 }
6088 #[doc = "Shutdown This bit controls the display shutdown in video mode."]
6089 #[inline(always)]
6090 pub fn set_shtdn(&mut self, val: bool) {
6091 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6092 }
6093 #[doc = "LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode."]
6094 #[inline(always)]
6095 pub const fn ltdcen(&self) -> bool {
6096 let val = (self.0 >> 2usize) & 0x01;
6097 val != 0
6098 }
6099 #[doc = "LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode."]
6100 #[inline(always)]
6101 pub fn set_ltdcen(&mut self, val: bool) {
6102 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
6103 }
6104 #[doc = "DSI enable This bit enables the DSI Wrapper."]
6105 #[inline(always)]
6106 pub const fn dsien(&self) -> bool {
6107 let val = (self.0 >> 3usize) & 0x01;
6108 val != 0
6109 }
6110 #[doc = "DSI enable This bit enables the DSI Wrapper."]
6111 #[inline(always)]
6112 pub fn set_dsien(&mut self, val: bool) {
6113 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
6114 }
6115 }
6116 impl Default for Wcr {
6117 #[inline(always)]
6118 fn default() -> Wcr {
6119 Wcr(0)
6120 }
6121 }
6122 impl core::fmt::Debug for Wcr {
6123 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6124 f.debug_struct("Wcr")
6125 .field("colm", &self.colm())
6126 .field("shtdn", &self.shtdn())
6127 .field("ltdcen", &self.ltdcen())
6128 .field("dsien", &self.dsien())
6129 .finish()
6130 }
6131 }
6132 #[cfg(feature = "defmt")]
6133 impl defmt::Format for Wcr {
6134 fn format(&self, f: defmt::Formatter) {
6135 #[derive(defmt :: Format)]
6136 struct Wcr {
6137 colm: bool,
6138 shtdn: bool,
6139 ltdcen: bool,
6140 dsien: bool,
6141 }
6142 let proxy = Wcr {
6143 colm: self.colm(),
6144 shtdn: self.shtdn(),
6145 ltdcen: self.ltdcen(),
6146 dsien: self.dsien(),
6147 };
6148 defmt::write!(f, "{}", proxy)
6149 }
6150 }
6151 #[doc = "DSI Wrapper interrupt enable register."]
6152 #[repr(transparent)]
6153 #[derive(Copy, Clone, Eq, PartialEq)]
6154 pub struct Wier(pub u32);
6155 impl Wier {
6156 #[doc = "Tearing effect interrupt enable This bit enables the tearing effect interrupt."]
6157 #[inline(always)]
6158 pub const fn teie(&self) -> bool {
6159 let val = (self.0 >> 0usize) & 0x01;
6160 val != 0
6161 }
6162 #[doc = "Tearing effect interrupt enable This bit enables the tearing effect interrupt."]
6163 #[inline(always)]
6164 pub fn set_teie(&mut self, val: bool) {
6165 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6166 }
6167 #[doc = "End of refresh interrupt enable This bit enables the end of refresh interrupt."]
6168 #[inline(always)]
6169 pub const fn erie(&self) -> bool {
6170 let val = (self.0 >> 1usize) & 0x01;
6171 val != 0
6172 }
6173 #[doc = "End of refresh interrupt enable This bit enables the end of refresh interrupt."]
6174 #[inline(always)]
6175 pub fn set_erie(&mut self, val: bool) {
6176 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6177 }
6178 #[doc = "PLL lock interrupt enable This bit enables the PLL lock interrupt."]
6179 #[inline(always)]
6180 pub const fn plllie(&self) -> bool {
6181 let val = (self.0 >> 9usize) & 0x01;
6182 val != 0
6183 }
6184 #[doc = "PLL lock interrupt enable This bit enables the PLL lock interrupt."]
6185 #[inline(always)]
6186 pub fn set_plllie(&mut self, val: bool) {
6187 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
6188 }
6189 #[doc = "PLL unlock interrupt enable This bit enables the PLL unlock interrupt."]
6190 #[inline(always)]
6191 pub const fn plluie(&self) -> bool {
6192 let val = (self.0 >> 10usize) & 0x01;
6193 val != 0
6194 }
6195 #[doc = "PLL unlock interrupt enable This bit enables the PLL unlock interrupt."]
6196 #[inline(always)]
6197 pub fn set_plluie(&mut self, val: bool) {
6198 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
6199 }
6200 }
6201 impl Default for Wier {
6202 #[inline(always)]
6203 fn default() -> Wier {
6204 Wier(0)
6205 }
6206 }
6207 impl core::fmt::Debug for Wier {
6208 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6209 f.debug_struct("Wier")
6210 .field("teie", &self.teie())
6211 .field("erie", &self.erie())
6212 .field("plllie", &self.plllie())
6213 .field("plluie", &self.plluie())
6214 .finish()
6215 }
6216 }
6217 #[cfg(feature = "defmt")]
6218 impl defmt::Format for Wier {
6219 fn format(&self, f: defmt::Formatter) {
6220 #[derive(defmt :: Format)]
6221 struct Wier {
6222 teie: bool,
6223 erie: bool,
6224 plllie: bool,
6225 plluie: bool,
6226 }
6227 let proxy = Wier {
6228 teie: self.teie(),
6229 erie: self.erie(),
6230 plllie: self.plllie(),
6231 plluie: self.plluie(),
6232 };
6233 defmt::write!(f, "{}", proxy)
6234 }
6235 }
6236 #[doc = "DSI Wrapper interrupt flag clear register."]
6237 #[repr(transparent)]
6238 #[derive(Copy, Clone, Eq, PartialEq)]
6239 pub struct Wifcr(pub u32);
6240 impl Wifcr {
6241 #[doc = "Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register."]
6242 #[inline(always)]
6243 pub const fn cteif(&self) -> bool {
6244 let val = (self.0 >> 0usize) & 0x01;
6245 val != 0
6246 }
6247 #[doc = "Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register."]
6248 #[inline(always)]
6249 pub fn set_cteif(&mut self, val: bool) {
6250 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6251 }
6252 #[doc = "Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register."]
6253 #[inline(always)]
6254 pub const fn cerif(&self) -> bool {
6255 let val = (self.0 >> 1usize) & 0x01;
6256 val != 0
6257 }
6258 #[doc = "Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register."]
6259 #[inline(always)]
6260 pub fn set_cerif(&mut self, val: bool) {
6261 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6262 }
6263 #[doc = "Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register."]
6264 #[inline(always)]
6265 pub const fn cplllif(&self) -> bool {
6266 let val = (self.0 >> 9usize) & 0x01;
6267 val != 0
6268 }
6269 #[doc = "Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register."]
6270 #[inline(always)]
6271 pub fn set_cplllif(&mut self, val: bool) {
6272 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
6273 }
6274 #[doc = "Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register."]
6275 #[inline(always)]
6276 pub const fn cplluif(&self) -> bool {
6277 let val = (self.0 >> 10usize) & 0x01;
6278 val != 0
6279 }
6280 #[doc = "Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register."]
6281 #[inline(always)]
6282 pub fn set_cplluif(&mut self, val: bool) {
6283 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
6284 }
6285 }
6286 impl Default for Wifcr {
6287 #[inline(always)]
6288 fn default() -> Wifcr {
6289 Wifcr(0)
6290 }
6291 }
6292 impl core::fmt::Debug for Wifcr {
6293 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6294 f.debug_struct("Wifcr")
6295 .field("cteif", &self.cteif())
6296 .field("cerif", &self.cerif())
6297 .field("cplllif", &self.cplllif())
6298 .field("cplluif", &self.cplluif())
6299 .finish()
6300 }
6301 }
6302 #[cfg(feature = "defmt")]
6303 impl defmt::Format for Wifcr {
6304 fn format(&self, f: defmt::Formatter) {
6305 #[derive(defmt :: Format)]
6306 struct Wifcr {
6307 cteif: bool,
6308 cerif: bool,
6309 cplllif: bool,
6310 cplluif: bool,
6311 }
6312 let proxy = Wifcr {
6313 cteif: self.cteif(),
6314 cerif: self.cerif(),
6315 cplllif: self.cplllif(),
6316 cplluif: self.cplluif(),
6317 };
6318 defmt::write!(f, "{}", proxy)
6319 }
6320 }
6321 #[doc = "DSI Wrapper interrupt and status register."]
6322 #[repr(transparent)]
6323 #[derive(Copy, Clone, Eq, PartialEq)]
6324 pub struct Wisr(pub u32);
6325 impl Wisr {
6326 #[doc = "Tearing effect interrupt flag This bit is set when a tearing effect event occurs."]
6327 #[inline(always)]
6328 pub const fn teif(&self) -> bool {
6329 let val = (self.0 >> 0usize) & 0x01;
6330 val != 0
6331 }
6332 #[doc = "Tearing effect interrupt flag This bit is set when a tearing effect event occurs."]
6333 #[inline(always)]
6334 pub fn set_teif(&mut self, val: bool) {
6335 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6336 }
6337 #[doc = "End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished."]
6338 #[inline(always)]
6339 pub const fn erif(&self) -> bool {
6340 let val = (self.0 >> 1usize) & 0x01;
6341 val != 0
6342 }
6343 #[doc = "End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished."]
6344 #[inline(always)]
6345 pub fn set_erif(&mut self, val: bool) {
6346 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6347 }
6348 #[doc = "Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing."]
6349 #[inline(always)]
6350 pub const fn busy(&self) -> bool {
6351 let val = (self.0 >> 2usize) & 0x01;
6352 val != 0
6353 }
6354 #[doc = "Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing."]
6355 #[inline(always)]
6356 pub fn set_busy(&mut self, val: bool) {
6357 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
6358 }
6359 #[doc = "PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked."]
6360 #[inline(always)]
6361 pub const fn pllls(&self) -> bool {
6362 let val = (self.0 >> 8usize) & 0x01;
6363 val != 0
6364 }
6365 #[doc = "PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked."]
6366 #[inline(always)]
6367 pub fn set_pllls(&mut self, val: bool) {
6368 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
6369 }
6370 #[doc = "PLL lock interrupt flag This bit is set when the PLL becomes locked."]
6371 #[inline(always)]
6372 pub const fn plllif(&self) -> bool {
6373 let val = (self.0 >> 9usize) & 0x01;
6374 val != 0
6375 }
6376 #[doc = "PLL lock interrupt flag This bit is set when the PLL becomes locked."]
6377 #[inline(always)]
6378 pub fn set_plllif(&mut self, val: bool) {
6379 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
6380 }
6381 #[doc = "PLL unlock interrupt flag This bit is set when the PLL becomes unlocked."]
6382 #[inline(always)]
6383 pub const fn plluif(&self) -> bool {
6384 let val = (self.0 >> 10usize) & 0x01;
6385 val != 0
6386 }
6387 #[doc = "PLL unlock interrupt flag This bit is set when the PLL becomes unlocked."]
6388 #[inline(always)]
6389 pub fn set_plluif(&mut self, val: bool) {
6390 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
6391 }
6392 }
6393 impl Default for Wisr {
6394 #[inline(always)]
6395 fn default() -> Wisr {
6396 Wisr(0)
6397 }
6398 }
6399 impl core::fmt::Debug for Wisr {
6400 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6401 f.debug_struct("Wisr")
6402 .field("teif", &self.teif())
6403 .field("erif", &self.erif())
6404 .field("busy", &self.busy())
6405 .field("pllls", &self.pllls())
6406 .field("plllif", &self.plllif())
6407 .field("plluif", &self.plluif())
6408 .finish()
6409 }
6410 }
6411 #[cfg(feature = "defmt")]
6412 impl defmt::Format for Wisr {
6413 fn format(&self, f: defmt::Formatter) {
6414 #[derive(defmt :: Format)]
6415 struct Wisr {
6416 teif: bool,
6417 erif: bool,
6418 busy: bool,
6419 pllls: bool,
6420 plllif: bool,
6421 plluif: bool,
6422 }
6423 let proxy = Wisr {
6424 teif: self.teif(),
6425 erif: self.erif(),
6426 busy: self.busy(),
6427 pllls: self.pllls(),
6428 plllif: self.plllif(),
6429 plluif: self.plluif(),
6430 };
6431 defmt::write!(f, "{}", proxy)
6432 }
6433 }
6434 #[doc = "DSI Wrapper PHY configuration register 0."]
6435 #[repr(transparent)]
6436 #[derive(Copy, Clone, Eq, PartialEq)]
6437 pub struct Wpcr0(pub u32);
6438 impl Wpcr0 {
6439 #[doc = "Swap clock lane pins This bit swaps the pins on clock lane."]
6440 #[inline(always)]
6441 pub const fn swcl(&self) -> bool {
6442 let val = (self.0 >> 6usize) & 0x01;
6443 val != 0
6444 }
6445 #[doc = "Swap clock lane pins This bit swaps the pins on clock lane."]
6446 #[inline(always)]
6447 pub fn set_swcl(&mut self, val: bool) {
6448 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
6449 }
6450 #[doc = "Swap data lane 0 pins This bit swaps the pins on data lane 0."]
6451 #[inline(always)]
6452 pub const fn swdl0(&self) -> bool {
6453 let val = (self.0 >> 7usize) & 0x01;
6454 val != 0
6455 }
6456 #[doc = "Swap data lane 0 pins This bit swaps the pins on data lane 0."]
6457 #[inline(always)]
6458 pub fn set_swdl0(&mut self, val: bool) {
6459 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
6460 }
6461 #[doc = "Swap data lane 1 pins This bit swaps the pins on clock lane."]
6462 #[inline(always)]
6463 pub const fn swdl1(&self) -> bool {
6464 let val = (self.0 >> 8usize) & 0x01;
6465 val != 0
6466 }
6467 #[doc = "Swap data lane 1 pins This bit swaps the pins on clock lane."]
6468 #[inline(always)]
6469 pub fn set_swdl1(&mut self, val: bool) {
6470 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
6471 }
6472 #[doc = "Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence."]
6473 #[inline(always)]
6474 pub const fn ftxsmcl(&self) -> bool {
6475 let val = (self.0 >> 12usize) & 0x01;
6476 val != 0
6477 }
6478 #[doc = "Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence."]
6479 #[inline(always)]
6480 pub fn set_ftxsmcl(&mut self, val: bool) {
6481 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
6482 }
6483 #[doc = "Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence."]
6484 #[inline(always)]
6485 pub const fn ftxsmdl(&self) -> bool {
6486 let val = (self.0 >> 13usize) & 0x01;
6487 val != 0
6488 }
6489 #[doc = "Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence."]
6490 #[inline(always)]
6491 pub fn set_ftxsmdl(&mut self, val: bool) {
6492 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
6493 }
6494 }
6495 impl Default for Wpcr0 {
6496 #[inline(always)]
6497 fn default() -> Wpcr0 {
6498 Wpcr0(0)
6499 }
6500 }
6501 impl core::fmt::Debug for Wpcr0 {
6502 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6503 f.debug_struct("Wpcr0")
6504 .field("swcl", &self.swcl())
6505 .field("swdl0", &self.swdl0())
6506 .field("swdl1", &self.swdl1())
6507 .field("ftxsmcl", &self.ftxsmcl())
6508 .field("ftxsmdl", &self.ftxsmdl())
6509 .finish()
6510 }
6511 }
6512 #[cfg(feature = "defmt")]
6513 impl defmt::Format for Wpcr0 {
6514 fn format(&self, f: defmt::Formatter) {
6515 #[derive(defmt :: Format)]
6516 struct Wpcr0 {
6517 swcl: bool,
6518 swdl0: bool,
6519 swdl1: bool,
6520 ftxsmcl: bool,
6521 ftxsmdl: bool,
6522 }
6523 let proxy = Wpcr0 {
6524 swcl: self.swcl(),
6525 swdl0: self.swdl0(),
6526 swdl1: self.swdl1(),
6527 ftxsmcl: self.ftxsmcl(),
6528 ftxsmdl: self.ftxsmdl(),
6529 };
6530 defmt::write!(f, "{}", proxy)
6531 }
6532 }
6533 #[doc = "DSI Wrapper regulator and PLL control register."]
6534 #[repr(transparent)]
6535 #[derive(Copy, Clone, Eq, PartialEq)]
6536 pub struct Wrpcr(pub u32);
6537 impl Wrpcr {
6538 #[doc = "PLL enable This bit enables the D-PHY PLL."]
6539 #[inline(always)]
6540 pub const fn pllen(&self) -> bool {
6541 let val = (self.0 >> 0usize) & 0x01;
6542 val != 0
6543 }
6544 #[doc = "PLL enable This bit enables the D-PHY PLL."]
6545 #[inline(always)]
6546 pub fn set_pllen(&mut self, val: bool) {
6547 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6548 }
6549 #[doc = "PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2."]
6550 #[inline(always)]
6551 pub const fn ndiv(&self) -> u16 {
6552 let val = (self.0 >> 2usize) & 0x01ff;
6553 val as u16
6554 }
6555 #[doc = "PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2."]
6556 #[inline(always)]
6557 pub fn set_ndiv(&mut self, val: u16) {
6558 self.0 = (self.0 & !(0x01ff << 2usize)) | (((val as u32) & 0x01ff) << 2usize);
6559 }
6560 #[doc = "PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511."]
6561 #[inline(always)]
6562 pub const fn idf(&self) -> u16 {
6563 let val = (self.0 >> 11usize) & 0x01ff;
6564 val as u16
6565 }
6566 #[doc = "PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511."]
6567 #[inline(always)]
6568 pub fn set_idf(&mut self, val: u16) {
6569 self.0 = (self.0 & !(0x01ff << 11usize)) | (((val as u32) & 0x01ff) << 11usize);
6570 }
6571 #[doc = "PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511."]
6572 #[inline(always)]
6573 pub const fn odf(&self) -> u16 {
6574 let val = (self.0 >> 20usize) & 0x01ff;
6575 val as u16
6576 }
6577 #[doc = "PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511."]
6578 #[inline(always)]
6579 pub fn set_odf(&mut self, val: u16) {
6580 self.0 = (self.0 & !(0x01ff << 20usize)) | (((val as u32) & 0x01ff) << 20usize);
6581 }
6582 }
6583 impl Default for Wrpcr {
6584 #[inline(always)]
6585 fn default() -> Wrpcr {
6586 Wrpcr(0)
6587 }
6588 }
6589 impl core::fmt::Debug for Wrpcr {
6590 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6591 f.debug_struct("Wrpcr")
6592 .field("pllen", &self.pllen())
6593 .field("ndiv", &self.ndiv())
6594 .field("idf", &self.idf())
6595 .field("odf", &self.odf())
6596 .finish()
6597 }
6598 }
6599 #[cfg(feature = "defmt")]
6600 impl defmt::Format for Wrpcr {
6601 fn format(&self, f: defmt::Formatter) {
6602 #[derive(defmt :: Format)]
6603 struct Wrpcr {
6604 pllen: bool,
6605 ndiv: u16,
6606 idf: u16,
6607 odf: u16,
6608 }
6609 let proxy = Wrpcr {
6610 pllen: self.pllen(),
6611 ndiv: self.ndiv(),
6612 idf: self.idf(),
6613 odf: self.odf(),
6614 };
6615 defmt::write!(f, "{}", proxy)
6616 }
6617 }
6618}
6619