1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "GFXMMU."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Gfxmmu {
9 ptr: *mut u8,
10}
11unsafe impl Send for Gfxmmu {}
12unsafe impl Sync for Gfxmmu {}
13impl Gfxmmu {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "GFXMMU configuration register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "GFXMMU status register."]
28 #[inline(always)]
29 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::R> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "GFXMMU flag clear register."]
33 #[inline(always)]
34 pub const fn fcr(self) -> crate::common::Reg<regs::Fcr, crate::common::W> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "GFXMMU cache control register."]
38 #[inline(always)]
39 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "GFXMMU default value register."]
43 #[inline(always)]
44 pub const fn dvr(self) -> crate::common::Reg<regs::Dvr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "GFXMMU buffer 0 configuration register."]
48 #[inline(always)]
49 pub const fn bcr(self, n: usize) -> crate::common::Reg<regs::Bcr, crate::common::RW> {
50 assert!(n < 4usize);
51 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) }
52 }
53 #[doc = "GFXMMU LUT entry 0 low."]
54 #[inline(always)]
55 pub const fn lutl(self, n: usize) -> crate::common::Reg<regs::Lutl, crate::common::RW> {
56 assert!(n < 1024usize);
57 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1000usize + n * 8usize) as _) }
58 }
59 #[doc = "GFXMMU LUT entry 0 high."]
60 #[inline(always)]
61 pub const fn luth(self, n: usize) -> crate::common::Reg<regs::Luth, crate::common::RW> {
62 assert!(n < 1024usize);
63 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1004usize + n * 8usize) as _) }
64 }
65}
66pub mod regs {
67 #[doc = "GFXMMU buffer configuration register."]
68 #[repr(transparent)]
69 #[derive(Copy, Clone, Eq, PartialEq)]
70 pub struct Bcr(pub u32);
71 impl Bcr {
72 #[doc = "Physical buffer offset. Offset of the physical buffer."]
73 #[inline(always)]
74 pub const fn pbo(&self) -> u32 {
75 let val = (self.0 >> 4usize) & 0x0007_ffff;
76 val as u32
77 }
78 #[doc = "Physical buffer offset. Offset of the physical buffer."]
79 #[inline(always)]
80 pub fn set_pbo(&mut self, val: u32) {
81 self.0 = (self.0 & !(0x0007_ffff << 4usize)) | (((val as u32) & 0x0007_ffff) << 4usize);
82 }
83 #[doc = "Physical buffer base address. Base address MSB of the physical buffer."]
84 #[inline(always)]
85 pub const fn pbba(&self) -> u16 {
86 let val = (self.0 >> 23usize) & 0x01ff;
87 val as u16
88 }
89 #[doc = "Physical buffer base address. Base address MSB of the physical buffer."]
90 #[inline(always)]
91 pub fn set_pbba(&mut self, val: u16) {
92 self.0 = (self.0 & !(0x01ff << 23usize)) | (((val as u32) & 0x01ff) << 23usize);
93 }
94 }
95 impl Default for Bcr {
96 #[inline(always)]
97 fn default() -> Bcr {
98 Bcr(0)
99 }
100 }
101 impl core::fmt::Debug for Bcr {
102 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
103 f.debug_struct("Bcr")
104 .field("pbo", &self.pbo())
105 .field("pbba", &self.pbba())
106 .finish()
107 }
108 }
109 #[cfg(feature = "defmt")]
110 impl defmt::Format for Bcr {
111 fn format(&self, f: defmt::Formatter) {
112 #[derive(defmt :: Format)]
113 struct Bcr {
114 pbo: u32,
115 pbba: u16,
116 }
117 let proxy = Bcr {
118 pbo: self.pbo(),
119 pbba: self.pbba(),
120 };
121 defmt::write!(f, "{}", proxy)
122 }
123 }
124 #[doc = "GFXMMU cache control register."]
125 #[repr(transparent)]
126 #[derive(Copy, Clone, Eq, PartialEq)]
127 pub struct Ccr(pub u32);
128 impl Ccr {
129 #[doc = "Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect."]
130 #[inline(always)]
131 pub const fn ff(&self) -> bool {
132 let val = (self.0 >> 0usize) & 0x01;
133 val != 0
134 }
135 #[doc = "Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect."]
136 #[inline(always)]
137 pub fn set_ff(&mut self, val: bool) {
138 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
139 }
140 #[doc = "Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect."]
141 #[inline(always)]
142 pub const fn fi(&self) -> bool {
143 let val = (self.0 >> 1usize) & 0x01;
144 val != 0
145 }
146 #[doc = "Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect."]
147 #[inline(always)]
148 pub fn set_fi(&mut self, val: bool) {
149 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
150 }
151 }
152 impl Default for Ccr {
153 #[inline(always)]
154 fn default() -> Ccr {
155 Ccr(0)
156 }
157 }
158 impl core::fmt::Debug for Ccr {
159 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
160 f.debug_struct("Ccr")
161 .field("ff", &self.ff())
162 .field("fi", &self.fi())
163 .finish()
164 }
165 }
166 #[cfg(feature = "defmt")]
167 impl defmt::Format for Ccr {
168 fn format(&self, f: defmt::Formatter) {
169 #[derive(defmt :: Format)]
170 struct Ccr {
171 ff: bool,
172 fi: bool,
173 }
174 let proxy = Ccr {
175 ff: self.ff(),
176 fi: self.fi(),
177 };
178 defmt::write!(f, "{}", proxy)
179 }
180 }
181 #[doc = "GFXMMU configuration register."]
182 #[repr(transparent)]
183 #[derive(Copy, Clone, Eq, PartialEq)]
184 pub struct Cr(pub u32);
185 impl Cr {
186 #[doc = "Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt."]
187 #[inline(always)]
188 pub const fn boie(&self, n: usize) -> bool {
189 assert!(n < 4usize);
190 let offs = 0usize + n * 1usize;
191 let val = (self.0 >> offs) & 0x01;
192 val != 0
193 }
194 #[doc = "Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt."]
195 #[inline(always)]
196 pub fn set_boie(&mut self, n: usize, val: bool) {
197 assert!(n < 4usize);
198 let offs = 0usize + n * 1usize;
199 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
200 }
201 #[doc = "AHB master error interrupt enable. This bit enables the AHB master error interrupt."]
202 #[inline(always)]
203 pub const fn ameie(&self) -> bool {
204 let val = (self.0 >> 4usize) & 0x01;
205 val != 0
206 }
207 #[doc = "AHB master error interrupt enable. This bit enables the AHB master error interrupt."]
208 #[inline(always)]
209 pub fn set_ameie(&mut self, val: bool) {
210 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
211 }
212 #[doc = "192 Block mode. This bit defines the number of blocks per line."]
213 #[inline(always)]
214 pub const fn bm(&self, n: usize) -> super::vals::Bm192 {
215 assert!(n < 1usize);
216 let offs = 6usize + n * 0usize;
217 let val = (self.0 >> offs) & 0x01;
218 super::vals::Bm192::from_bits(val as u8)
219 }
220 #[doc = "192 Block mode. This bit defines the number of blocks per line."]
221 #[inline(always)]
222 pub fn set_bm(&mut self, n: usize, val: super::vals::Bm192) {
223 assert!(n < 1usize);
224 let offs = 6usize + n * 0usize;
225 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
226 }
227 #[doc = "Cache enable. This bit enables the cache unit."]
228 #[inline(always)]
229 pub const fn ce(&self) -> bool {
230 let val = (self.0 >> 7usize) & 0x01;
231 val != 0
232 }
233 #[doc = "Cache enable. This bit enables the cache unit."]
234 #[inline(always)]
235 pub fn set_ce(&mut self, val: bool) {
236 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
237 }
238 #[doc = "Cache lock. This bit lock the cache onto the buffer defined in the CLB field."]
239 #[inline(always)]
240 pub const fn cl(&self) -> bool {
241 let val = (self.0 >> 8usize) & 0x01;
242 val != 0
243 }
244 #[doc = "Cache lock. This bit lock the cache onto the buffer defined in the CLB field."]
245 #[inline(always)]
246 pub fn set_cl(&mut self, val: bool) {
247 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
248 }
249 #[doc = "Cache lock buffer. This field select the buffer on which the cache is locked."]
250 #[inline(always)]
251 pub const fn clb(&self) -> super::vals::Clb {
252 let val = (self.0 >> 9usize) & 0x03;
253 super::vals::Clb::from_bits(val as u8)
254 }
255 #[doc = "Cache lock buffer. This field select the buffer on which the cache is locked."]
256 #[inline(always)]
257 pub fn set_clb(&mut self, val: super::vals::Clb) {
258 self.0 = (self.0 & !(0x03 << 9usize)) | (((val.to_bits() as u32) & 0x03) << 9usize);
259 }
260 #[doc = "Force caching. This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set)."]
261 #[inline(always)]
262 pub const fn fc(&self) -> bool {
263 let val = (self.0 >> 11usize) & 0x01;
264 val != 0
265 }
266 #[doc = "Force caching. This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set)."]
267 #[inline(always)]
268 pub fn set_fc(&mut self, val: bool) {
269 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
270 }
271 #[doc = "Prefetch disable. This bit disables the prefetch of the cache."]
272 #[inline(always)]
273 pub const fn pd(&self) -> bool {
274 let val = (self.0 >> 12usize) & 0x01;
275 val != 0
276 }
277 #[doc = "Prefetch disable. This bit disables the prefetch of the cache."]
278 #[inline(always)]
279 pub fn set_pd(&mut self, val: bool) {
280 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
281 }
282 #[doc = "Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache."]
283 #[inline(always)]
284 pub const fn oc(&self) -> bool {
285 let val = (self.0 >> 16usize) & 0x01;
286 val != 0
287 }
288 #[doc = "Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache."]
289 #[inline(always)]
290 pub fn set_oc(&mut self, val: bool) {
291 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
292 }
293 #[doc = "Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache."]
294 #[inline(always)]
295 pub const fn ob(&self) -> bool {
296 let val = (self.0 >> 17usize) & 0x01;
297 val != 0
298 }
299 #[doc = "Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache."]
300 #[inline(always)]
301 pub fn set_ob(&mut self, val: bool) {
302 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
303 }
304 }
305 impl Default for Cr {
306 #[inline(always)]
307 fn default() -> Cr {
308 Cr(0)
309 }
310 }
311 impl core::fmt::Debug for Cr {
312 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
313 f.debug_struct("Cr")
314 .field(
315 "boie",
316 &[
317 self.boie(0usize),
318 self.boie(1usize),
319 self.boie(2usize),
320 self.boie(3usize),
321 ],
322 )
323 .field("ameie", &self.ameie())
324 .field("bm", &[self.bm(0usize)])
325 .field("ce", &self.ce())
326 .field("cl", &self.cl())
327 .field("clb", &self.clb())
328 .field("fc", &self.fc())
329 .field("pd", &self.pd())
330 .field("oc", &self.oc())
331 .field("ob", &self.ob())
332 .finish()
333 }
334 }
335 #[cfg(feature = "defmt")]
336 impl defmt::Format for Cr {
337 fn format(&self, f: defmt::Formatter) {
338 #[derive(defmt :: Format)]
339 struct Cr {
340 boie: [bool; 4usize],
341 ameie: bool,
342 bm: [super::vals::Bm192; 1usize],
343 ce: bool,
344 cl: bool,
345 clb: super::vals::Clb,
346 fc: bool,
347 pd: bool,
348 oc: bool,
349 ob: bool,
350 }
351 let proxy = Cr {
352 boie: [
353 self.boie(0usize),
354 self.boie(1usize),
355 self.boie(2usize),
356 self.boie(3usize),
357 ],
358 ameie: self.ameie(),
359 bm: [self.bm(0usize)],
360 ce: self.ce(),
361 cl: self.cl(),
362 clb: self.clb(),
363 fc: self.fc(),
364 pd: self.pd(),
365 oc: self.oc(),
366 ob: self.ob(),
367 };
368 defmt::write!(f, "{}", proxy)
369 }
370 }
371 #[doc = "GFXMMU default value register."]
372 #[repr(transparent)]
373 #[derive(Copy, Clone, Eq, PartialEq)]
374 pub struct Dvr(pub u32);
375 impl Dvr {
376 #[doc = "Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped."]
377 #[inline(always)]
378 pub const fn dv(&self) -> u32 {
379 let val = (self.0 >> 0usize) & 0xffff_ffff;
380 val as u32
381 }
382 #[doc = "Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped."]
383 #[inline(always)]
384 pub fn set_dv(&mut self, val: u32) {
385 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
386 }
387 }
388 impl Default for Dvr {
389 #[inline(always)]
390 fn default() -> Dvr {
391 Dvr(0)
392 }
393 }
394 impl core::fmt::Debug for Dvr {
395 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
396 f.debug_struct("Dvr").field("dv", &self.dv()).finish()
397 }
398 }
399 #[cfg(feature = "defmt")]
400 impl defmt::Format for Dvr {
401 fn format(&self, f: defmt::Formatter) {
402 #[derive(defmt :: Format)]
403 struct Dvr {
404 dv: u32,
405 }
406 let proxy = Dvr { dv: self.dv() };
407 defmt::write!(f, "{}", proxy)
408 }
409 }
410 #[doc = "GFXMMU flag clear register."]
411 #[repr(transparent)]
412 #[derive(Copy, Clone, Eq, PartialEq)]
413 pub struct Fcr(pub u32);
414 impl Fcr {
415 #[doc = "Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register."]
416 #[inline(always)]
417 pub const fn cbof(&self, n: usize) -> bool {
418 assert!(n < 4usize);
419 let offs = 0usize + n * 1usize;
420 let val = (self.0 >> offs) & 0x01;
421 val != 0
422 }
423 #[doc = "Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register."]
424 #[inline(always)]
425 pub fn set_cbof(&mut self, n: usize, val: bool) {
426 assert!(n < 4usize);
427 let offs = 0usize + n * 1usize;
428 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
429 }
430 #[doc = "Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register."]
431 #[inline(always)]
432 pub const fn camef(&self) -> bool {
433 let val = (self.0 >> 4usize) & 0x01;
434 val != 0
435 }
436 #[doc = "Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register."]
437 #[inline(always)]
438 pub fn set_camef(&mut self, val: bool) {
439 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
440 }
441 }
442 impl Default for Fcr {
443 #[inline(always)]
444 fn default() -> Fcr {
445 Fcr(0)
446 }
447 }
448 impl core::fmt::Debug for Fcr {
449 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
450 f.debug_struct("Fcr")
451 .field(
452 "cbof",
453 &[
454 self.cbof(0usize),
455 self.cbof(1usize),
456 self.cbof(2usize),
457 self.cbof(3usize),
458 ],
459 )
460 .field("camef", &self.camef())
461 .finish()
462 }
463 }
464 #[cfg(feature = "defmt")]
465 impl defmt::Format for Fcr {
466 fn format(&self, f: defmt::Formatter) {
467 #[derive(defmt :: Format)]
468 struct Fcr {
469 cbof: [bool; 4usize],
470 camef: bool,
471 }
472 let proxy = Fcr {
473 cbof: [
474 self.cbof(0usize),
475 self.cbof(1usize),
476 self.cbof(2usize),
477 self.cbof(3usize),
478 ],
479 camef: self.camef(),
480 };
481 defmt::write!(f, "{}", proxy)
482 }
483 }
484 #[doc = "GFXMMU LUT entry high."]
485 #[repr(transparent)]
486 #[derive(Copy, Clone, Eq, PartialEq)]
487 pub struct Luth(pub u32);
488 impl Luth {
489 #[doc = "Line offset. Line offset of line number x (i.e. offset of block 0 of line x)."]
490 #[inline(always)]
491 pub const fn lo(&self) -> u32 {
492 let val = (self.0 >> 4usize) & 0x0003_ffff;
493 val as u32
494 }
495 #[doc = "Line offset. Line offset of line number x (i.e. offset of block 0 of line x)."]
496 #[inline(always)]
497 pub fn set_lo(&mut self, val: u32) {
498 self.0 = (self.0 & !(0x0003_ffff << 4usize)) | (((val as u32) & 0x0003_ffff) << 4usize);
499 }
500 }
501 impl Default for Luth {
502 #[inline(always)]
503 fn default() -> Luth {
504 Luth(0)
505 }
506 }
507 impl core::fmt::Debug for Luth {
508 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
509 f.debug_struct("Luth").field("lo", &self.lo()).finish()
510 }
511 }
512 #[cfg(feature = "defmt")]
513 impl defmt::Format for Luth {
514 fn format(&self, f: defmt::Formatter) {
515 #[derive(defmt :: Format)]
516 struct Luth {
517 lo: u32,
518 }
519 let proxy = Luth { lo: self.lo() };
520 defmt::write!(f, "{}", proxy)
521 }
522 }
523 #[doc = "GFXMMU LUT entry low."]
524 #[repr(transparent)]
525 #[derive(Copy, Clone, Eq, PartialEq)]
526 pub struct Lutl(pub u32);
527 impl Lutl {
528 #[doc = "Line enable."]
529 #[inline(always)]
530 pub const fn en(&self) -> bool {
531 let val = (self.0 >> 0usize) & 0x01;
532 val != 0
533 }
534 #[doc = "Line enable."]
535 #[inline(always)]
536 pub fn set_en(&mut self, val: bool) {
537 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
538 }
539 #[doc = "First Valid Block. Number of the first valid block of line number x."]
540 #[inline(always)]
541 pub const fn fvb(&self) -> u8 {
542 let val = (self.0 >> 8usize) & 0xff;
543 val as u8
544 }
545 #[doc = "First Valid Block. Number of the first valid block of line number x."]
546 #[inline(always)]
547 pub fn set_fvb(&mut self, val: u8) {
548 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
549 }
550 #[doc = "Last Valid Block. Number of the last valid block of line number X."]
551 #[inline(always)]
552 pub const fn lvb(&self) -> u8 {
553 let val = (self.0 >> 16usize) & 0xff;
554 val as u8
555 }
556 #[doc = "Last Valid Block. Number of the last valid block of line number X."]
557 #[inline(always)]
558 pub fn set_lvb(&mut self, val: u8) {
559 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
560 }
561 }
562 impl Default for Lutl {
563 #[inline(always)]
564 fn default() -> Lutl {
565 Lutl(0)
566 }
567 }
568 impl core::fmt::Debug for Lutl {
569 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
570 f.debug_struct("Lutl")
571 .field("en", &self.en())
572 .field("fvb", &self.fvb())
573 .field("lvb", &self.lvb())
574 .finish()
575 }
576 }
577 #[cfg(feature = "defmt")]
578 impl defmt::Format for Lutl {
579 fn format(&self, f: defmt::Formatter) {
580 #[derive(defmt :: Format)]
581 struct Lutl {
582 en: bool,
583 fvb: u8,
584 lvb: u8,
585 }
586 let proxy = Lutl {
587 en: self.en(),
588 fvb: self.fvb(),
589 lvb: self.lvb(),
590 };
591 defmt::write!(f, "{}", proxy)
592 }
593 }
594 #[doc = "GFXMMU status register."]
595 #[repr(transparent)]
596 #[derive(Copy, Clone, Eq, PartialEq)]
597 pub struct Sr(pub u32);
598 impl Sr {
599 #[doc = "Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF."]
600 #[inline(always)]
601 pub const fn bof(&self, n: usize) -> bool {
602 assert!(n < 4usize);
603 let offs = 0usize + n * 1usize;
604 let val = (self.0 >> offs) & 0x01;
605 val != 0
606 }
607 #[doc = "Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF."]
608 #[inline(always)]
609 pub fn set_bof(&mut self, n: usize, val: bool) {
610 assert!(n < 4usize);
611 let offs = 0usize + n * 1usize;
612 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
613 }
614 #[doc = "AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF."]
615 #[inline(always)]
616 pub const fn amef(&self) -> bool {
617 let val = (self.0 >> 4usize) & 0x01;
618 val != 0
619 }
620 #[doc = "AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF."]
621 #[inline(always)]
622 pub fn set_amef(&mut self, val: bool) {
623 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
624 }
625 }
626 impl Default for Sr {
627 #[inline(always)]
628 fn default() -> Sr {
629 Sr(0)
630 }
631 }
632 impl core::fmt::Debug for Sr {
633 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
634 f.debug_struct("Sr")
635 .field(
636 "bof",
637 &[self.bof(0usize), self.bof(1usize), self.bof(2usize), self.bof(3usize)],
638 )
639 .field("amef", &self.amef())
640 .finish()
641 }
642 }
643 #[cfg(feature = "defmt")]
644 impl defmt::Format for Sr {
645 fn format(&self, f: defmt::Formatter) {
646 #[derive(defmt :: Format)]
647 struct Sr {
648 bof: [bool; 4usize],
649 amef: bool,
650 }
651 let proxy = Sr {
652 bof: [self.bof(0usize), self.bof(1usize), self.bof(2usize), self.bof(3usize)],
653 amef: self.amef(),
654 };
655 defmt::write!(f, "{}", proxy)
656 }
657 }
658}
659pub mod vals {
660 #[repr(u8)]
661 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
662 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
663 pub enum Bm192 {
664 #[doc = "256 blocks per line."]
665 _256BLOCKS_PER_LINE = 0x0,
666 #[doc = "192 blocks per line."]
667 _192BLOCKS_PER_LINE = 0x01,
668 }
669 impl Bm192 {
670 #[inline(always)]
671 pub const fn from_bits(val: u8) -> Bm192 {
672 unsafe { core::mem::transmute(val & 0x01) }
673 }
674 #[inline(always)]
675 pub const fn to_bits(self) -> u8 {
676 unsafe { core::mem::transmute(self) }
677 }
678 }
679 impl From<u8> for Bm192 {
680 #[inline(always)]
681 fn from(val: u8) -> Bm192 {
682 Bm192::from_bits(val)
683 }
684 }
685 impl From<Bm192> for u8 {
686 #[inline(always)]
687 fn from(val: Bm192) -> u8 {
688 Bm192::to_bits(val)
689 }
690 }
691 #[repr(u8)]
692 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
693 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
694 pub enum Clb {
695 #[doc = "Cache locked on buffer 0."]
696 LOCKED_ON_BUFFER0 = 0x0,
697 #[doc = "Cache locked on buffer 1."]
698 LOCKED_ON_BUFFER1 = 0x01,
699 #[doc = "Cache locked on buffer 2."]
700 LOCKED_ON_BUFFER2 = 0x02,
701 #[doc = "Cache locked on buffer 3."]
702 LOCKED_ON_BUFFER3 = 0x03,
703 }
704 impl Clb {
705 #[inline(always)]
706 pub const fn from_bits(val: u8) -> Clb {
707 unsafe { core::mem::transmute(val & 0x03) }
708 }
709 #[inline(always)]
710 pub const fn to_bits(self) -> u8 {
711 unsafe { core::mem::transmute(self) }
712 }
713 }
714 impl From<u8> for Clb {
715 #[inline(always)]
716 fn from(val: u8) -> Clb {
717 Clb::from_bits(val)
718 }
719 }
720 impl From<Clb> for u8 {
721 #[inline(always)]
722 fn from(val: Clb) -> u8 {
723 Clb::to_bits(val)
724 }
725 }
726}
727