1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "General-purpose I/Os"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Gpio {
9 ptr: *mut u8,
10}
11unsafe impl Send for Gpio {}
12unsafe impl Sync for Gpio {}
13impl Gpio {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "GPIO port mode register"]
23 #[inline(always)]
24 pub const fn moder(self) -> crate::common::Reg<regs::Moder, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "GPIO port output type register"]
28 #[inline(always)]
29 pub const fn otyper(self) -> crate::common::Reg<regs::Otyper, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "GPIO port output speed register"]
33 #[inline(always)]
34 pub const fn ospeedr(self) -> crate::common::Reg<regs::Ospeedr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "GPIO port pull-up/pull-down register"]
38 #[inline(always)]
39 pub const fn pupdr(self) -> crate::common::Reg<regs::Pupdr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "GPIO port input data register"]
43 #[inline(always)]
44 pub const fn idr(self) -> crate::common::Reg<regs::Idr, crate::common::R> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "GPIO port output data register"]
48 #[inline(always)]
49 pub const fn odr(self) -> crate::common::Reg<regs::Odr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "GPIO port bit set/reset register"]
53 #[inline(always)]
54 pub const fn bsrr(self) -> crate::common::Reg<regs::Bsrr, crate::common::W> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[doc = "GPIO port configuration lock register"]
58 #[inline(always)]
59 pub const fn lckr(self) -> crate::common::Reg<regs::Lckr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
61 }
62 #[doc = "GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance."]
63 #[inline(always)]
64 pub const fn afr(self, n: usize) -> crate::common::Reg<regs::Afr, crate::common::RW> {
65 assert!(n < 2usize);
66 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) }
67 }
68}
69pub mod regs {
70 #[doc = "GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH)."]
71 #[repr(transparent)]
72 #[derive(Copy, Clone, Eq, PartialEq)]
73 pub struct Afr(pub u32);
74 impl Afr {
75 #[doc = "Alternate function selection for one of the pins controlled by this register (0-7)."]
76 #[inline(always)]
77 pub const fn afr(&self, n: usize) -> u8 {
78 assert!(n < 8usize);
79 let offs = 0usize + n * 4usize;
80 let val = (self.0 >> offs) & 0x0f;
81 val as u8
82 }
83 #[doc = "Alternate function selection for one of the pins controlled by this register (0-7)."]
84 #[inline(always)]
85 pub fn set_afr(&mut self, n: usize, val: u8) {
86 assert!(n < 8usize);
87 let offs = 0usize + n * 4usize;
88 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
89 }
90 }
91 impl Default for Afr {
92 #[inline(always)]
93 fn default() -> Afr {
94 Afr(0)
95 }
96 }
97 impl core::fmt::Debug for Afr {
98 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99 f.debug_struct("Afr")
100 .field(
101 "afr",
102 &[
103 self.afr(0usize),
104 self.afr(1usize),
105 self.afr(2usize),
106 self.afr(3usize),
107 self.afr(4usize),
108 self.afr(5usize),
109 self.afr(6usize),
110 self.afr(7usize),
111 ],
112 )
113 .finish()
114 }
115 }
116 #[cfg(feature = "defmt")]
117 impl defmt::Format for Afr {
118 fn format(&self, f: defmt::Formatter) {
119 #[derive(defmt :: Format)]
120 struct Afr {
121 afr: [u8; 8usize],
122 }
123 let proxy = Afr {
124 afr: [
125 self.afr(0usize),
126 self.afr(1usize),
127 self.afr(2usize),
128 self.afr(3usize),
129 self.afr(4usize),
130 self.afr(5usize),
131 self.afr(6usize),
132 self.afr(7usize),
133 ],
134 };
135 defmt::write!(f, "{}", proxy)
136 }
137 }
138 #[doc = "GPIO port bit set/reset register"]
139 #[repr(transparent)]
140 #[derive(Copy, Clone, Eq, PartialEq)]
141 pub struct Bsrr(pub u32);
142 impl Bsrr {
143 #[doc = "Port x set bit y (y= 0..15)"]
144 #[inline(always)]
145 pub const fn bs(&self, n: usize) -> bool {
146 assert!(n < 16usize);
147 let offs = 0usize + n * 1usize;
148 let val = (self.0 >> offs) & 0x01;
149 val != 0
150 }
151 #[doc = "Port x set bit y (y= 0..15)"]
152 #[inline(always)]
153 pub fn set_bs(&mut self, n: usize, val: bool) {
154 assert!(n < 16usize);
155 let offs = 0usize + n * 1usize;
156 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
157 }
158 #[doc = "Port x set bit y (y= 0..15)"]
159 #[inline(always)]
160 pub const fn br(&self, n: usize) -> bool {
161 assert!(n < 16usize);
162 let offs = 16usize + n * 1usize;
163 let val = (self.0 >> offs) & 0x01;
164 val != 0
165 }
166 #[doc = "Port x set bit y (y= 0..15)"]
167 #[inline(always)]
168 pub fn set_br(&mut self, n: usize, val: bool) {
169 assert!(n < 16usize);
170 let offs = 16usize + n * 1usize;
171 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
172 }
173 }
174 impl Default for Bsrr {
175 #[inline(always)]
176 fn default() -> Bsrr {
177 Bsrr(0)
178 }
179 }
180 impl core::fmt::Debug for Bsrr {
181 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
182 f.debug_struct("Bsrr")
183 .field(
184 "bs",
185 &[
186 self.bs(0usize),
187 self.bs(1usize),
188 self.bs(2usize),
189 self.bs(3usize),
190 self.bs(4usize),
191 self.bs(5usize),
192 self.bs(6usize),
193 self.bs(7usize),
194 self.bs(8usize),
195 self.bs(9usize),
196 self.bs(10usize),
197 self.bs(11usize),
198 self.bs(12usize),
199 self.bs(13usize),
200 self.bs(14usize),
201 self.bs(15usize),
202 ],
203 )
204 .field(
205 "br",
206 &[
207 self.br(0usize),
208 self.br(1usize),
209 self.br(2usize),
210 self.br(3usize),
211 self.br(4usize),
212 self.br(5usize),
213 self.br(6usize),
214 self.br(7usize),
215 self.br(8usize),
216 self.br(9usize),
217 self.br(10usize),
218 self.br(11usize),
219 self.br(12usize),
220 self.br(13usize),
221 self.br(14usize),
222 self.br(15usize),
223 ],
224 )
225 .finish()
226 }
227 }
228 #[cfg(feature = "defmt")]
229 impl defmt::Format for Bsrr {
230 fn format(&self, f: defmt::Formatter) {
231 #[derive(defmt :: Format)]
232 struct Bsrr {
233 bs: [bool; 16usize],
234 br: [bool; 16usize],
235 }
236 let proxy = Bsrr {
237 bs: [
238 self.bs(0usize),
239 self.bs(1usize),
240 self.bs(2usize),
241 self.bs(3usize),
242 self.bs(4usize),
243 self.bs(5usize),
244 self.bs(6usize),
245 self.bs(7usize),
246 self.bs(8usize),
247 self.bs(9usize),
248 self.bs(10usize),
249 self.bs(11usize),
250 self.bs(12usize),
251 self.bs(13usize),
252 self.bs(14usize),
253 self.bs(15usize),
254 ],
255 br: [
256 self.br(0usize),
257 self.br(1usize),
258 self.br(2usize),
259 self.br(3usize),
260 self.br(4usize),
261 self.br(5usize),
262 self.br(6usize),
263 self.br(7usize),
264 self.br(8usize),
265 self.br(9usize),
266 self.br(10usize),
267 self.br(11usize),
268 self.br(12usize),
269 self.br(13usize),
270 self.br(14usize),
271 self.br(15usize),
272 ],
273 };
274 defmt::write!(f, "{}", proxy)
275 }
276 }
277 #[doc = "GPIO port input data register"]
278 #[repr(transparent)]
279 #[derive(Copy, Clone, Eq, PartialEq)]
280 pub struct Idr(pub u32);
281 impl Idr {
282 #[doc = "Port input data (y = 0..15)"]
283 #[inline(always)]
284 pub const fn idr(&self, n: usize) -> super::vals::Idr {
285 assert!(n < 16usize);
286 let offs = 0usize + n * 1usize;
287 let val = (self.0 >> offs) & 0x01;
288 super::vals::Idr::from_bits(val as u8)
289 }
290 #[doc = "Port input data (y = 0..15)"]
291 #[inline(always)]
292 pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
293 assert!(n < 16usize);
294 let offs = 0usize + n * 1usize;
295 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
296 }
297 }
298 impl Default for Idr {
299 #[inline(always)]
300 fn default() -> Idr {
301 Idr(0)
302 }
303 }
304 impl core::fmt::Debug for Idr {
305 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
306 f.debug_struct("Idr")
307 .field(
308 "idr",
309 &[
310 self.idr(0usize),
311 self.idr(1usize),
312 self.idr(2usize),
313 self.idr(3usize),
314 self.idr(4usize),
315 self.idr(5usize),
316 self.idr(6usize),
317 self.idr(7usize),
318 self.idr(8usize),
319 self.idr(9usize),
320 self.idr(10usize),
321 self.idr(11usize),
322 self.idr(12usize),
323 self.idr(13usize),
324 self.idr(14usize),
325 self.idr(15usize),
326 ],
327 )
328 .finish()
329 }
330 }
331 #[cfg(feature = "defmt")]
332 impl defmt::Format for Idr {
333 fn format(&self, f: defmt::Formatter) {
334 #[derive(defmt :: Format)]
335 struct Idr {
336 idr: [super::vals::Idr; 16usize],
337 }
338 let proxy = Idr {
339 idr: [
340 self.idr(0usize),
341 self.idr(1usize),
342 self.idr(2usize),
343 self.idr(3usize),
344 self.idr(4usize),
345 self.idr(5usize),
346 self.idr(6usize),
347 self.idr(7usize),
348 self.idr(8usize),
349 self.idr(9usize),
350 self.idr(10usize),
351 self.idr(11usize),
352 self.idr(12usize),
353 self.idr(13usize),
354 self.idr(14usize),
355 self.idr(15usize),
356 ],
357 };
358 defmt::write!(f, "{}", proxy)
359 }
360 }
361 #[doc = "GPIO port configuration lock register"]
362 #[repr(transparent)]
363 #[derive(Copy, Clone, Eq, PartialEq)]
364 pub struct Lckr(pub u32);
365 impl Lckr {
366 #[doc = "Port configuration locked"]
367 #[inline(always)]
368 pub const fn lck(&self, n: usize) -> bool {
369 assert!(n < 16usize);
370 let offs = 0usize + n * 1usize;
371 let val = (self.0 >> offs) & 0x01;
372 val != 0
373 }
374 #[doc = "Port configuration locked"]
375 #[inline(always)]
376 pub fn set_lck(&mut self, n: usize, val: bool) {
377 assert!(n < 16usize);
378 let offs = 0usize + n * 1usize;
379 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
380 }
381 #[doc = "Port configuration lock key active"]
382 #[inline(always)]
383 pub const fn lckk(&self) -> bool {
384 let val = (self.0 >> 16usize) & 0x01;
385 val != 0
386 }
387 #[doc = "Port configuration lock key active"]
388 #[inline(always)]
389 pub fn set_lckk(&mut self, val: bool) {
390 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
391 }
392 }
393 impl Default for Lckr {
394 #[inline(always)]
395 fn default() -> Lckr {
396 Lckr(0)
397 }
398 }
399 impl core::fmt::Debug for Lckr {
400 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
401 f.debug_struct("Lckr")
402 .field(
403 "lck",
404 &[
405 self.lck(0usize),
406 self.lck(1usize),
407 self.lck(2usize),
408 self.lck(3usize),
409 self.lck(4usize),
410 self.lck(5usize),
411 self.lck(6usize),
412 self.lck(7usize),
413 self.lck(8usize),
414 self.lck(9usize),
415 self.lck(10usize),
416 self.lck(11usize),
417 self.lck(12usize),
418 self.lck(13usize),
419 self.lck(14usize),
420 self.lck(15usize),
421 ],
422 )
423 .field("lckk", &self.lckk())
424 .finish()
425 }
426 }
427 #[cfg(feature = "defmt")]
428 impl defmt::Format for Lckr {
429 fn format(&self, f: defmt::Formatter) {
430 #[derive(defmt :: Format)]
431 struct Lckr {
432 lck: [bool; 16usize],
433 lckk: bool,
434 }
435 let proxy = Lckr {
436 lck: [
437 self.lck(0usize),
438 self.lck(1usize),
439 self.lck(2usize),
440 self.lck(3usize),
441 self.lck(4usize),
442 self.lck(5usize),
443 self.lck(6usize),
444 self.lck(7usize),
445 self.lck(8usize),
446 self.lck(9usize),
447 self.lck(10usize),
448 self.lck(11usize),
449 self.lck(12usize),
450 self.lck(13usize),
451 self.lck(14usize),
452 self.lck(15usize),
453 ],
454 lckk: self.lckk(),
455 };
456 defmt::write!(f, "{}", proxy)
457 }
458 }
459 #[doc = "GPIO port mode register"]
460 #[repr(transparent)]
461 #[derive(Copy, Clone, Eq, PartialEq)]
462 pub struct Moder(pub u32);
463 impl Moder {
464 #[doc = "Port x configuration bits (y = 0..15)"]
465 #[inline(always)]
466 pub const fn moder(&self, n: usize) -> super::vals::Moder {
467 assert!(n < 16usize);
468 let offs = 0usize + n * 2usize;
469 let val = (self.0 >> offs) & 0x03;
470 super::vals::Moder::from_bits(val as u8)
471 }
472 #[doc = "Port x configuration bits (y = 0..15)"]
473 #[inline(always)]
474 pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
475 assert!(n < 16usize);
476 let offs = 0usize + n * 2usize;
477 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
478 }
479 }
480 impl Default for Moder {
481 #[inline(always)]
482 fn default() -> Moder {
483 Moder(0)
484 }
485 }
486 impl core::fmt::Debug for Moder {
487 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
488 f.debug_struct("Moder")
489 .field(
490 "moder",
491 &[
492 self.moder(0usize),
493 self.moder(1usize),
494 self.moder(2usize),
495 self.moder(3usize),
496 self.moder(4usize),
497 self.moder(5usize),
498 self.moder(6usize),
499 self.moder(7usize),
500 self.moder(8usize),
501 self.moder(9usize),
502 self.moder(10usize),
503 self.moder(11usize),
504 self.moder(12usize),
505 self.moder(13usize),
506 self.moder(14usize),
507 self.moder(15usize),
508 ],
509 )
510 .finish()
511 }
512 }
513 #[cfg(feature = "defmt")]
514 impl defmt::Format for Moder {
515 fn format(&self, f: defmt::Formatter) {
516 #[derive(defmt :: Format)]
517 struct Moder {
518 moder: [super::vals::Moder; 16usize],
519 }
520 let proxy = Moder {
521 moder: [
522 self.moder(0usize),
523 self.moder(1usize),
524 self.moder(2usize),
525 self.moder(3usize),
526 self.moder(4usize),
527 self.moder(5usize),
528 self.moder(6usize),
529 self.moder(7usize),
530 self.moder(8usize),
531 self.moder(9usize),
532 self.moder(10usize),
533 self.moder(11usize),
534 self.moder(12usize),
535 self.moder(13usize),
536 self.moder(14usize),
537 self.moder(15usize),
538 ],
539 };
540 defmt::write!(f, "{}", proxy)
541 }
542 }
543 #[doc = "GPIO port output data register"]
544 #[repr(transparent)]
545 #[derive(Copy, Clone, Eq, PartialEq)]
546 pub struct Odr(pub u32);
547 impl Odr {
548 #[doc = "Port output data (y = 0..15)"]
549 #[inline(always)]
550 pub const fn odr(&self, n: usize) -> super::vals::Odr {
551 assert!(n < 16usize);
552 let offs = 0usize + n * 1usize;
553 let val = (self.0 >> offs) & 0x01;
554 super::vals::Odr::from_bits(val as u8)
555 }
556 #[doc = "Port output data (y = 0..15)"]
557 #[inline(always)]
558 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
559 assert!(n < 16usize);
560 let offs = 0usize + n * 1usize;
561 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
562 }
563 }
564 impl Default for Odr {
565 #[inline(always)]
566 fn default() -> Odr {
567 Odr(0)
568 }
569 }
570 impl core::fmt::Debug for Odr {
571 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
572 f.debug_struct("Odr")
573 .field(
574 "odr",
575 &[
576 self.odr(0usize),
577 self.odr(1usize),
578 self.odr(2usize),
579 self.odr(3usize),
580 self.odr(4usize),
581 self.odr(5usize),
582 self.odr(6usize),
583 self.odr(7usize),
584 self.odr(8usize),
585 self.odr(9usize),
586 self.odr(10usize),
587 self.odr(11usize),
588 self.odr(12usize),
589 self.odr(13usize),
590 self.odr(14usize),
591 self.odr(15usize),
592 ],
593 )
594 .finish()
595 }
596 }
597 #[cfg(feature = "defmt")]
598 impl defmt::Format for Odr {
599 fn format(&self, f: defmt::Formatter) {
600 #[derive(defmt :: Format)]
601 struct Odr {
602 odr: [super::vals::Odr; 16usize],
603 }
604 let proxy = Odr {
605 odr: [
606 self.odr(0usize),
607 self.odr(1usize),
608 self.odr(2usize),
609 self.odr(3usize),
610 self.odr(4usize),
611 self.odr(5usize),
612 self.odr(6usize),
613 self.odr(7usize),
614 self.odr(8usize),
615 self.odr(9usize),
616 self.odr(10usize),
617 self.odr(11usize),
618 self.odr(12usize),
619 self.odr(13usize),
620 self.odr(14usize),
621 self.odr(15usize),
622 ],
623 };
624 defmt::write!(f, "{}", proxy)
625 }
626 }
627 #[doc = "GPIO port output speed register"]
628 #[repr(transparent)]
629 #[derive(Copy, Clone, Eq, PartialEq)]
630 pub struct Ospeedr(pub u32);
631 impl Ospeedr {
632 #[doc = "Port x configuration bits (y = 0..15)"]
633 #[inline(always)]
634 pub const fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
635 assert!(n < 16usize);
636 let offs = 0usize + n * 2usize;
637 let val = (self.0 >> offs) & 0x03;
638 super::vals::Ospeedr::from_bits(val as u8)
639 }
640 #[doc = "Port x configuration bits (y = 0..15)"]
641 #[inline(always)]
642 pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
643 assert!(n < 16usize);
644 let offs = 0usize + n * 2usize;
645 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
646 }
647 }
648 impl Default for Ospeedr {
649 #[inline(always)]
650 fn default() -> Ospeedr {
651 Ospeedr(0)
652 }
653 }
654 impl core::fmt::Debug for Ospeedr {
655 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
656 f.debug_struct("Ospeedr")
657 .field(
658 "ospeedr",
659 &[
660 self.ospeedr(0usize),
661 self.ospeedr(1usize),
662 self.ospeedr(2usize),
663 self.ospeedr(3usize),
664 self.ospeedr(4usize),
665 self.ospeedr(5usize),
666 self.ospeedr(6usize),
667 self.ospeedr(7usize),
668 self.ospeedr(8usize),
669 self.ospeedr(9usize),
670 self.ospeedr(10usize),
671 self.ospeedr(11usize),
672 self.ospeedr(12usize),
673 self.ospeedr(13usize),
674 self.ospeedr(14usize),
675 self.ospeedr(15usize),
676 ],
677 )
678 .finish()
679 }
680 }
681 #[cfg(feature = "defmt")]
682 impl defmt::Format for Ospeedr {
683 fn format(&self, f: defmt::Formatter) {
684 #[derive(defmt :: Format)]
685 struct Ospeedr {
686 ospeedr: [super::vals::Ospeedr; 16usize],
687 }
688 let proxy = Ospeedr {
689 ospeedr: [
690 self.ospeedr(0usize),
691 self.ospeedr(1usize),
692 self.ospeedr(2usize),
693 self.ospeedr(3usize),
694 self.ospeedr(4usize),
695 self.ospeedr(5usize),
696 self.ospeedr(6usize),
697 self.ospeedr(7usize),
698 self.ospeedr(8usize),
699 self.ospeedr(9usize),
700 self.ospeedr(10usize),
701 self.ospeedr(11usize),
702 self.ospeedr(12usize),
703 self.ospeedr(13usize),
704 self.ospeedr(14usize),
705 self.ospeedr(15usize),
706 ],
707 };
708 defmt::write!(f, "{}", proxy)
709 }
710 }
711 #[doc = "GPIO port output type register"]
712 #[repr(transparent)]
713 #[derive(Copy, Clone, Eq, PartialEq)]
714 pub struct Otyper(pub u32);
715 impl Otyper {
716 #[doc = "Port x configuration bits (y = 0..15)"]
717 #[inline(always)]
718 pub const fn ot(&self, n: usize) -> super::vals::Ot {
719 assert!(n < 16usize);
720 let offs = 0usize + n * 1usize;
721 let val = (self.0 >> offs) & 0x01;
722 super::vals::Ot::from_bits(val as u8)
723 }
724 #[doc = "Port x configuration bits (y = 0..15)"]
725 #[inline(always)]
726 pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) {
727 assert!(n < 16usize);
728 let offs = 0usize + n * 1usize;
729 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
730 }
731 }
732 impl Default for Otyper {
733 #[inline(always)]
734 fn default() -> Otyper {
735 Otyper(0)
736 }
737 }
738 impl core::fmt::Debug for Otyper {
739 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
740 f.debug_struct("Otyper")
741 .field(
742 "ot",
743 &[
744 self.ot(0usize),
745 self.ot(1usize),
746 self.ot(2usize),
747 self.ot(3usize),
748 self.ot(4usize),
749 self.ot(5usize),
750 self.ot(6usize),
751 self.ot(7usize),
752 self.ot(8usize),
753 self.ot(9usize),
754 self.ot(10usize),
755 self.ot(11usize),
756 self.ot(12usize),
757 self.ot(13usize),
758 self.ot(14usize),
759 self.ot(15usize),
760 ],
761 )
762 .finish()
763 }
764 }
765 #[cfg(feature = "defmt")]
766 impl defmt::Format for Otyper {
767 fn format(&self, f: defmt::Formatter) {
768 #[derive(defmt :: Format)]
769 struct Otyper {
770 ot: [super::vals::Ot; 16usize],
771 }
772 let proxy = Otyper {
773 ot: [
774 self.ot(0usize),
775 self.ot(1usize),
776 self.ot(2usize),
777 self.ot(3usize),
778 self.ot(4usize),
779 self.ot(5usize),
780 self.ot(6usize),
781 self.ot(7usize),
782 self.ot(8usize),
783 self.ot(9usize),
784 self.ot(10usize),
785 self.ot(11usize),
786 self.ot(12usize),
787 self.ot(13usize),
788 self.ot(14usize),
789 self.ot(15usize),
790 ],
791 };
792 defmt::write!(f, "{}", proxy)
793 }
794 }
795 #[doc = "GPIO port pull-up/pull-down register"]
796 #[repr(transparent)]
797 #[derive(Copy, Clone, Eq, PartialEq)]
798 pub struct Pupdr(pub u32);
799 impl Pupdr {
800 #[doc = "Port x configuration bits (y = 0..15)"]
801 #[inline(always)]
802 pub const fn pupdr(&self, n: usize) -> super::vals::Pupdr {
803 assert!(n < 16usize);
804 let offs = 0usize + n * 2usize;
805 let val = (self.0 >> offs) & 0x03;
806 super::vals::Pupdr::from_bits(val as u8)
807 }
808 #[doc = "Port x configuration bits (y = 0..15)"]
809 #[inline(always)]
810 pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) {
811 assert!(n < 16usize);
812 let offs = 0usize + n * 2usize;
813 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
814 }
815 }
816 impl Default for Pupdr {
817 #[inline(always)]
818 fn default() -> Pupdr {
819 Pupdr(0)
820 }
821 }
822 impl core::fmt::Debug for Pupdr {
823 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824 f.debug_struct("Pupdr")
825 .field(
826 "pupdr",
827 &[
828 self.pupdr(0usize),
829 self.pupdr(1usize),
830 self.pupdr(2usize),
831 self.pupdr(3usize),
832 self.pupdr(4usize),
833 self.pupdr(5usize),
834 self.pupdr(6usize),
835 self.pupdr(7usize),
836 self.pupdr(8usize),
837 self.pupdr(9usize),
838 self.pupdr(10usize),
839 self.pupdr(11usize),
840 self.pupdr(12usize),
841 self.pupdr(13usize),
842 self.pupdr(14usize),
843 self.pupdr(15usize),
844 ],
845 )
846 .finish()
847 }
848 }
849 #[cfg(feature = "defmt")]
850 impl defmt::Format for Pupdr {
851 fn format(&self, f: defmt::Formatter) {
852 #[derive(defmt :: Format)]
853 struct Pupdr {
854 pupdr: [super::vals::Pupdr; 16usize],
855 }
856 let proxy = Pupdr {
857 pupdr: [
858 self.pupdr(0usize),
859 self.pupdr(1usize),
860 self.pupdr(2usize),
861 self.pupdr(3usize),
862 self.pupdr(4usize),
863 self.pupdr(5usize),
864 self.pupdr(6usize),
865 self.pupdr(7usize),
866 self.pupdr(8usize),
867 self.pupdr(9usize),
868 self.pupdr(10usize),
869 self.pupdr(11usize),
870 self.pupdr(12usize),
871 self.pupdr(13usize),
872 self.pupdr(14usize),
873 self.pupdr(15usize),
874 ],
875 };
876 defmt::write!(f, "{}", proxy)
877 }
878 }
879}
880pub mod vals {
881 #[repr(u8)]
882 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
883 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
884 pub enum Idr {
885 #[doc = "Input is logic low"]
886 LOW = 0x0,
887 #[doc = "Input is logic high"]
888 HIGH = 0x01,
889 }
890 impl Idr {
891 #[inline(always)]
892 pub const fn from_bits(val: u8) -> Idr {
893 unsafe { core::mem::transmute(val & 0x01) }
894 }
895 #[inline(always)]
896 pub const fn to_bits(self) -> u8 {
897 unsafe { core::mem::transmute(self) }
898 }
899 }
900 impl From<u8> for Idr {
901 #[inline(always)]
902 fn from(val: u8) -> Idr {
903 Idr::from_bits(val)
904 }
905 }
906 impl From<Idr> for u8 {
907 #[inline(always)]
908 fn from(val: Idr) -> u8 {
909 Idr::to_bits(val)
910 }
911 }
912 #[repr(u8)]
913 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
914 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
915 pub enum Moder {
916 #[doc = "Input mode (reset state)"]
917 INPUT = 0x0,
918 #[doc = "General purpose output mode"]
919 OUTPUT = 0x01,
920 #[doc = "Alternate function mode"]
921 ALTERNATE = 0x02,
922 #[doc = "Analog mode"]
923 ANALOG = 0x03,
924 }
925 impl Moder {
926 #[inline(always)]
927 pub const fn from_bits(val: u8) -> Moder {
928 unsafe { core::mem::transmute(val & 0x03) }
929 }
930 #[inline(always)]
931 pub const fn to_bits(self) -> u8 {
932 unsafe { core::mem::transmute(self) }
933 }
934 }
935 impl From<u8> for Moder {
936 #[inline(always)]
937 fn from(val: u8) -> Moder {
938 Moder::from_bits(val)
939 }
940 }
941 impl From<Moder> for u8 {
942 #[inline(always)]
943 fn from(val: Moder) -> u8 {
944 Moder::to_bits(val)
945 }
946 }
947 #[repr(u8)]
948 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
949 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
950 pub enum Odr {
951 #[doc = "Set output to logic low"]
952 LOW = 0x0,
953 #[doc = "Set output to logic high"]
954 HIGH = 0x01,
955 }
956 impl Odr {
957 #[inline(always)]
958 pub const fn from_bits(val: u8) -> Odr {
959 unsafe { core::mem::transmute(val & 0x01) }
960 }
961 #[inline(always)]
962 pub const fn to_bits(self) -> u8 {
963 unsafe { core::mem::transmute(self) }
964 }
965 }
966 impl From<u8> for Odr {
967 #[inline(always)]
968 fn from(val: u8) -> Odr {
969 Odr::from_bits(val)
970 }
971 }
972 impl From<Odr> for u8 {
973 #[inline(always)]
974 fn from(val: Odr) -> u8 {
975 Odr::to_bits(val)
976 }
977 }
978 #[repr(u8)]
979 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
980 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
981 pub enum Ospeedr {
982 #[doc = "Low speed"]
983 LOW_SPEED = 0x0,
984 #[doc = "Medium speed"]
985 MEDIUM_SPEED = 0x01,
986 #[doc = "High speed"]
987 HIGH_SPEED = 0x02,
988 #[doc = "Very high speed"]
989 VERY_HIGH_SPEED = 0x03,
990 }
991 impl Ospeedr {
992 #[inline(always)]
993 pub const fn from_bits(val: u8) -> Ospeedr {
994 unsafe { core::mem::transmute(val & 0x03) }
995 }
996 #[inline(always)]
997 pub const fn to_bits(self) -> u8 {
998 unsafe { core::mem::transmute(self) }
999 }
1000 }
1001 impl From<u8> for Ospeedr {
1002 #[inline(always)]
1003 fn from(val: u8) -> Ospeedr {
1004 Ospeedr::from_bits(val)
1005 }
1006 }
1007 impl From<Ospeedr> for u8 {
1008 #[inline(always)]
1009 fn from(val: Ospeedr) -> u8 {
1010 Ospeedr::to_bits(val)
1011 }
1012 }
1013 #[repr(u8)]
1014 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1015 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1016 pub enum Ot {
1017 #[doc = "Output push-pull (reset state)"]
1018 PUSH_PULL = 0x0,
1019 #[doc = "Output open-drain"]
1020 OPEN_DRAIN = 0x01,
1021 }
1022 impl Ot {
1023 #[inline(always)]
1024 pub const fn from_bits(val: u8) -> Ot {
1025 unsafe { core::mem::transmute(val & 0x01) }
1026 }
1027 #[inline(always)]
1028 pub const fn to_bits(self) -> u8 {
1029 unsafe { core::mem::transmute(self) }
1030 }
1031 }
1032 impl From<u8> for Ot {
1033 #[inline(always)]
1034 fn from(val: u8) -> Ot {
1035 Ot::from_bits(val)
1036 }
1037 }
1038 impl From<Ot> for u8 {
1039 #[inline(always)]
1040 fn from(val: Ot) -> u8 {
1041 Ot::to_bits(val)
1042 }
1043 }
1044 #[repr(u8)]
1045 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1046 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1047 pub enum Pupdr {
1048 #[doc = "No pull-up, pull-down"]
1049 FLOATING = 0x0,
1050 #[doc = "Pull-up"]
1051 PULL_UP = 0x01,
1052 #[doc = "Pull-down"]
1053 PULL_DOWN = 0x02,
1054 _RESERVED_3 = 0x03,
1055 }
1056 impl Pupdr {
1057 #[inline(always)]
1058 pub const fn from_bits(val: u8) -> Pupdr {
1059 unsafe { core::mem::transmute(val & 0x03) }
1060 }
1061 #[inline(always)]
1062 pub const fn to_bits(self) -> u8 {
1063 unsafe { core::mem::transmute(self) }
1064 }
1065 }
1066 impl From<u8> for Pupdr {
1067 #[inline(always)]
1068 fn from(val: u8) -> Pupdr {
1069 Pupdr::from_bits(val)
1070 }
1071 }
1072 impl From<Pupdr> for u8 {
1073 #[inline(always)]
1074 fn from(val: Pupdr) -> u8 {
1075 Pupdr::to_bits(val)
1076 }
1077 }
1078}
1079