1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "HSPI."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Hspi {
9 ptr: *mut u8,
10}
11unsafe impl Send for Hspi {}
12unsafe impl Sync for Hspi {}
13impl Hspi {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "HSPI control register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "HSPI device configuration register 1."]
28 #[inline(always)]
29 pub const fn dcr1(self) -> crate::common::Reg<regs::Dcr1, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
31 }
32 #[doc = "HSPI device configuration register 2."]
33 #[inline(always)]
34 pub const fn dcr2(self) -> crate::common::Reg<regs::Dcr2, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
36 }
37 #[doc = "HSPI device configuration register 3."]
38 #[inline(always)]
39 pub const fn dcr3(self) -> crate::common::Reg<regs::Dcr3, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
41 }
42 #[doc = "HSPI device configuration register 4."]
43 #[inline(always)]
44 pub const fn dcr4(self) -> crate::common::Reg<regs::Dcr4, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
46 }
47 #[inline(always)]
48 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
49 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
50 }
51 #[inline(always)]
52 pub const fn fcr(self) -> crate::common::Reg<regs::Fcr, crate::common::RW> {
53 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
54 }
55 #[doc = "HSPI data length register."]
56 #[inline(always)]
57 pub const fn dlr(self) -> crate::common::Reg<regs::Dlr, crate::common::RW> {
58 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
59 }
60 #[inline(always)]
61 pub const fn ar(self) -> crate::common::Reg<regs::Ar, crate::common::RW> {
62 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
63 }
64 #[inline(always)]
65 pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::RW> {
66 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
67 }
68 #[doc = "HSPI polling status mask register."]
69 #[inline(always)]
70 pub const fn psmkr(self) -> crate::common::Reg<regs::Psmkr, crate::common::RW> {
71 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
72 }
73 #[doc = "HSPI polling status match register."]
74 #[inline(always)]
75 pub const fn psmar(self) -> crate::common::Reg<regs::Psmar, crate::common::RW> {
76 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
77 }
78 #[doc = "HSPI polling interval register."]
79 #[inline(always)]
80 pub const fn pir(self) -> crate::common::Reg<regs::Pir, crate::common::RW> {
81 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
82 }
83 #[doc = "HSPI communication configuration register."]
84 #[inline(always)]
85 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
86 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) }
87 }
88 #[doc = "HSPI timing configuration register."]
89 #[inline(always)]
90 pub const fn tcr(self) -> crate::common::Reg<regs::Tcr, crate::common::RW> {
91 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) }
92 }
93 #[doc = "HSPI instruction register."]
94 #[inline(always)]
95 pub const fn ir(self) -> crate::common::Reg<regs::Ir, crate::common::RW> {
96 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) }
97 }
98 #[doc = "HSPI alternate bytes register."]
99 #[inline(always)]
100 pub const fn abr(self) -> crate::common::Reg<regs::Abr, crate::common::RW> {
101 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0120usize) as _) }
102 }
103 #[doc = "HSPI low-power timeout register."]
104 #[inline(always)]
105 pub const fn lptr(self) -> crate::common::Reg<regs::Lptr, crate::common::RW> {
106 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize) as _) }
107 }
108 #[doc = "HSPI wrap communication configuration register."]
109 #[inline(always)]
110 pub const fn wpccr(self) -> crate::common::Reg<regs::Wpccr, crate::common::RW> {
111 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) }
112 }
113 #[doc = "HSPI wrap timing configuration register."]
114 #[inline(always)]
115 pub const fn wptcr(self) -> crate::common::Reg<regs::Wptcr, crate::common::RW> {
116 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) }
117 }
118 #[doc = "HSPI wrap instruction register."]
119 #[inline(always)]
120 pub const fn wpir(self) -> crate::common::Reg<regs::Wpir, crate::common::RW> {
121 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) }
122 }
123 #[doc = "HSPI wrap alternate bytes register."]
124 #[inline(always)]
125 pub const fn wpabr(self) -> crate::common::Reg<regs::Wpabr, crate::common::RW> {
126 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) }
127 }
128 #[doc = "HSPI write communication configuration register."]
129 #[inline(always)]
130 pub const fn wccr(self) -> crate::common::Reg<regs::Wccr, crate::common::RW> {
131 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0180usize) as _) }
132 }
133 #[doc = "HSPI write timing configuration register."]
134 #[inline(always)]
135 pub const fn wtcr(self) -> crate::common::Reg<regs::Wtcr, crate::common::RW> {
136 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0188usize) as _) }
137 }
138 #[doc = "HSPI write instruction register."]
139 #[inline(always)]
140 pub const fn wir(self) -> crate::common::Reg<regs::Wir, crate::common::RW> {
141 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0190usize) as _) }
142 }
143 #[doc = "HSPI write alternate bytes register."]
144 #[inline(always)]
145 pub const fn wabr(self) -> crate::common::Reg<regs::Wabr, crate::common::RW> {
146 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01a0usize) as _) }
147 }
148 #[doc = "HSPI HyperBus latency configuration register."]
149 #[inline(always)]
150 pub const fn hlcr(self) -> crate::common::Reg<regs::Hlcr, crate::common::RW> {
151 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) }
152 }
153 #[doc = "HSPI full-cycle calibration configuration."]
154 #[inline(always)]
155 pub const fn calfcr(self) -> crate::common::Reg<regs::Calfcr, crate::common::RW> {
156 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0210usize) as _) }
157 }
158 #[doc = "HSPI DLL master calibration configuration."]
159 #[inline(always)]
160 pub const fn calmr(self) -> crate::common::Reg<regs::Calmr, crate::common::RW> {
161 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0218usize) as _) }
162 }
163 #[doc = "HSPI DLL slave output calibration configuration."]
164 #[inline(always)]
165 pub const fn calsor(self) -> crate::common::Reg<regs::Calsor, crate::common::RW> {
166 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0220usize) as _) }
167 }
168 #[doc = "HSPI DLL slave input calibration configuration."]
169 #[inline(always)]
170 pub const fn calsir(self) -> crate::common::Reg<regs::Calsir, crate::common::RW> {
171 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0228usize) as _) }
172 }
173}
174pub mod regs {
175 #[doc = "HSPI alternate bytes register."]
176 #[repr(transparent)]
177 #[derive(Copy, Clone, Eq, PartialEq)]
178 pub struct Abr(pub u32);
179 impl Abr {
180 #[doc = "31: 0\\]: Alternate bytes Optional data to be send to the external SPI device right after the address."]
181 #[inline(always)]
182 pub const fn alternate(&self) -> u32 {
183 let val = (self.0 >> 0usize) & 0xffff_ffff;
184 val as u32
185 }
186 #[doc = "31: 0\\]: Alternate bytes Optional data to be send to the external SPI device right after the address."]
187 #[inline(always)]
188 pub fn set_alternate(&mut self, val: u32) {
189 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
190 }
191 }
192 impl Default for Abr {
193 #[inline(always)]
194 fn default() -> Abr {
195 Abr(0)
196 }
197 }
198 impl core::fmt::Debug for Abr {
199 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
200 f.debug_struct("Abr").field("alternate", &self.alternate()).finish()
201 }
202 }
203 #[cfg(feature = "defmt")]
204 impl defmt::Format for Abr {
205 fn format(&self, f: defmt::Formatter) {
206 #[derive(defmt :: Format)]
207 struct Abr {
208 alternate: u32,
209 }
210 let proxy = Abr {
211 alternate: self.alternate(),
212 };
213 defmt::write!(f, "{}", proxy)
214 }
215 }
216 #[repr(transparent)]
217 #[derive(Copy, Clone, Eq, PartialEq)]
218 pub struct Ar(pub u32);
219 impl Ar {
220 #[doc = "Address Address to be sent to the external device. In HyperBus mode, this field must be even as this protocol is 16-bit word oriented. In dual-memory mode, AR\\[0\\]
221is forced to 1. Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode)."]
222 #[inline(always)]
223 pub const fn address(&self) -> u32 {
224 let val = (self.0 >> 0usize) & 0xffff_ffff;
225 val as u32
226 }
227 #[doc = "Address Address to be sent to the external device. In HyperBus mode, this field must be even as this protocol is 16-bit word oriented. In dual-memory mode, AR\\[0\\]
228is forced to 1. Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode)."]
229 #[inline(always)]
230 pub fn set_address(&mut self, val: u32) {
231 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
232 }
233 }
234 impl Default for Ar {
235 #[inline(always)]
236 fn default() -> Ar {
237 Ar(0)
238 }
239 }
240 impl core::fmt::Debug for Ar {
241 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
242 f.debug_struct("Ar").field("address", &self.address()).finish()
243 }
244 }
245 #[cfg(feature = "defmt")]
246 impl defmt::Format for Ar {
247 fn format(&self, f: defmt::Formatter) {
248 #[derive(defmt :: Format)]
249 struct Ar {
250 address: u32,
251 }
252 let proxy = Ar {
253 address: self.address(),
254 };
255 defmt::write!(f, "{}", proxy)
256 }
257 }
258 #[doc = "HSPI full-cycle calibration configuration."]
259 #[repr(transparent)]
260 #[derive(Copy, Clone, Eq, PartialEq)]
261 pub struct Calfcr(pub u32);
262 impl Calfcr {
263 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
264 #[inline(always)]
265 pub const fn fine(&self) -> u8 {
266 let val = (self.0 >> 0usize) & 0x7f;
267 val as u8
268 }
269 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
270 #[inline(always)]
271 pub fn set_fine(&mut self, val: u8) {
272 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
273 }
274 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
275 #[inline(always)]
276 pub const fn coarse(&self) -> u8 {
277 let val = (self.0 >> 16usize) & 0x1f;
278 val as u8
279 }
280 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
281 #[inline(always)]
282 pub fn set_coarse(&mut self, val: u8) {
283 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
284 }
285 #[doc = "Max value This bit gets set when the memory-clock period is outside the range of DLLM, in which case CALFCR and CALSR are updated with the values for the maximum delay."]
286 #[inline(always)]
287 pub const fn calmax(&self) -> bool {
288 let val = (self.0 >> 31usize) & 0x01;
289 val != 0
290 }
291 #[doc = "Max value This bit gets set when the memory-clock period is outside the range of DLLM, in which case CALFCR and CALSR are updated with the values for the maximum delay."]
292 #[inline(always)]
293 pub fn set_calmax(&mut self, val: bool) {
294 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
295 }
296 }
297 impl Default for Calfcr {
298 #[inline(always)]
299 fn default() -> Calfcr {
300 Calfcr(0)
301 }
302 }
303 impl core::fmt::Debug for Calfcr {
304 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
305 f.debug_struct("Calfcr")
306 .field("fine", &self.fine())
307 .field("coarse", &self.coarse())
308 .field("calmax", &self.calmax())
309 .finish()
310 }
311 }
312 #[cfg(feature = "defmt")]
313 impl defmt::Format for Calfcr {
314 fn format(&self, f: defmt::Formatter) {
315 #[derive(defmt :: Format)]
316 struct Calfcr {
317 fine: u8,
318 coarse: u8,
319 calmax: bool,
320 }
321 let proxy = Calfcr {
322 fine: self.fine(),
323 coarse: self.coarse(),
324 calmax: self.calmax(),
325 };
326 defmt::write!(f, "{}", proxy)
327 }
328 }
329 #[doc = "HSPI DLL master calibration configuration."]
330 #[repr(transparent)]
331 #[derive(Copy, Clone, Eq, PartialEq)]
332 pub struct Calmr(pub u32);
333 impl Calmr {
334 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
335 #[inline(always)]
336 pub const fn fine(&self) -> u8 {
337 let val = (self.0 >> 0usize) & 0x7f;
338 val as u8
339 }
340 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
341 #[inline(always)]
342 pub fn set_fine(&mut self, val: u8) {
343 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
344 }
345 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
346 #[inline(always)]
347 pub const fn coarse(&self) -> u8 {
348 let val = (self.0 >> 16usize) & 0x1f;
349 val as u8
350 }
351 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
352 #[inline(always)]
353 pub fn set_coarse(&mut self, val: u8) {
354 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
355 }
356 }
357 impl Default for Calmr {
358 #[inline(always)]
359 fn default() -> Calmr {
360 Calmr(0)
361 }
362 }
363 impl core::fmt::Debug for Calmr {
364 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
365 f.debug_struct("Calmr")
366 .field("fine", &self.fine())
367 .field("coarse", &self.coarse())
368 .finish()
369 }
370 }
371 #[cfg(feature = "defmt")]
372 impl defmt::Format for Calmr {
373 fn format(&self, f: defmt::Formatter) {
374 #[derive(defmt :: Format)]
375 struct Calmr {
376 fine: u8,
377 coarse: u8,
378 }
379 let proxy = Calmr {
380 fine: self.fine(),
381 coarse: self.coarse(),
382 };
383 defmt::write!(f, "{}", proxy)
384 }
385 }
386 #[doc = "HSPI DLL slave input calibration configuration."]
387 #[repr(transparent)]
388 #[derive(Copy, Clone, Eq, PartialEq)]
389 pub struct Calsir(pub u32);
390 impl Calsir {
391 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
392 #[inline(always)]
393 pub const fn fine(&self) -> u8 {
394 let val = (self.0 >> 0usize) & 0x7f;
395 val as u8
396 }
397 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
398 #[inline(always)]
399 pub fn set_fine(&mut self, val: u8) {
400 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
401 }
402 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
403 #[inline(always)]
404 pub const fn coarse(&self) -> u8 {
405 let val = (self.0 >> 16usize) & 0x1f;
406 val as u8
407 }
408 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
409 #[inline(always)]
410 pub fn set_coarse(&mut self, val: u8) {
411 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
412 }
413 }
414 impl Default for Calsir {
415 #[inline(always)]
416 fn default() -> Calsir {
417 Calsir(0)
418 }
419 }
420 impl core::fmt::Debug for Calsir {
421 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
422 f.debug_struct("Calsir")
423 .field("fine", &self.fine())
424 .field("coarse", &self.coarse())
425 .finish()
426 }
427 }
428 #[cfg(feature = "defmt")]
429 impl defmt::Format for Calsir {
430 fn format(&self, f: defmt::Formatter) {
431 #[derive(defmt :: Format)]
432 struct Calsir {
433 fine: u8,
434 coarse: u8,
435 }
436 let proxy = Calsir {
437 fine: self.fine(),
438 coarse: self.coarse(),
439 };
440 defmt::write!(f, "{}", proxy)
441 }
442 }
443 #[doc = "HSPI DLL slave output calibration configuration."]
444 #[repr(transparent)]
445 #[derive(Copy, Clone, Eq, PartialEq)]
446 pub struct Calsor(pub u32);
447 impl Calsor {
448 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
449 #[inline(always)]
450 pub const fn fine(&self) -> u8 {
451 let val = (self.0 >> 0usize) & 0x7f;
452 val as u8
453 }
454 #[doc = "6: 0\\]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
455 #[inline(always)]
456 pub fn set_fine(&mut self, val: u8) {
457 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
458 }
459 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
460 #[inline(always)]
461 pub const fn coarse(&self) -> u8 {
462 let val = (self.0 >> 16usize) & 0x1f;
463 val as u8
464 }
465 #[doc = "4: 0\\]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet)."]
466 #[inline(always)]
467 pub fn set_coarse(&mut self, val: u8) {
468 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
469 }
470 }
471 impl Default for Calsor {
472 #[inline(always)]
473 fn default() -> Calsor {
474 Calsor(0)
475 }
476 }
477 impl core::fmt::Debug for Calsor {
478 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
479 f.debug_struct("Calsor")
480 .field("fine", &self.fine())
481 .field("coarse", &self.coarse())
482 .finish()
483 }
484 }
485 #[cfg(feature = "defmt")]
486 impl defmt::Format for Calsor {
487 fn format(&self, f: defmt::Formatter) {
488 #[derive(defmt :: Format)]
489 struct Calsor {
490 fine: u8,
491 coarse: u8,
492 }
493 let proxy = Calsor {
494 fine: self.fine(),
495 coarse: self.coarse(),
496 };
497 defmt::write!(f, "{}", proxy)
498 }
499 }
500 #[doc = "HSPI communication configuration register."]
501 #[repr(transparent)]
502 #[derive(Copy, Clone, Eq, PartialEq)]
503 pub struct Ccr(pub u32);
504 impl Ccr {
505 #[doc = "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved."]
506 #[inline(always)]
507 pub const fn imode(&self) -> u8 {
508 let val = (self.0 >> 0usize) & 0x07;
509 val as u8
510 }
511 #[doc = "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved."]
512 #[inline(always)]
513 pub fn set_imode(&mut self, val: u8) {
514 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
515 }
516 #[doc = "Instruction double transfer rate This bit sets the DTR mode for the instruction phase."]
517 #[inline(always)]
518 pub const fn idtr(&self) -> bool {
519 let val = (self.0 >> 3usize) & 0x01;
520 val != 0
521 }
522 #[doc = "Instruction double transfer rate This bit sets the DTR mode for the instruction phase."]
523 #[inline(always)]
524 pub fn set_idtr(&mut self, val: bool) {
525 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
526 }
527 #[doc = "Instruction size This bit defines instruction size."]
528 #[inline(always)]
529 pub const fn isize(&self) -> u8 {
530 let val = (self.0 >> 4usize) & 0x03;
531 val as u8
532 }
533 #[doc = "Instruction size This bit defines instruction size."]
534 #[inline(always)]
535 pub fn set_isize(&mut self, val: u8) {
536 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
537 }
538 #[doc = "Address mode This field defines the address phase mode of operation. 101-111: Reserved."]
539 #[inline(always)]
540 pub const fn admode(&self) -> u8 {
541 let val = (self.0 >> 8usize) & 0x07;
542 val as u8
543 }
544 #[doc = "Address mode This field defines the address phase mode of operation. 101-111: Reserved."]
545 #[inline(always)]
546 pub fn set_admode(&mut self, val: u8) {
547 self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
548 }
549 #[doc = "Address double transfer rate This bit sets the DTR mode for the address phase."]
550 #[inline(always)]
551 pub const fn addtr(&self) -> bool {
552 let val = (self.0 >> 11usize) & 0x01;
553 val != 0
554 }
555 #[doc = "Address double transfer rate This bit sets the DTR mode for the address phase."]
556 #[inline(always)]
557 pub fn set_addtr(&mut self, val: bool) {
558 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
559 }
560 #[doc = "Address size This field defines address size."]
561 #[inline(always)]
562 pub const fn adsize(&self) -> u8 {
563 let val = (self.0 >> 12usize) & 0x03;
564 val as u8
565 }
566 #[doc = "Address size This field defines address size."]
567 #[inline(always)]
568 pub fn set_adsize(&mut self, val: u8) {
569 self.0 = (self.0 & !(0x03 << 12usize)) | (((val as u32) & 0x03) << 12usize);
570 }
571 #[doc = "Alternate-byte mode This field defines the alternate byte phase mode of operation. 100-111: Reserved."]
572 #[inline(always)]
573 pub const fn abmode(&self) -> u8 {
574 let val = (self.0 >> 16usize) & 0x07;
575 val as u8
576 }
577 #[doc = "Alternate-byte mode This field defines the alternate byte phase mode of operation. 100-111: Reserved."]
578 #[inline(always)]
579 pub fn set_abmode(&mut self, val: u8) {
580 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
581 }
582 #[doc = "Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0."]
583 #[inline(always)]
584 pub const fn abdtr(&self) -> bool {
585 let val = (self.0 >> 19usize) & 0x01;
586 val != 0
587 }
588 #[doc = "Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0."]
589 #[inline(always)]
590 pub fn set_abdtr(&mut self, val: bool) {
591 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
592 }
593 #[doc = "Alternate bytes size This bit defines alternate bytes size."]
594 #[inline(always)]
595 pub const fn absize(&self) -> u8 {
596 let val = (self.0 >> 20usize) & 0x03;
597 val as u8
598 }
599 #[doc = "Alternate bytes size This bit defines alternate bytes size."]
600 #[inline(always)]
601 pub fn set_absize(&mut self, val: u8) {
602 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
603 }
604 #[doc = "Data mode This field defines the data phase mode of operation. 110-111: Reserved."]
605 #[inline(always)]
606 pub const fn dmode(&self) -> u8 {
607 let val = (self.0 >> 24usize) & 0x07;
608 val as u8
609 }
610 #[doc = "Data mode This field defines the data phase mode of operation. 110-111: Reserved."]
611 #[inline(always)]
612 pub fn set_dmode(&mut self, val: u8) {
613 self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize);
614 }
615 #[doc = "Data double transfer rate This bit sets the DTR mode for the data phase."]
616 #[inline(always)]
617 pub const fn ddtr(&self) -> bool {
618 let val = (self.0 >> 27usize) & 0x01;
619 val != 0
620 }
621 #[doc = "Data double transfer rate This bit sets the DTR mode for the data phase."]
622 #[inline(always)]
623 pub fn set_ddtr(&mut self, val: bool) {
624 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
625 }
626 #[doc = "DQS enable This bit enables the data strobe management."]
627 #[inline(always)]
628 pub const fn dqse(&self) -> bool {
629 let val = (self.0 >> 29usize) & 0x01;
630 val != 0
631 }
632 #[doc = "DQS enable This bit enables the data strobe management."]
633 #[inline(always)]
634 pub fn set_dqse(&mut self, val: bool) {
635 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
636 }
637 #[doc = "Send instruction only once mode This bit has no effect when IMODE = 00 (see )."]
638 #[inline(always)]
639 pub const fn sioo(&self) -> bool {
640 let val = (self.0 >> 31usize) & 0x01;
641 val != 0
642 }
643 #[doc = "Send instruction only once mode This bit has no effect when IMODE = 00 (see )."]
644 #[inline(always)]
645 pub fn set_sioo(&mut self, val: bool) {
646 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
647 }
648 }
649 impl Default for Ccr {
650 #[inline(always)]
651 fn default() -> Ccr {
652 Ccr(0)
653 }
654 }
655 impl core::fmt::Debug for Ccr {
656 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
657 f.debug_struct("Ccr")
658 .field("imode", &self.imode())
659 .field("idtr", &self.idtr())
660 .field("isize", &self.isize())
661 .field("admode", &self.admode())
662 .field("addtr", &self.addtr())
663 .field("adsize", &self.adsize())
664 .field("abmode", &self.abmode())
665 .field("abdtr", &self.abdtr())
666 .field("absize", &self.absize())
667 .field("dmode", &self.dmode())
668 .field("ddtr", &self.ddtr())
669 .field("dqse", &self.dqse())
670 .field("sioo", &self.sioo())
671 .finish()
672 }
673 }
674 #[cfg(feature = "defmt")]
675 impl defmt::Format for Ccr {
676 fn format(&self, f: defmt::Formatter) {
677 #[derive(defmt :: Format)]
678 struct Ccr {
679 imode: u8,
680 idtr: bool,
681 isize: u8,
682 admode: u8,
683 addtr: bool,
684 adsize: u8,
685 abmode: u8,
686 abdtr: bool,
687 absize: u8,
688 dmode: u8,
689 ddtr: bool,
690 dqse: bool,
691 sioo: bool,
692 }
693 let proxy = Ccr {
694 imode: self.imode(),
695 idtr: self.idtr(),
696 isize: self.isize(),
697 admode: self.admode(),
698 addtr: self.addtr(),
699 adsize: self.adsize(),
700 abmode: self.abmode(),
701 abdtr: self.abdtr(),
702 absize: self.absize(),
703 dmode: self.dmode(),
704 ddtr: self.ddtr(),
705 dqse: self.dqse(),
706 sioo: self.sioo(),
707 };
708 defmt::write!(f, "{}", proxy)
709 }
710 }
711 #[doc = "HSPI control register."]
712 #[repr(transparent)]
713 #[derive(Copy, Clone, Eq, PartialEq)]
714 pub struct Cr(pub u32);
715 impl Cr {
716 #[doc = "Enable This bit enables the HSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active."]
717 #[inline(always)]
718 pub const fn en(&self) -> bool {
719 let val = (self.0 >> 0usize) & 0x01;
720 val != 0
721 }
722 #[doc = "Enable This bit enables the HSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active."]
723 #[inline(always)]
724 pub fn set_en(&mut self, val: bool) {
725 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
726 }
727 #[doc = "Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0."]
728 #[inline(always)]
729 pub const fn abort(&self) -> bool {
730 let val = (self.0 >> 1usize) & 0x01;
731 val != 0
732 }
733 #[doc = "Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0."]
734 #[inline(always)]
735 pub fn set_abort(&mut self, val: bool) {
736 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
737 }
738 #[doc = "DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation."]
739 #[inline(always)]
740 pub const fn dmaen(&self) -> bool {
741 let val = (self.0 >> 2usize) & 0x01;
742 val != 0
743 }
744 #[doc = "DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation."]
745 #[inline(always)]
746 pub fn set_dmaen(&mut self, val: bool) {
747 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
748 }
749 #[doc = "Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE\\[1:0\\] = 11) is selected. This bit enables the timeout counter."]
750 #[inline(always)]
751 pub const fn tcen(&self) -> bool {
752 let val = (self.0 >> 3usize) & 0x01;
753 val != 0
754 }
755 #[doc = "Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE\\[1:0\\] = 11) is selected. This bit enables the timeout counter."]
756 #[inline(always)]
757 pub fn set_tcen(&mut self, val: bool) {
758 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
759 }
760 #[doc = "Dual-memory mode This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity."]
761 #[inline(always)]
762 pub const fn dmm(&self) -> bool {
763 let val = (self.0 >> 6usize) & 0x01;
764 val != 0
765 }
766 #[doc = "Dual-memory mode This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity."]
767 #[inline(always)]
768 pub fn set_dmm(&mut self, val: bool) {
769 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
770 }
771 #[doc = "Memory select This bit is the mirror of bit 30. Refer to the description of MSEL\\[1:0\\]
772above. This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0."]
773 #[inline(always)]
774 pub const fn fsel(&self) -> bool {
775 let val = (self.0 >> 7usize) & 0x01;
776 val != 0
777 }
778 #[doc = "Memory select This bit is the mirror of bit 30. Refer to the description of MSEL\\[1:0\\]
779above. This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0."]
780 #[inline(always)]
781 pub fn set_fsel(&mut self, val: bool) {
782 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
783 }
784 #[doc = "FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES\\[5:0\\]
785value."]
786 #[inline(always)]
787 pub const fn fthres(&self) -> u8 {
788 let val = (self.0 >> 8usize) & 0x3f;
789 val as u8
790 }
791 #[doc = "FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES\\[5:0\\]
792value."]
793 #[inline(always)]
794 pub fn set_fthres(&mut self, val: u8) {
795 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
796 }
797 #[doc = "Transfer error interrupt enable This bit enables the transfer error interrupt."]
798 #[inline(always)]
799 pub const fn teie(&self) -> bool {
800 let val = (self.0 >> 16usize) & 0x01;
801 val != 0
802 }
803 #[doc = "Transfer error interrupt enable This bit enables the transfer error interrupt."]
804 #[inline(always)]
805 pub fn set_teie(&mut self, val: bool) {
806 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
807 }
808 #[doc = "Transfer complete interrupt enable This bit enables the transfer complete interrupt."]
809 #[inline(always)]
810 pub const fn tcie(&self) -> bool {
811 let val = (self.0 >> 17usize) & 0x01;
812 val != 0
813 }
814 #[doc = "Transfer complete interrupt enable This bit enables the transfer complete interrupt."]
815 #[inline(always)]
816 pub fn set_tcie(&mut self, val: bool) {
817 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
818 }
819 #[doc = "FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt."]
820 #[inline(always)]
821 pub const fn ftie(&self) -> bool {
822 let val = (self.0 >> 18usize) & 0x01;
823 val != 0
824 }
825 #[doc = "FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt."]
826 #[inline(always)]
827 pub fn set_ftie(&mut self, val: bool) {
828 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
829 }
830 #[doc = "Status match interrupt enable This bit enables the status match interrupt."]
831 #[inline(always)]
832 pub const fn smie(&self) -> bool {
833 let val = (self.0 >> 19usize) & 0x01;
834 val != 0
835 }
836 #[doc = "Status match interrupt enable This bit enables the status match interrupt."]
837 #[inline(always)]
838 pub fn set_smie(&mut self, val: bool) {
839 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
840 }
841 #[doc = "Timeout interrupt enable This bit enables the timeout interrupt."]
842 #[inline(always)]
843 pub const fn toie(&self) -> bool {
844 let val = (self.0 >> 20usize) & 0x01;
845 val != 0
846 }
847 #[doc = "Timeout interrupt enable This bit enables the timeout interrupt."]
848 #[inline(always)]
849 pub fn set_toie(&mut self, val: bool) {
850 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
851 }
852 #[doc = "Automatic-polling mode stop This bit determines if the automatic polling is stopped after a match."]
853 #[inline(always)]
854 pub const fn apms(&self) -> bool {
855 let val = (self.0 >> 22usize) & 0x01;
856 val != 0
857 }
858 #[doc = "Automatic-polling mode stop This bit determines if the automatic polling is stopped after a match."]
859 #[inline(always)]
860 pub fn set_apms(&mut self, val: bool) {
861 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
862 }
863 #[doc = "Polling match mode This bit indicates which method must be used to determine a match during the Automatic-polling mode."]
864 #[inline(always)]
865 pub const fn pmm(&self) -> bool {
866 let val = (self.0 >> 23usize) & 0x01;
867 val != 0
868 }
869 #[doc = "Polling match mode This bit indicates which method must be used to determine a match during the Automatic-polling mode."]
870 #[inline(always)]
871 pub fn set_pmm(&mut self, val: bool) {
872 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
873 }
874 #[doc = "Functional mode This field defines the HSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE\\[1:0\\]
875value. If FMODE\\[1:0\\]
876and FTHRES\\[4:0\\]
877are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state."]
878 #[inline(always)]
879 pub const fn fmode(&self) -> u8 {
880 let val = (self.0 >> 28usize) & 0x03;
881 val as u8
882 }
883 #[doc = "Functional mode This field defines the HSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE\\[1:0\\]
884value. If FMODE\\[1:0\\]
885and FTHRES\\[4:0\\]
886are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state."]
887 #[inline(always)]
888 pub fn set_fmode(&mut self, val: u8) {
889 self.0 = (self.0 & !(0x03 << 28usize)) | (((val as u32) & 0x03) << 28usize);
890 }
891 #[doc = "Flash select These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in singleâ\u{80}\u{91}memory configuration (when DMM = 0). - when in Quad mode: - when in Octal mode or Dual-quad mode: 0x: data exchanged over IO\\[7:0\\]
8921x: data exchanged over IO\\[15:8\\]
893These bits are ignored when in dual-octal configuration (data on 8 bits and DMM = 1) or 16â\u{80}\u{91}bit configuration (data exchanged over IO\\[15:0\\])."]
894 #[inline(always)]
895 pub const fn msel(&self) -> u8 {
896 let val = (self.0 >> 30usize) & 0x03;
897 val as u8
898 }
899 #[doc = "Flash select These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in singleâ\u{80}\u{91}memory configuration (when DMM = 0). - when in Quad mode: - when in Octal mode or Dual-quad mode: 0x: data exchanged over IO\\[7:0\\]
9001x: data exchanged over IO\\[15:8\\]
901These bits are ignored when in dual-octal configuration (data on 8 bits and DMM = 1) or 16â\u{80}\u{91}bit configuration (data exchanged over IO\\[15:0\\])."]
902 #[inline(always)]
903 pub fn set_msel(&mut self, val: u8) {
904 self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize);
905 }
906 }
907 impl Default for Cr {
908 #[inline(always)]
909 fn default() -> Cr {
910 Cr(0)
911 }
912 }
913 impl core::fmt::Debug for Cr {
914 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
915 f.debug_struct("Cr")
916 .field("en", &self.en())
917 .field("abort", &self.abort())
918 .field("dmaen", &self.dmaen())
919 .field("tcen", &self.tcen())
920 .field("dmm", &self.dmm())
921 .field("fsel", &self.fsel())
922 .field("fthres", &self.fthres())
923 .field("teie", &self.teie())
924 .field("tcie", &self.tcie())
925 .field("ftie", &self.ftie())
926 .field("smie", &self.smie())
927 .field("toie", &self.toie())
928 .field("apms", &self.apms())
929 .field("pmm", &self.pmm())
930 .field("fmode", &self.fmode())
931 .field("msel", &self.msel())
932 .finish()
933 }
934 }
935 #[cfg(feature = "defmt")]
936 impl defmt::Format for Cr {
937 fn format(&self, f: defmt::Formatter) {
938 #[derive(defmt :: Format)]
939 struct Cr {
940 en: bool,
941 abort: bool,
942 dmaen: bool,
943 tcen: bool,
944 dmm: bool,
945 fsel: bool,
946 fthres: u8,
947 teie: bool,
948 tcie: bool,
949 ftie: bool,
950 smie: bool,
951 toie: bool,
952 apms: bool,
953 pmm: bool,
954 fmode: u8,
955 msel: u8,
956 }
957 let proxy = Cr {
958 en: self.en(),
959 abort: self.abort(),
960 dmaen: self.dmaen(),
961 tcen: self.tcen(),
962 dmm: self.dmm(),
963 fsel: self.fsel(),
964 fthres: self.fthres(),
965 teie: self.teie(),
966 tcie: self.tcie(),
967 ftie: self.ftie(),
968 smie: self.smie(),
969 toie: self.toie(),
970 apms: self.apms(),
971 pmm: self.pmm(),
972 fmode: self.fmode(),
973 msel: self.msel(),
974 };
975 defmt::write!(f, "{}", proxy)
976 }
977 }
978 #[doc = "HSPI device configuration register 1."]
979 #[repr(transparent)]
980 #[derive(Copy, Clone, Eq, PartialEq)]
981 pub struct Dcr1(pub u32);
982 impl Dcr1 {
983 #[doc = "Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when nCS = 1)."]
984 #[inline(always)]
985 pub const fn ckmode(&self) -> bool {
986 let val = (self.0 >> 0usize) & 0x01;
987 val != 0
988 }
989 #[doc = "Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when nCS = 1)."]
990 #[inline(always)]
991 pub fn set_ckmode(&mut self, val: bool) {
992 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
993 }
994 #[doc = "Free running clock This bit configures the free running clock."]
995 #[inline(always)]
996 pub const fn frck(&self) -> bool {
997 let val = (self.0 >> 1usize) & 0x01;
998 val != 0
999 }
1000 #[doc = "Free running clock This bit configures the free running clock."]
1001 #[inline(always)]
1002 pub fn set_frck(&mut self, val: bool) {
1003 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1004 }
1005 #[doc = "Delay block bypass."]
1006 #[inline(always)]
1007 pub const fn dlybyp(&self) -> bool {
1008 let val = (self.0 >> 3usize) & 0x01;
1009 val != 0
1010 }
1011 #[doc = "Delay block bypass."]
1012 #[inline(always)]
1013 pub fn set_dlybyp(&mut self, val: bool) {
1014 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1015 }
1016 #[doc = "Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device. ... 63: nCS stays high for at least 64 cycles between external device commands. Note: When the extended CSHT timeout feature is not supported, CSHT\\[5:3\\]
1017are reserved and the number of cycles is limited to eight (refer to implementation)."]
1018 #[inline(always)]
1019 pub const fn csht(&self) -> u8 {
1020 let val = (self.0 >> 8usize) & 0x3f;
1021 val as u8
1022 }
1023 #[doc = "Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device. ... 63: nCS stays high for at least 64 cycles between external device commands. Note: When the extended CSHT timeout feature is not supported, CSHT\\[5:3\\]
1024are reserved and the number of cycles is limited to eight (refer to implementation)."]
1025 #[inline(always)]
1026 pub fn set_csht(&mut self, val: u8) {
1027 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
1028 }
1029 #[doc = "Device size This field defines the size of the external device using the following formula: Number of bytes in device = 2\\[DEVSIZE+1\\]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command mode, if DMM = 1, DEVSIZE\\[4:0\\]
1030indicates the total capacity of the two devices together."]
1031 #[inline(always)]
1032 pub const fn devsize(&self) -> u8 {
1033 let val = (self.0 >> 16usize) & 0x1f;
1034 val as u8
1035 }
1036 #[doc = "Device size This field defines the size of the external device using the following formula: Number of bytes in device = 2\\[DEVSIZE+1\\]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command mode, if DMM = 1, DEVSIZE\\[4:0\\]
1037indicates the total capacity of the two devices together."]
1038 #[inline(always)]
1039 pub fn set_devsize(&mut self, val: u8) {
1040 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
1041 }
1042 #[doc = "Memory type This bit indicates the type of memory to be supported. Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP\\[2:0\\]
1043for memories different from Micron. Others: Reserved."]
1044 #[inline(always)]
1045 pub const fn mtyp(&self) -> u8 {
1046 let val = (self.0 >> 24usize) & 0x07;
1047 val as u8
1048 }
1049 #[doc = "Memory type This bit indicates the type of memory to be supported. Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP\\[2:0\\]
1050for memories different from Micron. Others: Reserved."]
1051 #[inline(always)]
1052 pub fn set_mtyp(&mut self, val: u8) {
1053 self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize);
1054 }
1055 }
1056 impl Default for Dcr1 {
1057 #[inline(always)]
1058 fn default() -> Dcr1 {
1059 Dcr1(0)
1060 }
1061 }
1062 impl core::fmt::Debug for Dcr1 {
1063 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1064 f.debug_struct("Dcr1")
1065 .field("ckmode", &self.ckmode())
1066 .field("frck", &self.frck())
1067 .field("dlybyp", &self.dlybyp())
1068 .field("csht", &self.csht())
1069 .field("devsize", &self.devsize())
1070 .field("mtyp", &self.mtyp())
1071 .finish()
1072 }
1073 }
1074 #[cfg(feature = "defmt")]
1075 impl defmt::Format for Dcr1 {
1076 fn format(&self, f: defmt::Formatter) {
1077 #[derive(defmt :: Format)]
1078 struct Dcr1 {
1079 ckmode: bool,
1080 frck: bool,
1081 dlybyp: bool,
1082 csht: u8,
1083 devsize: u8,
1084 mtyp: u8,
1085 }
1086 let proxy = Dcr1 {
1087 ckmode: self.ckmode(),
1088 frck: self.frck(),
1089 dlybyp: self.dlybyp(),
1090 csht: self.csht(),
1091 devsize: self.devsize(),
1092 mtyp: self.mtyp(),
1093 };
1094 defmt::write!(f, "{}", proxy)
1095 }
1096 }
1097 #[doc = "HSPI device configuration register 2."]
1098 #[repr(transparent)]
1099 #[derive(Copy, Clone, Eq, PartialEq)]
1100 pub struct Dcr2(pub u32);
1101 impl Dcr2 {
1102 #[doc = "Clock prescaler This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. Writing this field automatically starts a new calibration of high-speed interface DLL at the start of next transfer, except in case CALOSR or CALISR have been written in the meantime. BUSY stays high during the whole calibration execution."]
1103 #[inline(always)]
1104 pub const fn prescaler(&self) -> u8 {
1105 let val = (self.0 >> 0usize) & 0xff;
1106 val as u8
1107 }
1108 #[doc = "Clock prescaler This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. Writing this field automatically starts a new calibration of high-speed interface DLL at the start of next transfer, except in case CALOSR or CALISR have been written in the meantime. BUSY stays high during the whole calibration execution."]
1109 #[inline(always)]
1110 pub fn set_prescaler(&mut self, val: u8) {
1111 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1112 }
1113 #[doc = "Wrap size This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the WPIR register. 110-111: Reserved."]
1114 #[inline(always)]
1115 pub const fn wrapsize(&self) -> u8 {
1116 let val = (self.0 >> 16usize) & 0x07;
1117 val as u8
1118 }
1119 #[doc = "Wrap size This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the WPIR register. 110-111: Reserved."]
1120 #[inline(always)]
1121 pub fn set_wrapsize(&mut self, val: u8) {
1122 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
1123 }
1124 }
1125 impl Default for Dcr2 {
1126 #[inline(always)]
1127 fn default() -> Dcr2 {
1128 Dcr2(0)
1129 }
1130 }
1131 impl core::fmt::Debug for Dcr2 {
1132 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1133 f.debug_struct("Dcr2")
1134 .field("prescaler", &self.prescaler())
1135 .field("wrapsize", &self.wrapsize())
1136 .finish()
1137 }
1138 }
1139 #[cfg(feature = "defmt")]
1140 impl defmt::Format for Dcr2 {
1141 fn format(&self, f: defmt::Formatter) {
1142 #[derive(defmt :: Format)]
1143 struct Dcr2 {
1144 prescaler: u8,
1145 wrapsize: u8,
1146 }
1147 let proxy = Dcr2 {
1148 prescaler: self.prescaler(),
1149 wrapsize: self.wrapsize(),
1150 };
1151 defmt::write!(f, "{}", proxy)
1152 }
1153 }
1154 #[doc = "HSPI device configuration register 3."]
1155 #[repr(transparent)]
1156 #[derive(Copy, Clone, Eq, PartialEq)]
1157 pub struct Dcr3(pub u32);
1158 impl Dcr3 {
1159 #[doc = "Maximum transfer This field enables the communication regulation feature. The nCS is released every MAXTRAN+1 clock cycles when the other HSPI request the access to the bus. others: Maximum communication is set to MAXTRAN+1 bytes."]
1160 #[inline(always)]
1161 pub const fn maxtran(&self) -> u8 {
1162 let val = (self.0 >> 0usize) & 0xff;
1163 val as u8
1164 }
1165 #[doc = "Maximum transfer This field enables the communication regulation feature. The nCS is released every MAXTRAN+1 clock cycles when the other HSPI request the access to the bus. others: Maximum communication is set to MAXTRAN+1 bytes."]
1166 #[inline(always)]
1167 pub fn set_maxtran(&mut self, val: u8) {
1168 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1169 }
1170 #[doc = "CS boundary This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The nCS is released on each boundary of 2CSBOUND bytes. others: CS boundary set to 2CSBOUND bytes."]
1171 #[inline(always)]
1172 pub const fn csbound(&self) -> u8 {
1173 let val = (self.0 >> 16usize) & 0x1f;
1174 val as u8
1175 }
1176 #[doc = "CS boundary This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The nCS is released on each boundary of 2CSBOUND bytes. others: CS boundary set to 2CSBOUND bytes."]
1177 #[inline(always)]
1178 pub fn set_csbound(&mut self, val: u8) {
1179 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
1180 }
1181 }
1182 impl Default for Dcr3 {
1183 #[inline(always)]
1184 fn default() -> Dcr3 {
1185 Dcr3(0)
1186 }
1187 }
1188 impl core::fmt::Debug for Dcr3 {
1189 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1190 f.debug_struct("Dcr3")
1191 .field("maxtran", &self.maxtran())
1192 .field("csbound", &self.csbound())
1193 .finish()
1194 }
1195 }
1196 #[cfg(feature = "defmt")]
1197 impl defmt::Format for Dcr3 {
1198 fn format(&self, f: defmt::Formatter) {
1199 #[derive(defmt :: Format)]
1200 struct Dcr3 {
1201 maxtran: u8,
1202 csbound: u8,
1203 }
1204 let proxy = Dcr3 {
1205 maxtran: self.maxtran(),
1206 csbound: self.csbound(),
1207 };
1208 defmt::write!(f, "{}", proxy)
1209 }
1210 }
1211 #[doc = "HSPI device configuration register 4."]
1212 #[repr(transparent)]
1213 #[derive(Copy, Clone, Eq, PartialEq)]
1214 pub struct Dcr4(pub u32);
1215 impl Dcr4 {
1216 #[doc = "Refresh rate This field enables the refresh rate feature. The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single, dual or quad mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH+1 clock cycles."]
1217 #[inline(always)]
1218 pub const fn refresh(&self) -> u32 {
1219 let val = (self.0 >> 0usize) & 0xffff_ffff;
1220 val as u32
1221 }
1222 #[doc = "Refresh rate This field enables the refresh rate feature. The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single, dual or quad mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH+1 clock cycles."]
1223 #[inline(always)]
1224 pub fn set_refresh(&mut self, val: u32) {
1225 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1226 }
1227 }
1228 impl Default for Dcr4 {
1229 #[inline(always)]
1230 fn default() -> Dcr4 {
1231 Dcr4(0)
1232 }
1233 }
1234 impl core::fmt::Debug for Dcr4 {
1235 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1236 f.debug_struct("Dcr4").field("refresh", &self.refresh()).finish()
1237 }
1238 }
1239 #[cfg(feature = "defmt")]
1240 impl defmt::Format for Dcr4 {
1241 fn format(&self, f: defmt::Formatter) {
1242 #[derive(defmt :: Format)]
1243 struct Dcr4 {
1244 refresh: u32,
1245 }
1246 let proxy = Dcr4 {
1247 refresh: self.refresh(),
1248 };
1249 defmt::write!(f, "{}", proxy)
1250 }
1251 }
1252 #[doc = "HSPI data length register."]
1253 #[repr(transparent)]
1254 #[derive(Copy, Clone, Eq, PartialEq)]
1255 pub struct Dlr(pub u32);
1256 impl Dlr {
1257 #[doc = "31: 0\\]: Data length Number of data to be retrieved (value+1) in Indirect and Status-polling modes. A value not greater than three (indicating 4 bytes) must be used for status polling-mode. All 1's in Indirect mode means undefined length, where HSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL\\[0\\]
1258is stuck at 1 in Dual-memory mode (DMM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in Memory-mapped mode."]
1259 #[inline(always)]
1260 pub const fn dl(&self) -> u32 {
1261 let val = (self.0 >> 0usize) & 0xffff_ffff;
1262 val as u32
1263 }
1264 #[doc = "31: 0\\]: Data length Number of data to be retrieved (value+1) in Indirect and Status-polling modes. A value not greater than three (indicating 4 bytes) must be used for status polling-mode. All 1's in Indirect mode means undefined length, where HSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL\\[0\\]
1265is stuck at 1 in Dual-memory mode (DMM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in Memory-mapped mode."]
1266 #[inline(always)]
1267 pub fn set_dl(&mut self, val: u32) {
1268 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1269 }
1270 }
1271 impl Default for Dlr {
1272 #[inline(always)]
1273 fn default() -> Dlr {
1274 Dlr(0)
1275 }
1276 }
1277 impl core::fmt::Debug for Dlr {
1278 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1279 f.debug_struct("Dlr").field("dl", &self.dl()).finish()
1280 }
1281 }
1282 #[cfg(feature = "defmt")]
1283 impl defmt::Format for Dlr {
1284 fn format(&self, f: defmt::Formatter) {
1285 #[derive(defmt :: Format)]
1286 struct Dlr {
1287 dl: u32,
1288 }
1289 let proxy = Dlr { dl: self.dl() };
1290 defmt::write!(f, "{}", proxy)
1291 }
1292 }
1293 #[repr(transparent)]
1294 #[derive(Copy, Clone, Eq, PartialEq)]
1295 pub struct Dr(pub u32);
1296 impl Dr {
1297 #[doc = "31: 0\\]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of this register: A byte read must read DATA\\[7:0\\]
1298and a half-word read must read DATA\\[15:0\\]."]
1299 #[inline(always)]
1300 pub const fn data(&self) -> u32 {
1301 let val = (self.0 >> 0usize) & 0xffff_ffff;
1302 val as u32
1303 }
1304 #[doc = "31: 0\\]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of this register: A byte read must read DATA\\[7:0\\]
1305and a half-word read must read DATA\\[15:0\\]."]
1306 #[inline(always)]
1307 pub fn set_data(&mut self, val: u32) {
1308 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1309 }
1310 }
1311 impl Default for Dr {
1312 #[inline(always)]
1313 fn default() -> Dr {
1314 Dr(0)
1315 }
1316 }
1317 impl core::fmt::Debug for Dr {
1318 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1319 f.debug_struct("Dr").field("data", &self.data()).finish()
1320 }
1321 }
1322 #[cfg(feature = "defmt")]
1323 impl defmt::Format for Dr {
1324 fn format(&self, f: defmt::Formatter) {
1325 #[derive(defmt :: Format)]
1326 struct Dr {
1327 data: u32,
1328 }
1329 let proxy = Dr { data: self.data() };
1330 defmt::write!(f, "{}", proxy)
1331 }
1332 }
1333 #[repr(transparent)]
1334 #[derive(Copy, Clone, Eq, PartialEq)]
1335 pub struct Fcr(pub u32);
1336 impl Fcr {
1337 #[doc = "Clear transfer error flag Writing 1 clears the TEF flag in the SR register."]
1338 #[inline(always)]
1339 pub const fn ctef(&self) -> bool {
1340 let val = (self.0 >> 0usize) & 0x01;
1341 val != 0
1342 }
1343 #[doc = "Clear transfer error flag Writing 1 clears the TEF flag in the SR register."]
1344 #[inline(always)]
1345 pub fn set_ctef(&mut self, val: bool) {
1346 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1347 }
1348 #[doc = "Clear transfer complete flag Writing 1 clears the TCF flag in the SR register."]
1349 #[inline(always)]
1350 pub const fn ctcf(&self) -> bool {
1351 let val = (self.0 >> 1usize) & 0x01;
1352 val != 0
1353 }
1354 #[doc = "Clear transfer complete flag Writing 1 clears the TCF flag in the SR register."]
1355 #[inline(always)]
1356 pub fn set_ctcf(&mut self, val: bool) {
1357 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1358 }
1359 #[doc = "Clear status match flag Writing 1 clears the SMF flag in the SR register."]
1360 #[inline(always)]
1361 pub const fn csmf(&self) -> bool {
1362 let val = (self.0 >> 3usize) & 0x01;
1363 val != 0
1364 }
1365 #[doc = "Clear status match flag Writing 1 clears the SMF flag in the SR register."]
1366 #[inline(always)]
1367 pub fn set_csmf(&mut self, val: bool) {
1368 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1369 }
1370 #[doc = "Clear timeout flag Writing 1 clears the TOF flag in the SR register."]
1371 #[inline(always)]
1372 pub const fn ctof(&self) -> bool {
1373 let val = (self.0 >> 4usize) & 0x01;
1374 val != 0
1375 }
1376 #[doc = "Clear timeout flag Writing 1 clears the TOF flag in the SR register."]
1377 #[inline(always)]
1378 pub fn set_ctof(&mut self, val: bool) {
1379 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1380 }
1381 }
1382 impl Default for Fcr {
1383 #[inline(always)]
1384 fn default() -> Fcr {
1385 Fcr(0)
1386 }
1387 }
1388 impl core::fmt::Debug for Fcr {
1389 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1390 f.debug_struct("Fcr")
1391 .field("ctef", &self.ctef())
1392 .field("ctcf", &self.ctcf())
1393 .field("csmf", &self.csmf())
1394 .field("ctof", &self.ctof())
1395 .finish()
1396 }
1397 }
1398 #[cfg(feature = "defmt")]
1399 impl defmt::Format for Fcr {
1400 fn format(&self, f: defmt::Formatter) {
1401 #[derive(defmt :: Format)]
1402 struct Fcr {
1403 ctef: bool,
1404 ctcf: bool,
1405 csmf: bool,
1406 ctof: bool,
1407 }
1408 let proxy = Fcr {
1409 ctef: self.ctef(),
1410 ctcf: self.ctcf(),
1411 csmf: self.csmf(),
1412 ctof: self.ctof(),
1413 };
1414 defmt::write!(f, "{}", proxy)
1415 }
1416 }
1417 #[doc = "HSPI HyperBus latency configuration register."]
1418 #[repr(transparent)]
1419 #[derive(Copy, Clone, Eq, PartialEq)]
1420 pub struct Hlcr(pub u32);
1421 impl Hlcr {
1422 #[doc = "Latency mode This bit selects the Latency mode."]
1423 #[inline(always)]
1424 pub const fn lm(&self) -> bool {
1425 let val = (self.0 >> 0usize) & 0x01;
1426 val != 0
1427 }
1428 #[doc = "Latency mode This bit selects the Latency mode."]
1429 #[inline(always)]
1430 pub fn set_lm(&mut self, val: bool) {
1431 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1432 }
1433 #[doc = "Write zero latency This bit enables zero latency on write operations."]
1434 #[inline(always)]
1435 pub const fn wzl(&self) -> bool {
1436 let val = (self.0 >> 1usize) & 0x01;
1437 val != 0
1438 }
1439 #[doc = "Write zero latency This bit enables zero latency on write operations."]
1440 #[inline(always)]
1441 pub fn set_wzl(&mut self, val: bool) {
1442 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1443 }
1444 #[doc = "7: 0\\]: Access time Device access time expressed in number of communication clock cycles."]
1445 #[inline(always)]
1446 pub const fn tacc(&self) -> u8 {
1447 let val = (self.0 >> 8usize) & 0xff;
1448 val as u8
1449 }
1450 #[doc = "7: 0\\]: Access time Device access time expressed in number of communication clock cycles."]
1451 #[inline(always)]
1452 pub fn set_tacc(&mut self, val: u8) {
1453 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
1454 }
1455 #[doc = "Read write recovery time Device read write recovery time expressed in number of communication clock cycles."]
1456 #[inline(always)]
1457 pub const fn trwr(&self) -> u8 {
1458 let val = (self.0 >> 16usize) & 0xff;
1459 val as u8
1460 }
1461 #[doc = "Read write recovery time Device read write recovery time expressed in number of communication clock cycles."]
1462 #[inline(always)]
1463 pub fn set_trwr(&mut self, val: u8) {
1464 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
1465 }
1466 }
1467 impl Default for Hlcr {
1468 #[inline(always)]
1469 fn default() -> Hlcr {
1470 Hlcr(0)
1471 }
1472 }
1473 impl core::fmt::Debug for Hlcr {
1474 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1475 f.debug_struct("Hlcr")
1476 .field("lm", &self.lm())
1477 .field("wzl", &self.wzl())
1478 .field("tacc", &self.tacc())
1479 .field("trwr", &self.trwr())
1480 .finish()
1481 }
1482 }
1483 #[cfg(feature = "defmt")]
1484 impl defmt::Format for Hlcr {
1485 fn format(&self, f: defmt::Formatter) {
1486 #[derive(defmt :: Format)]
1487 struct Hlcr {
1488 lm: bool,
1489 wzl: bool,
1490 tacc: u8,
1491 trwr: u8,
1492 }
1493 let proxy = Hlcr {
1494 lm: self.lm(),
1495 wzl: self.wzl(),
1496 tacc: self.tacc(),
1497 trwr: self.trwr(),
1498 };
1499 defmt::write!(f, "{}", proxy)
1500 }
1501 }
1502 #[doc = "HSPI instruction register."]
1503 #[repr(transparent)]
1504 #[derive(Copy, Clone, Eq, PartialEq)]
1505 pub struct Ir(pub u32);
1506 impl Ir {
1507 #[doc = "Instruction Instruction to be sent to the external SPI device."]
1508 #[inline(always)]
1509 pub const fn instruction(&self) -> u32 {
1510 let val = (self.0 >> 0usize) & 0xffff_ffff;
1511 val as u32
1512 }
1513 #[doc = "Instruction Instruction to be sent to the external SPI device."]
1514 #[inline(always)]
1515 pub fn set_instruction(&mut self, val: u32) {
1516 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1517 }
1518 }
1519 impl Default for Ir {
1520 #[inline(always)]
1521 fn default() -> Ir {
1522 Ir(0)
1523 }
1524 }
1525 impl core::fmt::Debug for Ir {
1526 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1527 f.debug_struct("Ir").field("instruction", &self.instruction()).finish()
1528 }
1529 }
1530 #[cfg(feature = "defmt")]
1531 impl defmt::Format for Ir {
1532 fn format(&self, f: defmt::Formatter) {
1533 #[derive(defmt :: Format)]
1534 struct Ir {
1535 instruction: u32,
1536 }
1537 let proxy = Ir {
1538 instruction: self.instruction(),
1539 };
1540 defmt::write!(f, "{}", proxy)
1541 }
1542 }
1543 #[doc = "HSPI low-power timeout register."]
1544 #[repr(transparent)]
1545 #[derive(Copy, Clone, Eq, PartialEq)]
1546 pub struct Lptr(pub u32);
1547 impl Lptr {
1548 #[doc = "15: 0\\]: Timeout period After each access in Memory-mapped mode, the HSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the HSPI waits after the clock becomes inactive and until it raises the nCS, putting the external device in a lower-consumption state."]
1549 #[inline(always)]
1550 pub const fn timeout(&self) -> u16 {
1551 let val = (self.0 >> 0usize) & 0xffff;
1552 val as u16
1553 }
1554 #[doc = "15: 0\\]: Timeout period After each access in Memory-mapped mode, the HSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the HSPI waits after the clock becomes inactive and until it raises the nCS, putting the external device in a lower-consumption state."]
1555 #[inline(always)]
1556 pub fn set_timeout(&mut self, val: u16) {
1557 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1558 }
1559 }
1560 impl Default for Lptr {
1561 #[inline(always)]
1562 fn default() -> Lptr {
1563 Lptr(0)
1564 }
1565 }
1566 impl core::fmt::Debug for Lptr {
1567 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1568 f.debug_struct("Lptr").field("timeout", &self.timeout()).finish()
1569 }
1570 }
1571 #[cfg(feature = "defmt")]
1572 impl defmt::Format for Lptr {
1573 fn format(&self, f: defmt::Formatter) {
1574 #[derive(defmt :: Format)]
1575 struct Lptr {
1576 timeout: u16,
1577 }
1578 let proxy = Lptr {
1579 timeout: self.timeout(),
1580 };
1581 defmt::write!(f, "{}", proxy)
1582 }
1583 }
1584 #[doc = "HSPI polling interval register."]
1585 #[repr(transparent)]
1586 #[derive(Copy, Clone, Eq, PartialEq)]
1587 pub struct Pir(pub u32);
1588 impl Pir {
1589 #[doc = "15: 0\\]: Polling interval Number of CLK cycle between a read during the automatic-polling phases."]
1590 #[inline(always)]
1591 pub const fn interval(&self) -> u16 {
1592 let val = (self.0 >> 0usize) & 0xffff;
1593 val as u16
1594 }
1595 #[doc = "15: 0\\]: Polling interval Number of CLK cycle between a read during the automatic-polling phases."]
1596 #[inline(always)]
1597 pub fn set_interval(&mut self, val: u16) {
1598 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1599 }
1600 }
1601 impl Default for Pir {
1602 #[inline(always)]
1603 fn default() -> Pir {
1604 Pir(0)
1605 }
1606 }
1607 impl core::fmt::Debug for Pir {
1608 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1609 f.debug_struct("Pir").field("interval", &self.interval()).finish()
1610 }
1611 }
1612 #[cfg(feature = "defmt")]
1613 impl defmt::Format for Pir {
1614 fn format(&self, f: defmt::Formatter) {
1615 #[derive(defmt :: Format)]
1616 struct Pir {
1617 interval: u16,
1618 }
1619 let proxy = Pir {
1620 interval: self.interval(),
1621 };
1622 defmt::write!(f, "{}", proxy)
1623 }
1624 }
1625 #[doc = "HSPI polling status match register."]
1626 #[repr(transparent)]
1627 #[derive(Copy, Clone, Eq, PartialEq)]
1628 pub struct Psmar(pub u32);
1629 impl Psmar {
1630 #[doc = "31: 0\\]: Status match Value to be compared with the masked status register to get a match."]
1631 #[inline(always)]
1632 pub const fn match_(&self) -> u32 {
1633 let val = (self.0 >> 0usize) & 0xffff_ffff;
1634 val as u32
1635 }
1636 #[doc = "31: 0\\]: Status match Value to be compared with the masked status register to get a match."]
1637 #[inline(always)]
1638 pub fn set_match_(&mut self, val: u32) {
1639 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1640 }
1641 }
1642 impl Default for Psmar {
1643 #[inline(always)]
1644 fn default() -> Psmar {
1645 Psmar(0)
1646 }
1647 }
1648 impl core::fmt::Debug for Psmar {
1649 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1650 f.debug_struct("Psmar").field("match_", &self.match_()).finish()
1651 }
1652 }
1653 #[cfg(feature = "defmt")]
1654 impl defmt::Format for Psmar {
1655 fn format(&self, f: defmt::Formatter) {
1656 #[derive(defmt :: Format)]
1657 struct Psmar {
1658 match_: u32,
1659 }
1660 let proxy = Psmar { match_: self.match_() };
1661 defmt::write!(f, "{}", proxy)
1662 }
1663 }
1664 #[doc = "HSPI polling status mask register."]
1665 #[repr(transparent)]
1666 #[derive(Copy, Clone, Eq, PartialEq)]
1667 pub struct Psmkr(pub u32);
1668 impl Psmkr {
1669 #[doc = "Status mask Mask to be applied to the status bytes received in Polling mode For bit n:."]
1670 #[inline(always)]
1671 pub const fn mask(&self) -> u32 {
1672 let val = (self.0 >> 0usize) & 0xffff_ffff;
1673 val as u32
1674 }
1675 #[doc = "Status mask Mask to be applied to the status bytes received in Polling mode For bit n:."]
1676 #[inline(always)]
1677 pub fn set_mask(&mut self, val: u32) {
1678 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1679 }
1680 }
1681 impl Default for Psmkr {
1682 #[inline(always)]
1683 fn default() -> Psmkr {
1684 Psmkr(0)
1685 }
1686 }
1687 impl core::fmt::Debug for Psmkr {
1688 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1689 f.debug_struct("Psmkr").field("mask", &self.mask()).finish()
1690 }
1691 }
1692 #[cfg(feature = "defmt")]
1693 impl defmt::Format for Psmkr {
1694 fn format(&self, f: defmt::Formatter) {
1695 #[derive(defmt :: Format)]
1696 struct Psmkr {
1697 mask: u32,
1698 }
1699 let proxy = Psmkr { mask: self.mask() };
1700 defmt::write!(f, "{}", proxy)
1701 }
1702 }
1703 #[repr(transparent)]
1704 #[derive(Copy, Clone, Eq, PartialEq)]
1705 pub struct Sr(pub u32);
1706 impl Sr {
1707 #[doc = "Transfer error flag This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF."]
1708 #[inline(always)]
1709 pub const fn tef(&self) -> bool {
1710 let val = (self.0 >> 0usize) & 0x01;
1711 val != 0
1712 }
1713 #[doc = "Transfer error flag This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF."]
1714 #[inline(always)]
1715 pub fn set_tef(&mut self, val: bool) {
1716 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1717 }
1718 #[doc = "Transfer complete flag This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF."]
1719 #[inline(always)]
1720 pub const fn tcf(&self) -> bool {
1721 let val = (self.0 >> 1usize) & 0x01;
1722 val != 0
1723 }
1724 #[doc = "Transfer complete flag This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF."]
1725 #[inline(always)]
1726 pub fn set_tcf(&mut self, val: bool) {
1727 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1728 }
1729 #[doc = "FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read."]
1730 #[inline(always)]
1731 pub const fn ftf(&self) -> bool {
1732 let val = (self.0 >> 2usize) & 0x01;
1733 val != 0
1734 }
1735 #[doc = "FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read."]
1736 #[inline(always)]
1737 pub fn set_ftf(&mut self, val: bool) {
1738 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1739 }
1740 #[doc = "Status match flag This bit is set in Automatic-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF."]
1741 #[inline(always)]
1742 pub const fn smf(&self) -> bool {
1743 let val = (self.0 >> 3usize) & 0x01;
1744 val != 0
1745 }
1746 #[doc = "Status match flag This bit is set in Automatic-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF."]
1747 #[inline(always)]
1748 pub fn set_smf(&mut self, val: bool) {
1749 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1750 }
1751 #[doc = "Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF."]
1752 #[inline(always)]
1753 pub const fn tof(&self) -> bool {
1754 let val = (self.0 >> 4usize) & 0x01;
1755 val != 0
1756 }
1757 #[doc = "Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF."]
1758 #[inline(always)]
1759 pub fn set_tof(&mut self, val: bool) {
1760 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1761 }
1762 #[doc = "Busy This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty."]
1763 #[inline(always)]
1764 pub const fn busy(&self) -> bool {
1765 let val = (self.0 >> 5usize) & 0x01;
1766 val != 0
1767 }
1768 #[doc = "Busy This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty."]
1769 #[inline(always)]
1770 pub fn set_busy(&mut self, val: bool) {
1771 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1772 }
1773 #[doc = "FIFO level This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 64 when it is full. In Automatic-status polling mode, FLEVEL is zero."]
1774 #[inline(always)]
1775 pub const fn flevel(&self) -> u8 {
1776 let val = (self.0 >> 8usize) & 0x7f;
1777 val as u8
1778 }
1779 #[doc = "FIFO level This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 64 when it is full. In Automatic-status polling mode, FLEVEL is zero."]
1780 #[inline(always)]
1781 pub fn set_flevel(&mut self, val: u8) {
1782 self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize);
1783 }
1784 }
1785 impl Default for Sr {
1786 #[inline(always)]
1787 fn default() -> Sr {
1788 Sr(0)
1789 }
1790 }
1791 impl core::fmt::Debug for Sr {
1792 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1793 f.debug_struct("Sr")
1794 .field("tef", &self.tef())
1795 .field("tcf", &self.tcf())
1796 .field("ftf", &self.ftf())
1797 .field("smf", &self.smf())
1798 .field("tof", &self.tof())
1799 .field("busy", &self.busy())
1800 .field("flevel", &self.flevel())
1801 .finish()
1802 }
1803 }
1804 #[cfg(feature = "defmt")]
1805 impl defmt::Format for Sr {
1806 fn format(&self, f: defmt::Formatter) {
1807 #[derive(defmt :: Format)]
1808 struct Sr {
1809 tef: bool,
1810 tcf: bool,
1811 ftf: bool,
1812 smf: bool,
1813 tof: bool,
1814 busy: bool,
1815 flevel: u8,
1816 }
1817 let proxy = Sr {
1818 tef: self.tef(),
1819 tcf: self.tcf(),
1820 ftf: self.ftf(),
1821 smf: self.smf(),
1822 tof: self.tof(),
1823 busy: self.busy(),
1824 flevel: self.flevel(),
1825 };
1826 defmt::write!(f, "{}", proxy)
1827 }
1828 }
1829 #[doc = "HSPI timing configuration register."]
1830 #[repr(transparent)]
1831 #[derive(Copy, Clone, Eq, PartialEq)]
1832 pub struct Tcr(pub u32);
1833 impl Tcr {
1834 #[doc = "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31)."]
1835 #[inline(always)]
1836 pub const fn dcyc(&self) -> u8 {
1837 let val = (self.0 >> 0usize) & 0x1f;
1838 val as u8
1839 }
1840 #[doc = "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31)."]
1841 #[inline(always)]
1842 pub fn set_dcyc(&mut self, val: u8) {
1843 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
1844 }
1845 #[doc = "Delay hold quarter cycle."]
1846 #[inline(always)]
1847 pub const fn dhqc(&self) -> bool {
1848 let val = (self.0 >> 28usize) & 0x01;
1849 val != 0
1850 }
1851 #[doc = "Delay hold quarter cycle."]
1852 #[inline(always)]
1853 pub fn set_dhqc(&mut self, val: bool) {
1854 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1855 }
1856 #[doc = "Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.)."]
1857 #[inline(always)]
1858 pub const fn sshift(&self) -> bool {
1859 let val = (self.0 >> 30usize) & 0x01;
1860 val != 0
1861 }
1862 #[doc = "Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.)."]
1863 #[inline(always)]
1864 pub fn set_sshift(&mut self, val: bool) {
1865 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
1866 }
1867 }
1868 impl Default for Tcr {
1869 #[inline(always)]
1870 fn default() -> Tcr {
1871 Tcr(0)
1872 }
1873 }
1874 impl core::fmt::Debug for Tcr {
1875 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1876 f.debug_struct("Tcr")
1877 .field("dcyc", &self.dcyc())
1878 .field("dhqc", &self.dhqc())
1879 .field("sshift", &self.sshift())
1880 .finish()
1881 }
1882 }
1883 #[cfg(feature = "defmt")]
1884 impl defmt::Format for Tcr {
1885 fn format(&self, f: defmt::Formatter) {
1886 #[derive(defmt :: Format)]
1887 struct Tcr {
1888 dcyc: u8,
1889 dhqc: bool,
1890 sshift: bool,
1891 }
1892 let proxy = Tcr {
1893 dcyc: self.dcyc(),
1894 dhqc: self.dhqc(),
1895 sshift: self.sshift(),
1896 };
1897 defmt::write!(f, "{}", proxy)
1898 }
1899 }
1900 #[doc = "HSPI write alternate bytes register."]
1901 #[repr(transparent)]
1902 #[derive(Copy, Clone, Eq, PartialEq)]
1903 pub struct Wabr(pub u32);
1904 impl Wabr {
1905 #[doc = "31: 0\\]: Alternate bytes Optional data to be sent to the external SPI device right after the address."]
1906 #[inline(always)]
1907 pub const fn alternate(&self) -> u32 {
1908 let val = (self.0 >> 0usize) & 0xffff_ffff;
1909 val as u32
1910 }
1911 #[doc = "31: 0\\]: Alternate bytes Optional data to be sent to the external SPI device right after the address."]
1912 #[inline(always)]
1913 pub fn set_alternate(&mut self, val: u32) {
1914 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1915 }
1916 }
1917 impl Default for Wabr {
1918 #[inline(always)]
1919 fn default() -> Wabr {
1920 Wabr(0)
1921 }
1922 }
1923 impl core::fmt::Debug for Wabr {
1924 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1925 f.debug_struct("Wabr").field("alternate", &self.alternate()).finish()
1926 }
1927 }
1928 #[cfg(feature = "defmt")]
1929 impl defmt::Format for Wabr {
1930 fn format(&self, f: defmt::Formatter) {
1931 #[derive(defmt :: Format)]
1932 struct Wabr {
1933 alternate: u32,
1934 }
1935 let proxy = Wabr {
1936 alternate: self.alternate(),
1937 };
1938 defmt::write!(f, "{}", proxy)
1939 }
1940 }
1941 #[doc = "HSPI write communication configuration register."]
1942 #[repr(transparent)]
1943 #[derive(Copy, Clone, Eq, PartialEq)]
1944 pub struct Wccr(pub u32);
1945 impl Wccr {
1946 #[doc = "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved."]
1947 #[inline(always)]
1948 pub const fn imode(&self) -> u8 {
1949 let val = (self.0 >> 0usize) & 0x07;
1950 val as u8
1951 }
1952 #[doc = "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved."]
1953 #[inline(always)]
1954 pub fn set_imode(&mut self, val: u8) {
1955 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
1956 }
1957 #[doc = "Instruction double transfer rate This bit sets the DTR mode for the instruction phase."]
1958 #[inline(always)]
1959 pub const fn idtr(&self) -> bool {
1960 let val = (self.0 >> 3usize) & 0x01;
1961 val != 0
1962 }
1963 #[doc = "Instruction double transfer rate This bit sets the DTR mode for the instruction phase."]
1964 #[inline(always)]
1965 pub fn set_idtr(&mut self, val: bool) {
1966 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1967 }
1968 #[doc = "Instruction size This bit defines instruction size:."]
1969 #[inline(always)]
1970 pub const fn isize(&self) -> u8 {
1971 let val = (self.0 >> 4usize) & 0x03;
1972 val as u8
1973 }
1974 #[doc = "Instruction size This bit defines instruction size:."]
1975 #[inline(always)]
1976 pub fn set_isize(&mut self, val: u8) {
1977 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
1978 }
1979 #[doc = "Address mode This field defines the address phase mode of operation. 101-111: Reserved."]
1980 #[inline(always)]
1981 pub const fn admode(&self) -> u8 {
1982 let val = (self.0 >> 8usize) & 0x07;
1983 val as u8
1984 }
1985 #[doc = "Address mode This field defines the address phase mode of operation. 101-111: Reserved."]
1986 #[inline(always)]
1987 pub fn set_admode(&mut self, val: u8) {
1988 self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
1989 }
1990 #[doc = "Address double transfer rate This bit sets the DTR mode for the address phase."]
1991 #[inline(always)]
1992 pub const fn addtr(&self) -> bool {
1993 let val = (self.0 >> 11usize) & 0x01;
1994 val != 0
1995 }
1996 #[doc = "Address double transfer rate This bit sets the DTR mode for the address phase."]
1997 #[inline(always)]
1998 pub fn set_addtr(&mut self, val: bool) {
1999 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2000 }
2001 #[doc = "Address size This field defines address size."]
2002 #[inline(always)]
2003 pub const fn adsize(&self) -> u8 {
2004 let val = (self.0 >> 12usize) & 0x03;
2005 val as u8
2006 }
2007 #[doc = "Address size This field defines address size."]
2008 #[inline(always)]
2009 pub fn set_adsize(&mut self, val: u8) {
2010 self.0 = (self.0 & !(0x03 << 12usize)) | (((val as u32) & 0x03) << 12usize);
2011 }
2012 #[doc = "Alternate-byte mode This field defines the alternate-byte phase mode of operation. 101-111: Reserved."]
2013 #[inline(always)]
2014 pub const fn abmode(&self) -> u8 {
2015 let val = (self.0 >> 16usize) & 0x07;
2016 val as u8
2017 }
2018 #[doc = "Alternate-byte mode This field defines the alternate-byte phase mode of operation. 101-111: Reserved."]
2019 #[inline(always)]
2020 pub fn set_abmode(&mut self, val: u8) {
2021 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
2022 }
2023 #[doc = "Alternate bytes double-transfer rate This bit sets the DTR mode for the alternate-bytes phase."]
2024 #[inline(always)]
2025 pub const fn abdtr(&self) -> bool {
2026 let val = (self.0 >> 19usize) & 0x01;
2027 val != 0
2028 }
2029 #[doc = "Alternate bytes double-transfer rate This bit sets the DTR mode for the alternate-bytes phase."]
2030 #[inline(always)]
2031 pub fn set_abdtr(&mut self, val: bool) {
2032 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2033 }
2034 #[doc = "Alternate bytes size This field defines alternate bytes size:."]
2035 #[inline(always)]
2036 pub const fn absize(&self) -> u8 {
2037 let val = (self.0 >> 20usize) & 0x03;
2038 val as u8
2039 }
2040 #[doc = "Alternate bytes size This field defines alternate bytes size:."]
2041 #[inline(always)]
2042 pub fn set_absize(&mut self, val: u8) {
2043 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
2044 }
2045 #[doc = "Data mode This field defines the data phase mode of operation."]
2046 #[inline(always)]
2047 pub const fn dmode(&self) -> u8 {
2048 let val = (self.0 >> 24usize) & 0x07;
2049 val as u8
2050 }
2051 #[doc = "Data mode This field defines the data phase mode of operation."]
2052 #[inline(always)]
2053 pub fn set_dmode(&mut self, val: u8) {
2054 self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize);
2055 }
2056 #[doc = "data double transfer rate This bit sets the DTR mode for the data phase."]
2057 #[inline(always)]
2058 pub const fn ddtr(&self) -> bool {
2059 let val = (self.0 >> 27usize) & 0x01;
2060 val != 0
2061 }
2062 #[doc = "data double transfer rate This bit sets the DTR mode for the data phase."]
2063 #[inline(always)]
2064 pub fn set_ddtr(&mut self, val: bool) {
2065 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2066 }
2067 #[doc = "DQS enable This bit enables the data strobe management."]
2068 #[inline(always)]
2069 pub const fn dqse(&self) -> bool {
2070 let val = (self.0 >> 29usize) & 0x01;
2071 val != 0
2072 }
2073 #[doc = "DQS enable This bit enables the data strobe management."]
2074 #[inline(always)]
2075 pub fn set_dqse(&mut self, val: bool) {
2076 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
2077 }
2078 }
2079 impl Default for Wccr {
2080 #[inline(always)]
2081 fn default() -> Wccr {
2082 Wccr(0)
2083 }
2084 }
2085 impl core::fmt::Debug for Wccr {
2086 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2087 f.debug_struct("Wccr")
2088 .field("imode", &self.imode())
2089 .field("idtr", &self.idtr())
2090 .field("isize", &self.isize())
2091 .field("admode", &self.admode())
2092 .field("addtr", &self.addtr())
2093 .field("adsize", &self.adsize())
2094 .field("abmode", &self.abmode())
2095 .field("abdtr", &self.abdtr())
2096 .field("absize", &self.absize())
2097 .field("dmode", &self.dmode())
2098 .field("ddtr", &self.ddtr())
2099 .field("dqse", &self.dqse())
2100 .finish()
2101 }
2102 }
2103 #[cfg(feature = "defmt")]
2104 impl defmt::Format for Wccr {
2105 fn format(&self, f: defmt::Formatter) {
2106 #[derive(defmt :: Format)]
2107 struct Wccr {
2108 imode: u8,
2109 idtr: bool,
2110 isize: u8,
2111 admode: u8,
2112 addtr: bool,
2113 adsize: u8,
2114 abmode: u8,
2115 abdtr: bool,
2116 absize: u8,
2117 dmode: u8,
2118 ddtr: bool,
2119 dqse: bool,
2120 }
2121 let proxy = Wccr {
2122 imode: self.imode(),
2123 idtr: self.idtr(),
2124 isize: self.isize(),
2125 admode: self.admode(),
2126 addtr: self.addtr(),
2127 adsize: self.adsize(),
2128 abmode: self.abmode(),
2129 abdtr: self.abdtr(),
2130 absize: self.absize(),
2131 dmode: self.dmode(),
2132 ddtr: self.ddtr(),
2133 dqse: self.dqse(),
2134 };
2135 defmt::write!(f, "{}", proxy)
2136 }
2137 }
2138 #[doc = "HSPI write instruction register."]
2139 #[repr(transparent)]
2140 #[derive(Copy, Clone, Eq, PartialEq)]
2141 pub struct Wir(pub u32);
2142 impl Wir {
2143 #[doc = "Instruction Instruction to be sent to the external SPI device."]
2144 #[inline(always)]
2145 pub const fn instruction(&self) -> u32 {
2146 let val = (self.0 >> 0usize) & 0xffff_ffff;
2147 val as u32
2148 }
2149 #[doc = "Instruction Instruction to be sent to the external SPI device."]
2150 #[inline(always)]
2151 pub fn set_instruction(&mut self, val: u32) {
2152 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2153 }
2154 }
2155 impl Default for Wir {
2156 #[inline(always)]
2157 fn default() -> Wir {
2158 Wir(0)
2159 }
2160 }
2161 impl core::fmt::Debug for Wir {
2162 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2163 f.debug_struct("Wir").field("instruction", &self.instruction()).finish()
2164 }
2165 }
2166 #[cfg(feature = "defmt")]
2167 impl defmt::Format for Wir {
2168 fn format(&self, f: defmt::Formatter) {
2169 #[derive(defmt :: Format)]
2170 struct Wir {
2171 instruction: u32,
2172 }
2173 let proxy = Wir {
2174 instruction: self.instruction(),
2175 };
2176 defmt::write!(f, "{}", proxy)
2177 }
2178 }
2179 #[doc = "HSPI wrap alternate bytes register."]
2180 #[repr(transparent)]
2181 #[derive(Copy, Clone, Eq, PartialEq)]
2182 pub struct Wpabr(pub u32);
2183 impl Wpabr {
2184 #[doc = "31: 0\\]: Alternate bytes Optional data to be sent to the external SPI device right after the address."]
2185 #[inline(always)]
2186 pub const fn alternate(&self) -> u32 {
2187 let val = (self.0 >> 0usize) & 0xffff_ffff;
2188 val as u32
2189 }
2190 #[doc = "31: 0\\]: Alternate bytes Optional data to be sent to the external SPI device right after the address."]
2191 #[inline(always)]
2192 pub fn set_alternate(&mut self, val: u32) {
2193 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2194 }
2195 }
2196 impl Default for Wpabr {
2197 #[inline(always)]
2198 fn default() -> Wpabr {
2199 Wpabr(0)
2200 }
2201 }
2202 impl core::fmt::Debug for Wpabr {
2203 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2204 f.debug_struct("Wpabr").field("alternate", &self.alternate()).finish()
2205 }
2206 }
2207 #[cfg(feature = "defmt")]
2208 impl defmt::Format for Wpabr {
2209 fn format(&self, f: defmt::Formatter) {
2210 #[derive(defmt :: Format)]
2211 struct Wpabr {
2212 alternate: u32,
2213 }
2214 let proxy = Wpabr {
2215 alternate: self.alternate(),
2216 };
2217 defmt::write!(f, "{}", proxy)
2218 }
2219 }
2220 #[doc = "HSPI wrap communication configuration register."]
2221 #[repr(transparent)]
2222 #[derive(Copy, Clone, Eq, PartialEq)]
2223 pub struct Wpccr(pub u32);
2224 impl Wpccr {
2225 #[doc = "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved."]
2226 #[inline(always)]
2227 pub const fn imode(&self) -> u8 {
2228 let val = (self.0 >> 0usize) & 0x07;
2229 val as u8
2230 }
2231 #[doc = "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved."]
2232 #[inline(always)]
2233 pub fn set_imode(&mut self, val: u8) {
2234 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
2235 }
2236 #[doc = "Instruction double transfer rate This bit sets the DTR mode for the instruction phase."]
2237 #[inline(always)]
2238 pub const fn idtr(&self) -> bool {
2239 let val = (self.0 >> 3usize) & 0x01;
2240 val != 0
2241 }
2242 #[doc = "Instruction double transfer rate This bit sets the DTR mode for the instruction phase."]
2243 #[inline(always)]
2244 pub fn set_idtr(&mut self, val: bool) {
2245 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2246 }
2247 #[doc = "Instruction size This field defines instruction size."]
2248 #[inline(always)]
2249 pub const fn isize(&self) -> u8 {
2250 let val = (self.0 >> 4usize) & 0x03;
2251 val as u8
2252 }
2253 #[doc = "Instruction size This field defines instruction size."]
2254 #[inline(always)]
2255 pub fn set_isize(&mut self, val: u8) {
2256 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
2257 }
2258 #[doc = "Address mode This field defines the address phase mode of operation. 101-111: Reserved."]
2259 #[inline(always)]
2260 pub const fn admode(&self) -> u8 {
2261 let val = (self.0 >> 8usize) & 0x07;
2262 val as u8
2263 }
2264 #[doc = "Address mode This field defines the address phase mode of operation. 101-111: Reserved."]
2265 #[inline(always)]
2266 pub fn set_admode(&mut self, val: u8) {
2267 self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
2268 }
2269 #[doc = "Address double transfer rate This bit sets the DTR mode for the address phase."]
2270 #[inline(always)]
2271 pub const fn addtr(&self) -> bool {
2272 let val = (self.0 >> 11usize) & 0x01;
2273 val != 0
2274 }
2275 #[doc = "Address double transfer rate This bit sets the DTR mode for the address phase."]
2276 #[inline(always)]
2277 pub fn set_addtr(&mut self, val: bool) {
2278 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2279 }
2280 #[doc = "Address size This field defines address size."]
2281 #[inline(always)]
2282 pub const fn adsize(&self) -> u8 {
2283 let val = (self.0 >> 12usize) & 0x03;
2284 val as u8
2285 }
2286 #[doc = "Address size This field defines address size."]
2287 #[inline(always)]
2288 pub fn set_adsize(&mut self, val: u8) {
2289 self.0 = (self.0 & !(0x03 << 12usize)) | (((val as u32) & 0x03) << 12usize);
2290 }
2291 #[doc = "Alternate-byte mode This field defines the alternate byte phase mode of operation."]
2292 #[inline(always)]
2293 pub const fn abmode(&self) -> u8 {
2294 let val = (self.0 >> 16usize) & 0x07;
2295 val as u8
2296 }
2297 #[doc = "Alternate-byte mode This field defines the alternate byte phase mode of operation."]
2298 #[inline(always)]
2299 pub fn set_abmode(&mut self, val: u8) {
2300 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
2301 }
2302 #[doc = "Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase."]
2303 #[inline(always)]
2304 pub const fn abdtr(&self) -> bool {
2305 let val = (self.0 >> 19usize) & 0x01;
2306 val != 0
2307 }
2308 #[doc = "Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase."]
2309 #[inline(always)]
2310 pub fn set_abdtr(&mut self, val: bool) {
2311 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2312 }
2313 #[doc = "Alternate bytes size This bit defines alternate bytes size."]
2314 #[inline(always)]
2315 pub const fn absize(&self) -> u8 {
2316 let val = (self.0 >> 20usize) & 0x03;
2317 val as u8
2318 }
2319 #[doc = "Alternate bytes size This bit defines alternate bytes size."]
2320 #[inline(always)]
2321 pub fn set_absize(&mut self, val: u8) {
2322 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
2323 }
2324 #[doc = "Data mode This field defines the data phase mode of operation. 101; Data on 16 lines 110-111: Reserved."]
2325 #[inline(always)]
2326 pub const fn dmode(&self) -> u8 {
2327 let val = (self.0 >> 24usize) & 0x07;
2328 val as u8
2329 }
2330 #[doc = "Data mode This field defines the data phase mode of operation. 101; Data on 16 lines 110-111: Reserved."]
2331 #[inline(always)]
2332 pub fn set_dmode(&mut self, val: u8) {
2333 self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize);
2334 }
2335 #[doc = "Data double transfer rate This bit sets the DTR mode for the data phase."]
2336 #[inline(always)]
2337 pub const fn ddtr(&self) -> bool {
2338 let val = (self.0 >> 27usize) & 0x01;
2339 val != 0
2340 }
2341 #[doc = "Data double transfer rate This bit sets the DTR mode for the data phase."]
2342 #[inline(always)]
2343 pub fn set_ddtr(&mut self, val: bool) {
2344 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2345 }
2346 #[doc = "DQS enable This bit enables the data strobe management."]
2347 #[inline(always)]
2348 pub const fn dqse(&self) -> bool {
2349 let val = (self.0 >> 29usize) & 0x01;
2350 val != 0
2351 }
2352 #[doc = "DQS enable This bit enables the data strobe management."]
2353 #[inline(always)]
2354 pub fn set_dqse(&mut self, val: bool) {
2355 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
2356 }
2357 }
2358 impl Default for Wpccr {
2359 #[inline(always)]
2360 fn default() -> Wpccr {
2361 Wpccr(0)
2362 }
2363 }
2364 impl core::fmt::Debug for Wpccr {
2365 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2366 f.debug_struct("Wpccr")
2367 .field("imode", &self.imode())
2368 .field("idtr", &self.idtr())
2369 .field("isize", &self.isize())
2370 .field("admode", &self.admode())
2371 .field("addtr", &self.addtr())
2372 .field("adsize", &self.adsize())
2373 .field("abmode", &self.abmode())
2374 .field("abdtr", &self.abdtr())
2375 .field("absize", &self.absize())
2376 .field("dmode", &self.dmode())
2377 .field("ddtr", &self.ddtr())
2378 .field("dqse", &self.dqse())
2379 .finish()
2380 }
2381 }
2382 #[cfg(feature = "defmt")]
2383 impl defmt::Format for Wpccr {
2384 fn format(&self, f: defmt::Formatter) {
2385 #[derive(defmt :: Format)]
2386 struct Wpccr {
2387 imode: u8,
2388 idtr: bool,
2389 isize: u8,
2390 admode: u8,
2391 addtr: bool,
2392 adsize: u8,
2393 abmode: u8,
2394 abdtr: bool,
2395 absize: u8,
2396 dmode: u8,
2397 ddtr: bool,
2398 dqse: bool,
2399 }
2400 let proxy = Wpccr {
2401 imode: self.imode(),
2402 idtr: self.idtr(),
2403 isize: self.isize(),
2404 admode: self.admode(),
2405 addtr: self.addtr(),
2406 adsize: self.adsize(),
2407 abmode: self.abmode(),
2408 abdtr: self.abdtr(),
2409 absize: self.absize(),
2410 dmode: self.dmode(),
2411 ddtr: self.ddtr(),
2412 dqse: self.dqse(),
2413 };
2414 defmt::write!(f, "{}", proxy)
2415 }
2416 }
2417 #[doc = "HSPI wrap instruction register."]
2418 #[repr(transparent)]
2419 #[derive(Copy, Clone, Eq, PartialEq)]
2420 pub struct Wpir(pub u32);
2421 impl Wpir {
2422 #[doc = "31: 0\\]: Instruction Instruction to be sent to the external SPI device."]
2423 #[inline(always)]
2424 pub const fn instruction(&self) -> u32 {
2425 let val = (self.0 >> 0usize) & 0xffff_ffff;
2426 val as u32
2427 }
2428 #[doc = "31: 0\\]: Instruction Instruction to be sent to the external SPI device."]
2429 #[inline(always)]
2430 pub fn set_instruction(&mut self, val: u32) {
2431 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2432 }
2433 }
2434 impl Default for Wpir {
2435 #[inline(always)]
2436 fn default() -> Wpir {
2437 Wpir(0)
2438 }
2439 }
2440 impl core::fmt::Debug for Wpir {
2441 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2442 f.debug_struct("Wpir")
2443 .field("instruction", &self.instruction())
2444 .finish()
2445 }
2446 }
2447 #[cfg(feature = "defmt")]
2448 impl defmt::Format for Wpir {
2449 fn format(&self, f: defmt::Formatter) {
2450 #[derive(defmt :: Format)]
2451 struct Wpir {
2452 instruction: u32,
2453 }
2454 let proxy = Wpir {
2455 instruction: self.instruction(),
2456 };
2457 defmt::write!(f, "{}", proxy)
2458 }
2459 }
2460 #[doc = "HSPI wrap timing configuration register."]
2461 #[repr(transparent)]
2462 #[derive(Copy, Clone, Eq, PartialEq)]
2463 pub struct Wptcr(pub u32);
2464 impl Wptcr {
2465 #[doc = "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2466 #[inline(always)]
2467 pub const fn dcyc(&self) -> u8 {
2468 let val = (self.0 >> 0usize) & 0x1f;
2469 val as u8
2470 }
2471 #[doc = "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2472 #[inline(always)]
2473 pub fn set_dcyc(&mut self, val: u8) {
2474 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
2475 }
2476 #[doc = "Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement."]
2477 #[inline(always)]
2478 pub const fn dhqc(&self) -> bool {
2479 let val = (self.0 >> 28usize) & 0x01;
2480 val != 0
2481 }
2482 #[doc = "Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement."]
2483 #[inline(always)]
2484 pub fn set_dhqc(&mut self, val: bool) {
2485 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2486 }
2487 #[doc = "Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1)."]
2488 #[inline(always)]
2489 pub const fn sshift(&self) -> bool {
2490 let val = (self.0 >> 30usize) & 0x01;
2491 val != 0
2492 }
2493 #[doc = "Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1)."]
2494 #[inline(always)]
2495 pub fn set_sshift(&mut self, val: bool) {
2496 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
2497 }
2498 }
2499 impl Default for Wptcr {
2500 #[inline(always)]
2501 fn default() -> Wptcr {
2502 Wptcr(0)
2503 }
2504 }
2505 impl core::fmt::Debug for Wptcr {
2506 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2507 f.debug_struct("Wptcr")
2508 .field("dcyc", &self.dcyc())
2509 .field("dhqc", &self.dhqc())
2510 .field("sshift", &self.sshift())
2511 .finish()
2512 }
2513 }
2514 #[cfg(feature = "defmt")]
2515 impl defmt::Format for Wptcr {
2516 fn format(&self, f: defmt::Formatter) {
2517 #[derive(defmt :: Format)]
2518 struct Wptcr {
2519 dcyc: u8,
2520 dhqc: bool,
2521 sshift: bool,
2522 }
2523 let proxy = Wptcr {
2524 dcyc: self.dcyc(),
2525 dhqc: self.dhqc(),
2526 sshift: self.sshift(),
2527 };
2528 defmt::write!(f, "{}", proxy)
2529 }
2530 }
2531 #[doc = "HSPI write timing configuration register."]
2532 #[repr(transparent)]
2533 #[derive(Copy, Clone, Eq, PartialEq)]
2534 pub struct Wtcr(pub u32);
2535 impl Wtcr {
2536 #[doc = "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2537 #[inline(always)]
2538 pub const fn dcyc(&self) -> u8 {
2539 let val = (self.0 >> 0usize) & 0x1f;
2540 val as u8
2541 }
2542 #[doc = "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2543 #[inline(always)]
2544 pub fn set_dcyc(&mut self, val: u8) {
2545 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
2546 }
2547 }
2548 impl Default for Wtcr {
2549 #[inline(always)]
2550 fn default() -> Wtcr {
2551 Wtcr(0)
2552 }
2553 }
2554 impl core::fmt::Debug for Wtcr {
2555 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2556 f.debug_struct("Wtcr").field("dcyc", &self.dcyc()).finish()
2557 }
2558 }
2559 #[cfg(feature = "defmt")]
2560 impl defmt::Format for Wtcr {
2561 fn format(&self, f: defmt::Formatter) {
2562 #[derive(defmt :: Format)]
2563 struct Wtcr {
2564 dcyc: u8,
2565 }
2566 let proxy = Wtcr { dcyc: self.dcyc() };
2567 defmt::write!(f, "{}", proxy)
2568 }
2569 }
2570}
2571