1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Inter-integrated circuit"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct I2c {
9 ptr: *mut u8,
10}
11unsafe impl Send for I2c {}
12unsafe impl Sync for I2c {}
13impl I2c {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "Control register 1"]
23 #[inline(always)]
24 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "Control register 2"]
28 #[inline(always)]
29 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "Own address register 1"]
33 #[inline(always)]
34 pub const fn oar1(self) -> crate::common::Reg<regs::Oar1, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "Own address register 2"]
38 #[inline(always)]
39 pub const fn oar2(self) -> crate::common::Reg<regs::Oar2, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "Timing register"]
43 #[inline(always)]
44 pub const fn timingr(self) -> crate::common::Reg<regs::Timingr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "Timeout register"]
48 #[inline(always)]
49 pub const fn timeoutr(self) -> crate::common::Reg<regs::Timeoutr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "Interrupt and Status register"]
53 #[inline(always)]
54 pub const fn isr(self) -> crate::common::Reg<regs::Isr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[doc = "Interrupt clear register"]
58 #[inline(always)]
59 pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
61 }
62 #[doc = "PEC register"]
63 #[inline(always)]
64 pub const fn pecr(self) -> crate::common::Reg<regs::Pecr, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
66 }
67 #[doc = "Receive data register"]
68 #[inline(always)]
69 pub const fn rxdr(self) -> crate::common::Reg<regs::Rxdr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
71 }
72 #[doc = "Transmit data register"]
73 #[inline(always)]
74 pub const fn txdr(self) -> crate::common::Reg<regs::Txdr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
76 }
77}
78pub mod regs {
79 #[doc = "Control register 1"]
80 #[repr(transparent)]
81 #[derive(Copy, Clone, Eq, PartialEq)]
82 pub struct Cr1(pub u32);
83 impl Cr1 {
84 #[doc = "Peripheral enable"]
85 #[inline(always)]
86 pub const fn pe(&self) -> bool {
87 let val = (self.0 >> 0usize) & 0x01;
88 val != 0
89 }
90 #[doc = "Peripheral enable"]
91 #[inline(always)]
92 pub fn set_pe(&mut self, val: bool) {
93 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
94 }
95 #[doc = "TX Interrupt enable"]
96 #[inline(always)]
97 pub const fn txie(&self) -> bool {
98 let val = (self.0 >> 1usize) & 0x01;
99 val != 0
100 }
101 #[doc = "TX Interrupt enable"]
102 #[inline(always)]
103 pub fn set_txie(&mut self, val: bool) {
104 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
105 }
106 #[doc = "RX Interrupt enable"]
107 #[inline(always)]
108 pub const fn rxie(&self) -> bool {
109 let val = (self.0 >> 2usize) & 0x01;
110 val != 0
111 }
112 #[doc = "RX Interrupt enable"]
113 #[inline(always)]
114 pub fn set_rxie(&mut self, val: bool) {
115 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
116 }
117 #[doc = "Address match interrupt enable (slave only)"]
118 #[inline(always)]
119 pub const fn addrie(&self) -> bool {
120 let val = (self.0 >> 3usize) & 0x01;
121 val != 0
122 }
123 #[doc = "Address match interrupt enable (slave only)"]
124 #[inline(always)]
125 pub fn set_addrie(&mut self, val: bool) {
126 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
127 }
128 #[doc = "Not acknowledge received interrupt enable"]
129 #[inline(always)]
130 pub const fn nackie(&self) -> bool {
131 let val = (self.0 >> 4usize) & 0x01;
132 val != 0
133 }
134 #[doc = "Not acknowledge received interrupt enable"]
135 #[inline(always)]
136 pub fn set_nackie(&mut self, val: bool) {
137 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
138 }
139 #[doc = "STOP detection Interrupt enable"]
140 #[inline(always)]
141 pub const fn stopie(&self) -> bool {
142 let val = (self.0 >> 5usize) & 0x01;
143 val != 0
144 }
145 #[doc = "STOP detection Interrupt enable"]
146 #[inline(always)]
147 pub fn set_stopie(&mut self, val: bool) {
148 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
149 }
150 #[doc = "Transfer Complete interrupt enable"]
151 #[inline(always)]
152 pub const fn tcie(&self) -> bool {
153 let val = (self.0 >> 6usize) & 0x01;
154 val != 0
155 }
156 #[doc = "Transfer Complete interrupt enable"]
157 #[inline(always)]
158 pub fn set_tcie(&mut self, val: bool) {
159 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
160 }
161 #[doc = "Error interrupts enable"]
162 #[inline(always)]
163 pub const fn errie(&self) -> bool {
164 let val = (self.0 >> 7usize) & 0x01;
165 val != 0
166 }
167 #[doc = "Error interrupts enable"]
168 #[inline(always)]
169 pub fn set_errie(&mut self, val: bool) {
170 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
171 }
172 #[doc = "Digital noise filter"]
173 #[inline(always)]
174 pub const fn dnf(&self) -> super::vals::Dnf {
175 let val = (self.0 >> 8usize) & 0x0f;
176 super::vals::Dnf::from_bits(val as u8)
177 }
178 #[doc = "Digital noise filter"]
179 #[inline(always)]
180 pub fn set_dnf(&mut self, val: super::vals::Dnf) {
181 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
182 }
183 #[doc = "Analog noise filter OFF"]
184 #[inline(always)]
185 pub const fn anfoff(&self) -> bool {
186 let val = (self.0 >> 12usize) & 0x01;
187 val != 0
188 }
189 #[doc = "Analog noise filter OFF"]
190 #[inline(always)]
191 pub fn set_anfoff(&mut self, val: bool) {
192 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
193 }
194 #[doc = "DMA transmission requests enable"]
195 #[inline(always)]
196 pub const fn txdmaen(&self) -> bool {
197 let val = (self.0 >> 14usize) & 0x01;
198 val != 0
199 }
200 #[doc = "DMA transmission requests enable"]
201 #[inline(always)]
202 pub fn set_txdmaen(&mut self, val: bool) {
203 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
204 }
205 #[doc = "DMA reception requests enable"]
206 #[inline(always)]
207 pub const fn rxdmaen(&self) -> bool {
208 let val = (self.0 >> 15usize) & 0x01;
209 val != 0
210 }
211 #[doc = "DMA reception requests enable"]
212 #[inline(always)]
213 pub fn set_rxdmaen(&mut self, val: bool) {
214 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
215 }
216 #[doc = "Slave byte control"]
217 #[inline(always)]
218 pub const fn sbc(&self) -> bool {
219 let val = (self.0 >> 16usize) & 0x01;
220 val != 0
221 }
222 #[doc = "Slave byte control"]
223 #[inline(always)]
224 pub fn set_sbc(&mut self, val: bool) {
225 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
226 }
227 #[doc = "Clock stretching disable"]
228 #[inline(always)]
229 pub const fn nostretch(&self) -> bool {
230 let val = (self.0 >> 17usize) & 0x01;
231 val != 0
232 }
233 #[doc = "Clock stretching disable"]
234 #[inline(always)]
235 pub fn set_nostretch(&mut self, val: bool) {
236 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
237 }
238 #[doc = "General call enable"]
239 #[inline(always)]
240 pub const fn gcen(&self) -> bool {
241 let val = (self.0 >> 19usize) & 0x01;
242 val != 0
243 }
244 #[doc = "General call enable"]
245 #[inline(always)]
246 pub fn set_gcen(&mut self, val: bool) {
247 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
248 }
249 #[doc = "SMBus Host address enable"]
250 #[inline(always)]
251 pub const fn smbhen(&self) -> bool {
252 let val = (self.0 >> 20usize) & 0x01;
253 val != 0
254 }
255 #[doc = "SMBus Host address enable"]
256 #[inline(always)]
257 pub fn set_smbhen(&mut self, val: bool) {
258 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
259 }
260 #[doc = "SMBus Device Default address enable"]
261 #[inline(always)]
262 pub const fn smbden(&self) -> bool {
263 let val = (self.0 >> 21usize) & 0x01;
264 val != 0
265 }
266 #[doc = "SMBus Device Default address enable"]
267 #[inline(always)]
268 pub fn set_smbden(&mut self, val: bool) {
269 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
270 }
271 #[doc = "SMBUS alert enable"]
272 #[inline(always)]
273 pub const fn alerten(&self) -> bool {
274 let val = (self.0 >> 22usize) & 0x01;
275 val != 0
276 }
277 #[doc = "SMBUS alert enable"]
278 #[inline(always)]
279 pub fn set_alerten(&mut self, val: bool) {
280 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
281 }
282 #[doc = "PEC enable"]
283 #[inline(always)]
284 pub const fn pecen(&self) -> bool {
285 let val = (self.0 >> 23usize) & 0x01;
286 val != 0
287 }
288 #[doc = "PEC enable"]
289 #[inline(always)]
290 pub fn set_pecen(&mut self, val: bool) {
291 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
292 }
293 }
294 impl Default for Cr1 {
295 #[inline(always)]
296 fn default() -> Cr1 {
297 Cr1(0)
298 }
299 }
300 impl core::fmt::Debug for Cr1 {
301 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
302 f.debug_struct("Cr1")
303 .field("pe", &self.pe())
304 .field("txie", &self.txie())
305 .field("rxie", &self.rxie())
306 .field("addrie", &self.addrie())
307 .field("nackie", &self.nackie())
308 .field("stopie", &self.stopie())
309 .field("tcie", &self.tcie())
310 .field("errie", &self.errie())
311 .field("dnf", &self.dnf())
312 .field("anfoff", &self.anfoff())
313 .field("txdmaen", &self.txdmaen())
314 .field("rxdmaen", &self.rxdmaen())
315 .field("sbc", &self.sbc())
316 .field("nostretch", &self.nostretch())
317 .field("gcen", &self.gcen())
318 .field("smbhen", &self.smbhen())
319 .field("smbden", &self.smbden())
320 .field("alerten", &self.alerten())
321 .field("pecen", &self.pecen())
322 .finish()
323 }
324 }
325 #[cfg(feature = "defmt")]
326 impl defmt::Format for Cr1 {
327 fn format(&self, f: defmt::Formatter) {
328 #[derive(defmt :: Format)]
329 struct Cr1 {
330 pe: bool,
331 txie: bool,
332 rxie: bool,
333 addrie: bool,
334 nackie: bool,
335 stopie: bool,
336 tcie: bool,
337 errie: bool,
338 dnf: super::vals::Dnf,
339 anfoff: bool,
340 txdmaen: bool,
341 rxdmaen: bool,
342 sbc: bool,
343 nostretch: bool,
344 gcen: bool,
345 smbhen: bool,
346 smbden: bool,
347 alerten: bool,
348 pecen: bool,
349 }
350 let proxy = Cr1 {
351 pe: self.pe(),
352 txie: self.txie(),
353 rxie: self.rxie(),
354 addrie: self.addrie(),
355 nackie: self.nackie(),
356 stopie: self.stopie(),
357 tcie: self.tcie(),
358 errie: self.errie(),
359 dnf: self.dnf(),
360 anfoff: self.anfoff(),
361 txdmaen: self.txdmaen(),
362 rxdmaen: self.rxdmaen(),
363 sbc: self.sbc(),
364 nostretch: self.nostretch(),
365 gcen: self.gcen(),
366 smbhen: self.smbhen(),
367 smbden: self.smbden(),
368 alerten: self.alerten(),
369 pecen: self.pecen(),
370 };
371 defmt::write!(f, "{}", proxy)
372 }
373 }
374 #[doc = "Control register 2"]
375 #[repr(transparent)]
376 #[derive(Copy, Clone, Eq, PartialEq)]
377 pub struct Cr2(pub u32);
378 impl Cr2 {
379 #[doc = "Slave address bit (master mode)"]
380 #[inline(always)]
381 pub const fn sadd(&self) -> u16 {
382 let val = (self.0 >> 0usize) & 0x03ff;
383 val as u16
384 }
385 #[doc = "Slave address bit (master mode)"]
386 #[inline(always)]
387 pub fn set_sadd(&mut self, val: u16) {
388 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
389 }
390 #[doc = "Transfer direction (master mode)"]
391 #[inline(always)]
392 pub const fn dir(&self) -> super::vals::Dir {
393 let val = (self.0 >> 10usize) & 0x01;
394 super::vals::Dir::from_bits(val as u8)
395 }
396 #[doc = "Transfer direction (master mode)"]
397 #[inline(always)]
398 pub fn set_dir(&mut self, val: super::vals::Dir) {
399 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
400 }
401 #[doc = "10-bit addressing mode (master mode)"]
402 #[inline(always)]
403 pub const fn add10(&self) -> super::vals::Addmode {
404 let val = (self.0 >> 11usize) & 0x01;
405 super::vals::Addmode::from_bits(val as u8)
406 }
407 #[doc = "10-bit addressing mode (master mode)"]
408 #[inline(always)]
409 pub fn set_add10(&mut self, val: super::vals::Addmode) {
410 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
411 }
412 #[doc = "10-bit address header only read direction (master receiver mode)"]
413 #[inline(always)]
414 pub const fn head10r(&self) -> super::vals::Headr {
415 let val = (self.0 >> 12usize) & 0x01;
416 super::vals::Headr::from_bits(val as u8)
417 }
418 #[doc = "10-bit address header only read direction (master receiver mode)"]
419 #[inline(always)]
420 pub fn set_head10r(&mut self, val: super::vals::Headr) {
421 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
422 }
423 #[doc = "Start generation"]
424 #[inline(always)]
425 pub const fn start(&self) -> bool {
426 let val = (self.0 >> 13usize) & 0x01;
427 val != 0
428 }
429 #[doc = "Start generation"]
430 #[inline(always)]
431 pub fn set_start(&mut self, val: bool) {
432 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
433 }
434 #[doc = "Stop generation (master mode)"]
435 #[inline(always)]
436 pub const fn stop(&self) -> bool {
437 let val = (self.0 >> 14usize) & 0x01;
438 val != 0
439 }
440 #[doc = "Stop generation (master mode)"]
441 #[inline(always)]
442 pub fn set_stop(&mut self, val: bool) {
443 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
444 }
445 #[doc = "NACK generation (slave mode)"]
446 #[inline(always)]
447 pub const fn nack(&self) -> bool {
448 let val = (self.0 >> 15usize) & 0x01;
449 val != 0
450 }
451 #[doc = "NACK generation (slave mode)"]
452 #[inline(always)]
453 pub fn set_nack(&mut self, val: bool) {
454 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
455 }
456 #[doc = "Number of bytes"]
457 #[inline(always)]
458 pub const fn nbytes(&self) -> u8 {
459 let val = (self.0 >> 16usize) & 0xff;
460 val as u8
461 }
462 #[doc = "Number of bytes"]
463 #[inline(always)]
464 pub fn set_nbytes(&mut self, val: u8) {
465 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
466 }
467 #[doc = "NBYTES reload mode"]
468 #[inline(always)]
469 pub const fn reload(&self) -> super::vals::Reload {
470 let val = (self.0 >> 24usize) & 0x01;
471 super::vals::Reload::from_bits(val as u8)
472 }
473 #[doc = "NBYTES reload mode"]
474 #[inline(always)]
475 pub fn set_reload(&mut self, val: super::vals::Reload) {
476 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize);
477 }
478 #[doc = "Automatic end mode (master mode)"]
479 #[inline(always)]
480 pub const fn autoend(&self) -> super::vals::Autoend {
481 let val = (self.0 >> 25usize) & 0x01;
482 super::vals::Autoend::from_bits(val as u8)
483 }
484 #[doc = "Automatic end mode (master mode)"]
485 #[inline(always)]
486 pub fn set_autoend(&mut self, val: super::vals::Autoend) {
487 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
488 }
489 #[doc = "Packet error checking byte"]
490 #[inline(always)]
491 pub const fn pecbyte(&self) -> bool {
492 let val = (self.0 >> 26usize) & 0x01;
493 val != 0
494 }
495 #[doc = "Packet error checking byte"]
496 #[inline(always)]
497 pub fn set_pecbyte(&mut self, val: bool) {
498 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
499 }
500 }
501 impl Default for Cr2 {
502 #[inline(always)]
503 fn default() -> Cr2 {
504 Cr2(0)
505 }
506 }
507 impl core::fmt::Debug for Cr2 {
508 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
509 f.debug_struct("Cr2")
510 .field("sadd", &self.sadd())
511 .field("dir", &self.dir())
512 .field("add10", &self.add10())
513 .field("head10r", &self.head10r())
514 .field("start", &self.start())
515 .field("stop", &self.stop())
516 .field("nack", &self.nack())
517 .field("nbytes", &self.nbytes())
518 .field("reload", &self.reload())
519 .field("autoend", &self.autoend())
520 .field("pecbyte", &self.pecbyte())
521 .finish()
522 }
523 }
524 #[cfg(feature = "defmt")]
525 impl defmt::Format for Cr2 {
526 fn format(&self, f: defmt::Formatter) {
527 #[derive(defmt :: Format)]
528 struct Cr2 {
529 sadd: u16,
530 dir: super::vals::Dir,
531 add10: super::vals::Addmode,
532 head10r: super::vals::Headr,
533 start: bool,
534 stop: bool,
535 nack: bool,
536 nbytes: u8,
537 reload: super::vals::Reload,
538 autoend: super::vals::Autoend,
539 pecbyte: bool,
540 }
541 let proxy = Cr2 {
542 sadd: self.sadd(),
543 dir: self.dir(),
544 add10: self.add10(),
545 head10r: self.head10r(),
546 start: self.start(),
547 stop: self.stop(),
548 nack: self.nack(),
549 nbytes: self.nbytes(),
550 reload: self.reload(),
551 autoend: self.autoend(),
552 pecbyte: self.pecbyte(),
553 };
554 defmt::write!(f, "{}", proxy)
555 }
556 }
557 #[doc = "Interrupt clear register"]
558 #[repr(transparent)]
559 #[derive(Copy, Clone, Eq, PartialEq)]
560 pub struct Icr(pub u32);
561 impl Icr {
562 #[doc = "Address Matched flag clear"]
563 #[inline(always)]
564 pub const fn addrcf(&self) -> bool {
565 let val = (self.0 >> 3usize) & 0x01;
566 val != 0
567 }
568 #[doc = "Address Matched flag clear"]
569 #[inline(always)]
570 pub fn set_addrcf(&mut self, val: bool) {
571 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
572 }
573 #[doc = "Not Acknowledge flag clear"]
574 #[inline(always)]
575 pub const fn nackcf(&self) -> bool {
576 let val = (self.0 >> 4usize) & 0x01;
577 val != 0
578 }
579 #[doc = "Not Acknowledge flag clear"]
580 #[inline(always)]
581 pub fn set_nackcf(&mut self, val: bool) {
582 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
583 }
584 #[doc = "Stop detection flag clear"]
585 #[inline(always)]
586 pub const fn stopcf(&self) -> bool {
587 let val = (self.0 >> 5usize) & 0x01;
588 val != 0
589 }
590 #[doc = "Stop detection flag clear"]
591 #[inline(always)]
592 pub fn set_stopcf(&mut self, val: bool) {
593 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
594 }
595 #[doc = "Bus error flag clear"]
596 #[inline(always)]
597 pub const fn berrcf(&self) -> bool {
598 let val = (self.0 >> 8usize) & 0x01;
599 val != 0
600 }
601 #[doc = "Bus error flag clear"]
602 #[inline(always)]
603 pub fn set_berrcf(&mut self, val: bool) {
604 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
605 }
606 #[doc = "Arbitration lost flag clear"]
607 #[inline(always)]
608 pub const fn arlocf(&self) -> bool {
609 let val = (self.0 >> 9usize) & 0x01;
610 val != 0
611 }
612 #[doc = "Arbitration lost flag clear"]
613 #[inline(always)]
614 pub fn set_arlocf(&mut self, val: bool) {
615 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
616 }
617 #[doc = "Overrun/Underrun flag clear"]
618 #[inline(always)]
619 pub const fn ovrcf(&self) -> bool {
620 let val = (self.0 >> 10usize) & 0x01;
621 val != 0
622 }
623 #[doc = "Overrun/Underrun flag clear"]
624 #[inline(always)]
625 pub fn set_ovrcf(&mut self, val: bool) {
626 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
627 }
628 #[doc = "PEC Error flag clear"]
629 #[inline(always)]
630 pub const fn peccf(&self) -> bool {
631 let val = (self.0 >> 11usize) & 0x01;
632 val != 0
633 }
634 #[doc = "PEC Error flag clear"]
635 #[inline(always)]
636 pub fn set_peccf(&mut self, val: bool) {
637 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
638 }
639 #[doc = "Timeout detection flag clear"]
640 #[inline(always)]
641 pub const fn timoutcf(&self) -> bool {
642 let val = (self.0 >> 12usize) & 0x01;
643 val != 0
644 }
645 #[doc = "Timeout detection flag clear"]
646 #[inline(always)]
647 pub fn set_timoutcf(&mut self, val: bool) {
648 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
649 }
650 #[doc = "Alert flag clear"]
651 #[inline(always)]
652 pub const fn alertcf(&self) -> bool {
653 let val = (self.0 >> 13usize) & 0x01;
654 val != 0
655 }
656 #[doc = "Alert flag clear"]
657 #[inline(always)]
658 pub fn set_alertcf(&mut self, val: bool) {
659 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
660 }
661 }
662 impl Default for Icr {
663 #[inline(always)]
664 fn default() -> Icr {
665 Icr(0)
666 }
667 }
668 impl core::fmt::Debug for Icr {
669 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
670 f.debug_struct("Icr")
671 .field("addrcf", &self.addrcf())
672 .field("nackcf", &self.nackcf())
673 .field("stopcf", &self.stopcf())
674 .field("berrcf", &self.berrcf())
675 .field("arlocf", &self.arlocf())
676 .field("ovrcf", &self.ovrcf())
677 .field("peccf", &self.peccf())
678 .field("timoutcf", &self.timoutcf())
679 .field("alertcf", &self.alertcf())
680 .finish()
681 }
682 }
683 #[cfg(feature = "defmt")]
684 impl defmt::Format for Icr {
685 fn format(&self, f: defmt::Formatter) {
686 #[derive(defmt :: Format)]
687 struct Icr {
688 addrcf: bool,
689 nackcf: bool,
690 stopcf: bool,
691 berrcf: bool,
692 arlocf: bool,
693 ovrcf: bool,
694 peccf: bool,
695 timoutcf: bool,
696 alertcf: bool,
697 }
698 let proxy = Icr {
699 addrcf: self.addrcf(),
700 nackcf: self.nackcf(),
701 stopcf: self.stopcf(),
702 berrcf: self.berrcf(),
703 arlocf: self.arlocf(),
704 ovrcf: self.ovrcf(),
705 peccf: self.peccf(),
706 timoutcf: self.timoutcf(),
707 alertcf: self.alertcf(),
708 };
709 defmt::write!(f, "{}", proxy)
710 }
711 }
712 #[doc = "Interrupt and Status register"]
713 #[repr(transparent)]
714 #[derive(Copy, Clone, Eq, PartialEq)]
715 pub struct Isr(pub u32);
716 impl Isr {
717 #[doc = "Transmit data register empty (transmitters)"]
718 #[inline(always)]
719 pub const fn txe(&self) -> bool {
720 let val = (self.0 >> 0usize) & 0x01;
721 val != 0
722 }
723 #[doc = "Transmit data register empty (transmitters)"]
724 #[inline(always)]
725 pub fn set_txe(&mut self, val: bool) {
726 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
727 }
728 #[doc = "Transmit interrupt status (transmitters)"]
729 #[inline(always)]
730 pub const fn txis(&self) -> bool {
731 let val = (self.0 >> 1usize) & 0x01;
732 val != 0
733 }
734 #[doc = "Transmit interrupt status (transmitters)"]
735 #[inline(always)]
736 pub fn set_txis(&mut self, val: bool) {
737 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
738 }
739 #[doc = "Receive data register not empty (receivers)"]
740 #[inline(always)]
741 pub const fn rxne(&self) -> bool {
742 let val = (self.0 >> 2usize) & 0x01;
743 val != 0
744 }
745 #[doc = "Receive data register not empty (receivers)"]
746 #[inline(always)]
747 pub fn set_rxne(&mut self, val: bool) {
748 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
749 }
750 #[doc = "Address matched (slave mode)"]
751 #[inline(always)]
752 pub const fn addr(&self) -> bool {
753 let val = (self.0 >> 3usize) & 0x01;
754 val != 0
755 }
756 #[doc = "Address matched (slave mode)"]
757 #[inline(always)]
758 pub fn set_addr(&mut self, val: bool) {
759 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
760 }
761 #[doc = "Not acknowledge received flag"]
762 #[inline(always)]
763 pub const fn nackf(&self) -> bool {
764 let val = (self.0 >> 4usize) & 0x01;
765 val != 0
766 }
767 #[doc = "Not acknowledge received flag"]
768 #[inline(always)]
769 pub fn set_nackf(&mut self, val: bool) {
770 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
771 }
772 #[doc = "Stop detection flag"]
773 #[inline(always)]
774 pub const fn stopf(&self) -> bool {
775 let val = (self.0 >> 5usize) & 0x01;
776 val != 0
777 }
778 #[doc = "Stop detection flag"]
779 #[inline(always)]
780 pub fn set_stopf(&mut self, val: bool) {
781 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
782 }
783 #[doc = "Transfer Complete (master mode)"]
784 #[inline(always)]
785 pub const fn tc(&self) -> bool {
786 let val = (self.0 >> 6usize) & 0x01;
787 val != 0
788 }
789 #[doc = "Transfer Complete (master mode)"]
790 #[inline(always)]
791 pub fn set_tc(&mut self, val: bool) {
792 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
793 }
794 #[doc = "Transfer Complete Reload"]
795 #[inline(always)]
796 pub const fn tcr(&self) -> bool {
797 let val = (self.0 >> 7usize) & 0x01;
798 val != 0
799 }
800 #[doc = "Transfer Complete Reload"]
801 #[inline(always)]
802 pub fn set_tcr(&mut self, val: bool) {
803 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
804 }
805 #[doc = "Bus error"]
806 #[inline(always)]
807 pub const fn berr(&self) -> bool {
808 let val = (self.0 >> 8usize) & 0x01;
809 val != 0
810 }
811 #[doc = "Bus error"]
812 #[inline(always)]
813 pub fn set_berr(&mut self, val: bool) {
814 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
815 }
816 #[doc = "Arbitration lost"]
817 #[inline(always)]
818 pub const fn arlo(&self) -> bool {
819 let val = (self.0 >> 9usize) & 0x01;
820 val != 0
821 }
822 #[doc = "Arbitration lost"]
823 #[inline(always)]
824 pub fn set_arlo(&mut self, val: bool) {
825 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
826 }
827 #[doc = "Overrun/Underrun (slave mode)"]
828 #[inline(always)]
829 pub const fn ovr(&self) -> bool {
830 let val = (self.0 >> 10usize) & 0x01;
831 val != 0
832 }
833 #[doc = "Overrun/Underrun (slave mode)"]
834 #[inline(always)]
835 pub fn set_ovr(&mut self, val: bool) {
836 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
837 }
838 #[doc = "PEC Error in reception"]
839 #[inline(always)]
840 pub const fn pecerr(&self) -> bool {
841 let val = (self.0 >> 11usize) & 0x01;
842 val != 0
843 }
844 #[doc = "PEC Error in reception"]
845 #[inline(always)]
846 pub fn set_pecerr(&mut self, val: bool) {
847 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
848 }
849 #[doc = "Timeout or t_low detection flag"]
850 #[inline(always)]
851 pub const fn timeout(&self) -> bool {
852 let val = (self.0 >> 12usize) & 0x01;
853 val != 0
854 }
855 #[doc = "Timeout or t_low detection flag"]
856 #[inline(always)]
857 pub fn set_timeout(&mut self, val: bool) {
858 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
859 }
860 #[doc = "SMBus alert"]
861 #[inline(always)]
862 pub const fn alert(&self) -> bool {
863 let val = (self.0 >> 13usize) & 0x01;
864 val != 0
865 }
866 #[doc = "SMBus alert"]
867 #[inline(always)]
868 pub fn set_alert(&mut self, val: bool) {
869 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
870 }
871 #[doc = "Bus busy"]
872 #[inline(always)]
873 pub const fn busy(&self) -> bool {
874 let val = (self.0 >> 15usize) & 0x01;
875 val != 0
876 }
877 #[doc = "Bus busy"]
878 #[inline(always)]
879 pub fn set_busy(&mut self, val: bool) {
880 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
881 }
882 #[doc = "Transfer direction (Slave mode)"]
883 #[inline(always)]
884 pub const fn dir(&self) -> super::vals::Dir {
885 let val = (self.0 >> 16usize) & 0x01;
886 super::vals::Dir::from_bits(val as u8)
887 }
888 #[doc = "Transfer direction (Slave mode)"]
889 #[inline(always)]
890 pub fn set_dir(&mut self, val: super::vals::Dir) {
891 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize);
892 }
893 #[doc = "Address match code (Slave mode)"]
894 #[inline(always)]
895 pub const fn addcode(&self) -> u8 {
896 let val = (self.0 >> 17usize) & 0x7f;
897 val as u8
898 }
899 #[doc = "Address match code (Slave mode)"]
900 #[inline(always)]
901 pub fn set_addcode(&mut self, val: u8) {
902 self.0 = (self.0 & !(0x7f << 17usize)) | (((val as u32) & 0x7f) << 17usize);
903 }
904 }
905 impl Default for Isr {
906 #[inline(always)]
907 fn default() -> Isr {
908 Isr(0)
909 }
910 }
911 impl core::fmt::Debug for Isr {
912 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
913 f.debug_struct("Isr")
914 .field("txe", &self.txe())
915 .field("txis", &self.txis())
916 .field("rxne", &self.rxne())
917 .field("addr", &self.addr())
918 .field("nackf", &self.nackf())
919 .field("stopf", &self.stopf())
920 .field("tc", &self.tc())
921 .field("tcr", &self.tcr())
922 .field("berr", &self.berr())
923 .field("arlo", &self.arlo())
924 .field("ovr", &self.ovr())
925 .field("pecerr", &self.pecerr())
926 .field("timeout", &self.timeout())
927 .field("alert", &self.alert())
928 .field("busy", &self.busy())
929 .field("dir", &self.dir())
930 .field("addcode", &self.addcode())
931 .finish()
932 }
933 }
934 #[cfg(feature = "defmt")]
935 impl defmt::Format for Isr {
936 fn format(&self, f: defmt::Formatter) {
937 #[derive(defmt :: Format)]
938 struct Isr {
939 txe: bool,
940 txis: bool,
941 rxne: bool,
942 addr: bool,
943 nackf: bool,
944 stopf: bool,
945 tc: bool,
946 tcr: bool,
947 berr: bool,
948 arlo: bool,
949 ovr: bool,
950 pecerr: bool,
951 timeout: bool,
952 alert: bool,
953 busy: bool,
954 dir: super::vals::Dir,
955 addcode: u8,
956 }
957 let proxy = Isr {
958 txe: self.txe(),
959 txis: self.txis(),
960 rxne: self.rxne(),
961 addr: self.addr(),
962 nackf: self.nackf(),
963 stopf: self.stopf(),
964 tc: self.tc(),
965 tcr: self.tcr(),
966 berr: self.berr(),
967 arlo: self.arlo(),
968 ovr: self.ovr(),
969 pecerr: self.pecerr(),
970 timeout: self.timeout(),
971 alert: self.alert(),
972 busy: self.busy(),
973 dir: self.dir(),
974 addcode: self.addcode(),
975 };
976 defmt::write!(f, "{}", proxy)
977 }
978 }
979 #[doc = "Own address register 1"]
980 #[repr(transparent)]
981 #[derive(Copy, Clone, Eq, PartialEq)]
982 pub struct Oar1(pub u32);
983 impl Oar1 {
984 #[doc = "Interface address"]
985 #[inline(always)]
986 pub const fn oa1(&self) -> u16 {
987 let val = (self.0 >> 0usize) & 0x03ff;
988 val as u16
989 }
990 #[doc = "Interface address"]
991 #[inline(always)]
992 pub fn set_oa1(&mut self, val: u16) {
993 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
994 }
995 #[doc = "Own Address 1 10-bit mode"]
996 #[inline(always)]
997 pub const fn oa1mode(&self) -> super::vals::Addmode {
998 let val = (self.0 >> 10usize) & 0x01;
999 super::vals::Addmode::from_bits(val as u8)
1000 }
1001 #[doc = "Own Address 1 10-bit mode"]
1002 #[inline(always)]
1003 pub fn set_oa1mode(&mut self, val: super::vals::Addmode) {
1004 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
1005 }
1006 #[doc = "Own Address 1 enable"]
1007 #[inline(always)]
1008 pub const fn oa1en(&self) -> bool {
1009 let val = (self.0 >> 15usize) & 0x01;
1010 val != 0
1011 }
1012 #[doc = "Own Address 1 enable"]
1013 #[inline(always)]
1014 pub fn set_oa1en(&mut self, val: bool) {
1015 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1016 }
1017 }
1018 impl Default for Oar1 {
1019 #[inline(always)]
1020 fn default() -> Oar1 {
1021 Oar1(0)
1022 }
1023 }
1024 impl core::fmt::Debug for Oar1 {
1025 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1026 f.debug_struct("Oar1")
1027 .field("oa1", &self.oa1())
1028 .field("oa1mode", &self.oa1mode())
1029 .field("oa1en", &self.oa1en())
1030 .finish()
1031 }
1032 }
1033 #[cfg(feature = "defmt")]
1034 impl defmt::Format for Oar1 {
1035 fn format(&self, f: defmt::Formatter) {
1036 #[derive(defmt :: Format)]
1037 struct Oar1 {
1038 oa1: u16,
1039 oa1mode: super::vals::Addmode,
1040 oa1en: bool,
1041 }
1042 let proxy = Oar1 {
1043 oa1: self.oa1(),
1044 oa1mode: self.oa1mode(),
1045 oa1en: self.oa1en(),
1046 };
1047 defmt::write!(f, "{}", proxy)
1048 }
1049 }
1050 #[doc = "Own address register 2"]
1051 #[repr(transparent)]
1052 #[derive(Copy, Clone, Eq, PartialEq)]
1053 pub struct Oar2(pub u32);
1054 impl Oar2 {
1055 #[doc = "Interface address"]
1056 #[inline(always)]
1057 pub const fn oa2(&self) -> u8 {
1058 let val = (self.0 >> 1usize) & 0x7f;
1059 val as u8
1060 }
1061 #[doc = "Interface address"]
1062 #[inline(always)]
1063 pub fn set_oa2(&mut self, val: u8) {
1064 self.0 = (self.0 & !(0x7f << 1usize)) | (((val as u32) & 0x7f) << 1usize);
1065 }
1066 #[doc = "Own Address 2 masks"]
1067 #[inline(always)]
1068 pub const fn oa2msk(&self) -> super::vals::Oamsk {
1069 let val = (self.0 >> 8usize) & 0x07;
1070 super::vals::Oamsk::from_bits(val as u8)
1071 }
1072 #[doc = "Own Address 2 masks"]
1073 #[inline(always)]
1074 pub fn set_oa2msk(&mut self, val: super::vals::Oamsk) {
1075 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
1076 }
1077 #[doc = "Own Address 2 enable"]
1078 #[inline(always)]
1079 pub const fn oa2en(&self) -> bool {
1080 let val = (self.0 >> 15usize) & 0x01;
1081 val != 0
1082 }
1083 #[doc = "Own Address 2 enable"]
1084 #[inline(always)]
1085 pub fn set_oa2en(&mut self, val: bool) {
1086 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1087 }
1088 }
1089 impl Default for Oar2 {
1090 #[inline(always)]
1091 fn default() -> Oar2 {
1092 Oar2(0)
1093 }
1094 }
1095 impl core::fmt::Debug for Oar2 {
1096 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1097 f.debug_struct("Oar2")
1098 .field("oa2", &self.oa2())
1099 .field("oa2msk", &self.oa2msk())
1100 .field("oa2en", &self.oa2en())
1101 .finish()
1102 }
1103 }
1104 #[cfg(feature = "defmt")]
1105 impl defmt::Format for Oar2 {
1106 fn format(&self, f: defmt::Formatter) {
1107 #[derive(defmt :: Format)]
1108 struct Oar2 {
1109 oa2: u8,
1110 oa2msk: super::vals::Oamsk,
1111 oa2en: bool,
1112 }
1113 let proxy = Oar2 {
1114 oa2: self.oa2(),
1115 oa2msk: self.oa2msk(),
1116 oa2en: self.oa2en(),
1117 };
1118 defmt::write!(f, "{}", proxy)
1119 }
1120 }
1121 #[doc = "PEC register"]
1122 #[repr(transparent)]
1123 #[derive(Copy, Clone, Eq, PartialEq)]
1124 pub struct Pecr(pub u32);
1125 impl Pecr {
1126 #[doc = "Packet error checking register"]
1127 #[inline(always)]
1128 pub const fn pec(&self) -> u8 {
1129 let val = (self.0 >> 0usize) & 0xff;
1130 val as u8
1131 }
1132 #[doc = "Packet error checking register"]
1133 #[inline(always)]
1134 pub fn set_pec(&mut self, val: u8) {
1135 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1136 }
1137 }
1138 impl Default for Pecr {
1139 #[inline(always)]
1140 fn default() -> Pecr {
1141 Pecr(0)
1142 }
1143 }
1144 impl core::fmt::Debug for Pecr {
1145 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1146 f.debug_struct("Pecr").field("pec", &self.pec()).finish()
1147 }
1148 }
1149 #[cfg(feature = "defmt")]
1150 impl defmt::Format for Pecr {
1151 fn format(&self, f: defmt::Formatter) {
1152 #[derive(defmt :: Format)]
1153 struct Pecr {
1154 pec: u8,
1155 }
1156 let proxy = Pecr { pec: self.pec() };
1157 defmt::write!(f, "{}", proxy)
1158 }
1159 }
1160 #[doc = "Receive data register"]
1161 #[repr(transparent)]
1162 #[derive(Copy, Clone, Eq, PartialEq)]
1163 pub struct Rxdr(pub u32);
1164 impl Rxdr {
1165 #[doc = "8-bit receive data"]
1166 #[inline(always)]
1167 pub const fn rxdata(&self) -> u8 {
1168 let val = (self.0 >> 0usize) & 0xff;
1169 val as u8
1170 }
1171 #[doc = "8-bit receive data"]
1172 #[inline(always)]
1173 pub fn set_rxdata(&mut self, val: u8) {
1174 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1175 }
1176 }
1177 impl Default for Rxdr {
1178 #[inline(always)]
1179 fn default() -> Rxdr {
1180 Rxdr(0)
1181 }
1182 }
1183 impl core::fmt::Debug for Rxdr {
1184 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1185 f.debug_struct("Rxdr").field("rxdata", &self.rxdata()).finish()
1186 }
1187 }
1188 #[cfg(feature = "defmt")]
1189 impl defmt::Format for Rxdr {
1190 fn format(&self, f: defmt::Formatter) {
1191 #[derive(defmt :: Format)]
1192 struct Rxdr {
1193 rxdata: u8,
1194 }
1195 let proxy = Rxdr { rxdata: self.rxdata() };
1196 defmt::write!(f, "{}", proxy)
1197 }
1198 }
1199 #[doc = "Timeout register"]
1200 #[repr(transparent)]
1201 #[derive(Copy, Clone, Eq, PartialEq)]
1202 pub struct Timeoutr(pub u32);
1203 impl Timeoutr {
1204 #[doc = "Bus timeout A"]
1205 #[inline(always)]
1206 pub const fn timeouta(&self) -> u16 {
1207 let val = (self.0 >> 0usize) & 0x0fff;
1208 val as u16
1209 }
1210 #[doc = "Bus timeout A"]
1211 #[inline(always)]
1212 pub fn set_timeouta(&mut self, val: u16) {
1213 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
1214 }
1215 #[doc = "Idle clock timeout detection"]
1216 #[inline(always)]
1217 pub const fn tidle(&self) -> bool {
1218 let val = (self.0 >> 12usize) & 0x01;
1219 val != 0
1220 }
1221 #[doc = "Idle clock timeout detection"]
1222 #[inline(always)]
1223 pub fn set_tidle(&mut self, val: bool) {
1224 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1225 }
1226 #[doc = "Clock timeout enable"]
1227 #[inline(always)]
1228 pub const fn timouten(&self) -> bool {
1229 let val = (self.0 >> 15usize) & 0x01;
1230 val != 0
1231 }
1232 #[doc = "Clock timeout enable"]
1233 #[inline(always)]
1234 pub fn set_timouten(&mut self, val: bool) {
1235 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1236 }
1237 #[doc = "Bus timeout B"]
1238 #[inline(always)]
1239 pub const fn timeoutb(&self) -> u16 {
1240 let val = (self.0 >> 16usize) & 0x0fff;
1241 val as u16
1242 }
1243 #[doc = "Bus timeout B"]
1244 #[inline(always)]
1245 pub fn set_timeoutb(&mut self, val: u16) {
1246 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
1247 }
1248 #[doc = "Extended clock timeout enable"]
1249 #[inline(always)]
1250 pub const fn texten(&self) -> bool {
1251 let val = (self.0 >> 31usize) & 0x01;
1252 val != 0
1253 }
1254 #[doc = "Extended clock timeout enable"]
1255 #[inline(always)]
1256 pub fn set_texten(&mut self, val: bool) {
1257 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1258 }
1259 }
1260 impl Default for Timeoutr {
1261 #[inline(always)]
1262 fn default() -> Timeoutr {
1263 Timeoutr(0)
1264 }
1265 }
1266 impl core::fmt::Debug for Timeoutr {
1267 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1268 f.debug_struct("Timeoutr")
1269 .field("timeouta", &self.timeouta())
1270 .field("tidle", &self.tidle())
1271 .field("timouten", &self.timouten())
1272 .field("timeoutb", &self.timeoutb())
1273 .field("texten", &self.texten())
1274 .finish()
1275 }
1276 }
1277 #[cfg(feature = "defmt")]
1278 impl defmt::Format for Timeoutr {
1279 fn format(&self, f: defmt::Formatter) {
1280 #[derive(defmt :: Format)]
1281 struct Timeoutr {
1282 timeouta: u16,
1283 tidle: bool,
1284 timouten: bool,
1285 timeoutb: u16,
1286 texten: bool,
1287 }
1288 let proxy = Timeoutr {
1289 timeouta: self.timeouta(),
1290 tidle: self.tidle(),
1291 timouten: self.timouten(),
1292 timeoutb: self.timeoutb(),
1293 texten: self.texten(),
1294 };
1295 defmt::write!(f, "{}", proxy)
1296 }
1297 }
1298 #[doc = "Timing register"]
1299 #[repr(transparent)]
1300 #[derive(Copy, Clone, Eq, PartialEq)]
1301 pub struct Timingr(pub u32);
1302 impl Timingr {
1303 #[doc = "SCL low period (master mode)"]
1304 #[inline(always)]
1305 pub const fn scll(&self) -> u8 {
1306 let val = (self.0 >> 0usize) & 0xff;
1307 val as u8
1308 }
1309 #[doc = "SCL low period (master mode)"]
1310 #[inline(always)]
1311 pub fn set_scll(&mut self, val: u8) {
1312 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1313 }
1314 #[doc = "SCL high period (master mode)"]
1315 #[inline(always)]
1316 pub const fn sclh(&self) -> u8 {
1317 let val = (self.0 >> 8usize) & 0xff;
1318 val as u8
1319 }
1320 #[doc = "SCL high period (master mode)"]
1321 #[inline(always)]
1322 pub fn set_sclh(&mut self, val: u8) {
1323 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
1324 }
1325 #[doc = "Data hold time"]
1326 #[inline(always)]
1327 pub const fn sdadel(&self) -> u8 {
1328 let val = (self.0 >> 16usize) & 0x0f;
1329 val as u8
1330 }
1331 #[doc = "Data hold time"]
1332 #[inline(always)]
1333 pub fn set_sdadel(&mut self, val: u8) {
1334 self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
1335 }
1336 #[doc = "Data setup time"]
1337 #[inline(always)]
1338 pub const fn scldel(&self) -> u8 {
1339 let val = (self.0 >> 20usize) & 0x0f;
1340 val as u8
1341 }
1342 #[doc = "Data setup time"]
1343 #[inline(always)]
1344 pub fn set_scldel(&mut self, val: u8) {
1345 self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
1346 }
1347 #[doc = "Timing prescaler"]
1348 #[inline(always)]
1349 pub const fn presc(&self) -> u8 {
1350 let val = (self.0 >> 28usize) & 0x0f;
1351 val as u8
1352 }
1353 #[doc = "Timing prescaler"]
1354 #[inline(always)]
1355 pub fn set_presc(&mut self, val: u8) {
1356 self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
1357 }
1358 }
1359 impl Default for Timingr {
1360 #[inline(always)]
1361 fn default() -> Timingr {
1362 Timingr(0)
1363 }
1364 }
1365 impl core::fmt::Debug for Timingr {
1366 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1367 f.debug_struct("Timingr")
1368 .field("scll", &self.scll())
1369 .field("sclh", &self.sclh())
1370 .field("sdadel", &self.sdadel())
1371 .field("scldel", &self.scldel())
1372 .field("presc", &self.presc())
1373 .finish()
1374 }
1375 }
1376 #[cfg(feature = "defmt")]
1377 impl defmt::Format for Timingr {
1378 fn format(&self, f: defmt::Formatter) {
1379 #[derive(defmt :: Format)]
1380 struct Timingr {
1381 scll: u8,
1382 sclh: u8,
1383 sdadel: u8,
1384 scldel: u8,
1385 presc: u8,
1386 }
1387 let proxy = Timingr {
1388 scll: self.scll(),
1389 sclh: self.sclh(),
1390 sdadel: self.sdadel(),
1391 scldel: self.scldel(),
1392 presc: self.presc(),
1393 };
1394 defmt::write!(f, "{}", proxy)
1395 }
1396 }
1397 #[doc = "Transmit data register"]
1398 #[repr(transparent)]
1399 #[derive(Copy, Clone, Eq, PartialEq)]
1400 pub struct Txdr(pub u32);
1401 impl Txdr {
1402 #[doc = "8-bit transmit data"]
1403 #[inline(always)]
1404 pub const fn txdata(&self) -> u8 {
1405 let val = (self.0 >> 0usize) & 0xff;
1406 val as u8
1407 }
1408 #[doc = "8-bit transmit data"]
1409 #[inline(always)]
1410 pub fn set_txdata(&mut self, val: u8) {
1411 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1412 }
1413 }
1414 impl Default for Txdr {
1415 #[inline(always)]
1416 fn default() -> Txdr {
1417 Txdr(0)
1418 }
1419 }
1420 impl core::fmt::Debug for Txdr {
1421 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1422 f.debug_struct("Txdr").field("txdata", &self.txdata()).finish()
1423 }
1424 }
1425 #[cfg(feature = "defmt")]
1426 impl defmt::Format for Txdr {
1427 fn format(&self, f: defmt::Formatter) {
1428 #[derive(defmt :: Format)]
1429 struct Txdr {
1430 txdata: u8,
1431 }
1432 let proxy = Txdr { txdata: self.txdata() };
1433 defmt::write!(f, "{}", proxy)
1434 }
1435 }
1436}
1437pub mod vals {
1438 #[repr(u8)]
1439 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1440 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1441 pub enum Addmode {
1442 #[doc = "7-bit addressing mode"]
1443 BIT7 = 0x0,
1444 #[doc = "10-bit addressing mode"]
1445 BIT10 = 0x01,
1446 }
1447 impl Addmode {
1448 #[inline(always)]
1449 pub const fn from_bits(val: u8) -> Addmode {
1450 unsafe { core::mem::transmute(val & 0x01) }
1451 }
1452 #[inline(always)]
1453 pub const fn to_bits(self) -> u8 {
1454 unsafe { core::mem::transmute(self) }
1455 }
1456 }
1457 impl From<u8> for Addmode {
1458 #[inline(always)]
1459 fn from(val: u8) -> Addmode {
1460 Addmode::from_bits(val)
1461 }
1462 }
1463 impl From<Addmode> for u8 {
1464 #[inline(always)]
1465 fn from(val: Addmode) -> u8 {
1466 Addmode::to_bits(val)
1467 }
1468 }
1469 #[repr(u8)]
1470 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1471 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1472 pub enum Autoend {
1473 #[doc = "Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low"]
1474 SOFTWARE = 0x0,
1475 #[doc = "Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred"]
1476 AUTOMATIC = 0x01,
1477 }
1478 impl Autoend {
1479 #[inline(always)]
1480 pub const fn from_bits(val: u8) -> Autoend {
1481 unsafe { core::mem::transmute(val & 0x01) }
1482 }
1483 #[inline(always)]
1484 pub const fn to_bits(self) -> u8 {
1485 unsafe { core::mem::transmute(self) }
1486 }
1487 }
1488 impl From<u8> for Autoend {
1489 #[inline(always)]
1490 fn from(val: u8) -> Autoend {
1491 Autoend::from_bits(val)
1492 }
1493 }
1494 impl From<Autoend> for u8 {
1495 #[inline(always)]
1496 fn from(val: Autoend) -> u8 {
1497 Autoend::to_bits(val)
1498 }
1499 }
1500 #[repr(u8)]
1501 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1502 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1503 pub enum Dir {
1504 #[doc = "Write transfer, slave enters receiver mode"]
1505 WRITE = 0x0,
1506 #[doc = "Read transfer, slave enters transmitter mode"]
1507 READ = 0x01,
1508 }
1509 impl Dir {
1510 #[inline(always)]
1511 pub const fn from_bits(val: u8) -> Dir {
1512 unsafe { core::mem::transmute(val & 0x01) }
1513 }
1514 #[inline(always)]
1515 pub const fn to_bits(self) -> u8 {
1516 unsafe { core::mem::transmute(self) }
1517 }
1518 }
1519 impl From<u8> for Dir {
1520 #[inline(always)]
1521 fn from(val: u8) -> Dir {
1522 Dir::from_bits(val)
1523 }
1524 }
1525 impl From<Dir> for u8 {
1526 #[inline(always)]
1527 fn from(val: Dir) -> u8 {
1528 Dir::to_bits(val)
1529 }
1530 }
1531 #[repr(u8)]
1532 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1533 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1534 pub enum Dnf {
1535 #[doc = "Digital filter disabled"]
1536 NO_FILTER = 0x0,
1537 #[doc = "Digital filter enabled and filtering capability up to 1 tI2CCLK"]
1538 FILTER1 = 0x01,
1539 #[doc = "Digital filter enabled and filtering capability up to 2 tI2CCLK"]
1540 FILTER2 = 0x02,
1541 #[doc = "Digital filter enabled and filtering capability up to 3 tI2CCLK"]
1542 FILTER3 = 0x03,
1543 #[doc = "Digital filter enabled and filtering capability up to 4 tI2CCLK"]
1544 FILTER4 = 0x04,
1545 #[doc = "Digital filter enabled and filtering capability up to 5 tI2CCLK"]
1546 FILTER5 = 0x05,
1547 #[doc = "Digital filter enabled and filtering capability up to 6 tI2CCLK"]
1548 FILTER6 = 0x06,
1549 #[doc = "Digital filter enabled and filtering capability up to 7 tI2CCLK"]
1550 FILTER7 = 0x07,
1551 #[doc = "Digital filter enabled and filtering capability up to 8 tI2CCLK"]
1552 FILTER8 = 0x08,
1553 #[doc = "Digital filter enabled and filtering capability up to 9 tI2CCLK"]
1554 FILTER9 = 0x09,
1555 #[doc = "Digital filter enabled and filtering capability up to 10 tI2CCLK"]
1556 FILTER10 = 0x0a,
1557 #[doc = "Digital filter enabled and filtering capability up to 11 tI2CCLK"]
1558 FILTER11 = 0x0b,
1559 #[doc = "Digital filter enabled and filtering capability up to 12 tI2CCLK"]
1560 FILTER12 = 0x0c,
1561 #[doc = "Digital filter enabled and filtering capability up to 13 tI2CCLK"]
1562 FILTER13 = 0x0d,
1563 #[doc = "Digital filter enabled and filtering capability up to 14 tI2CCLK"]
1564 FILTER14 = 0x0e,
1565 #[doc = "Digital filter enabled and filtering capability up to 15 tI2CCLK"]
1566 FILTER15 = 0x0f,
1567 }
1568 impl Dnf {
1569 #[inline(always)]
1570 pub const fn from_bits(val: u8) -> Dnf {
1571 unsafe { core::mem::transmute(val & 0x0f) }
1572 }
1573 #[inline(always)]
1574 pub const fn to_bits(self) -> u8 {
1575 unsafe { core::mem::transmute(self) }
1576 }
1577 }
1578 impl From<u8> for Dnf {
1579 #[inline(always)]
1580 fn from(val: u8) -> Dnf {
1581 Dnf::from_bits(val)
1582 }
1583 }
1584 impl From<Dnf> for u8 {
1585 #[inline(always)]
1586 fn from(val: Dnf) -> u8 {
1587 Dnf::to_bits(val)
1588 }
1589 }
1590 #[repr(u8)]
1591 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1592 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1593 pub enum Headr {
1594 #[doc = "The master sends the complete 10 bit slave address read sequence"]
1595 COMPLETE = 0x0,
1596 #[doc = "The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction"]
1597 PARTIAL = 0x01,
1598 }
1599 impl Headr {
1600 #[inline(always)]
1601 pub const fn from_bits(val: u8) -> Headr {
1602 unsafe { core::mem::transmute(val & 0x01) }
1603 }
1604 #[inline(always)]
1605 pub const fn to_bits(self) -> u8 {
1606 unsafe { core::mem::transmute(self) }
1607 }
1608 }
1609 impl From<u8> for Headr {
1610 #[inline(always)]
1611 fn from(val: u8) -> Headr {
1612 Headr::from_bits(val)
1613 }
1614 }
1615 impl From<Headr> for u8 {
1616 #[inline(always)]
1617 fn from(val: Headr) -> u8 {
1618 Headr::to_bits(val)
1619 }
1620 }
1621 #[repr(u8)]
1622 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1623 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1624 pub enum Oamsk {
1625 #[doc = "No mask"]
1626 NO_MASK = 0x0,
1627 #[doc = "OA2\\[1\\]
1628is masked and don’t care. Only OA2\\[7:2\\]
1629are compared"]
1630 MASK1 = 0x01,
1631 #[doc = "OA2\\[2:1\\]
1632are masked and don’t care. Only OA2\\[7:3\\]
1633are compared"]
1634 MASK2 = 0x02,
1635 #[doc = "OA2\\[3:1\\]
1636are masked and don’t care. Only OA2\\[7:4\\]
1637are compared"]
1638 MASK3 = 0x03,
1639 #[doc = "OA2\\[4:1\\]
1640are masked and don’t care. Only OA2\\[7:5\\]
1641are compared"]
1642 MASK4 = 0x04,
1643 #[doc = "OA2\\[5:1\\]
1644are masked and don’t care. Only OA2\\[7:6\\]
1645are compared"]
1646 MASK5 = 0x05,
1647 #[doc = "OA2\\[6:1\\]
1648are masked and don’t care. Only OA2\\[7\\]
1649is compared."]
1650 MASK6 = 0x06,
1651 #[doc = "OA2\\[7:1\\]
1652are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged"]
1653 MASK7 = 0x07,
1654 }
1655 impl Oamsk {
1656 #[inline(always)]
1657 pub const fn from_bits(val: u8) -> Oamsk {
1658 unsafe { core::mem::transmute(val & 0x07) }
1659 }
1660 #[inline(always)]
1661 pub const fn to_bits(self) -> u8 {
1662 unsafe { core::mem::transmute(self) }
1663 }
1664 }
1665 impl From<u8> for Oamsk {
1666 #[inline(always)]
1667 fn from(val: u8) -> Oamsk {
1668 Oamsk::from_bits(val)
1669 }
1670 }
1671 impl From<Oamsk> for u8 {
1672 #[inline(always)]
1673 fn from(val: Oamsk) -> u8 {
1674 Oamsk::to_bits(val)
1675 }
1676 }
1677 #[repr(u8)]
1678 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1679 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1680 pub enum Reload {
1681 #[doc = "The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)"]
1682 COMPLETED = 0x0,
1683 #[doc = "The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)"]
1684 NOT_COMPLETED = 0x01,
1685 }
1686 impl Reload {
1687 #[inline(always)]
1688 pub const fn from_bits(val: u8) -> Reload {
1689 unsafe { core::mem::transmute(val & 0x01) }
1690 }
1691 #[inline(always)]
1692 pub const fn to_bits(self) -> u8 {
1693 unsafe { core::mem::transmute(self) }
1694 }
1695 }
1696 impl From<u8> for Reload {
1697 #[inline(always)]
1698 fn from(val: u8) -> Reload {
1699 Reload::from_bits(val)
1700 }
1701 }
1702 impl From<Reload> for u8 {
1703 #[inline(always)]
1704 fn from(val: Reload) -> u8 {
1705 Reload::to_bits(val)
1706 }
1707 }
1708}
1709