1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Instruction Cache Control Registers."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Icache {
9 ptr: *mut u8,
10}
11unsafe impl Send for Icache {}
12unsafe impl Sync for Icache {}
13impl Icache {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "ICACHE control register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "ICACHE status register."]
28 #[inline(always)]
29 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::R> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "ICACHE interrupt enable register."]
33 #[inline(always)]
34 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "ICACHE flag clear register."]
38 #[inline(always)]
39 pub const fn fcr(self) -> crate::common::Reg<regs::Fcr, crate::common::W> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "ICACHE hit monitor register."]
43 #[inline(always)]
44 pub const fn hmonr(self) -> crate::common::Reg<u32, crate::common::R> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "ICACHE miss monitor register."]
48 #[inline(always)]
49 pub const fn mmonr(self) -> crate::common::Reg<regs::Mmonr, crate::common::R> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "Cluster CRR%s, container region configuration registers."]
53 #[inline(always)]
54 pub const fn crr(self, n: usize) -> crate::common::Reg<regs::Crr, crate::common::RW> {
55 assert!(n < 3usize);
56 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) }
57 }
58}
59pub mod regs {
60 #[doc = "ICACHE control register."]
61 #[repr(transparent)]
62 #[derive(Copy, Clone, Eq, PartialEq)]
63 pub struct Cr(pub u32);
64 impl Cr {
65 #[doc = "EN."]
66 #[inline(always)]
67 pub const fn en(&self) -> bool {
68 let val = (self.0 >> 0usize) & 0x01;
69 val != 0
70 }
71 #[doc = "EN."]
72 #[inline(always)]
73 pub fn set_en(&mut self, val: bool) {
74 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
75 }
76 #[doc = "Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect."]
77 #[inline(always)]
78 pub const fn cacheinv(&self) -> bool {
79 let val = (self.0 >> 1usize) & 0x01;
80 val != 0
81 }
82 #[doc = "Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect."]
83 #[inline(always)]
84 pub fn set_cacheinv(&mut self, val: bool) {
85 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
86 }
87 #[doc = "This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0)."]
88 #[inline(always)]
89 pub const fn waysel(&self) -> super::vals::Waysel {
90 let val = (self.0 >> 2usize) & 0x01;
91 super::vals::Waysel::from_bits(val as u8)
92 }
93 #[doc = "This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0)."]
94 #[inline(always)]
95 pub fn set_waysel(&mut self, val: super::vals::Waysel) {
96 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
97 }
98 #[doc = "Hit monitor enable."]
99 #[inline(always)]
100 pub const fn hitmen(&self) -> bool {
101 let val = (self.0 >> 16usize) & 0x01;
102 val != 0
103 }
104 #[doc = "Hit monitor enable."]
105 #[inline(always)]
106 pub fn set_hitmen(&mut self, val: bool) {
107 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
108 }
109 #[doc = "Miss monitor enable."]
110 #[inline(always)]
111 pub const fn missmen(&self) -> bool {
112 let val = (self.0 >> 17usize) & 0x01;
113 val != 0
114 }
115 #[doc = "Miss monitor enable."]
116 #[inline(always)]
117 pub fn set_missmen(&mut self, val: bool) {
118 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
119 }
120 #[doc = "Hit monitor reset."]
121 #[inline(always)]
122 pub const fn hitmrst(&self) -> bool {
123 let val = (self.0 >> 18usize) & 0x01;
124 val != 0
125 }
126 #[doc = "Hit monitor reset."]
127 #[inline(always)]
128 pub fn set_hitmrst(&mut self, val: bool) {
129 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
130 }
131 #[doc = "Miss monitor reset."]
132 #[inline(always)]
133 pub const fn missmrst(&self) -> bool {
134 let val = (self.0 >> 19usize) & 0x01;
135 val != 0
136 }
137 #[doc = "Miss monitor reset."]
138 #[inline(always)]
139 pub fn set_missmrst(&mut self, val: bool) {
140 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
141 }
142 }
143 impl Default for Cr {
144 #[inline(always)]
145 fn default() -> Cr {
146 Cr(0)
147 }
148 }
149 impl core::fmt::Debug for Cr {
150 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
151 f.debug_struct("Cr")
152 .field("en", &self.en())
153 .field("cacheinv", &self.cacheinv())
154 .field("waysel", &self.waysel())
155 .field("hitmen", &self.hitmen())
156 .field("missmen", &self.missmen())
157 .field("hitmrst", &self.hitmrst())
158 .field("missmrst", &self.missmrst())
159 .finish()
160 }
161 }
162 #[cfg(feature = "defmt")]
163 impl defmt::Format for Cr {
164 fn format(&self, f: defmt::Formatter) {
165 #[derive(defmt :: Format)]
166 struct Cr {
167 en: bool,
168 cacheinv: bool,
169 waysel: super::vals::Waysel,
170 hitmen: bool,
171 missmen: bool,
172 hitmrst: bool,
173 missmrst: bool,
174 }
175 let proxy = Cr {
176 en: self.en(),
177 cacheinv: self.cacheinv(),
178 waysel: self.waysel(),
179 hitmen: self.hitmen(),
180 missmen: self.missmen(),
181 hitmrst: self.hitmrst(),
182 missmrst: self.missmrst(),
183 };
184 defmt::write!(f, "{}", proxy)
185 }
186 }
187 #[doc = "ICACHE region configuration register."]
188 #[repr(transparent)]
189 #[derive(Copy, Clone, Eq, PartialEq)]
190 pub struct Crr(pub u32);
191 impl Crr {
192 #[doc = "base address for region."]
193 #[inline(always)]
194 pub const fn baseaddr(&self) -> u8 {
195 let val = (self.0 >> 0usize) & 0xff;
196 val as u8
197 }
198 #[doc = "base address for region."]
199 #[inline(always)]
200 pub fn set_baseaddr(&mut self, val: u8) {
201 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
202 }
203 #[doc = "size for region."]
204 #[inline(always)]
205 pub const fn rsize(&self) -> super::vals::Rsize {
206 let val = (self.0 >> 9usize) & 0x07;
207 super::vals::Rsize::from_bits(val as u8)
208 }
209 #[doc = "size for region."]
210 #[inline(always)]
211 pub fn set_rsize(&mut self, val: super::vals::Rsize) {
212 self.0 = (self.0 & !(0x07 << 9usize)) | (((val.to_bits() as u32) & 0x07) << 9usize);
213 }
214 #[doc = "enable for region."]
215 #[inline(always)]
216 pub const fn ren(&self) -> bool {
217 let val = (self.0 >> 15usize) & 0x01;
218 val != 0
219 }
220 #[doc = "enable for region."]
221 #[inline(always)]
222 pub fn set_ren(&mut self, val: bool) {
223 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
224 }
225 #[doc = "remapped address for region."]
226 #[inline(always)]
227 pub const fn remapaddr(&self) -> u16 {
228 let val = (self.0 >> 16usize) & 0x07ff;
229 val as u16
230 }
231 #[doc = "remapped address for region."]
232 #[inline(always)]
233 pub fn set_remapaddr(&mut self, val: u16) {
234 self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
235 }
236 #[doc = "AHB cache master selection for region."]
237 #[inline(always)]
238 pub const fn mstsel(&self) -> super::vals::Mstsel {
239 let val = (self.0 >> 28usize) & 0x01;
240 super::vals::Mstsel::from_bits(val as u8)
241 }
242 #[doc = "AHB cache master selection for region."]
243 #[inline(always)]
244 pub fn set_mstsel(&mut self, val: super::vals::Mstsel) {
245 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.to_bits() as u32) & 0x01) << 28usize);
246 }
247 #[doc = "output burst type for region."]
248 #[inline(always)]
249 pub const fn hburst(&self) -> super::vals::Hburst {
250 let val = (self.0 >> 31usize) & 0x01;
251 super::vals::Hburst::from_bits(val as u8)
252 }
253 #[doc = "output burst type for region."]
254 #[inline(always)]
255 pub fn set_hburst(&mut self, val: super::vals::Hburst) {
256 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize);
257 }
258 }
259 impl Default for Crr {
260 #[inline(always)]
261 fn default() -> Crr {
262 Crr(0)
263 }
264 }
265 impl core::fmt::Debug for Crr {
266 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
267 f.debug_struct("Crr")
268 .field("baseaddr", &self.baseaddr())
269 .field("rsize", &self.rsize())
270 .field("ren", &self.ren())
271 .field("remapaddr", &self.remapaddr())
272 .field("mstsel", &self.mstsel())
273 .field("hburst", &self.hburst())
274 .finish()
275 }
276 }
277 #[cfg(feature = "defmt")]
278 impl defmt::Format for Crr {
279 fn format(&self, f: defmt::Formatter) {
280 #[derive(defmt :: Format)]
281 struct Crr {
282 baseaddr: u8,
283 rsize: super::vals::Rsize,
284 ren: bool,
285 remapaddr: u16,
286 mstsel: super::vals::Mstsel,
287 hburst: super::vals::Hburst,
288 }
289 let proxy = Crr {
290 baseaddr: self.baseaddr(),
291 rsize: self.rsize(),
292 ren: self.ren(),
293 remapaddr: self.remapaddr(),
294 mstsel: self.mstsel(),
295 hburst: self.hburst(),
296 };
297 defmt::write!(f, "{}", proxy)
298 }
299 }
300 #[doc = "ICACHE flag clear register."]
301 #[repr(transparent)]
302 #[derive(Copy, Clone, Eq, PartialEq)]
303 pub struct Fcr(pub u32);
304 impl Fcr {
305 #[doc = "Clear busy end flag."]
306 #[inline(always)]
307 pub const fn cbsyendf(&self) -> bool {
308 let val = (self.0 >> 1usize) & 0x01;
309 val != 0
310 }
311 #[doc = "Clear busy end flag."]
312 #[inline(always)]
313 pub fn set_cbsyendf(&mut self, val: bool) {
314 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
315 }
316 #[doc = "Clear ERRF flag in SR."]
317 #[inline(always)]
318 pub const fn cerrf(&self) -> bool {
319 let val = (self.0 >> 2usize) & 0x01;
320 val != 0
321 }
322 #[doc = "Clear ERRF flag in SR."]
323 #[inline(always)]
324 pub fn set_cerrf(&mut self, val: bool) {
325 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
326 }
327 }
328 impl Default for Fcr {
329 #[inline(always)]
330 fn default() -> Fcr {
331 Fcr(0)
332 }
333 }
334 impl core::fmt::Debug for Fcr {
335 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
336 f.debug_struct("Fcr")
337 .field("cbsyendf", &self.cbsyendf())
338 .field("cerrf", &self.cerrf())
339 .finish()
340 }
341 }
342 #[cfg(feature = "defmt")]
343 impl defmt::Format for Fcr {
344 fn format(&self, f: defmt::Formatter) {
345 #[derive(defmt :: Format)]
346 struct Fcr {
347 cbsyendf: bool,
348 cerrf: bool,
349 }
350 let proxy = Fcr {
351 cbsyendf: self.cbsyendf(),
352 cerrf: self.cerrf(),
353 };
354 defmt::write!(f, "{}", proxy)
355 }
356 }
357 #[doc = "ICACHE interrupt enable register."]
358 #[repr(transparent)]
359 #[derive(Copy, Clone, Eq, PartialEq)]
360 pub struct Ier(pub u32);
361 impl Ier {
362 #[doc = "Interrupt enable on busy end."]
363 #[inline(always)]
364 pub const fn bsyendie(&self) -> bool {
365 let val = (self.0 >> 1usize) & 0x01;
366 val != 0
367 }
368 #[doc = "Interrupt enable on busy end."]
369 #[inline(always)]
370 pub fn set_bsyendie(&mut self, val: bool) {
371 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
372 }
373 #[doc = "Error interrupt on cache error."]
374 #[inline(always)]
375 pub const fn errie(&self) -> bool {
376 let val = (self.0 >> 2usize) & 0x01;
377 val != 0
378 }
379 #[doc = "Error interrupt on cache error."]
380 #[inline(always)]
381 pub fn set_errie(&mut self, val: bool) {
382 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
383 }
384 }
385 impl Default for Ier {
386 #[inline(always)]
387 fn default() -> Ier {
388 Ier(0)
389 }
390 }
391 impl core::fmt::Debug for Ier {
392 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
393 f.debug_struct("Ier")
394 .field("bsyendie", &self.bsyendie())
395 .field("errie", &self.errie())
396 .finish()
397 }
398 }
399 #[cfg(feature = "defmt")]
400 impl defmt::Format for Ier {
401 fn format(&self, f: defmt::Formatter) {
402 #[derive(defmt :: Format)]
403 struct Ier {
404 bsyendie: bool,
405 errie: bool,
406 }
407 let proxy = Ier {
408 bsyendie: self.bsyendie(),
409 errie: self.errie(),
410 };
411 defmt::write!(f, "{}", proxy)
412 }
413 }
414 #[doc = "ICACHE miss monitor register."]
415 #[repr(transparent)]
416 #[derive(Copy, Clone, Eq, PartialEq)]
417 pub struct Mmonr(pub u32);
418 impl Mmonr {
419 #[doc = "Miss monitor register."]
420 #[inline(always)]
421 pub const fn missmon(&self) -> u16 {
422 let val = (self.0 >> 0usize) & 0xffff;
423 val as u16
424 }
425 #[doc = "Miss monitor register."]
426 #[inline(always)]
427 pub fn set_missmon(&mut self, val: u16) {
428 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
429 }
430 }
431 impl Default for Mmonr {
432 #[inline(always)]
433 fn default() -> Mmonr {
434 Mmonr(0)
435 }
436 }
437 impl core::fmt::Debug for Mmonr {
438 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
439 f.debug_struct("Mmonr").field("missmon", &self.missmon()).finish()
440 }
441 }
442 #[cfg(feature = "defmt")]
443 impl defmt::Format for Mmonr {
444 fn format(&self, f: defmt::Formatter) {
445 #[derive(defmt :: Format)]
446 struct Mmonr {
447 missmon: u16,
448 }
449 let proxy = Mmonr {
450 missmon: self.missmon(),
451 };
452 defmt::write!(f, "{}", proxy)
453 }
454 }
455 #[doc = "ICACHE status register."]
456 #[repr(transparent)]
457 #[derive(Copy, Clone, Eq, PartialEq)]
458 pub struct Sr(pub u32);
459 impl Sr {
460 #[doc = "cache busy executing a full invalidate CACHEINV operation."]
461 #[inline(always)]
462 pub const fn busyf(&self) -> bool {
463 let val = (self.0 >> 0usize) & 0x01;
464 val != 0
465 }
466 #[doc = "cache busy executing a full invalidate CACHEINV operation."]
467 #[inline(always)]
468 pub fn set_busyf(&mut self, val: bool) {
469 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
470 }
471 #[doc = "full invalidate CACHEINV operation finished."]
472 #[inline(always)]
473 pub const fn bsyendf(&self) -> bool {
474 let val = (self.0 >> 1usize) & 0x01;
475 val != 0
476 }
477 #[doc = "full invalidate CACHEINV operation finished."]
478 #[inline(always)]
479 pub fn set_bsyendf(&mut self, val: bool) {
480 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
481 }
482 #[doc = "an error occurred during the operation."]
483 #[inline(always)]
484 pub const fn errf(&self) -> bool {
485 let val = (self.0 >> 2usize) & 0x01;
486 val != 0
487 }
488 #[doc = "an error occurred during the operation."]
489 #[inline(always)]
490 pub fn set_errf(&mut self, val: bool) {
491 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
492 }
493 }
494 impl Default for Sr {
495 #[inline(always)]
496 fn default() -> Sr {
497 Sr(0)
498 }
499 }
500 impl core::fmt::Debug for Sr {
501 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
502 f.debug_struct("Sr")
503 .field("busyf", &self.busyf())
504 .field("bsyendf", &self.bsyendf())
505 .field("errf", &self.errf())
506 .finish()
507 }
508 }
509 #[cfg(feature = "defmt")]
510 impl defmt::Format for Sr {
511 fn format(&self, f: defmt::Formatter) {
512 #[derive(defmt :: Format)]
513 struct Sr {
514 busyf: bool,
515 bsyendf: bool,
516 errf: bool,
517 }
518 let proxy = Sr {
519 busyf: self.busyf(),
520 bsyendf: self.bsyendf(),
521 errf: self.errf(),
522 };
523 defmt::write!(f, "{}", proxy)
524 }
525 }
526}
527pub mod vals {
528 #[repr(u8)]
529 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
530 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
531 pub enum Hburst {
532 WRAP = 0x0,
533 INCREMENT = 0x01,
534 }
535 impl Hburst {
536 #[inline(always)]
537 pub const fn from_bits(val: u8) -> Hburst {
538 unsafe { core::mem::transmute(val & 0x01) }
539 }
540 #[inline(always)]
541 pub const fn to_bits(self) -> u8 {
542 unsafe { core::mem::transmute(self) }
543 }
544 }
545 impl From<u8> for Hburst {
546 #[inline(always)]
547 fn from(val: u8) -> Hburst {
548 Hburst::from_bits(val)
549 }
550 }
551 impl From<Hburst> for u8 {
552 #[inline(always)]
553 fn from(val: Hburst) -> u8 {
554 Hburst::to_bits(val)
555 }
556 }
557 #[repr(u8)]
558 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
559 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
560 pub enum Mstsel {
561 MASTER1SELECTED = 0x0,
562 MASTER2SELECTED = 0x01,
563 }
564 impl Mstsel {
565 #[inline(always)]
566 pub const fn from_bits(val: u8) -> Mstsel {
567 unsafe { core::mem::transmute(val & 0x01) }
568 }
569 #[inline(always)]
570 pub const fn to_bits(self) -> u8 {
571 unsafe { core::mem::transmute(self) }
572 }
573 }
574 impl From<u8> for Mstsel {
575 #[inline(always)]
576 fn from(val: u8) -> Mstsel {
577 Mstsel::from_bits(val)
578 }
579 }
580 impl From<Mstsel> for u8 {
581 #[inline(always)]
582 fn from(val: Mstsel) -> u8 {
583 Mstsel::to_bits(val)
584 }
585 }
586 #[repr(u8)]
587 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
588 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
589 pub enum Rsize {
590 _RESERVED_0 = 0x0,
591 MEGA_BYTES2 = 0x01,
592 MEGA_BYTES4 = 0x02,
593 MEGA_BYTES8 = 0x03,
594 MEGA_BYTES16 = 0x04,
595 MEGA_BYTES32 = 0x05,
596 MEGA_BYTES64 = 0x06,
597 MEGA_BYTES128 = 0x07,
598 }
599 impl Rsize {
600 #[inline(always)]
601 pub const fn from_bits(val: u8) -> Rsize {
602 unsafe { core::mem::transmute(val & 0x07) }
603 }
604 #[inline(always)]
605 pub const fn to_bits(self) -> u8 {
606 unsafe { core::mem::transmute(self) }
607 }
608 }
609 impl From<u8> for Rsize {
610 #[inline(always)]
611 fn from(val: u8) -> Rsize {
612 Rsize::from_bits(val)
613 }
614 }
615 impl From<Rsize> for u8 {
616 #[inline(always)]
617 fn from(val: Rsize) -> u8 {
618 Rsize::to_bits(val)
619 }
620 }
621 #[repr(u8)]
622 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
623 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
624 pub enum Waysel {
625 #[doc = "direct mapped cache (1-way cache)"]
626 DIRECT_MAPPED = 0x0,
627 #[doc = "n-way set associative cache (reset value)"]
628 NWAY_SET_ASSOCIATIVE = 0x01,
629 }
630 impl Waysel {
631 #[inline(always)]
632 pub const fn from_bits(val: u8) -> Waysel {
633 unsafe { core::mem::transmute(val & 0x01) }
634 }
635 #[inline(always)]
636 pub const fn to_bits(self) -> u8 {
637 unsafe { core::mem::transmute(self) }
638 }
639 }
640 impl From<u8> for Waysel {
641 #[inline(always)]
642 fn from(val: u8) -> Waysel {
643 Waysel::from_bits(val)
644 }
645 }
646 impl From<Waysel> for u8 {
647 #[inline(always)]
648 fn from(val: Waysel) -> u8 {
649 Waysel::to_bits(val)
650 }
651 }
652}
653