1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Low power timer with Output Compare"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Lptim {
9 ptr: *mut u8,
10}
11unsafe impl Send for Lptim {}
12unsafe impl Sync for Lptim {}
13impl Lptim {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "LPTIM interrupt and status register."]
23 #[inline(always)]
24 pub const fn isr(self) -> crate::common::Reg<regs::IsrAdv, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "LPTIM interrupt clear register."]
28 #[inline(always)]
29 pub const fn icr(self) -> crate::common::Reg<regs::IcrAdv, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "LPTIM interrupt enable register."]
33 #[inline(always)]
34 pub const fn dier(self) -> crate::common::Reg<regs::DierAdv, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "LPTIM configuration register."]
38 #[inline(always)]
39 pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "LPTIM control register."]
43 #[inline(always)]
44 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "LPTIM compare register 1."]
48 #[inline(always)]
49 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
50 assert!(n < 2usize);
51 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 32usize) as _) }
52 }
53 #[doc = "LPTIM autoreload register."]
54 #[inline(always)]
55 pub const fn arr(self) -> crate::common::Reg<regs::Arr, crate::common::RW> {
56 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
57 }
58 #[doc = "LPTIM counter register."]
59 #[inline(always)]
60 pub const fn cnt(self) -> crate::common::Reg<regs::Cnt, crate::common::RW> {
61 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
62 }
63 #[doc = "LPTIM configuration register 2."]
64 #[inline(always)]
65 pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
66 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
67 }
68 #[doc = "LPTIM repetition register."]
69 #[inline(always)]
70 pub const fn rcr(self) -> crate::common::Reg<regs::Rcr, crate::common::RW> {
71 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
72 }
73 #[doc = "LPTIM capture/compare mode register 1."]
74 #[inline(always)]
75 pub const fn ccmr(self, n: usize) -> crate::common::Reg<regs::Ccmr, crate::common::RW> {
76 assert!(n < 1usize);
77 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize + n * 1usize) as _) }
78 }
79}
80#[doc = "Low power timer with Output Compare"]
81#[derive(Copy, Clone, Eq, PartialEq)]
82pub struct LptimBasic {
83 ptr: *mut u8,
84}
85unsafe impl Send for LptimBasic {}
86unsafe impl Sync for LptimBasic {}
87impl LptimBasic {
88 #[inline(always)]
89 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
90 Self { ptr: ptr as _ }
91 }
92 #[inline(always)]
93 pub const fn as_ptr(&self) -> *mut () {
94 self.ptr as _
95 }
96 #[doc = "LPTIM interrupt and status register."]
97 #[inline(always)]
98 pub const fn isr(self) -> crate::common::Reg<regs::IsrBasic, crate::common::RW> {
99 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
100 }
101 #[doc = "LPTIM interrupt clear register."]
102 #[inline(always)]
103 pub const fn icr(self) -> crate::common::Reg<regs::IcrBasic, crate::common::RW> {
104 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
105 }
106 #[doc = "LPTIM interrupt enable register."]
107 #[inline(always)]
108 pub const fn dier(self) -> crate::common::Reg<regs::DierBasic, crate::common::RW> {
109 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
110 }
111 #[doc = "LPTIM configuration register."]
112 #[inline(always)]
113 pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
114 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
115 }
116 #[doc = "LPTIM control register."]
117 #[inline(always)]
118 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
119 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
120 }
121 #[doc = "LPTIM compare register 1."]
122 #[inline(always)]
123 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
124 assert!(n < 1usize);
125 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 32usize) as _) }
126 }
127 #[doc = "LPTIM autoreload register."]
128 #[inline(always)]
129 pub const fn arr(self) -> crate::common::Reg<regs::Arr, crate::common::RW> {
130 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
131 }
132 #[doc = "LPTIM counter register."]
133 #[inline(always)]
134 pub const fn cnt(self) -> crate::common::Reg<regs::Cnt, crate::common::RW> {
135 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
136 }
137 #[doc = "LPTIM configuration register 2."]
138 #[inline(always)]
139 pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
140 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
141 }
142 #[doc = "LPTIM repetition register."]
143 #[inline(always)]
144 pub const fn rcr(self) -> crate::common::Reg<regs::Rcr, crate::common::RW> {
145 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
146 }
147}
148pub mod regs {
149 #[doc = "LPTIM autoreload register."]
150 #[repr(transparent)]
151 #[derive(Copy, Clone, Eq, PartialEq)]
152 pub struct Arr(pub u32);
153 impl Arr {
154 #[doc = "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx\\[15:0\\]
155value."]
156 #[inline(always)]
157 pub const fn arr(&self) -> u16 {
158 let val = (self.0 >> 0usize) & 0xffff;
159 val as u16
160 }
161 #[doc = "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx\\[15:0\\]
162value."]
163 #[inline(always)]
164 pub fn set_arr(&mut self, val: u16) {
165 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
166 }
167 }
168 impl Default for Arr {
169 #[inline(always)]
170 fn default() -> Arr {
171 Arr(0)
172 }
173 }
174 impl core::fmt::Debug for Arr {
175 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
176 f.debug_struct("Arr").field("arr", &self.arr()).finish()
177 }
178 }
179 #[cfg(feature = "defmt")]
180 impl defmt::Format for Arr {
181 fn format(&self, f: defmt::Formatter) {
182 #[derive(defmt :: Format)]
183 struct Arr {
184 arr: u16,
185 }
186 let proxy = Arr { arr: self.arr() };
187 defmt::write!(f, "{}", proxy)
188 }
189 }
190 #[doc = "LPTIM capture/compare mode register 1."]
191 #[repr(transparent)]
192 #[derive(Copy, Clone, Eq, PartialEq)]
193 pub struct Ccmr(pub u32);
194 impl Ccmr {
195 #[doc = "Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode."]
196 #[inline(always)]
197 pub const fn ccsel(&self, n: usize) -> super::vals::Ccsel {
198 assert!(n < 2usize);
199 let offs = 0usize + n * 16usize;
200 let val = (self.0 >> offs) & 0x01;
201 super::vals::Ccsel::from_bits(val as u8)
202 }
203 #[doc = "Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode."]
204 #[inline(always)]
205 pub fn set_ccsel(&mut self, n: usize, val: super::vals::Ccsel) {
206 assert!(n < 2usize);
207 let offs = 0usize + n * 16usize;
208 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
209 }
210 #[doc = "Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not."]
211 #[inline(always)]
212 pub const fn cce(&self, n: usize) -> bool {
213 assert!(n < 2usize);
214 let offs = 1usize + n * 16usize;
215 let val = (self.0 >> offs) & 0x01;
216 val != 0
217 }
218 #[doc = "Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not."]
219 #[inline(always)]
220 pub fn set_cce(&mut self, n: usize, val: bool) {
221 assert!(n < 2usize);
222 let offs = 1usize + n * 16usize;
223 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
224 }
225 #[doc = "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations."]
226 #[inline(always)]
227 pub const fn ccp_input(&self, n: usize) -> super::vals::CcpInput {
228 assert!(n < 2usize);
229 let offs = 2usize + n * 16usize;
230 let val = (self.0 >> offs) & 0x03;
231 super::vals::CcpInput::from_bits(val as u8)
232 }
233 #[doc = "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations."]
234 #[inline(always)]
235 pub fn set_ccp_input(&mut self, n: usize, val: super::vals::CcpInput) {
236 assert!(n < 2usize);
237 let offs = 2usize + n * 16usize;
238 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
239 }
240 #[doc = "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations."]
241 #[inline(always)]
242 pub const fn ccp_output(&self, n: usize) -> super::vals::CcpOutput {
243 assert!(n < 2usize);
244 let offs = 2usize + n * 16usize;
245 let val = (self.0 >> offs) & 0x03;
246 super::vals::CcpOutput::from_bits(val as u8)
247 }
248 #[doc = "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations."]
249 #[inline(always)]
250 pub fn set_ccp_output(&mut self, n: usize, val: super::vals::CcpOutput) {
251 assert!(n < 2usize);
252 let offs = 2usize + n * 16usize;
253 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
254 }
255 #[doc = "Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1)."]
256 #[inline(always)]
257 pub const fn icpsc(&self, n: usize) -> super::vals::Filter {
258 assert!(n < 2usize);
259 let offs = 8usize + n * 16usize;
260 let val = (self.0 >> offs) & 0x03;
261 super::vals::Filter::from_bits(val as u8)
262 }
263 #[doc = "Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1)."]
264 #[inline(always)]
265 pub fn set_icpsc(&mut self, n: usize, val: super::vals::Filter) {
266 assert!(n < 2usize);
267 let offs = 8usize + n * 16usize;
268 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
269 }
270 #[doc = "Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature."]
271 #[inline(always)]
272 pub const fn icf(&self, n: usize) -> super::vals::Filter {
273 assert!(n < 2usize);
274 let offs = 12usize + n * 16usize;
275 let val = (self.0 >> offs) & 0x03;
276 super::vals::Filter::from_bits(val as u8)
277 }
278 #[doc = "Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature."]
279 #[inline(always)]
280 pub fn set_icf(&mut self, n: usize, val: super::vals::Filter) {
281 assert!(n < 2usize);
282 let offs = 12usize + n * 16usize;
283 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
284 }
285 }
286 impl Default for Ccmr {
287 #[inline(always)]
288 fn default() -> Ccmr {
289 Ccmr(0)
290 }
291 }
292 impl core::fmt::Debug for Ccmr {
293 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
294 f.debug_struct("Ccmr")
295 .field("ccsel", &[self.ccsel(0usize), self.ccsel(1usize)])
296 .field("cce", &[self.cce(0usize), self.cce(1usize)])
297 .field("ccp_input", &[self.ccp_input(0usize), self.ccp_input(1usize)])
298 .field("ccp_output", &[self.ccp_output(0usize), self.ccp_output(1usize)])
299 .field("icpsc", &[self.icpsc(0usize), self.icpsc(1usize)])
300 .field("icf", &[self.icf(0usize), self.icf(1usize)])
301 .finish()
302 }
303 }
304 #[cfg(feature = "defmt")]
305 impl defmt::Format for Ccmr {
306 fn format(&self, f: defmt::Formatter) {
307 #[derive(defmt :: Format)]
308 struct Ccmr {
309 ccsel: [super::vals::Ccsel; 2usize],
310 cce: [bool; 2usize],
311 ccp_input: [super::vals::CcpInput; 2usize],
312 ccp_output: [super::vals::CcpOutput; 2usize],
313 icpsc: [super::vals::Filter; 2usize],
314 icf: [super::vals::Filter; 2usize],
315 }
316 let proxy = Ccmr {
317 ccsel: [self.ccsel(0usize), self.ccsel(1usize)],
318 cce: [self.cce(0usize), self.cce(1usize)],
319 ccp_input: [self.ccp_input(0usize), self.ccp_input(1usize)],
320 ccp_output: [self.ccp_output(0usize), self.ccp_output(1usize)],
321 icpsc: [self.icpsc(0usize), self.icpsc(1usize)],
322 icf: [self.icf(0usize), self.icf(1usize)],
323 };
324 defmt::write!(f, "{}", proxy)
325 }
326 }
327 #[doc = "LPTIM compare register 1."]
328 #[repr(transparent)]
329 #[derive(Copy, Clone, Eq, PartialEq)]
330 pub struct Ccr(pub u32);
331 impl Ccr {
332 #[doc = "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output."]
333 #[inline(always)]
334 pub const fn ccr(&self) -> u16 {
335 let val = (self.0 >> 0usize) & 0xffff;
336 val as u16
337 }
338 #[doc = "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output."]
339 #[inline(always)]
340 pub fn set_ccr(&mut self, val: u16) {
341 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
342 }
343 }
344 impl Default for Ccr {
345 #[inline(always)]
346 fn default() -> Ccr {
347 Ccr(0)
348 }
349 }
350 impl core::fmt::Debug for Ccr {
351 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
352 f.debug_struct("Ccr").field("ccr", &self.ccr()).finish()
353 }
354 }
355 #[cfg(feature = "defmt")]
356 impl defmt::Format for Ccr {
357 fn format(&self, f: defmt::Formatter) {
358 #[derive(defmt :: Format)]
359 struct Ccr {
360 ccr: u16,
361 }
362 let proxy = Ccr { ccr: self.ccr() };
363 defmt::write!(f, "{}", proxy)
364 }
365 }
366 #[doc = "LPTIM configuration register."]
367 #[repr(transparent)]
368 #[derive(Copy, Clone, Eq, PartialEq)]
369 pub struct Cfgr(pub u32);
370 impl Cfgr {
371 #[doc = "Clock selector The CKSEL bit selects which clock source the LPTIM uses:."]
372 #[inline(always)]
373 pub const fn cksel(&self) -> super::vals::ClockSource {
374 let val = (self.0 >> 0usize) & 0x01;
375 super::vals::ClockSource::from_bits(val as u8)
376 }
377 #[doc = "Clock selector The CKSEL bit selects which clock source the LPTIM uses:."]
378 #[inline(always)]
379 pub fn set_cksel(&mut self, val: super::vals::ClockSource) {
380 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
381 }
382 #[doc = "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes."]
383 #[inline(always)]
384 pub const fn ckpol(&self) -> super::vals::Ckpol {
385 let val = (self.0 >> 1usize) & 0x03;
386 super::vals::Ckpol::from_bits(val as u8)
387 }
388 #[doc = "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes."]
389 #[inline(always)]
390 pub fn set_ckpol(&mut self, val: super::vals::Ckpol) {
391 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
392 }
393 #[doc = "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature."]
394 #[inline(always)]
395 pub const fn ckflt(&self) -> super::vals::Filter {
396 let val = (self.0 >> 3usize) & 0x03;
397 super::vals::Filter::from_bits(val as u8)
398 }
399 #[doc = "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature."]
400 #[inline(always)]
401 pub fn set_ckflt(&mut self, val: super::vals::Filter) {
402 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
403 }
404 #[doc = "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature."]
405 #[inline(always)]
406 pub const fn trgflt(&self) -> super::vals::Filter {
407 let val = (self.0 >> 6usize) & 0x03;
408 super::vals::Filter::from_bits(val as u8)
409 }
410 #[doc = "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature."]
411 #[inline(always)]
412 pub fn set_trgflt(&mut self, val: super::vals::Filter) {
413 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
414 }
415 #[doc = "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:."]
416 #[inline(always)]
417 pub const fn presc(&self) -> super::vals::Presc {
418 let val = (self.0 >> 9usize) & 0x07;
419 super::vals::Presc::from_bits(val as u8)
420 }
421 #[doc = "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:."]
422 #[inline(always)]
423 pub fn set_presc(&mut self, val: super::vals::Presc) {
424 self.0 = (self.0 & !(0x07 << 9usize)) | (((val.to_bits() as u32) & 0x07) << 9usize);
425 }
426 #[doc = "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details."]
427 #[inline(always)]
428 pub const fn trigsel(&self) -> u8 {
429 let val = (self.0 >> 13usize) & 0x07;
430 val as u8
431 }
432 #[doc = "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details."]
433 #[inline(always)]
434 pub fn set_trigsel(&mut self, val: u8) {
435 self.0 = (self.0 & !(0x07 << 13usize)) | (((val as u32) & 0x07) << 13usize);
436 }
437 #[doc = "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:."]
438 #[inline(always)]
439 pub const fn trigen(&self) -> super::vals::Trigen {
440 let val = (self.0 >> 17usize) & 0x03;
441 super::vals::Trigen::from_bits(val as u8)
442 }
443 #[doc = "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:."]
444 #[inline(always)]
445 pub fn set_trigen(&mut self, val: super::vals::Trigen) {
446 self.0 = (self.0 & !(0x03 << 17usize)) | (((val.to_bits() as u32) & 0x03) << 17usize);
447 }
448 #[doc = "Timeout enable The TIMOUT bit controls the Timeout feature."]
449 #[inline(always)]
450 pub const fn timout(&self) -> bool {
451 let val = (self.0 >> 19usize) & 0x01;
452 val != 0
453 }
454 #[doc = "Timeout enable The TIMOUT bit controls the Timeout feature."]
455 #[inline(always)]
456 pub fn set_timout(&mut self, val: bool) {
457 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
458 }
459 #[doc = "Waveform shape The WAVE bit controls the output shape."]
460 #[inline(always)]
461 pub const fn wave(&self) -> bool {
462 let val = (self.0 >> 20usize) & 0x01;
463 val != 0
464 }
465 #[doc = "Waveform shape The WAVE bit controls the output shape."]
466 #[inline(always)]
467 pub fn set_wave(&mut self, val: bool) {
468 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
469 }
470 #[doc = "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to."]
471 #[inline(always)]
472 pub const fn wavpol(&self) -> super::vals::Wavpol {
473 let val = (self.0 >> 21usize) & 0x01;
474 super::vals::Wavpol::from_bits(val as u8)
475 }
476 #[doc = "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to."]
477 #[inline(always)]
478 pub fn set_wavpol(&mut self, val: super::vals::Wavpol) {
479 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.to_bits() as u32) & 0x01) << 21usize);
480 }
481 #[doc = "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality."]
482 #[inline(always)]
483 pub const fn preload(&self) -> bool {
484 let val = (self.0 >> 22usize) & 0x01;
485 val != 0
486 }
487 #[doc = "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality."]
488 #[inline(always)]
489 pub fn set_preload(&mut self, val: bool) {
490 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
491 }
492 #[doc = "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:."]
493 #[inline(always)]
494 pub const fn countmode(&self) -> super::vals::ClockSource {
495 let val = (self.0 >> 23usize) & 0x01;
496 super::vals::ClockSource::from_bits(val as u8)
497 }
498 #[doc = "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:."]
499 #[inline(always)]
500 pub fn set_countmode(&mut self, val: super::vals::ClockSource) {
501 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize);
502 }
503 #[doc = "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
504 #[inline(always)]
505 pub const fn enc(&self) -> bool {
506 let val = (self.0 >> 24usize) & 0x01;
507 val != 0
508 }
509 #[doc = "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
510 #[inline(always)]
511 pub fn set_enc(&mut self, val: bool) {
512 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
513 }
514 }
515 impl Default for Cfgr {
516 #[inline(always)]
517 fn default() -> Cfgr {
518 Cfgr(0)
519 }
520 }
521 impl core::fmt::Debug for Cfgr {
522 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
523 f.debug_struct("Cfgr")
524 .field("cksel", &self.cksel())
525 .field("ckpol", &self.ckpol())
526 .field("ckflt", &self.ckflt())
527 .field("trgflt", &self.trgflt())
528 .field("presc", &self.presc())
529 .field("trigsel", &self.trigsel())
530 .field("trigen", &self.trigen())
531 .field("timout", &self.timout())
532 .field("wave", &self.wave())
533 .field("wavpol", &self.wavpol())
534 .field("preload", &self.preload())
535 .field("countmode", &self.countmode())
536 .field("enc", &self.enc())
537 .finish()
538 }
539 }
540 #[cfg(feature = "defmt")]
541 impl defmt::Format for Cfgr {
542 fn format(&self, f: defmt::Formatter) {
543 #[derive(defmt :: Format)]
544 struct Cfgr {
545 cksel: super::vals::ClockSource,
546 ckpol: super::vals::Ckpol,
547 ckflt: super::vals::Filter,
548 trgflt: super::vals::Filter,
549 presc: super::vals::Presc,
550 trigsel: u8,
551 trigen: super::vals::Trigen,
552 timout: bool,
553 wave: bool,
554 wavpol: super::vals::Wavpol,
555 preload: bool,
556 countmode: super::vals::ClockSource,
557 enc: bool,
558 }
559 let proxy = Cfgr {
560 cksel: self.cksel(),
561 ckpol: self.ckpol(),
562 ckflt: self.ckflt(),
563 trgflt: self.trgflt(),
564 presc: self.presc(),
565 trigsel: self.trigsel(),
566 trigen: self.trigen(),
567 timout: self.timout(),
568 wave: self.wave(),
569 wavpol: self.wavpol(),
570 preload: self.preload(),
571 countmode: self.countmode(),
572 enc: self.enc(),
573 };
574 defmt::write!(f, "{}", proxy)
575 }
576 }
577 #[doc = "LPTIM configuration register 2."]
578 #[repr(transparent)]
579 #[derive(Copy, Clone, Eq, PartialEq)]
580 pub struct Cfgr2(pub u32);
581 impl Cfgr2 {
582 #[doc = "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to."]
583 #[inline(always)]
584 pub const fn insel(&self, n: usize) -> u8 {
585 assert!(n < 2usize);
586 let offs = 0usize + n * 4usize;
587 let val = (self.0 >> offs) & 0x03;
588 val as u8
589 }
590 #[doc = "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to."]
591 #[inline(always)]
592 pub fn set_insel(&mut self, n: usize, val: u8) {
593 assert!(n < 2usize);
594 let offs = 0usize + n * 4usize;
595 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
596 }
597 #[doc = "LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to."]
598 #[inline(always)]
599 pub const fn icsel(&self, n: usize) -> u8 {
600 assert!(n < 2usize);
601 let offs = 16usize + n * 4usize;
602 let val = (self.0 >> offs) & 0x03;
603 val as u8
604 }
605 #[doc = "LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to."]
606 #[inline(always)]
607 pub fn set_icsel(&mut self, n: usize, val: u8) {
608 assert!(n < 2usize);
609 let offs = 16usize + n * 4usize;
610 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
611 }
612 }
613 impl Default for Cfgr2 {
614 #[inline(always)]
615 fn default() -> Cfgr2 {
616 Cfgr2(0)
617 }
618 }
619 impl core::fmt::Debug for Cfgr2 {
620 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
621 f.debug_struct("Cfgr2")
622 .field("insel", &[self.insel(0usize), self.insel(1usize)])
623 .field("icsel", &[self.icsel(0usize), self.icsel(1usize)])
624 .finish()
625 }
626 }
627 #[cfg(feature = "defmt")]
628 impl defmt::Format for Cfgr2 {
629 fn format(&self, f: defmt::Formatter) {
630 #[derive(defmt :: Format)]
631 struct Cfgr2 {
632 insel: [u8; 2usize],
633 icsel: [u8; 2usize],
634 }
635 let proxy = Cfgr2 {
636 insel: [self.insel(0usize), self.insel(1usize)],
637 icsel: [self.icsel(0usize), self.icsel(1usize)],
638 };
639 defmt::write!(f, "{}", proxy)
640 }
641 }
642 #[doc = "LPTIM counter register."]
643 #[repr(transparent)]
644 #[derive(Copy, Clone, Eq, PartialEq)]
645 pub struct Cnt(pub u32);
646 impl Cnt {
647 #[doc = "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
648 #[inline(always)]
649 pub const fn cnt(&self) -> u16 {
650 let val = (self.0 >> 0usize) & 0xffff;
651 val as u16
652 }
653 #[doc = "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
654 #[inline(always)]
655 pub fn set_cnt(&mut self, val: u16) {
656 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
657 }
658 }
659 impl Default for Cnt {
660 #[inline(always)]
661 fn default() -> Cnt {
662 Cnt(0)
663 }
664 }
665 impl core::fmt::Debug for Cnt {
666 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
667 f.debug_struct("Cnt").field("cnt", &self.cnt()).finish()
668 }
669 }
670 #[cfg(feature = "defmt")]
671 impl defmt::Format for Cnt {
672 fn format(&self, f: defmt::Formatter) {
673 #[derive(defmt :: Format)]
674 struct Cnt {
675 cnt: u16,
676 }
677 let proxy = Cnt { cnt: self.cnt() };
678 defmt::write!(f, "{}", proxy)
679 }
680 }
681 #[doc = "LPTIM control register."]
682 #[repr(transparent)]
683 #[derive(Copy, Clone, Eq, PartialEq)]
684 pub struct Cr(pub u32);
685 impl Cr {
686 #[doc = "LPTIM enable The ENABLE bit is set and cleared by software."]
687 #[inline(always)]
688 pub const fn enable(&self) -> bool {
689 let val = (self.0 >> 0usize) & 0x01;
690 val != 0
691 }
692 #[doc = "LPTIM enable The ENABLE bit is set and cleared by software."]
693 #[inline(always)]
694 pub fn set_enable(&mut self, val: bool) {
695 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
696 }
697 #[doc = "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
698= ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
699different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware."]
700 #[inline(always)]
701 pub const fn sngstrt(&self) -> bool {
702 let val = (self.0 >> 1usize) & 0x01;
703 val != 0
704 }
705 #[doc = "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
706= ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
707different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware."]
708 #[inline(always)]
709 pub fn set_sngstrt(&mut self, val: bool) {
710 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
711 }
712 #[doc = "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
713= ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
714different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware."]
715 #[inline(always)]
716 pub const fn cntstrt(&self) -> bool {
717 let val = (self.0 >> 2usize) & 0x01;
718 val != 0
719 }
720 #[doc = "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
721= ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
722different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware."]
723 #[inline(always)]
724 pub fn set_cntstrt(&mut self, val: bool) {
725 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
726 }
727 #[doc = "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'."]
728 #[inline(always)]
729 pub const fn countrst(&self) -> bool {
730 let val = (self.0 >> 3usize) & 0x01;
731 val != 0
732 }
733 #[doc = "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'."]
734 #[inline(always)]
735 pub fn set_countrst(&mut self, val: bool) {
736 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
737 }
738 #[doc = "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled."]
739 #[inline(always)]
740 pub const fn rstare(&self) -> bool {
741 let val = (self.0 >> 4usize) & 0x01;
742 val != 0
743 }
744 #[doc = "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled."]
745 #[inline(always)]
746 pub fn set_rstare(&mut self, val: bool) {
747 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
748 }
749 }
750 impl Default for Cr {
751 #[inline(always)]
752 fn default() -> Cr {
753 Cr(0)
754 }
755 }
756 impl core::fmt::Debug for Cr {
757 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
758 f.debug_struct("Cr")
759 .field("enable", &self.enable())
760 .field("sngstrt", &self.sngstrt())
761 .field("cntstrt", &self.cntstrt())
762 .field("countrst", &self.countrst())
763 .field("rstare", &self.rstare())
764 .finish()
765 }
766 }
767 #[cfg(feature = "defmt")]
768 impl defmt::Format for Cr {
769 fn format(&self, f: defmt::Formatter) {
770 #[derive(defmt :: Format)]
771 struct Cr {
772 enable: bool,
773 sngstrt: bool,
774 cntstrt: bool,
775 countrst: bool,
776 rstare: bool,
777 }
778 let proxy = Cr {
779 enable: self.enable(),
780 sngstrt: self.sngstrt(),
781 cntstrt: self.cntstrt(),
782 countrst: self.countrst(),
783 rstare: self.rstare(),
784 };
785 defmt::write!(f, "{}", proxy)
786 }
787 }
788 #[doc = "LPTIM interrupt enable register."]
789 #[repr(transparent)]
790 #[derive(Copy, Clone, Eq, PartialEq)]
791 pub struct DierAdv(pub u32);
792 impl DierAdv {
793 #[doc = "Capture/compare 1 interrupt enable."]
794 #[inline(always)]
795 pub const fn ccie(&self, n: usize) -> bool {
796 assert!(n < 2usize);
797 let offs = 0usize + n * 9usize;
798 let val = (self.0 >> offs) & 0x01;
799 val != 0
800 }
801 #[doc = "Capture/compare 1 interrupt enable."]
802 #[inline(always)]
803 pub fn set_ccie(&mut self, n: usize, val: bool) {
804 assert!(n < 2usize);
805 let offs = 0usize + n * 9usize;
806 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
807 }
808 #[doc = "Autoreload match Interrupt Enable."]
809 #[inline(always)]
810 pub const fn arrmie(&self) -> bool {
811 let val = (self.0 >> 1usize) & 0x01;
812 val != 0
813 }
814 #[doc = "Autoreload match Interrupt Enable."]
815 #[inline(always)]
816 pub fn set_arrmie(&mut self, val: bool) {
817 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
818 }
819 #[doc = "External trigger valid edge Interrupt Enable."]
820 #[inline(always)]
821 pub const fn exttrigie(&self) -> bool {
822 let val = (self.0 >> 2usize) & 0x01;
823 val != 0
824 }
825 #[doc = "External trigger valid edge Interrupt Enable."]
826 #[inline(always)]
827 pub fn set_exttrigie(&mut self, val: bool) {
828 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
829 }
830 #[doc = "Compare register 1 update OK interrupt enable."]
831 #[inline(always)]
832 pub const fn cmpokie(&self, n: usize) -> bool {
833 assert!(n < 2usize);
834 let offs = 3usize + n * 16usize;
835 let val = (self.0 >> offs) & 0x01;
836 val != 0
837 }
838 #[doc = "Compare register 1 update OK interrupt enable."]
839 #[inline(always)]
840 pub fn set_cmpokie(&mut self, n: usize, val: bool) {
841 assert!(n < 2usize);
842 let offs = 3usize + n * 16usize;
843 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
844 }
845 #[doc = "Autoreload register update OK Interrupt Enable."]
846 #[inline(always)]
847 pub const fn arrokie(&self) -> bool {
848 let val = (self.0 >> 4usize) & 0x01;
849 val != 0
850 }
851 #[doc = "Autoreload register update OK Interrupt Enable."]
852 #[inline(always)]
853 pub fn set_arrokie(&mut self, val: bool) {
854 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
855 }
856 #[doc = "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
857 #[inline(always)]
858 pub const fn upie(&self) -> bool {
859 let val = (self.0 >> 5usize) & 0x01;
860 val != 0
861 }
862 #[doc = "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
863 #[inline(always)]
864 pub fn set_upie(&mut self, val: bool) {
865 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
866 }
867 #[doc = "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
868 #[inline(always)]
869 pub const fn downie(&self) -> bool {
870 let val = (self.0 >> 6usize) & 0x01;
871 val != 0
872 }
873 #[doc = "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
874 #[inline(always)]
875 pub fn set_downie(&mut self, val: bool) {
876 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
877 }
878 #[doc = "Update event interrupt enable."]
879 #[inline(always)]
880 pub const fn ueie(&self) -> bool {
881 let val = (self.0 >> 7usize) & 0x01;
882 val != 0
883 }
884 #[doc = "Update event interrupt enable."]
885 #[inline(always)]
886 pub fn set_ueie(&mut self, val: bool) {
887 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
888 }
889 #[doc = "Repetition register update OK interrupt Enable."]
890 #[inline(always)]
891 pub const fn repokie(&self) -> bool {
892 let val = (self.0 >> 8usize) & 0x01;
893 val != 0
894 }
895 #[doc = "Repetition register update OK interrupt Enable."]
896 #[inline(always)]
897 pub fn set_repokie(&mut self, val: bool) {
898 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
899 }
900 #[doc = "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
901 #[inline(always)]
902 pub const fn ccoie(&self, n: usize) -> bool {
903 assert!(n < 2usize);
904 let offs = 12usize + n * 1usize;
905 let val = (self.0 >> offs) & 0x01;
906 val != 0
907 }
908 #[doc = "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
909 #[inline(always)]
910 pub fn set_ccoie(&mut self, n: usize, val: bool) {
911 assert!(n < 2usize);
912 let offs = 12usize + n * 1usize;
913 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
914 }
915 #[doc = "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
916 #[inline(always)]
917 pub const fn ccde(&self, n: usize) -> bool {
918 assert!(n < 2usize);
919 let offs = 16usize + n * 9usize;
920 let val = (self.0 >> offs) & 0x01;
921 val != 0
922 }
923 #[doc = "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
924 #[inline(always)]
925 pub fn set_ccde(&mut self, n: usize, val: bool) {
926 assert!(n < 2usize);
927 let offs = 16usize + n * 9usize;
928 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
929 }
930 }
931 impl Default for DierAdv {
932 #[inline(always)]
933 fn default() -> DierAdv {
934 DierAdv(0)
935 }
936 }
937 impl core::fmt::Debug for DierAdv {
938 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
939 f.debug_struct("DierAdv")
940 .field("ccie", &[self.ccie(0usize), self.ccie(1usize)])
941 .field("arrmie", &self.arrmie())
942 .field("exttrigie", &self.exttrigie())
943 .field("cmpokie", &[self.cmpokie(0usize), self.cmpokie(1usize)])
944 .field("arrokie", &self.arrokie())
945 .field("upie", &self.upie())
946 .field("downie", &self.downie())
947 .field("ueie", &self.ueie())
948 .field("repokie", &self.repokie())
949 .field("ccoie", &[self.ccoie(0usize), self.ccoie(1usize)])
950 .field("ccde", &[self.ccde(0usize), self.ccde(1usize)])
951 .finish()
952 }
953 }
954 #[cfg(feature = "defmt")]
955 impl defmt::Format for DierAdv {
956 fn format(&self, f: defmt::Formatter) {
957 #[derive(defmt :: Format)]
958 struct DierAdv {
959 ccie: [bool; 2usize],
960 arrmie: bool,
961 exttrigie: bool,
962 cmpokie: [bool; 2usize],
963 arrokie: bool,
964 upie: bool,
965 downie: bool,
966 ueie: bool,
967 repokie: bool,
968 ccoie: [bool; 2usize],
969 ccde: [bool; 2usize],
970 }
971 let proxy = DierAdv {
972 ccie: [self.ccie(0usize), self.ccie(1usize)],
973 arrmie: self.arrmie(),
974 exttrigie: self.exttrigie(),
975 cmpokie: [self.cmpokie(0usize), self.cmpokie(1usize)],
976 arrokie: self.arrokie(),
977 upie: self.upie(),
978 downie: self.downie(),
979 ueie: self.ueie(),
980 repokie: self.repokie(),
981 ccoie: [self.ccoie(0usize), self.ccoie(1usize)],
982 ccde: [self.ccde(0usize), self.ccde(1usize)],
983 };
984 defmt::write!(f, "{}", proxy)
985 }
986 }
987 #[doc = "LPTIM interrupt enable register."]
988 #[repr(transparent)]
989 #[derive(Copy, Clone, Eq, PartialEq)]
990 pub struct DierBasic(pub u32);
991 impl DierBasic {
992 #[doc = "Capture/compare 1 interrupt enable."]
993 #[inline(always)]
994 pub const fn ccie(&self, n: usize) -> bool {
995 assert!(n < 1usize);
996 let offs = 0usize + n * 9usize;
997 let val = (self.0 >> offs) & 0x01;
998 val != 0
999 }
1000 #[doc = "Capture/compare 1 interrupt enable."]
1001 #[inline(always)]
1002 pub fn set_ccie(&mut self, n: usize, val: bool) {
1003 assert!(n < 1usize);
1004 let offs = 0usize + n * 9usize;
1005 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1006 }
1007 #[doc = "Autoreload match Interrupt Enable."]
1008 #[inline(always)]
1009 pub const fn arrmie(&self) -> bool {
1010 let val = (self.0 >> 1usize) & 0x01;
1011 val != 0
1012 }
1013 #[doc = "Autoreload match Interrupt Enable."]
1014 #[inline(always)]
1015 pub fn set_arrmie(&mut self, val: bool) {
1016 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1017 }
1018 #[doc = "External trigger valid edge Interrupt Enable."]
1019 #[inline(always)]
1020 pub const fn exttrigie(&self) -> bool {
1021 let val = (self.0 >> 2usize) & 0x01;
1022 val != 0
1023 }
1024 #[doc = "External trigger valid edge Interrupt Enable."]
1025 #[inline(always)]
1026 pub fn set_exttrigie(&mut self, val: bool) {
1027 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1028 }
1029 #[doc = "Compare register 1 update OK interrupt enable."]
1030 #[inline(always)]
1031 pub const fn cmpokie(&self, n: usize) -> bool {
1032 assert!(n < 1usize);
1033 let offs = 3usize + n * 16usize;
1034 let val = (self.0 >> offs) & 0x01;
1035 val != 0
1036 }
1037 #[doc = "Compare register 1 update OK interrupt enable."]
1038 #[inline(always)]
1039 pub fn set_cmpokie(&mut self, n: usize, val: bool) {
1040 assert!(n < 1usize);
1041 let offs = 3usize + n * 16usize;
1042 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1043 }
1044 #[doc = "Autoreload register update OK Interrupt Enable."]
1045 #[inline(always)]
1046 pub const fn arrokie(&self) -> bool {
1047 let val = (self.0 >> 4usize) & 0x01;
1048 val != 0
1049 }
1050 #[doc = "Autoreload register update OK Interrupt Enable."]
1051 #[inline(always)]
1052 pub fn set_arrokie(&mut self, val: bool) {
1053 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1054 }
1055 #[doc = "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1056 #[inline(always)]
1057 pub const fn upie(&self) -> bool {
1058 let val = (self.0 >> 5usize) & 0x01;
1059 val != 0
1060 }
1061 #[doc = "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1062 #[inline(always)]
1063 pub fn set_upie(&mut self, val: bool) {
1064 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1065 }
1066 #[doc = "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1067 #[inline(always)]
1068 pub const fn downie(&self) -> bool {
1069 let val = (self.0 >> 6usize) & 0x01;
1070 val != 0
1071 }
1072 #[doc = "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1073 #[inline(always)]
1074 pub fn set_downie(&mut self, val: bool) {
1075 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1076 }
1077 #[doc = "Update event interrupt enable."]
1078 #[inline(always)]
1079 pub const fn ueie(&self) -> bool {
1080 let val = (self.0 >> 7usize) & 0x01;
1081 val != 0
1082 }
1083 #[doc = "Update event interrupt enable."]
1084 #[inline(always)]
1085 pub fn set_ueie(&mut self, val: bool) {
1086 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1087 }
1088 #[doc = "Repetition register update OK interrupt Enable."]
1089 #[inline(always)]
1090 pub const fn repokie(&self) -> bool {
1091 let val = (self.0 >> 8usize) & 0x01;
1092 val != 0
1093 }
1094 #[doc = "Repetition register update OK interrupt Enable."]
1095 #[inline(always)]
1096 pub fn set_repokie(&mut self, val: bool) {
1097 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1098 }
1099 }
1100 impl Default for DierBasic {
1101 #[inline(always)]
1102 fn default() -> DierBasic {
1103 DierBasic(0)
1104 }
1105 }
1106 impl core::fmt::Debug for DierBasic {
1107 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1108 f.debug_struct("DierBasic")
1109 .field("ccie", &[self.ccie(0usize)])
1110 .field("arrmie", &self.arrmie())
1111 .field("exttrigie", &self.exttrigie())
1112 .field("cmpokie", &[self.cmpokie(0usize)])
1113 .field("arrokie", &self.arrokie())
1114 .field("upie", &self.upie())
1115 .field("downie", &self.downie())
1116 .field("ueie", &self.ueie())
1117 .field("repokie", &self.repokie())
1118 .finish()
1119 }
1120 }
1121 #[cfg(feature = "defmt")]
1122 impl defmt::Format for DierBasic {
1123 fn format(&self, f: defmt::Formatter) {
1124 #[derive(defmt :: Format)]
1125 struct DierBasic {
1126 ccie: [bool; 1usize],
1127 arrmie: bool,
1128 exttrigie: bool,
1129 cmpokie: [bool; 1usize],
1130 arrokie: bool,
1131 upie: bool,
1132 downie: bool,
1133 ueie: bool,
1134 repokie: bool,
1135 }
1136 let proxy = DierBasic {
1137 ccie: [self.ccie(0usize)],
1138 arrmie: self.arrmie(),
1139 exttrigie: self.exttrigie(),
1140 cmpokie: [self.cmpokie(0usize)],
1141 arrokie: self.arrokie(),
1142 upie: self.upie(),
1143 downie: self.downie(),
1144 ueie: self.ueie(),
1145 repokie: self.repokie(),
1146 };
1147 defmt::write!(f, "{}", proxy)
1148 }
1149 }
1150 #[doc = "LPTIM interrupt clear register."]
1151 #[repr(transparent)]
1152 #[derive(Copy, Clone, Eq, PartialEq)]
1153 pub struct IcrAdv(pub u32);
1154 impl IcrAdv {
1155 #[doc = "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register."]
1156 #[inline(always)]
1157 pub const fn cccf(&self, n: usize) -> bool {
1158 assert!(n < 2usize);
1159 let offs = 0usize + n * 9usize;
1160 let val = (self.0 >> offs) & 0x01;
1161 val != 0
1162 }
1163 #[doc = "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register."]
1164 #[inline(always)]
1165 pub fn set_cccf(&mut self, n: usize, val: bool) {
1166 assert!(n < 2usize);
1167 let offs = 0usize + n * 9usize;
1168 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1169 }
1170 #[doc = "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register."]
1171 #[inline(always)]
1172 pub const fn arrmcf(&self) -> bool {
1173 let val = (self.0 >> 1usize) & 0x01;
1174 val != 0
1175 }
1176 #[doc = "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register."]
1177 #[inline(always)]
1178 pub fn set_arrmcf(&mut self, val: bool) {
1179 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1180 }
1181 #[doc = "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register."]
1182 #[inline(always)]
1183 pub const fn exttrigcf(&self) -> bool {
1184 let val = (self.0 >> 2usize) & 0x01;
1185 val != 0
1186 }
1187 #[doc = "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register."]
1188 #[inline(always)]
1189 pub fn set_exttrigcf(&mut self, val: bool) {
1190 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1191 }
1192 #[doc = "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register."]
1193 #[inline(always)]
1194 pub const fn cmpokcf(&self, n: usize) -> bool {
1195 assert!(n < 2usize);
1196 let offs = 3usize + n * 16usize;
1197 let val = (self.0 >> offs) & 0x01;
1198 val != 0
1199 }
1200 #[doc = "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register."]
1201 #[inline(always)]
1202 pub fn set_cmpokcf(&mut self, n: usize, val: bool) {
1203 assert!(n < 2usize);
1204 let offs = 3usize + n * 16usize;
1205 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1206 }
1207 #[doc = "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register."]
1208 #[inline(always)]
1209 pub const fn arrokcf(&self) -> bool {
1210 let val = (self.0 >> 4usize) & 0x01;
1211 val != 0
1212 }
1213 #[doc = "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register."]
1214 #[inline(always)]
1215 pub fn set_arrokcf(&mut self, val: bool) {
1216 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1217 }
1218 #[doc = "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1219 #[inline(always)]
1220 pub const fn upcf(&self) -> bool {
1221 let val = (self.0 >> 5usize) & 0x01;
1222 val != 0
1223 }
1224 #[doc = "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1225 #[inline(always)]
1226 pub fn set_upcf(&mut self, val: bool) {
1227 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1228 }
1229 #[doc = "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1230 #[inline(always)]
1231 pub const fn downcf(&self) -> bool {
1232 let val = (self.0 >> 6usize) & 0x01;
1233 val != 0
1234 }
1235 #[doc = "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1236 #[inline(always)]
1237 pub fn set_downcf(&mut self, val: bool) {
1238 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1239 }
1240 #[doc = "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
1241 #[inline(always)]
1242 pub const fn uecf(&self) -> bool {
1243 let val = (self.0 >> 7usize) & 0x01;
1244 val != 0
1245 }
1246 #[doc = "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
1247 #[inline(always)]
1248 pub fn set_uecf(&mut self, val: bool) {
1249 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1250 }
1251 #[doc = "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register."]
1252 #[inline(always)]
1253 pub const fn repokcf(&self) -> bool {
1254 let val = (self.0 >> 8usize) & 0x01;
1255 val != 0
1256 }
1257 #[doc = "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register."]
1258 #[inline(always)]
1259 pub fn set_repokcf(&mut self, val: bool) {
1260 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1261 }
1262 #[doc = "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
1263 #[inline(always)]
1264 pub const fn ccocf(&self, n: usize) -> bool {
1265 assert!(n < 2usize);
1266 let offs = 12usize + n * 1usize;
1267 let val = (self.0 >> offs) & 0x01;
1268 val != 0
1269 }
1270 #[doc = "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
1271 #[inline(always)]
1272 pub fn set_ccocf(&mut self, n: usize, val: bool) {
1273 assert!(n < 2usize);
1274 let offs = 12usize + n * 1usize;
1275 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1276 }
1277 #[doc = "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register."]
1278 #[inline(always)]
1279 pub const fn dierokcf(&self) -> bool {
1280 let val = (self.0 >> 24usize) & 0x01;
1281 val != 0
1282 }
1283 #[doc = "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register."]
1284 #[inline(always)]
1285 pub fn set_dierokcf(&mut self, val: bool) {
1286 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1287 }
1288 }
1289 impl Default for IcrAdv {
1290 #[inline(always)]
1291 fn default() -> IcrAdv {
1292 IcrAdv(0)
1293 }
1294 }
1295 impl core::fmt::Debug for IcrAdv {
1296 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1297 f.debug_struct("IcrAdv")
1298 .field("cccf", &[self.cccf(0usize), self.cccf(1usize)])
1299 .field("arrmcf", &self.arrmcf())
1300 .field("exttrigcf", &self.exttrigcf())
1301 .field("cmpokcf", &[self.cmpokcf(0usize), self.cmpokcf(1usize)])
1302 .field("arrokcf", &self.arrokcf())
1303 .field("upcf", &self.upcf())
1304 .field("downcf", &self.downcf())
1305 .field("uecf", &self.uecf())
1306 .field("repokcf", &self.repokcf())
1307 .field("ccocf", &[self.ccocf(0usize), self.ccocf(1usize)])
1308 .field("dierokcf", &self.dierokcf())
1309 .finish()
1310 }
1311 }
1312 #[cfg(feature = "defmt")]
1313 impl defmt::Format for IcrAdv {
1314 fn format(&self, f: defmt::Formatter) {
1315 #[derive(defmt :: Format)]
1316 struct IcrAdv {
1317 cccf: [bool; 2usize],
1318 arrmcf: bool,
1319 exttrigcf: bool,
1320 cmpokcf: [bool; 2usize],
1321 arrokcf: bool,
1322 upcf: bool,
1323 downcf: bool,
1324 uecf: bool,
1325 repokcf: bool,
1326 ccocf: [bool; 2usize],
1327 dierokcf: bool,
1328 }
1329 let proxy = IcrAdv {
1330 cccf: [self.cccf(0usize), self.cccf(1usize)],
1331 arrmcf: self.arrmcf(),
1332 exttrigcf: self.exttrigcf(),
1333 cmpokcf: [self.cmpokcf(0usize), self.cmpokcf(1usize)],
1334 arrokcf: self.arrokcf(),
1335 upcf: self.upcf(),
1336 downcf: self.downcf(),
1337 uecf: self.uecf(),
1338 repokcf: self.repokcf(),
1339 ccocf: [self.ccocf(0usize), self.ccocf(1usize)],
1340 dierokcf: self.dierokcf(),
1341 };
1342 defmt::write!(f, "{}", proxy)
1343 }
1344 }
1345 #[doc = "LPTIM interrupt clear register."]
1346 #[repr(transparent)]
1347 #[derive(Copy, Clone, Eq, PartialEq)]
1348 pub struct IcrBasic(pub u32);
1349 impl IcrBasic {
1350 #[doc = "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register."]
1351 #[inline(always)]
1352 pub const fn cccf(&self, n: usize) -> bool {
1353 assert!(n < 1usize);
1354 let offs = 0usize + n * 9usize;
1355 let val = (self.0 >> offs) & 0x01;
1356 val != 0
1357 }
1358 #[doc = "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register."]
1359 #[inline(always)]
1360 pub fn set_cccf(&mut self, n: usize, val: bool) {
1361 assert!(n < 1usize);
1362 let offs = 0usize + n * 9usize;
1363 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1364 }
1365 #[doc = "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register."]
1366 #[inline(always)]
1367 pub const fn arrmcf(&self) -> bool {
1368 let val = (self.0 >> 1usize) & 0x01;
1369 val != 0
1370 }
1371 #[doc = "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register."]
1372 #[inline(always)]
1373 pub fn set_arrmcf(&mut self, val: bool) {
1374 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1375 }
1376 #[doc = "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register."]
1377 #[inline(always)]
1378 pub const fn exttrigcf(&self) -> bool {
1379 let val = (self.0 >> 2usize) & 0x01;
1380 val != 0
1381 }
1382 #[doc = "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register."]
1383 #[inline(always)]
1384 pub fn set_exttrigcf(&mut self, val: bool) {
1385 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1386 }
1387 #[doc = "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register."]
1388 #[inline(always)]
1389 pub const fn cmpokcf(&self, n: usize) -> bool {
1390 assert!(n < 1usize);
1391 let offs = 3usize + n * 16usize;
1392 let val = (self.0 >> offs) & 0x01;
1393 val != 0
1394 }
1395 #[doc = "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register."]
1396 #[inline(always)]
1397 pub fn set_cmpokcf(&mut self, n: usize, val: bool) {
1398 assert!(n < 1usize);
1399 let offs = 3usize + n * 16usize;
1400 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1401 }
1402 #[doc = "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register."]
1403 #[inline(always)]
1404 pub const fn arrokcf(&self) -> bool {
1405 let val = (self.0 >> 4usize) & 0x01;
1406 val != 0
1407 }
1408 #[doc = "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register."]
1409 #[inline(always)]
1410 pub fn set_arrokcf(&mut self, val: bool) {
1411 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1412 }
1413 #[doc = "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1414 #[inline(always)]
1415 pub const fn upcf(&self) -> bool {
1416 let val = (self.0 >> 5usize) & 0x01;
1417 val != 0
1418 }
1419 #[doc = "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1420 #[inline(always)]
1421 pub fn set_upcf(&mut self, val: bool) {
1422 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1423 }
1424 #[doc = "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1425 #[inline(always)]
1426 pub const fn downcf(&self) -> bool {
1427 let val = (self.0 >> 6usize) & 0x01;
1428 val != 0
1429 }
1430 #[doc = "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1431 #[inline(always)]
1432 pub fn set_downcf(&mut self, val: bool) {
1433 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1434 }
1435 #[doc = "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
1436 #[inline(always)]
1437 pub const fn uecf(&self) -> bool {
1438 let val = (self.0 >> 7usize) & 0x01;
1439 val != 0
1440 }
1441 #[doc = "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
1442 #[inline(always)]
1443 pub fn set_uecf(&mut self, val: bool) {
1444 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1445 }
1446 #[doc = "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register."]
1447 #[inline(always)]
1448 pub const fn repokcf(&self) -> bool {
1449 let val = (self.0 >> 8usize) & 0x01;
1450 val != 0
1451 }
1452 #[doc = "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register."]
1453 #[inline(always)]
1454 pub fn set_repokcf(&mut self, val: bool) {
1455 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1456 }
1457 #[doc = "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register."]
1458 #[inline(always)]
1459 pub const fn dierokcf(&self) -> bool {
1460 let val = (self.0 >> 24usize) & 0x01;
1461 val != 0
1462 }
1463 #[doc = "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register."]
1464 #[inline(always)]
1465 pub fn set_dierokcf(&mut self, val: bool) {
1466 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1467 }
1468 }
1469 impl Default for IcrBasic {
1470 #[inline(always)]
1471 fn default() -> IcrBasic {
1472 IcrBasic(0)
1473 }
1474 }
1475 impl core::fmt::Debug for IcrBasic {
1476 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1477 f.debug_struct("IcrBasic")
1478 .field("cccf", &[self.cccf(0usize)])
1479 .field("arrmcf", &self.arrmcf())
1480 .field("exttrigcf", &self.exttrigcf())
1481 .field("cmpokcf", &[self.cmpokcf(0usize)])
1482 .field("arrokcf", &self.arrokcf())
1483 .field("upcf", &self.upcf())
1484 .field("downcf", &self.downcf())
1485 .field("uecf", &self.uecf())
1486 .field("repokcf", &self.repokcf())
1487 .field("dierokcf", &self.dierokcf())
1488 .finish()
1489 }
1490 }
1491 #[cfg(feature = "defmt")]
1492 impl defmt::Format for IcrBasic {
1493 fn format(&self, f: defmt::Formatter) {
1494 #[derive(defmt :: Format)]
1495 struct IcrBasic {
1496 cccf: [bool; 1usize],
1497 arrmcf: bool,
1498 exttrigcf: bool,
1499 cmpokcf: [bool; 1usize],
1500 arrokcf: bool,
1501 upcf: bool,
1502 downcf: bool,
1503 uecf: bool,
1504 repokcf: bool,
1505 dierokcf: bool,
1506 }
1507 let proxy = IcrBasic {
1508 cccf: [self.cccf(0usize)],
1509 arrmcf: self.arrmcf(),
1510 exttrigcf: self.exttrigcf(),
1511 cmpokcf: [self.cmpokcf(0usize)],
1512 arrokcf: self.arrokcf(),
1513 upcf: self.upcf(),
1514 downcf: self.downcf(),
1515 uecf: self.uecf(),
1516 repokcf: self.repokcf(),
1517 dierokcf: self.dierokcf(),
1518 };
1519 defmt::write!(f, "{}", proxy)
1520 }
1521 }
1522 #[doc = "LPTIM interrupt and status register."]
1523 #[repr(transparent)]
1524 #[derive(Copy, Clone, Eq, PartialEq)]
1525 pub struct IsrAdv(pub u32);
1526 impl IsrAdv {
1527 #[doc = "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register."]
1528 #[inline(always)]
1529 pub const fn ccif(&self, n: usize) -> bool {
1530 assert!(n < 2usize);
1531 let offs = 0usize + n * 9usize;
1532 let val = (self.0 >> offs) & 0x01;
1533 val != 0
1534 }
1535 #[doc = "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register."]
1536 #[inline(always)]
1537 pub fn set_ccif(&mut self, n: usize, val: bool) {
1538 assert!(n < 2usize);
1539 let offs = 0usize + n * 9usize;
1540 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1541 }
1542 #[doc = "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register."]
1543 #[inline(always)]
1544 pub const fn arrm(&self) -> bool {
1545 let val = (self.0 >> 1usize) & 0x01;
1546 val != 0
1547 }
1548 #[doc = "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register."]
1549 #[inline(always)]
1550 pub fn set_arrm(&mut self, val: bool) {
1551 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1552 }
1553 #[doc = "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register."]
1554 #[inline(always)]
1555 pub const fn exttrig(&self) -> bool {
1556 let val = (self.0 >> 2usize) & 0x01;
1557 val != 0
1558 }
1559 #[doc = "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register."]
1560 #[inline(always)]
1561 pub fn set_exttrig(&mut self, val: bool) {
1562 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1563 }
1564 #[doc = "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register."]
1565 #[inline(always)]
1566 pub const fn cmpok(&self, n: usize) -> bool {
1567 assert!(n < 2usize);
1568 let offs = 3usize + n * 16usize;
1569 let val = (self.0 >> offs) & 0x01;
1570 val != 0
1571 }
1572 #[doc = "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register."]
1573 #[inline(always)]
1574 pub fn set_cmpok(&mut self, n: usize, val: bool) {
1575 assert!(n < 2usize);
1576 let offs = 3usize + n * 16usize;
1577 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1578 }
1579 #[doc = "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register."]
1580 #[inline(always)]
1581 pub const fn arrok(&self) -> bool {
1582 let val = (self.0 >> 4usize) & 0x01;
1583 val != 0
1584 }
1585 #[doc = "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register."]
1586 #[inline(always)]
1587 pub fn set_arrok(&mut self, val: bool) {
1588 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1589 }
1590 #[doc = "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1591 #[inline(always)]
1592 pub const fn up(&self) -> bool {
1593 let val = (self.0 >> 5usize) & 0x01;
1594 val != 0
1595 }
1596 #[doc = "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1597 #[inline(always)]
1598 pub fn set_up(&mut self, val: bool) {
1599 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1600 }
1601 #[doc = "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1602 #[inline(always)]
1603 pub const fn down(&self) -> bool {
1604 let val = (self.0 >> 6usize) & 0x01;
1605 val != 0
1606 }
1607 #[doc = "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1608 #[inline(always)]
1609 pub fn set_down(&mut self, val: bool) {
1610 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1611 }
1612 #[doc = "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register."]
1613 #[inline(always)]
1614 pub const fn ue(&self) -> bool {
1615 let val = (self.0 >> 7usize) & 0x01;
1616 val != 0
1617 }
1618 #[doc = "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register."]
1619 #[inline(always)]
1620 pub fn set_ue(&mut self, val: bool) {
1621 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1622 }
1623 #[doc = "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register."]
1624 #[inline(always)]
1625 pub const fn repok(&self) -> bool {
1626 let val = (self.0 >> 8usize) & 0x01;
1627 val != 0
1628 }
1629 #[doc = "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register."]
1630 #[inline(always)]
1631 pub fn set_repok(&mut self, val: bool) {
1632 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1633 }
1634 #[doc = "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
1635 #[inline(always)]
1636 pub const fn ccof(&self, n: usize) -> bool {
1637 assert!(n < 2usize);
1638 let offs = 12usize + n * 1usize;
1639 let val = (self.0 >> offs) & 0x01;
1640 val != 0
1641 }
1642 #[doc = "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to."]
1643 #[inline(always)]
1644 pub fn set_ccof(&mut self, n: usize, val: bool) {
1645 assert!(n < 2usize);
1646 let offs = 12usize + n * 1usize;
1647 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1648 }
1649 #[doc = "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register."]
1650 #[inline(always)]
1651 pub const fn dierok(&self) -> bool {
1652 let val = (self.0 >> 24usize) & 0x01;
1653 val != 0
1654 }
1655 #[doc = "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register."]
1656 #[inline(always)]
1657 pub fn set_dierok(&mut self, val: bool) {
1658 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1659 }
1660 }
1661 impl Default for IsrAdv {
1662 #[inline(always)]
1663 fn default() -> IsrAdv {
1664 IsrAdv(0)
1665 }
1666 }
1667 impl core::fmt::Debug for IsrAdv {
1668 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1669 f.debug_struct("IsrAdv")
1670 .field("ccif", &[self.ccif(0usize), self.ccif(1usize)])
1671 .field("arrm", &self.arrm())
1672 .field("exttrig", &self.exttrig())
1673 .field("cmpok", &[self.cmpok(0usize), self.cmpok(1usize)])
1674 .field("arrok", &self.arrok())
1675 .field("up", &self.up())
1676 .field("down", &self.down())
1677 .field("ue", &self.ue())
1678 .field("repok", &self.repok())
1679 .field("ccof", &[self.ccof(0usize), self.ccof(1usize)])
1680 .field("dierok", &self.dierok())
1681 .finish()
1682 }
1683 }
1684 #[cfg(feature = "defmt")]
1685 impl defmt::Format for IsrAdv {
1686 fn format(&self, f: defmt::Formatter) {
1687 #[derive(defmt :: Format)]
1688 struct IsrAdv {
1689 ccif: [bool; 2usize],
1690 arrm: bool,
1691 exttrig: bool,
1692 cmpok: [bool; 2usize],
1693 arrok: bool,
1694 up: bool,
1695 down: bool,
1696 ue: bool,
1697 repok: bool,
1698 ccof: [bool; 2usize],
1699 dierok: bool,
1700 }
1701 let proxy = IsrAdv {
1702 ccif: [self.ccif(0usize), self.ccif(1usize)],
1703 arrm: self.arrm(),
1704 exttrig: self.exttrig(),
1705 cmpok: [self.cmpok(0usize), self.cmpok(1usize)],
1706 arrok: self.arrok(),
1707 up: self.up(),
1708 down: self.down(),
1709 ue: self.ue(),
1710 repok: self.repok(),
1711 ccof: [self.ccof(0usize), self.ccof(1usize)],
1712 dierok: self.dierok(),
1713 };
1714 defmt::write!(f, "{}", proxy)
1715 }
1716 }
1717 #[doc = "LPTIM interrupt and status register."]
1718 #[repr(transparent)]
1719 #[derive(Copy, Clone, Eq, PartialEq)]
1720 pub struct IsrBasic(pub u32);
1721 impl IsrBasic {
1722 #[doc = "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register."]
1723 #[inline(always)]
1724 pub const fn ccif(&self, n: usize) -> bool {
1725 assert!(n < 1usize);
1726 let offs = 0usize + n * 9usize;
1727 let val = (self.0 >> offs) & 0x01;
1728 val != 0
1729 }
1730 #[doc = "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register."]
1731 #[inline(always)]
1732 pub fn set_ccif(&mut self, n: usize, val: bool) {
1733 assert!(n < 1usize);
1734 let offs = 0usize + n * 9usize;
1735 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1736 }
1737 #[doc = "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register."]
1738 #[inline(always)]
1739 pub const fn arrm(&self) -> bool {
1740 let val = (self.0 >> 1usize) & 0x01;
1741 val != 0
1742 }
1743 #[doc = "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register."]
1744 #[inline(always)]
1745 pub fn set_arrm(&mut self, val: bool) {
1746 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1747 }
1748 #[doc = "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register."]
1749 #[inline(always)]
1750 pub const fn exttrig(&self) -> bool {
1751 let val = (self.0 >> 2usize) & 0x01;
1752 val != 0
1753 }
1754 #[doc = "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register."]
1755 #[inline(always)]
1756 pub fn set_exttrig(&mut self, val: bool) {
1757 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1758 }
1759 #[doc = "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register."]
1760 #[inline(always)]
1761 pub const fn cmpok(&self, n: usize) -> bool {
1762 assert!(n < 1usize);
1763 let offs = 3usize + n * 16usize;
1764 let val = (self.0 >> offs) & 0x01;
1765 val != 0
1766 }
1767 #[doc = "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register."]
1768 #[inline(always)]
1769 pub fn set_cmpok(&mut self, n: usize, val: bool) {
1770 assert!(n < 1usize);
1771 let offs = 3usize + n * 16usize;
1772 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1773 }
1774 #[doc = "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register."]
1775 #[inline(always)]
1776 pub const fn arrok(&self) -> bool {
1777 let val = (self.0 >> 4usize) & 0x01;
1778 val != 0
1779 }
1780 #[doc = "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register."]
1781 #[inline(always)]
1782 pub fn set_arrok(&mut self, val: bool) {
1783 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1784 }
1785 #[doc = "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1786 #[inline(always)]
1787 pub const fn up(&self) -> bool {
1788 let val = (self.0 >> 5usize) & 0x01;
1789 val != 0
1790 }
1791 #[doc = "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1792 #[inline(always)]
1793 pub fn set_up(&mut self, val: bool) {
1794 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1795 }
1796 #[doc = "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1797 #[inline(always)]
1798 pub const fn down(&self) -> bool {
1799 let val = (self.0 >> 6usize) & 0x01;
1800 val != 0
1801 }
1802 #[doc = "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to."]
1803 #[inline(always)]
1804 pub fn set_down(&mut self, val: bool) {
1805 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1806 }
1807 #[doc = "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register."]
1808 #[inline(always)]
1809 pub const fn ue(&self) -> bool {
1810 let val = (self.0 >> 7usize) & 0x01;
1811 val != 0
1812 }
1813 #[doc = "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register."]
1814 #[inline(always)]
1815 pub fn set_ue(&mut self, val: bool) {
1816 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1817 }
1818 #[doc = "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register."]
1819 #[inline(always)]
1820 pub const fn repok(&self) -> bool {
1821 let val = (self.0 >> 8usize) & 0x01;
1822 val != 0
1823 }
1824 #[doc = "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register."]
1825 #[inline(always)]
1826 pub fn set_repok(&mut self, val: bool) {
1827 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1828 }
1829 #[doc = "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register."]
1830 #[inline(always)]
1831 pub const fn dierok(&self) -> bool {
1832 let val = (self.0 >> 24usize) & 0x01;
1833 val != 0
1834 }
1835 #[doc = "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register."]
1836 #[inline(always)]
1837 pub fn set_dierok(&mut self, val: bool) {
1838 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1839 }
1840 }
1841 impl Default for IsrBasic {
1842 #[inline(always)]
1843 fn default() -> IsrBasic {
1844 IsrBasic(0)
1845 }
1846 }
1847 impl core::fmt::Debug for IsrBasic {
1848 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1849 f.debug_struct("IsrBasic")
1850 .field("ccif", &[self.ccif(0usize)])
1851 .field("arrm", &self.arrm())
1852 .field("exttrig", &self.exttrig())
1853 .field("cmpok", &[self.cmpok(0usize)])
1854 .field("arrok", &self.arrok())
1855 .field("up", &self.up())
1856 .field("down", &self.down())
1857 .field("ue", &self.ue())
1858 .field("repok", &self.repok())
1859 .field("dierok", &self.dierok())
1860 .finish()
1861 }
1862 }
1863 #[cfg(feature = "defmt")]
1864 impl defmt::Format for IsrBasic {
1865 fn format(&self, f: defmt::Formatter) {
1866 #[derive(defmt :: Format)]
1867 struct IsrBasic {
1868 ccif: [bool; 1usize],
1869 arrm: bool,
1870 exttrig: bool,
1871 cmpok: [bool; 1usize],
1872 arrok: bool,
1873 up: bool,
1874 down: bool,
1875 ue: bool,
1876 repok: bool,
1877 dierok: bool,
1878 }
1879 let proxy = IsrBasic {
1880 ccif: [self.ccif(0usize)],
1881 arrm: self.arrm(),
1882 exttrig: self.exttrig(),
1883 cmpok: [self.cmpok(0usize)],
1884 arrok: self.arrok(),
1885 up: self.up(),
1886 down: self.down(),
1887 ue: self.ue(),
1888 repok: self.repok(),
1889 dierok: self.dierok(),
1890 };
1891 defmt::write!(f, "{}", proxy)
1892 }
1893 }
1894 #[doc = "LPTIM repetition register."]
1895 #[repr(transparent)]
1896 #[derive(Copy, Clone, Eq, PartialEq)]
1897 pub struct Rcr(pub u32);
1898 impl Rcr {
1899 #[doc = "Repetition register value REP is the repetition value for the LPTIM."]
1900 #[inline(always)]
1901 pub const fn rep(&self) -> u8 {
1902 let val = (self.0 >> 0usize) & 0xff;
1903 val as u8
1904 }
1905 #[doc = "Repetition register value REP is the repetition value for the LPTIM."]
1906 #[inline(always)]
1907 pub fn set_rep(&mut self, val: u8) {
1908 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1909 }
1910 }
1911 impl Default for Rcr {
1912 #[inline(always)]
1913 fn default() -> Rcr {
1914 Rcr(0)
1915 }
1916 }
1917 impl core::fmt::Debug for Rcr {
1918 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1919 f.debug_struct("Rcr").field("rep", &self.rep()).finish()
1920 }
1921 }
1922 #[cfg(feature = "defmt")]
1923 impl defmt::Format for Rcr {
1924 fn format(&self, f: defmt::Formatter) {
1925 #[derive(defmt :: Format)]
1926 struct Rcr {
1927 rep: u8,
1928 }
1929 let proxy = Rcr { rep: self.rep() };
1930 defmt::write!(f, "{}", proxy)
1931 }
1932 }
1933}
1934pub mod vals {
1935 #[repr(u8)]
1936 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1937 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1938 pub enum CcpInput {
1939 RISING = 0x0,
1940 FALLING = 0x01,
1941 _RESERVED_2 = 0x02,
1942 BOTH = 0x03,
1943 }
1944 impl CcpInput {
1945 #[inline(always)]
1946 pub const fn from_bits(val: u8) -> CcpInput {
1947 unsafe { core::mem::transmute(val & 0x03) }
1948 }
1949 #[inline(always)]
1950 pub const fn to_bits(self) -> u8 {
1951 unsafe { core::mem::transmute(self) }
1952 }
1953 }
1954 impl From<u8> for CcpInput {
1955 #[inline(always)]
1956 fn from(val: u8) -> CcpInput {
1957 CcpInput::from_bits(val)
1958 }
1959 }
1960 impl From<CcpInput> for u8 {
1961 #[inline(always)]
1962 fn from(val: CcpInput) -> u8 {
1963 CcpInput::to_bits(val)
1964 }
1965 }
1966 #[repr(u8)]
1967 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1968 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1969 pub enum CcpOutput {
1970 ACTIVE_HIGH = 0x0,
1971 ACTIVE_LOW = 0x01,
1972 _RESERVED_2 = 0x02,
1973 _RESERVED_3 = 0x03,
1974 }
1975 impl CcpOutput {
1976 #[inline(always)]
1977 pub const fn from_bits(val: u8) -> CcpOutput {
1978 unsafe { core::mem::transmute(val & 0x03) }
1979 }
1980 #[inline(always)]
1981 pub const fn to_bits(self) -> u8 {
1982 unsafe { core::mem::transmute(self) }
1983 }
1984 }
1985 impl From<u8> for CcpOutput {
1986 #[inline(always)]
1987 fn from(val: u8) -> CcpOutput {
1988 CcpOutput::from_bits(val)
1989 }
1990 }
1991 impl From<CcpOutput> for u8 {
1992 #[inline(always)]
1993 fn from(val: CcpOutput) -> u8 {
1994 CcpOutput::to_bits(val)
1995 }
1996 }
1997 #[repr(u8)]
1998 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1999 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2000 pub enum Ccsel {
2001 #[doc = "channel is configured in output PWM mode"]
2002 OUTPUT_COMPARE = 0x0,
2003 #[doc = "channel is configured in input capture mode"]
2004 INPUT_CAPTURE = 0x01,
2005 }
2006 impl Ccsel {
2007 #[inline(always)]
2008 pub const fn from_bits(val: u8) -> Ccsel {
2009 unsafe { core::mem::transmute(val & 0x01) }
2010 }
2011 #[inline(always)]
2012 pub const fn to_bits(self) -> u8 {
2013 unsafe { core::mem::transmute(self) }
2014 }
2015 }
2016 impl From<u8> for Ccsel {
2017 #[inline(always)]
2018 fn from(val: u8) -> Ccsel {
2019 Ccsel::from_bits(val)
2020 }
2021 }
2022 impl From<Ccsel> for u8 {
2023 #[inline(always)]
2024 fn from(val: Ccsel) -> u8 {
2025 Ccsel::to_bits(val)
2026 }
2027 }
2028 #[repr(u8)]
2029 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2030 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2031 pub enum Ckpol {
2032 #[doc = "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active."]
2033 RISING = 0x0,
2034 #[doc = "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active."]
2035 FALLING = 0x01,
2036 #[doc = "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active."]
2037 BOTH = 0x02,
2038 _RESERVED_3 = 0x03,
2039 }
2040 impl Ckpol {
2041 #[inline(always)]
2042 pub const fn from_bits(val: u8) -> Ckpol {
2043 unsafe { core::mem::transmute(val & 0x03) }
2044 }
2045 #[inline(always)]
2046 pub const fn to_bits(self) -> u8 {
2047 unsafe { core::mem::transmute(self) }
2048 }
2049 }
2050 impl From<u8> for Ckpol {
2051 #[inline(always)]
2052 fn from(val: u8) -> Ckpol {
2053 Ckpol::from_bits(val)
2054 }
2055 }
2056 impl From<Ckpol> for u8 {
2057 #[inline(always)]
2058 fn from(val: Ckpol) -> u8 {
2059 Ckpol::to_bits(val)
2060 }
2061 }
2062 #[repr(u8)]
2063 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2064 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2065 pub enum ClockSource {
2066 #[doc = "clocked by internal clock source (APB clock or any of the embedded oscillators)"]
2067 INTERNAL = 0x0,
2068 #[doc = "clocked by an external clock source through the LPTIM external Input1"]
2069 EXTERNAL = 0x01,
2070 }
2071 impl ClockSource {
2072 #[inline(always)]
2073 pub const fn from_bits(val: u8) -> ClockSource {
2074 unsafe { core::mem::transmute(val & 0x01) }
2075 }
2076 #[inline(always)]
2077 pub const fn to_bits(self) -> u8 {
2078 unsafe { core::mem::transmute(self) }
2079 }
2080 }
2081 impl From<u8> for ClockSource {
2082 #[inline(always)]
2083 fn from(val: u8) -> ClockSource {
2084 ClockSource::from_bits(val)
2085 }
2086 }
2087 impl From<ClockSource> for u8 {
2088 #[inline(always)]
2089 fn from(val: ClockSource) -> u8 {
2090 ClockSource::to_bits(val)
2091 }
2092 }
2093 #[repr(u8)]
2094 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2095 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2096 pub enum Filter {
2097 COUNT1 = 0x0,
2098 COUNT2 = 0x01,
2099 COUNT4 = 0x02,
2100 COUNT8 = 0x03,
2101 }
2102 impl Filter {
2103 #[inline(always)]
2104 pub const fn from_bits(val: u8) -> Filter {
2105 unsafe { core::mem::transmute(val & 0x03) }
2106 }
2107 #[inline(always)]
2108 pub const fn to_bits(self) -> u8 {
2109 unsafe { core::mem::transmute(self) }
2110 }
2111 }
2112 impl From<u8> for Filter {
2113 #[inline(always)]
2114 fn from(val: u8) -> Filter {
2115 Filter::from_bits(val)
2116 }
2117 }
2118 impl From<Filter> for u8 {
2119 #[inline(always)]
2120 fn from(val: Filter) -> u8 {
2121 Filter::to_bits(val)
2122 }
2123 }
2124 #[repr(u8)]
2125 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2126 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2127 pub enum Presc {
2128 DIV1 = 0x0,
2129 DIV2 = 0x01,
2130 DIV4 = 0x02,
2131 DIV8 = 0x03,
2132 DIV16 = 0x04,
2133 DIV32 = 0x05,
2134 DIV64 = 0x06,
2135 DIV128 = 0x07,
2136 }
2137 impl Presc {
2138 #[inline(always)]
2139 pub const fn from_bits(val: u8) -> Presc {
2140 unsafe { core::mem::transmute(val & 0x07) }
2141 }
2142 #[inline(always)]
2143 pub const fn to_bits(self) -> u8 {
2144 unsafe { core::mem::transmute(self) }
2145 }
2146 }
2147 impl From<u8> for Presc {
2148 #[inline(always)]
2149 fn from(val: u8) -> Presc {
2150 Presc::from_bits(val)
2151 }
2152 }
2153 impl From<Presc> for u8 {
2154 #[inline(always)]
2155 fn from(val: Presc) -> u8 {
2156 Presc::to_bits(val)
2157 }
2158 }
2159 #[repr(u8)]
2160 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2161 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2162 pub enum Trigen {
2163 #[doc = "software trigger (counting start is initiated by software)"]
2164 SOFTWARE = 0x0,
2165 #[doc = "rising edge is the active edge"]
2166 RISING_EDGE = 0x01,
2167 #[doc = "falling edge is the active edge"]
2168 FALLING_EDGE = 0x02,
2169 #[doc = "both edges are active edges"]
2170 BOTH_EDGE = 0x03,
2171 }
2172 impl Trigen {
2173 #[inline(always)]
2174 pub const fn from_bits(val: u8) -> Trigen {
2175 unsafe { core::mem::transmute(val & 0x03) }
2176 }
2177 #[inline(always)]
2178 pub const fn to_bits(self) -> u8 {
2179 unsafe { core::mem::transmute(self) }
2180 }
2181 }
2182 impl From<u8> for Trigen {
2183 #[inline(always)]
2184 fn from(val: u8) -> Trigen {
2185 Trigen::from_bits(val)
2186 }
2187 }
2188 impl From<Trigen> for u8 {
2189 #[inline(always)]
2190 fn from(val: Trigen) -> u8 {
2191 Trigen::to_bits(val)
2192 }
2193 }
2194 #[repr(u8)]
2195 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2196 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2197 pub enum Wavpol {
2198 #[doc = "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers."]
2199 POSITIVE = 0x0,
2200 #[doc = "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers."]
2201 NEGATIVE = 0x01,
2202 }
2203 impl Wavpol {
2204 #[inline(always)]
2205 pub const fn from_bits(val: u8) -> Wavpol {
2206 unsafe { core::mem::transmute(val & 0x01) }
2207 }
2208 #[inline(always)]
2209 pub const fn to_bits(self) -> u8 {
2210 unsafe { core::mem::transmute(self) }
2211 }
2212 }
2213 impl From<u8> for Wavpol {
2214 #[inline(always)]
2215 fn from(val: u8) -> Wavpol {
2216 Wavpol::from_bits(val)
2217 }
2218 }
2219 impl From<Wavpol> for u8 {
2220 #[inline(always)]
2221 fn from(val: Wavpol) -> u8 {
2222 Wavpol::to_bits(val)
2223 }
2224 }
2225}
2226