1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "OctoSPI"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Octospi {
9 ptr: *mut u8,
10}
11unsafe impl Send for Octospi {}
12unsafe impl Sync for Octospi {}
13impl Octospi {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "control register"]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "device configuration register 1"]
28 #[inline(always)]
29 pub const fn dcr1(self) -> crate::common::Reg<regs::Dcr1, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
31 }
32 #[doc = "device configuration register 2"]
33 #[inline(always)]
34 pub const fn dcr2(self) -> crate::common::Reg<regs::Dcr2, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
36 }
37 #[doc = "device configuration register 3"]
38 #[inline(always)]
39 pub const fn dcr3(self) -> crate::common::Reg<regs::Dcr3, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
41 }
42 #[doc = "device configuration register 4"]
43 #[inline(always)]
44 pub const fn dcr4(self) -> crate::common::Reg<regs::Dcr4, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
46 }
47 #[doc = "status register"]
48 #[inline(always)]
49 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::R> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
51 }
52 #[doc = "flag clear register"]
53 #[inline(always)]
54 pub const fn fcr(self) -> crate::common::Reg<regs::Fcr, crate::common::W> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
56 }
57 #[doc = "data length register"]
58 #[inline(always)]
59 pub const fn dlr(self) -> crate::common::Reg<regs::Dlr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
61 }
62 #[doc = "address register"]
63 #[inline(always)]
64 pub const fn ar(self) -> crate::common::Reg<regs::Ar, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
66 }
67 #[doc = "data register"]
68 #[inline(always)]
69 pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
71 }
72 #[doc = "polling status mask register"]
73 #[inline(always)]
74 pub const fn psmkr(self) -> crate::common::Reg<regs::Psmkr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
76 }
77 #[doc = "polling status match register"]
78 #[inline(always)]
79 pub const fn psmar(self) -> crate::common::Reg<regs::Psmar, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
81 }
82 #[doc = "polling interval register"]
83 #[inline(always)]
84 pub const fn pir(self) -> crate::common::Reg<regs::Pir, crate::common::RW> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
86 }
87 #[doc = "communication configuration register"]
88 #[inline(always)]
89 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) }
91 }
92 #[doc = "timing configuration register"]
93 #[inline(always)]
94 pub const fn tcr(self) -> crate::common::Reg<regs::Tcr, crate::common::RW> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) }
96 }
97 #[doc = "instruction register"]
98 #[inline(always)]
99 pub const fn ir(self) -> crate::common::Reg<regs::Ir, crate::common::RW> {
100 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) }
101 }
102 #[doc = "alternate bytes register"]
103 #[inline(always)]
104 pub const fn abr(self) -> crate::common::Reg<regs::Abr, crate::common::RW> {
105 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0120usize) as _) }
106 }
107 #[doc = "low-power timeout register"]
108 #[inline(always)]
109 pub const fn lptr(self) -> crate::common::Reg<regs::Lptr, crate::common::RW> {
110 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize) as _) }
111 }
112 #[doc = "wrap communication configuration register"]
113 #[inline(always)]
114 pub const fn wpccr(self) -> crate::common::Reg<regs::Wpccr, crate::common::RW> {
115 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) }
116 }
117 #[doc = "wrap timing configuration register"]
118 #[inline(always)]
119 pub const fn wptcr(self) -> crate::common::Reg<regs::Wptcr, crate::common::RW> {
120 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) }
121 }
122 #[doc = "wrap instruction register"]
123 #[inline(always)]
124 pub const fn wpir(self) -> crate::common::Reg<regs::Wpir, crate::common::RW> {
125 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) }
126 }
127 #[doc = "wrap alternate bytes register"]
128 #[inline(always)]
129 pub const fn wpabr(self) -> crate::common::Reg<regs::Wpabr, crate::common::RW> {
130 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) }
131 }
132 #[doc = "write communication configuration register"]
133 #[inline(always)]
134 pub const fn wccr(self) -> crate::common::Reg<regs::Wccr, crate::common::RW> {
135 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0180usize) as _) }
136 }
137 #[doc = "write timing configuration register"]
138 #[inline(always)]
139 pub const fn wtcr(self) -> crate::common::Reg<regs::Wtcr, crate::common::RW> {
140 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0188usize) as _) }
141 }
142 #[doc = "write instruction register"]
143 #[inline(always)]
144 pub const fn wir(self) -> crate::common::Reg<regs::Wir, crate::common::RW> {
145 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0190usize) as _) }
146 }
147 #[doc = "write alternate bytes register"]
148 #[inline(always)]
149 pub const fn wabr(self) -> crate::common::Reg<regs::Wabr, crate::common::RW> {
150 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01a0usize) as _) }
151 }
152 #[doc = "OCTOSPI HyperBus latency configuration register"]
153 #[inline(always)]
154 pub const fn hlcr(self) -> crate::common::Reg<regs::Hlcr, crate::common::RW> {
155 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) }
156 }
157}
158pub mod regs {
159 #[doc = "alternate bytes register"]
160 #[repr(transparent)]
161 #[derive(Copy, Clone, Eq, PartialEq)]
162 pub struct Abr(pub u32);
163 impl Abr {
164 #[doc = "Alternate bytes"]
165 #[inline(always)]
166 pub const fn alternate(&self) -> u32 {
167 let val = (self.0 >> 0usize) & 0xffff_ffff;
168 val as u32
169 }
170 #[doc = "Alternate bytes"]
171 #[inline(always)]
172 pub fn set_alternate(&mut self, val: u32) {
173 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
174 }
175 }
176 impl Default for Abr {
177 #[inline(always)]
178 fn default() -> Abr {
179 Abr(0)
180 }
181 }
182 impl core::fmt::Debug for Abr {
183 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
184 f.debug_struct("Abr").field("alternate", &self.alternate()).finish()
185 }
186 }
187 #[cfg(feature = "defmt")]
188 impl defmt::Format for Abr {
189 fn format(&self, f: defmt::Formatter) {
190 #[derive(defmt :: Format)]
191 struct Abr {
192 alternate: u32,
193 }
194 let proxy = Abr {
195 alternate: self.alternate(),
196 };
197 defmt::write!(f, "{}", proxy)
198 }
199 }
200 #[doc = "address register"]
201 #[repr(transparent)]
202 #[derive(Copy, Clone, Eq, PartialEq)]
203 pub struct Ar(pub u32);
204 impl Ar {
205 #[doc = "Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR\\[0\\]
206is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode)."]
207 #[inline(always)]
208 pub const fn address(&self) -> u32 {
209 let val = (self.0 >> 0usize) & 0xffff_ffff;
210 val as u32
211 }
212 #[doc = "Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR\\[0\\]
213is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode)."]
214 #[inline(always)]
215 pub fn set_address(&mut self, val: u32) {
216 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
217 }
218 }
219 impl Default for Ar {
220 #[inline(always)]
221 fn default() -> Ar {
222 Ar(0)
223 }
224 }
225 impl core::fmt::Debug for Ar {
226 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
227 f.debug_struct("Ar").field("address", &self.address()).finish()
228 }
229 }
230 #[cfg(feature = "defmt")]
231 impl defmt::Format for Ar {
232 fn format(&self, f: defmt::Formatter) {
233 #[derive(defmt :: Format)]
234 struct Ar {
235 address: u32,
236 }
237 let proxy = Ar {
238 address: self.address(),
239 };
240 defmt::write!(f, "{}", proxy)
241 }
242 }
243 #[doc = "communication configuration register"]
244 #[repr(transparent)]
245 #[derive(Copy, Clone, Eq, PartialEq)]
246 pub struct Ccr(pub u32);
247 impl Ccr {
248 #[doc = "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved"]
249 #[inline(always)]
250 pub const fn imode(&self) -> super::vals::PhaseMode {
251 let val = (self.0 >> 0usize) & 0x07;
252 super::vals::PhaseMode::from_bits(val as u8)
253 }
254 #[doc = "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved"]
255 #[inline(always)]
256 pub fn set_imode(&mut self, val: super::vals::PhaseMode) {
257 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
258 }
259 #[doc = "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase."]
260 #[inline(always)]
261 pub const fn idtr(&self) -> bool {
262 let val = (self.0 >> 3usize) & 0x01;
263 val != 0
264 }
265 #[doc = "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase."]
266 #[inline(always)]
267 pub fn set_idtr(&mut self, val: bool) {
268 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
269 }
270 #[doc = "Instruction size. This bit defines instruction size."]
271 #[inline(always)]
272 pub const fn isize(&self) -> super::vals::SizeInBits {
273 let val = (self.0 >> 4usize) & 0x03;
274 super::vals::SizeInBits::from_bits(val as u8)
275 }
276 #[doc = "Instruction size. This bit defines instruction size."]
277 #[inline(always)]
278 pub fn set_isize(&mut self, val: super::vals::SizeInBits) {
279 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
280 }
281 #[doc = "Address mode. This field defines the address phase mode of operation. 101-111: Reserved"]
282 #[inline(always)]
283 pub const fn admode(&self) -> super::vals::PhaseMode {
284 let val = (self.0 >> 8usize) & 0x07;
285 super::vals::PhaseMode::from_bits(val as u8)
286 }
287 #[doc = "Address mode. This field defines the address phase mode of operation. 101-111: Reserved"]
288 #[inline(always)]
289 pub fn set_admode(&mut self, val: super::vals::PhaseMode) {
290 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
291 }
292 #[doc = "Address double transfer rate. This bit sets the DTR mode for the address phase."]
293 #[inline(always)]
294 pub const fn addtr(&self) -> bool {
295 let val = (self.0 >> 11usize) & 0x01;
296 val != 0
297 }
298 #[doc = "Address double transfer rate. This bit sets the DTR mode for the address phase."]
299 #[inline(always)]
300 pub fn set_addtr(&mut self, val: bool) {
301 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
302 }
303 #[doc = "Address size. This field defines address size."]
304 #[inline(always)]
305 pub const fn adsize(&self) -> super::vals::SizeInBits {
306 let val = (self.0 >> 12usize) & 0x03;
307 super::vals::SizeInBits::from_bits(val as u8)
308 }
309 #[doc = "Address size. This field defines address size."]
310 #[inline(always)]
311 pub fn set_adsize(&mut self, val: super::vals::SizeInBits) {
312 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
313 }
314 #[doc = "Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved"]
315 #[inline(always)]
316 pub const fn abmode(&self) -> super::vals::PhaseMode {
317 let val = (self.0 >> 16usize) & 0x07;
318 super::vals::PhaseMode::from_bits(val as u8)
319 }
320 #[doc = "Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved"]
321 #[inline(always)]
322 pub fn set_abmode(&mut self, val: super::vals::PhaseMode) {
323 self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
324 }
325 #[doc = "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0."]
326 #[inline(always)]
327 pub const fn abdtr(&self) -> bool {
328 let val = (self.0 >> 19usize) & 0x01;
329 val != 0
330 }
331 #[doc = "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0."]
332 #[inline(always)]
333 pub fn set_abdtr(&mut self, val: bool) {
334 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
335 }
336 #[doc = "Alternate bytes size. This bit defines alternate bytes size."]
337 #[inline(always)]
338 pub const fn absize(&self) -> super::vals::SizeInBits {
339 let val = (self.0 >> 20usize) & 0x03;
340 super::vals::SizeInBits::from_bits(val as u8)
341 }
342 #[doc = "Alternate bytes size. This bit defines alternate bytes size."]
343 #[inline(always)]
344 pub fn set_absize(&mut self, val: super::vals::SizeInBits) {
345 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
346 }
347 #[doc = "Data mode. This field defines the data phase mode of operation. 101-111: Reserved"]
348 #[inline(always)]
349 pub const fn dmode(&self) -> super::vals::PhaseMode {
350 let val = (self.0 >> 24usize) & 0x07;
351 super::vals::PhaseMode::from_bits(val as u8)
352 }
353 #[doc = "Data mode. This field defines the data phase mode of operation. 101-111: Reserved"]
354 #[inline(always)]
355 pub fn set_dmode(&mut self, val: super::vals::PhaseMode) {
356 self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
357 }
358 #[doc = "Data double transfer rate. This bit sets the DTR mode for the data phase."]
359 #[inline(always)]
360 pub const fn ddtr(&self) -> bool {
361 let val = (self.0 >> 27usize) & 0x01;
362 val != 0
363 }
364 #[doc = "Data double transfer rate. This bit sets the DTR mode for the data phase."]
365 #[inline(always)]
366 pub fn set_ddtr(&mut self, val: bool) {
367 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
368 }
369 #[doc = "DQS enable. This bit enables the data strobe management."]
370 #[inline(always)]
371 pub const fn dqse(&self) -> bool {
372 let val = (self.0 >> 29usize) & 0x01;
373 val != 0
374 }
375 #[doc = "DQS enable. This bit enables the data strobe management."]
376 #[inline(always)]
377 pub fn set_dqse(&mut self, val: bool) {
378 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
379 }
380 #[doc = "Send instruction only once mode. This bit has no effect when IMODE = 00 (see )."]
381 #[inline(always)]
382 pub const fn sioo(&self) -> bool {
383 let val = (self.0 >> 31usize) & 0x01;
384 val != 0
385 }
386 #[doc = "Send instruction only once mode. This bit has no effect when IMODE = 00 (see )."]
387 #[inline(always)]
388 pub fn set_sioo(&mut self, val: bool) {
389 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
390 }
391 }
392 impl Default for Ccr {
393 #[inline(always)]
394 fn default() -> Ccr {
395 Ccr(0)
396 }
397 }
398 impl core::fmt::Debug for Ccr {
399 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
400 f.debug_struct("Ccr")
401 .field("imode", &self.imode())
402 .field("idtr", &self.idtr())
403 .field("isize", &self.isize())
404 .field("admode", &self.admode())
405 .field("addtr", &self.addtr())
406 .field("adsize", &self.adsize())
407 .field("abmode", &self.abmode())
408 .field("abdtr", &self.abdtr())
409 .field("absize", &self.absize())
410 .field("dmode", &self.dmode())
411 .field("ddtr", &self.ddtr())
412 .field("dqse", &self.dqse())
413 .field("sioo", &self.sioo())
414 .finish()
415 }
416 }
417 #[cfg(feature = "defmt")]
418 impl defmt::Format for Ccr {
419 fn format(&self, f: defmt::Formatter) {
420 #[derive(defmt :: Format)]
421 struct Ccr {
422 imode: super::vals::PhaseMode,
423 idtr: bool,
424 isize: super::vals::SizeInBits,
425 admode: super::vals::PhaseMode,
426 addtr: bool,
427 adsize: super::vals::SizeInBits,
428 abmode: super::vals::PhaseMode,
429 abdtr: bool,
430 absize: super::vals::SizeInBits,
431 dmode: super::vals::PhaseMode,
432 ddtr: bool,
433 dqse: bool,
434 sioo: bool,
435 }
436 let proxy = Ccr {
437 imode: self.imode(),
438 idtr: self.idtr(),
439 isize: self.isize(),
440 admode: self.admode(),
441 addtr: self.addtr(),
442 adsize: self.adsize(),
443 abmode: self.abmode(),
444 abdtr: self.abdtr(),
445 absize: self.absize(),
446 dmode: self.dmode(),
447 ddtr: self.ddtr(),
448 dqse: self.dqse(),
449 sioo: self.sioo(),
450 };
451 defmt::write!(f, "{}", proxy)
452 }
453 }
454 #[doc = "control register"]
455 #[repr(transparent)]
456 #[derive(Copy, Clone, Eq, PartialEq)]
457 pub struct Cr(pub u32);
458 impl Cr {
459 #[doc = "Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active."]
460 #[inline(always)]
461 pub const fn en(&self) -> bool {
462 let val = (self.0 >> 0usize) & 0x01;
463 val != 0
464 }
465 #[doc = "Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active."]
466 #[inline(always)]
467 pub fn set_en(&mut self, val: bool) {
468 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
469 }
470 #[doc = "Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0."]
471 #[inline(always)]
472 pub const fn abort(&self) -> bool {
473 let val = (self.0 >> 1usize) & 0x01;
474 val != 0
475 }
476 #[doc = "Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0."]
477 #[inline(always)]
478 pub fn set_abort(&mut self, val: bool) {
479 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
480 }
481 #[doc = "DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation."]
482 #[inline(always)]
483 pub const fn dmaen(&self) -> bool {
484 let val = (self.0 >> 2usize) & 0x01;
485 val != 0
486 }
487 #[doc = "DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation."]
488 #[inline(always)]
489 pub fn set_dmaen(&mut self, val: bool) {
490 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
491 }
492 #[doc = "Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE\\[1:0\\]
493= 11) is selected. This bit enables the timeout counter."]
494 #[inline(always)]
495 pub const fn tcen(&self) -> bool {
496 let val = (self.0 >> 3usize) & 0x01;
497 val != 0
498 }
499 #[doc = "Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE\\[1:0\\]
500= 11) is selected. This bit enables the timeout counter."]
501 #[inline(always)]
502 pub fn set_tcen(&mut self, val: bool) {
503 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
504 }
505 #[doc = "Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity"]
506 #[inline(always)]
507 pub const fn dmm(&self) -> bool {
508 let val = (self.0 >> 6usize) & 0x01;
509 val != 0
510 }
511 #[doc = "Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity"]
512 #[inline(always)]
513 pub fn set_dmm(&mut self, val: bool) {
514 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
515 }
516 #[doc = "Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected."]
517 #[inline(always)]
518 pub const fn fsel(&self) -> super::vals::FlashSelect {
519 let val = (self.0 >> 7usize) & 0x01;
520 super::vals::FlashSelect::from_bits(val as u8)
521 }
522 #[doc = "Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected."]
523 #[inline(always)]
524 pub fn set_fsel(&mut self, val: super::vals::FlashSelect) {
525 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
526 }
527 #[doc = "FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES\\[4:0\\]
528value."]
529 #[inline(always)]
530 pub const fn fthres(&self) -> super::vals::Threshold {
531 let val = (self.0 >> 8usize) & 0x1f;
532 super::vals::Threshold::from_bits(val as u8)
533 }
534 #[doc = "FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES\\[4:0\\]
535value."]
536 #[inline(always)]
537 pub fn set_fthres(&mut self, val: super::vals::Threshold) {
538 self.0 = (self.0 & !(0x1f << 8usize)) | (((val.to_bits() as u32) & 0x1f) << 8usize);
539 }
540 #[doc = "Transfer error interrupt enable. This bit enables the transfer error interrupt."]
541 #[inline(always)]
542 pub const fn teie(&self) -> bool {
543 let val = (self.0 >> 16usize) & 0x01;
544 val != 0
545 }
546 #[doc = "Transfer error interrupt enable. This bit enables the transfer error interrupt."]
547 #[inline(always)]
548 pub fn set_teie(&mut self, val: bool) {
549 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
550 }
551 #[doc = "Transfer complete interrupt enable. This bit enables the transfer complete interrupt."]
552 #[inline(always)]
553 pub const fn tcie(&self) -> bool {
554 let val = (self.0 >> 17usize) & 0x01;
555 val != 0
556 }
557 #[doc = "Transfer complete interrupt enable. This bit enables the transfer complete interrupt."]
558 #[inline(always)]
559 pub fn set_tcie(&mut self, val: bool) {
560 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
561 }
562 #[doc = "FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt."]
563 #[inline(always)]
564 pub const fn ftie(&self) -> bool {
565 let val = (self.0 >> 18usize) & 0x01;
566 val != 0
567 }
568 #[doc = "FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt."]
569 #[inline(always)]
570 pub fn set_ftie(&mut self, val: bool) {
571 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
572 }
573 #[doc = "Status match interrupt enable. This bit enables the status match interrupt."]
574 #[inline(always)]
575 pub const fn smie(&self) -> bool {
576 let val = (self.0 >> 19usize) & 0x01;
577 val != 0
578 }
579 #[doc = "Status match interrupt enable. This bit enables the status match interrupt."]
580 #[inline(always)]
581 pub fn set_smie(&mut self, val: bool) {
582 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
583 }
584 #[doc = "Timeout interrupt enable. This bit enables the timeout interrupt."]
585 #[inline(always)]
586 pub const fn toie(&self) -> bool {
587 let val = (self.0 >> 20usize) & 0x01;
588 val != 0
589 }
590 #[doc = "Timeout interrupt enable. This bit enables the timeout interrupt."]
591 #[inline(always)]
592 pub fn set_toie(&mut self, val: bool) {
593 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
594 }
595 #[doc = "Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match."]
596 #[inline(always)]
597 pub const fn apms(&self) -> bool {
598 let val = (self.0 >> 22usize) & 0x01;
599 val != 0
600 }
601 #[doc = "Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match."]
602 #[inline(always)]
603 pub fn set_apms(&mut self, val: bool) {
604 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
605 }
606 #[doc = "Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode."]
607 #[inline(always)]
608 pub const fn pmm(&self) -> super::vals::MatchMode {
609 let val = (self.0 >> 23usize) & 0x01;
610 super::vals::MatchMode::from_bits(val as u8)
611 }
612 #[doc = "Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode."]
613 #[inline(always)]
614 pub fn set_pmm(&mut self, val: super::vals::MatchMode) {
615 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize);
616 }
617 #[doc = "Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE\\[1:0\\]
618value. If FMODE\\[1:0\\]
619and FTHRES\\[4:0\\]
620are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state."]
621 #[inline(always)]
622 pub const fn fmode(&self) -> super::vals::FunctionalMode {
623 let val = (self.0 >> 28usize) & 0x03;
624 super::vals::FunctionalMode::from_bits(val as u8)
625 }
626 #[doc = "Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE\\[1:0\\]
627value. If FMODE\\[1:0\\]
628and FTHRES\\[4:0\\]
629are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state."]
630 #[inline(always)]
631 pub fn set_fmode(&mut self, val: super::vals::FunctionalMode) {
632 self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
633 }
634 }
635 impl Default for Cr {
636 #[inline(always)]
637 fn default() -> Cr {
638 Cr(0)
639 }
640 }
641 impl core::fmt::Debug for Cr {
642 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
643 f.debug_struct("Cr")
644 .field("en", &self.en())
645 .field("abort", &self.abort())
646 .field("dmaen", &self.dmaen())
647 .field("tcen", &self.tcen())
648 .field("dmm", &self.dmm())
649 .field("fsel", &self.fsel())
650 .field("fthres", &self.fthres())
651 .field("teie", &self.teie())
652 .field("tcie", &self.tcie())
653 .field("ftie", &self.ftie())
654 .field("smie", &self.smie())
655 .field("toie", &self.toie())
656 .field("apms", &self.apms())
657 .field("pmm", &self.pmm())
658 .field("fmode", &self.fmode())
659 .finish()
660 }
661 }
662 #[cfg(feature = "defmt")]
663 impl defmt::Format for Cr {
664 fn format(&self, f: defmt::Formatter) {
665 #[derive(defmt :: Format)]
666 struct Cr {
667 en: bool,
668 abort: bool,
669 dmaen: bool,
670 tcen: bool,
671 dmm: bool,
672 fsel: super::vals::FlashSelect,
673 fthres: super::vals::Threshold,
674 teie: bool,
675 tcie: bool,
676 ftie: bool,
677 smie: bool,
678 toie: bool,
679 apms: bool,
680 pmm: super::vals::MatchMode,
681 fmode: super::vals::FunctionalMode,
682 }
683 let proxy = Cr {
684 en: self.en(),
685 abort: self.abort(),
686 dmaen: self.dmaen(),
687 tcen: self.tcen(),
688 dmm: self.dmm(),
689 fsel: self.fsel(),
690 fthres: self.fthres(),
691 teie: self.teie(),
692 tcie: self.tcie(),
693 ftie: self.ftie(),
694 smie: self.smie(),
695 toie: self.toie(),
696 apms: self.apms(),
697 pmm: self.pmm(),
698 fmode: self.fmode(),
699 };
700 defmt::write!(f, "{}", proxy)
701 }
702 }
703 #[doc = "device configuration register 1"]
704 #[repr(transparent)]
705 #[derive(Copy, Clone, Eq, PartialEq)]
706 pub struct Dcr1(pub u32);
707 impl Dcr1 {
708 #[doc = "Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1)."]
709 #[inline(always)]
710 pub const fn ckmode(&self) -> bool {
711 let val = (self.0 >> 0usize) & 0x01;
712 val != 0
713 }
714 #[doc = "Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1)."]
715 #[inline(always)]
716 pub fn set_ckmode(&mut self, val: bool) {
717 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
718 }
719 #[doc = "Free running clock. This bit configures the free running clock."]
720 #[inline(always)]
721 pub const fn frck(&self) -> bool {
722 let val = (self.0 >> 1usize) & 0x01;
723 val != 0
724 }
725 #[doc = "Free running clock. This bit configures the free running clock."]
726 #[inline(always)]
727 pub fn set_frck(&mut self, val: bool) {
728 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
729 }
730 #[doc = "Delay block bypass"]
731 #[inline(always)]
732 pub const fn dlybyp(&self) -> bool {
733 let val = (self.0 >> 3usize) & 0x01;
734 val != 0
735 }
736 #[doc = "Delay block bypass"]
737 #[inline(always)]
738 pub fn set_dlybyp(&mut self, val: bool) {
739 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
740 }
741 #[doc = "Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ..."]
742 #[inline(always)]
743 pub const fn csht(&self) -> u8 {
744 let val = (self.0 >> 8usize) & 0x3f;
745 val as u8
746 }
747 #[doc = "Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ..."]
748 #[inline(always)]
749 pub fn set_csht(&mut self, val: u8) {
750 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
751 }
752 #[doc = "Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2\\[DEVSIZE+1\\]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE\\[4:0\\]
753indicates the total capacity of the two devices together."]
754 #[inline(always)]
755 pub const fn devsize(&self) -> u8 {
756 let val = (self.0 >> 16usize) & 0x1f;
757 val as u8
758 }
759 #[doc = "Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2\\[DEVSIZE+1\\]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE\\[4:0\\]
760indicates the total capacity of the two devices together."]
761 #[inline(always)]
762 pub fn set_devsize(&mut self, val: u8) {
763 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
764 }
765 #[doc = "Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP\\[2:0\\]
766for memories different from Micron. Others: Reserved"]
767 #[inline(always)]
768 pub const fn mtyp(&self) -> super::vals::MemType {
769 let val = (self.0 >> 24usize) & 0x07;
770 super::vals::MemType::from_bits(val as u8)
771 }
772 #[doc = "Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP\\[2:0\\]
773for memories different from Micron. Others: Reserved"]
774 #[inline(always)]
775 pub fn set_mtyp(&mut self, val: super::vals::MemType) {
776 self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
777 }
778 }
779 impl Default for Dcr1 {
780 #[inline(always)]
781 fn default() -> Dcr1 {
782 Dcr1(0)
783 }
784 }
785 impl core::fmt::Debug for Dcr1 {
786 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
787 f.debug_struct("Dcr1")
788 .field("ckmode", &self.ckmode())
789 .field("frck", &self.frck())
790 .field("dlybyp", &self.dlybyp())
791 .field("csht", &self.csht())
792 .field("devsize", &self.devsize())
793 .field("mtyp", &self.mtyp())
794 .finish()
795 }
796 }
797 #[cfg(feature = "defmt")]
798 impl defmt::Format for Dcr1 {
799 fn format(&self, f: defmt::Formatter) {
800 #[derive(defmt :: Format)]
801 struct Dcr1 {
802 ckmode: bool,
803 frck: bool,
804 dlybyp: bool,
805 csht: u8,
806 devsize: u8,
807 mtyp: super::vals::MemType,
808 }
809 let proxy = Dcr1 {
810 ckmode: self.ckmode(),
811 frck: self.frck(),
812 dlybyp: self.dlybyp(),
813 csht: self.csht(),
814 devsize: self.devsize(),
815 mtyp: self.mtyp(),
816 };
817 defmt::write!(f, "{}", proxy)
818 }
819 }
820 #[doc = "device configuration register 2"]
821 #[repr(transparent)]
822 #[derive(Copy, Clone, Eq, PartialEq)]
823 pub struct Dcr2(pub u32);
824 impl Dcr2 {
825 #[doc = "Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high."]
826 #[inline(always)]
827 pub const fn prescaler(&self) -> u8 {
828 let val = (self.0 >> 0usize) & 0xff;
829 val as u8
830 }
831 #[doc = "Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high."]
832 #[inline(always)]
833 pub fn set_prescaler(&mut self, val: u8) {
834 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
835 }
836 #[doc = "Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved"]
837 #[inline(always)]
838 pub const fn wrapsize(&self) -> u8 {
839 let val = (self.0 >> 16usize) & 0x07;
840 val as u8
841 }
842 #[doc = "Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved"]
843 #[inline(always)]
844 pub fn set_wrapsize(&mut self, val: u8) {
845 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
846 }
847 }
848 impl Default for Dcr2 {
849 #[inline(always)]
850 fn default() -> Dcr2 {
851 Dcr2(0)
852 }
853 }
854 impl core::fmt::Debug for Dcr2 {
855 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
856 f.debug_struct("Dcr2")
857 .field("prescaler", &self.prescaler())
858 .field("wrapsize", &self.wrapsize())
859 .finish()
860 }
861 }
862 #[cfg(feature = "defmt")]
863 impl defmt::Format for Dcr2 {
864 fn format(&self, f: defmt::Formatter) {
865 #[derive(defmt :: Format)]
866 struct Dcr2 {
867 prescaler: u8,
868 wrapsize: u8,
869 }
870 let proxy = Dcr2 {
871 prescaler: self.prescaler(),
872 wrapsize: self.wrapsize(),
873 };
874 defmt::write!(f, "{}", proxy)
875 }
876 }
877 #[doc = "device configuration register 3"]
878 #[repr(transparent)]
879 #[derive(Copy, Clone, Eq, PartialEq)]
880 pub struct Dcr3(pub u32);
881 impl Dcr3 {
882 #[doc = "Maximum transfer"]
883 #[inline(always)]
884 pub const fn maxtran(&self) -> u8 {
885 let val = (self.0 >> 0usize) & 0xff;
886 val as u8
887 }
888 #[doc = "Maximum transfer"]
889 #[inline(always)]
890 pub fn set_maxtran(&mut self, val: u8) {
891 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
892 }
893 #[doc = "NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes"]
894 #[inline(always)]
895 pub const fn csbound(&self) -> u8 {
896 let val = (self.0 >> 16usize) & 0x1f;
897 val as u8
898 }
899 #[doc = "NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes"]
900 #[inline(always)]
901 pub fn set_csbound(&mut self, val: u8) {
902 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
903 }
904 }
905 impl Default for Dcr3 {
906 #[inline(always)]
907 fn default() -> Dcr3 {
908 Dcr3(0)
909 }
910 }
911 impl core::fmt::Debug for Dcr3 {
912 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
913 f.debug_struct("Dcr3")
914 .field("maxtran", &self.maxtran())
915 .field("csbound", &self.csbound())
916 .finish()
917 }
918 }
919 #[cfg(feature = "defmt")]
920 impl defmt::Format for Dcr3 {
921 fn format(&self, f: defmt::Formatter) {
922 #[derive(defmt :: Format)]
923 struct Dcr3 {
924 maxtran: u8,
925 csbound: u8,
926 }
927 let proxy = Dcr3 {
928 maxtran: self.maxtran(),
929 csbound: self.csbound(),
930 };
931 defmt::write!(f, "{}", proxy)
932 }
933 }
934 #[doc = "device configuration register 4"]
935 #[repr(transparent)]
936 #[derive(Copy, Clone, Eq, PartialEq)]
937 pub struct Dcr4(pub u32);
938 impl Dcr4 {
939 #[doc = "Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles."]
940 #[inline(always)]
941 pub const fn refresh(&self) -> u32 {
942 let val = (self.0 >> 0usize) & 0xffff_ffff;
943 val as u32
944 }
945 #[doc = "Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles."]
946 #[inline(always)]
947 pub fn set_refresh(&mut self, val: u32) {
948 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
949 }
950 }
951 impl Default for Dcr4 {
952 #[inline(always)]
953 fn default() -> Dcr4 {
954 Dcr4(0)
955 }
956 }
957 impl core::fmt::Debug for Dcr4 {
958 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
959 f.debug_struct("Dcr4").field("refresh", &self.refresh()).finish()
960 }
961 }
962 #[cfg(feature = "defmt")]
963 impl defmt::Format for Dcr4 {
964 fn format(&self, f: defmt::Formatter) {
965 #[derive(defmt :: Format)]
966 struct Dcr4 {
967 refresh: u32,
968 }
969 let proxy = Dcr4 {
970 refresh: self.refresh(),
971 };
972 defmt::write!(f, "{}", proxy)
973 }
974 }
975 #[doc = "data length register"]
976 #[repr(transparent)]
977 #[derive(Copy, Clone, Eq, PartialEq)]
978 pub struct Dlr(pub u32);
979 impl Dlr {
980 #[doc = "31: 0\\]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL\\[0\\]
981is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode."]
982 #[inline(always)]
983 pub const fn dl(&self) -> u32 {
984 let val = (self.0 >> 0usize) & 0xffff_ffff;
985 val as u32
986 }
987 #[doc = "31: 0\\]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL\\[0\\]
988is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode."]
989 #[inline(always)]
990 pub fn set_dl(&mut self, val: u32) {
991 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
992 }
993 }
994 impl Default for Dlr {
995 #[inline(always)]
996 fn default() -> Dlr {
997 Dlr(0)
998 }
999 }
1000 impl core::fmt::Debug for Dlr {
1001 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1002 f.debug_struct("Dlr").field("dl", &self.dl()).finish()
1003 }
1004 }
1005 #[cfg(feature = "defmt")]
1006 impl defmt::Format for Dlr {
1007 fn format(&self, f: defmt::Formatter) {
1008 #[derive(defmt :: Format)]
1009 struct Dlr {
1010 dl: u32,
1011 }
1012 let proxy = Dlr { dl: self.dl() };
1013 defmt::write!(f, "{}", proxy)
1014 }
1015 }
1016 #[doc = "data register"]
1017 #[repr(transparent)]
1018 #[derive(Copy, Clone, Eq, PartialEq)]
1019 pub struct Dr(pub u32);
1020 impl Dr {
1021 #[doc = "31: 0\\]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA\\[7:0\\]
1022and a half-word read must read DATA\\[15:0\\]."]
1023 #[inline(always)]
1024 pub const fn data(&self) -> u32 {
1025 let val = (self.0 >> 0usize) & 0xffff_ffff;
1026 val as u32
1027 }
1028 #[doc = "31: 0\\]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA\\[7:0\\]
1029and a half-word read must read DATA\\[15:0\\]."]
1030 #[inline(always)]
1031 pub fn set_data(&mut self, val: u32) {
1032 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1033 }
1034 }
1035 impl Default for Dr {
1036 #[inline(always)]
1037 fn default() -> Dr {
1038 Dr(0)
1039 }
1040 }
1041 impl core::fmt::Debug for Dr {
1042 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1043 f.debug_struct("Dr").field("data", &self.data()).finish()
1044 }
1045 }
1046 #[cfg(feature = "defmt")]
1047 impl defmt::Format for Dr {
1048 fn format(&self, f: defmt::Formatter) {
1049 #[derive(defmt :: Format)]
1050 struct Dr {
1051 data: u32,
1052 }
1053 let proxy = Dr { data: self.data() };
1054 defmt::write!(f, "{}", proxy)
1055 }
1056 }
1057 #[doc = "flag clear register"]
1058 #[repr(transparent)]
1059 #[derive(Copy, Clone, Eq, PartialEq)]
1060 pub struct Fcr(pub u32);
1061 impl Fcr {
1062 #[doc = "Clear transfer error flag Writing 1 clears the TEF flag in the SR register."]
1063 #[inline(always)]
1064 pub const fn ctef(&self) -> bool {
1065 let val = (self.0 >> 0usize) & 0x01;
1066 val != 0
1067 }
1068 #[doc = "Clear transfer error flag Writing 1 clears the TEF flag in the SR register."]
1069 #[inline(always)]
1070 pub fn set_ctef(&mut self, val: bool) {
1071 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1072 }
1073 #[doc = "Clear transfer complete flag Writing 1 clears the TCF flag in the SR register."]
1074 #[inline(always)]
1075 pub const fn ctcf(&self) -> bool {
1076 let val = (self.0 >> 1usize) & 0x01;
1077 val != 0
1078 }
1079 #[doc = "Clear transfer complete flag Writing 1 clears the TCF flag in the SR register."]
1080 #[inline(always)]
1081 pub fn set_ctcf(&mut self, val: bool) {
1082 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1083 }
1084 #[doc = "Clear status match flag Writing 1 clears the SMF flag in the SR register."]
1085 #[inline(always)]
1086 pub const fn csmf(&self) -> bool {
1087 let val = (self.0 >> 3usize) & 0x01;
1088 val != 0
1089 }
1090 #[doc = "Clear status match flag Writing 1 clears the SMF flag in the SR register."]
1091 #[inline(always)]
1092 pub fn set_csmf(&mut self, val: bool) {
1093 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1094 }
1095 #[doc = "Clear timeout flag Writing 1 clears the TOF flag in the SR register."]
1096 #[inline(always)]
1097 pub const fn ctof(&self) -> bool {
1098 let val = (self.0 >> 4usize) & 0x01;
1099 val != 0
1100 }
1101 #[doc = "Clear timeout flag Writing 1 clears the TOF flag in the SR register."]
1102 #[inline(always)]
1103 pub fn set_ctof(&mut self, val: bool) {
1104 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1105 }
1106 }
1107 impl Default for Fcr {
1108 #[inline(always)]
1109 fn default() -> Fcr {
1110 Fcr(0)
1111 }
1112 }
1113 impl core::fmt::Debug for Fcr {
1114 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1115 f.debug_struct("Fcr")
1116 .field("ctef", &self.ctef())
1117 .field("ctcf", &self.ctcf())
1118 .field("csmf", &self.csmf())
1119 .field("ctof", &self.ctof())
1120 .finish()
1121 }
1122 }
1123 #[cfg(feature = "defmt")]
1124 impl defmt::Format for Fcr {
1125 fn format(&self, f: defmt::Formatter) {
1126 #[derive(defmt :: Format)]
1127 struct Fcr {
1128 ctef: bool,
1129 ctcf: bool,
1130 csmf: bool,
1131 ctof: bool,
1132 }
1133 let proxy = Fcr {
1134 ctef: self.ctef(),
1135 ctcf: self.ctcf(),
1136 csmf: self.csmf(),
1137 ctof: self.ctof(),
1138 };
1139 defmt::write!(f, "{}", proxy)
1140 }
1141 }
1142 #[doc = "OCTOSPI HyperBus latency configuration register"]
1143 #[repr(transparent)]
1144 #[derive(Copy, Clone, Eq, PartialEq)]
1145 pub struct Hlcr(pub u32);
1146 impl Hlcr {
1147 #[doc = "Latency mode. This bit selects the Latency mode."]
1148 #[inline(always)]
1149 pub const fn lm(&self) -> super::vals::LatencyMode {
1150 let val = (self.0 >> 0usize) & 0x01;
1151 super::vals::LatencyMode::from_bits(val as u8)
1152 }
1153 #[doc = "Latency mode. This bit selects the Latency mode."]
1154 #[inline(always)]
1155 pub fn set_lm(&mut self, val: super::vals::LatencyMode) {
1156 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
1157 }
1158 #[doc = "Write zero latency. This bit enables zero latency on write operations."]
1159 #[inline(always)]
1160 pub const fn wzl(&self) -> bool {
1161 let val = (self.0 >> 1usize) & 0x01;
1162 val != 0
1163 }
1164 #[doc = "Write zero latency. This bit enables zero latency on write operations."]
1165 #[inline(always)]
1166 pub fn set_wzl(&mut self, val: bool) {
1167 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1168 }
1169 #[doc = "7: 0\\]: Access time. Device access time expressed in number of communication clock cycles"]
1170 #[inline(always)]
1171 pub const fn tacc(&self) -> u8 {
1172 let val = (self.0 >> 8usize) & 0xff;
1173 val as u8
1174 }
1175 #[doc = "7: 0\\]: Access time. Device access time expressed in number of communication clock cycles"]
1176 #[inline(always)]
1177 pub fn set_tacc(&mut self, val: u8) {
1178 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
1179 }
1180 #[doc = "Read write recovery time Device read write recovery time expressed in number of communication clock cycles"]
1181 #[inline(always)]
1182 pub const fn trwr(&self) -> u8 {
1183 let val = (self.0 >> 16usize) & 0xff;
1184 val as u8
1185 }
1186 #[doc = "Read write recovery time Device read write recovery time expressed in number of communication clock cycles"]
1187 #[inline(always)]
1188 pub fn set_trwr(&mut self, val: u8) {
1189 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
1190 }
1191 }
1192 impl Default for Hlcr {
1193 #[inline(always)]
1194 fn default() -> Hlcr {
1195 Hlcr(0)
1196 }
1197 }
1198 impl core::fmt::Debug for Hlcr {
1199 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1200 f.debug_struct("Hlcr")
1201 .field("lm", &self.lm())
1202 .field("wzl", &self.wzl())
1203 .field("tacc", &self.tacc())
1204 .field("trwr", &self.trwr())
1205 .finish()
1206 }
1207 }
1208 #[cfg(feature = "defmt")]
1209 impl defmt::Format for Hlcr {
1210 fn format(&self, f: defmt::Formatter) {
1211 #[derive(defmt :: Format)]
1212 struct Hlcr {
1213 lm: super::vals::LatencyMode,
1214 wzl: bool,
1215 tacc: u8,
1216 trwr: u8,
1217 }
1218 let proxy = Hlcr {
1219 lm: self.lm(),
1220 wzl: self.wzl(),
1221 tacc: self.tacc(),
1222 trwr: self.trwr(),
1223 };
1224 defmt::write!(f, "{}", proxy)
1225 }
1226 }
1227 #[doc = "instruction register"]
1228 #[repr(transparent)]
1229 #[derive(Copy, Clone, Eq, PartialEq)]
1230 pub struct Ir(pub u32);
1231 impl Ir {
1232 #[doc = "Instruction to be sent to the external SPI device"]
1233 #[inline(always)]
1234 pub const fn instruction(&self) -> u32 {
1235 let val = (self.0 >> 0usize) & 0xffff_ffff;
1236 val as u32
1237 }
1238 #[doc = "Instruction to be sent to the external SPI device"]
1239 #[inline(always)]
1240 pub fn set_instruction(&mut self, val: u32) {
1241 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1242 }
1243 }
1244 impl Default for Ir {
1245 #[inline(always)]
1246 fn default() -> Ir {
1247 Ir(0)
1248 }
1249 }
1250 impl core::fmt::Debug for Ir {
1251 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1252 f.debug_struct("Ir").field("instruction", &self.instruction()).finish()
1253 }
1254 }
1255 #[cfg(feature = "defmt")]
1256 impl defmt::Format for Ir {
1257 fn format(&self, f: defmt::Formatter) {
1258 #[derive(defmt :: Format)]
1259 struct Ir {
1260 instruction: u32,
1261 }
1262 let proxy = Ir {
1263 instruction: self.instruction(),
1264 };
1265 defmt::write!(f, "{}", proxy)
1266 }
1267 }
1268 #[doc = "low-power timeout register"]
1269 #[repr(transparent)]
1270 #[derive(Copy, Clone, Eq, PartialEq)]
1271 pub struct Lptr(pub u32);
1272 impl Lptr {
1273 #[doc = "15: 0\\]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state."]
1274 #[inline(always)]
1275 pub const fn timeout(&self) -> u16 {
1276 let val = (self.0 >> 0usize) & 0xffff;
1277 val as u16
1278 }
1279 #[doc = "15: 0\\]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state."]
1280 #[inline(always)]
1281 pub fn set_timeout(&mut self, val: u16) {
1282 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1283 }
1284 }
1285 impl Default for Lptr {
1286 #[inline(always)]
1287 fn default() -> Lptr {
1288 Lptr(0)
1289 }
1290 }
1291 impl core::fmt::Debug for Lptr {
1292 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1293 f.debug_struct("Lptr").field("timeout", &self.timeout()).finish()
1294 }
1295 }
1296 #[cfg(feature = "defmt")]
1297 impl defmt::Format for Lptr {
1298 fn format(&self, f: defmt::Formatter) {
1299 #[derive(defmt :: Format)]
1300 struct Lptr {
1301 timeout: u16,
1302 }
1303 let proxy = Lptr {
1304 timeout: self.timeout(),
1305 };
1306 defmt::write!(f, "{}", proxy)
1307 }
1308 }
1309 #[doc = "polling interval register"]
1310 #[repr(transparent)]
1311 #[derive(Copy, Clone, Eq, PartialEq)]
1312 pub struct Pir(pub u32);
1313 impl Pir {
1314 #[doc = "15: 0\\]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases"]
1315 #[inline(always)]
1316 pub const fn interval(&self) -> u16 {
1317 let val = (self.0 >> 0usize) & 0xffff;
1318 val as u16
1319 }
1320 #[doc = "15: 0\\]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases"]
1321 #[inline(always)]
1322 pub fn set_interval(&mut self, val: u16) {
1323 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1324 }
1325 }
1326 impl Default for Pir {
1327 #[inline(always)]
1328 fn default() -> Pir {
1329 Pir(0)
1330 }
1331 }
1332 impl core::fmt::Debug for Pir {
1333 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1334 f.debug_struct("Pir").field("interval", &self.interval()).finish()
1335 }
1336 }
1337 #[cfg(feature = "defmt")]
1338 impl defmt::Format for Pir {
1339 fn format(&self, f: defmt::Formatter) {
1340 #[derive(defmt :: Format)]
1341 struct Pir {
1342 interval: u16,
1343 }
1344 let proxy = Pir {
1345 interval: self.interval(),
1346 };
1347 defmt::write!(f, "{}", proxy)
1348 }
1349 }
1350 #[doc = "polling status match register"]
1351 #[repr(transparent)]
1352 #[derive(Copy, Clone, Eq, PartialEq)]
1353 pub struct Psmar(pub u32);
1354 impl Psmar {
1355 #[doc = "31: 0\\]: Status match Value to be compared with the masked status register to get a match"]
1356 #[inline(always)]
1357 pub const fn match_(&self) -> u32 {
1358 let val = (self.0 >> 0usize) & 0xffff_ffff;
1359 val as u32
1360 }
1361 #[doc = "31: 0\\]: Status match Value to be compared with the masked status register to get a match"]
1362 #[inline(always)]
1363 pub fn set_match_(&mut self, val: u32) {
1364 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1365 }
1366 }
1367 impl Default for Psmar {
1368 #[inline(always)]
1369 fn default() -> Psmar {
1370 Psmar(0)
1371 }
1372 }
1373 impl core::fmt::Debug for Psmar {
1374 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1375 f.debug_struct("Psmar").field("match_", &self.match_()).finish()
1376 }
1377 }
1378 #[cfg(feature = "defmt")]
1379 impl defmt::Format for Psmar {
1380 fn format(&self, f: defmt::Formatter) {
1381 #[derive(defmt :: Format)]
1382 struct Psmar {
1383 match_: u32,
1384 }
1385 let proxy = Psmar { match_: self.match_() };
1386 defmt::write!(f, "{}", proxy)
1387 }
1388 }
1389 #[doc = "polling status mask register"]
1390 #[repr(transparent)]
1391 #[derive(Copy, Clone, Eq, PartialEq)]
1392 pub struct Psmkr(pub u32);
1393 impl Psmkr {
1394 #[doc = "Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n:"]
1395 #[inline(always)]
1396 pub const fn mask(&self) -> u32 {
1397 let val = (self.0 >> 0usize) & 0xffff_ffff;
1398 val as u32
1399 }
1400 #[doc = "Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n:"]
1401 #[inline(always)]
1402 pub fn set_mask(&mut self, val: u32) {
1403 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1404 }
1405 }
1406 impl Default for Psmkr {
1407 #[inline(always)]
1408 fn default() -> Psmkr {
1409 Psmkr(0)
1410 }
1411 }
1412 impl core::fmt::Debug for Psmkr {
1413 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1414 f.debug_struct("Psmkr").field("mask", &self.mask()).finish()
1415 }
1416 }
1417 #[cfg(feature = "defmt")]
1418 impl defmt::Format for Psmkr {
1419 fn format(&self, f: defmt::Formatter) {
1420 #[derive(defmt :: Format)]
1421 struct Psmkr {
1422 mask: u32,
1423 }
1424 let proxy = Psmkr { mask: self.mask() };
1425 defmt::write!(f, "{}", proxy)
1426 }
1427 }
1428 #[doc = "status register"]
1429 #[repr(transparent)]
1430 #[derive(Copy, Clone, Eq, PartialEq)]
1431 pub struct Sr(pub u32);
1432 impl Sr {
1433 #[doc = "Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF."]
1434 #[inline(always)]
1435 pub const fn tef(&self) -> bool {
1436 let val = (self.0 >> 0usize) & 0x01;
1437 val != 0
1438 }
1439 #[doc = "Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF."]
1440 #[inline(always)]
1441 pub fn set_tef(&mut self, val: bool) {
1442 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1443 }
1444 #[doc = "Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF."]
1445 #[inline(always)]
1446 pub const fn tcf(&self) -> bool {
1447 let val = (self.0 >> 1usize) & 0x01;
1448 val != 0
1449 }
1450 #[doc = "Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF."]
1451 #[inline(always)]
1452 pub fn set_tcf(&mut self, val: bool) {
1453 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1454 }
1455 #[doc = "FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read."]
1456 #[inline(always)]
1457 pub const fn ftf(&self) -> bool {
1458 let val = (self.0 >> 2usize) & 0x01;
1459 val != 0
1460 }
1461 #[doc = "FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read."]
1462 #[inline(always)]
1463 pub fn set_ftf(&mut self, val: bool) {
1464 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1465 }
1466 #[doc = "Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF."]
1467 #[inline(always)]
1468 pub const fn smf(&self) -> bool {
1469 let val = (self.0 >> 3usize) & 0x01;
1470 val != 0
1471 }
1472 #[doc = "Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF."]
1473 #[inline(always)]
1474 pub fn set_smf(&mut self, val: bool) {
1475 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1476 }
1477 #[doc = "Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF."]
1478 #[inline(always)]
1479 pub const fn tof(&self) -> bool {
1480 let val = (self.0 >> 4usize) & 0x01;
1481 val != 0
1482 }
1483 #[doc = "Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF."]
1484 #[inline(always)]
1485 pub fn set_tof(&mut self, val: bool) {
1486 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1487 }
1488 #[doc = "Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty."]
1489 #[inline(always)]
1490 pub const fn busy(&self) -> bool {
1491 let val = (self.0 >> 5usize) & 0x01;
1492 val != 0
1493 }
1494 #[doc = "Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty."]
1495 #[inline(always)]
1496 pub fn set_busy(&mut self, val: bool) {
1497 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1498 }
1499 #[doc = "FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero."]
1500 #[inline(always)]
1501 pub const fn flevel(&self) -> u8 {
1502 let val = (self.0 >> 8usize) & 0x3f;
1503 val as u8
1504 }
1505 #[doc = "FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero."]
1506 #[inline(always)]
1507 pub fn set_flevel(&mut self, val: u8) {
1508 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
1509 }
1510 }
1511 impl Default for Sr {
1512 #[inline(always)]
1513 fn default() -> Sr {
1514 Sr(0)
1515 }
1516 }
1517 impl core::fmt::Debug for Sr {
1518 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1519 f.debug_struct("Sr")
1520 .field("tef", &self.tef())
1521 .field("tcf", &self.tcf())
1522 .field("ftf", &self.ftf())
1523 .field("smf", &self.smf())
1524 .field("tof", &self.tof())
1525 .field("busy", &self.busy())
1526 .field("flevel", &self.flevel())
1527 .finish()
1528 }
1529 }
1530 #[cfg(feature = "defmt")]
1531 impl defmt::Format for Sr {
1532 fn format(&self, f: defmt::Formatter) {
1533 #[derive(defmt :: Format)]
1534 struct Sr {
1535 tef: bool,
1536 tcf: bool,
1537 ftf: bool,
1538 smf: bool,
1539 tof: bool,
1540 busy: bool,
1541 flevel: u8,
1542 }
1543 let proxy = Sr {
1544 tef: self.tef(),
1545 tcf: self.tcf(),
1546 ftf: self.ftf(),
1547 smf: self.smf(),
1548 tof: self.tof(),
1549 busy: self.busy(),
1550 flevel: self.flevel(),
1551 };
1552 defmt::write!(f, "{}", proxy)
1553 }
1554 }
1555 #[doc = "timing configuration register"]
1556 #[repr(transparent)]
1557 #[derive(Copy, Clone, Eq, PartialEq)]
1558 pub struct Tcr(pub u32);
1559 impl Tcr {
1560 #[doc = "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated."]
1561 #[inline(always)]
1562 pub const fn dcyc(&self) -> u8 {
1563 let val = (self.0 >> 0usize) & 0x1f;
1564 val as u8
1565 }
1566 #[doc = "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated."]
1567 #[inline(always)]
1568 pub fn set_dcyc(&mut self, val: u8) {
1569 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
1570 }
1571 #[doc = "Delay hold quarter cycle"]
1572 #[inline(always)]
1573 pub const fn dhqc(&self) -> bool {
1574 let val = (self.0 >> 28usize) & 0x01;
1575 val != 0
1576 }
1577 #[doc = "Delay hold quarter cycle"]
1578 #[inline(always)]
1579 pub fn set_dhqc(&mut self, val: bool) {
1580 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1581 }
1582 #[doc = "Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.)"]
1583 #[inline(always)]
1584 pub const fn sshift(&self) -> super::vals::SampleShift {
1585 let val = (self.0 >> 30usize) & 0x01;
1586 super::vals::SampleShift::from_bits(val as u8)
1587 }
1588 #[doc = "Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.)"]
1589 #[inline(always)]
1590 pub fn set_sshift(&mut self, val: super::vals::SampleShift) {
1591 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize);
1592 }
1593 }
1594 impl Default for Tcr {
1595 #[inline(always)]
1596 fn default() -> Tcr {
1597 Tcr(0)
1598 }
1599 }
1600 impl core::fmt::Debug for Tcr {
1601 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1602 f.debug_struct("Tcr")
1603 .field("dcyc", &self.dcyc())
1604 .field("dhqc", &self.dhqc())
1605 .field("sshift", &self.sshift())
1606 .finish()
1607 }
1608 }
1609 #[cfg(feature = "defmt")]
1610 impl defmt::Format for Tcr {
1611 fn format(&self, f: defmt::Formatter) {
1612 #[derive(defmt :: Format)]
1613 struct Tcr {
1614 dcyc: u8,
1615 dhqc: bool,
1616 sshift: super::vals::SampleShift,
1617 }
1618 let proxy = Tcr {
1619 dcyc: self.dcyc(),
1620 dhqc: self.dhqc(),
1621 sshift: self.sshift(),
1622 };
1623 defmt::write!(f, "{}", proxy)
1624 }
1625 }
1626 #[doc = "write alternate bytes register"]
1627 #[repr(transparent)]
1628 #[derive(Copy, Clone, Eq, PartialEq)]
1629 pub struct Wabr(pub u32);
1630 impl Wabr {
1631 #[doc = "31: 0\\]: Alternate bytes. Optional data to be sent to the external SPI device right after the address"]
1632 #[inline(always)]
1633 pub const fn alternate(&self) -> u32 {
1634 let val = (self.0 >> 0usize) & 0xffff_ffff;
1635 val as u32
1636 }
1637 #[doc = "31: 0\\]: Alternate bytes. Optional data to be sent to the external SPI device right after the address"]
1638 #[inline(always)]
1639 pub fn set_alternate(&mut self, val: u32) {
1640 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1641 }
1642 }
1643 impl Default for Wabr {
1644 #[inline(always)]
1645 fn default() -> Wabr {
1646 Wabr(0)
1647 }
1648 }
1649 impl core::fmt::Debug for Wabr {
1650 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1651 f.debug_struct("Wabr").field("alternate", &self.alternate()).finish()
1652 }
1653 }
1654 #[cfg(feature = "defmt")]
1655 impl defmt::Format for Wabr {
1656 fn format(&self, f: defmt::Formatter) {
1657 #[derive(defmt :: Format)]
1658 struct Wabr {
1659 alternate: u32,
1660 }
1661 let proxy = Wabr {
1662 alternate: self.alternate(),
1663 };
1664 defmt::write!(f, "{}", proxy)
1665 }
1666 }
1667 #[doc = "OCTOSPI write communication configuration register"]
1668 #[repr(transparent)]
1669 #[derive(Copy, Clone, Eq, PartialEq)]
1670 pub struct Wccr(pub u32);
1671 impl Wccr {
1672 #[doc = "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved"]
1673 #[inline(always)]
1674 pub const fn imode(&self) -> super::vals::PhaseMode {
1675 let val = (self.0 >> 0usize) & 0x07;
1676 super::vals::PhaseMode::from_bits(val as u8)
1677 }
1678 #[doc = "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved"]
1679 #[inline(always)]
1680 pub fn set_imode(&mut self, val: super::vals::PhaseMode) {
1681 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
1682 }
1683 #[doc = "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase."]
1684 #[inline(always)]
1685 pub const fn idtr(&self) -> bool {
1686 let val = (self.0 >> 3usize) & 0x01;
1687 val != 0
1688 }
1689 #[doc = "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase."]
1690 #[inline(always)]
1691 pub fn set_idtr(&mut self, val: bool) {
1692 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1693 }
1694 #[doc = "Instruction size. This bit defines instruction size:"]
1695 #[inline(always)]
1696 pub const fn isize(&self) -> super::vals::SizeInBits {
1697 let val = (self.0 >> 4usize) & 0x03;
1698 super::vals::SizeInBits::from_bits(val as u8)
1699 }
1700 #[doc = "Instruction size. This bit defines instruction size:"]
1701 #[inline(always)]
1702 pub fn set_isize(&mut self, val: super::vals::SizeInBits) {
1703 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
1704 }
1705 #[doc = "Address mode. This field defines the address phase mode of operation. 101-111: Reserved"]
1706 #[inline(always)]
1707 pub const fn admode(&self) -> super::vals::PhaseMode {
1708 let val = (self.0 >> 8usize) & 0x07;
1709 super::vals::PhaseMode::from_bits(val as u8)
1710 }
1711 #[doc = "Address mode. This field defines the address phase mode of operation. 101-111: Reserved"]
1712 #[inline(always)]
1713 pub fn set_admode(&mut self, val: super::vals::PhaseMode) {
1714 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
1715 }
1716 #[doc = "Address double transfer rate. This bit sets the DTR mode for the address phase."]
1717 #[inline(always)]
1718 pub const fn addtr(&self) -> bool {
1719 let val = (self.0 >> 11usize) & 0x01;
1720 val != 0
1721 }
1722 #[doc = "Address double transfer rate. This bit sets the DTR mode for the address phase."]
1723 #[inline(always)]
1724 pub fn set_addtr(&mut self, val: bool) {
1725 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1726 }
1727 #[doc = "Address size. This field defines address size."]
1728 #[inline(always)]
1729 pub const fn adsize(&self) -> super::vals::SizeInBits {
1730 let val = (self.0 >> 12usize) & 0x03;
1731 super::vals::SizeInBits::from_bits(val as u8)
1732 }
1733 #[doc = "Address size. This field defines address size."]
1734 #[inline(always)]
1735 pub fn set_adsize(&mut self, val: super::vals::SizeInBits) {
1736 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
1737 }
1738 #[doc = "Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved"]
1739 #[inline(always)]
1740 pub const fn abmode(&self) -> super::vals::PhaseMode {
1741 let val = (self.0 >> 16usize) & 0x07;
1742 super::vals::PhaseMode::from_bits(val as u8)
1743 }
1744 #[doc = "Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved"]
1745 #[inline(always)]
1746 pub fn set_abmode(&mut self, val: super::vals::PhaseMode) {
1747 self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
1748 }
1749 #[doc = "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase."]
1750 #[inline(always)]
1751 pub const fn abdtr(&self) -> bool {
1752 let val = (self.0 >> 19usize) & 0x01;
1753 val != 0
1754 }
1755 #[doc = "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase."]
1756 #[inline(always)]
1757 pub fn set_abdtr(&mut self, val: bool) {
1758 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1759 }
1760 #[doc = "Alternate bytes size. This field defines alternate bytes size:"]
1761 #[inline(always)]
1762 pub const fn absize(&self) -> super::vals::SizeInBits {
1763 let val = (self.0 >> 20usize) & 0x03;
1764 super::vals::SizeInBits::from_bits(val as u8)
1765 }
1766 #[doc = "Alternate bytes size. This field defines alternate bytes size:"]
1767 #[inline(always)]
1768 pub fn set_absize(&mut self, val: super::vals::SizeInBits) {
1769 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
1770 }
1771 #[doc = "Data mode. This field defines the data phase mode of operation. 101-111: Reserved"]
1772 #[inline(always)]
1773 pub const fn dmode(&self) -> super::vals::PhaseMode {
1774 let val = (self.0 >> 24usize) & 0x07;
1775 super::vals::PhaseMode::from_bits(val as u8)
1776 }
1777 #[doc = "Data mode. This field defines the data phase mode of operation. 101-111: Reserved"]
1778 #[inline(always)]
1779 pub fn set_dmode(&mut self, val: super::vals::PhaseMode) {
1780 self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
1781 }
1782 #[doc = "data double transfer rate. This bit sets the DTR mode for the data phase."]
1783 #[inline(always)]
1784 pub const fn ddtr(&self) -> bool {
1785 let val = (self.0 >> 27usize) & 0x01;
1786 val != 0
1787 }
1788 #[doc = "data double transfer rate. This bit sets the DTR mode for the data phase."]
1789 #[inline(always)]
1790 pub fn set_ddtr(&mut self, val: bool) {
1791 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
1792 }
1793 #[doc = "DQS enable. This bit enables the data strobe management."]
1794 #[inline(always)]
1795 pub const fn dqse(&self) -> bool {
1796 let val = (self.0 >> 29usize) & 0x01;
1797 val != 0
1798 }
1799 #[doc = "DQS enable. This bit enables the data strobe management."]
1800 #[inline(always)]
1801 pub fn set_dqse(&mut self, val: bool) {
1802 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
1803 }
1804 }
1805 impl Default for Wccr {
1806 #[inline(always)]
1807 fn default() -> Wccr {
1808 Wccr(0)
1809 }
1810 }
1811 impl core::fmt::Debug for Wccr {
1812 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1813 f.debug_struct("Wccr")
1814 .field("imode", &self.imode())
1815 .field("idtr", &self.idtr())
1816 .field("isize", &self.isize())
1817 .field("admode", &self.admode())
1818 .field("addtr", &self.addtr())
1819 .field("adsize", &self.adsize())
1820 .field("abmode", &self.abmode())
1821 .field("abdtr", &self.abdtr())
1822 .field("absize", &self.absize())
1823 .field("dmode", &self.dmode())
1824 .field("ddtr", &self.ddtr())
1825 .field("dqse", &self.dqse())
1826 .finish()
1827 }
1828 }
1829 #[cfg(feature = "defmt")]
1830 impl defmt::Format for Wccr {
1831 fn format(&self, f: defmt::Formatter) {
1832 #[derive(defmt :: Format)]
1833 struct Wccr {
1834 imode: super::vals::PhaseMode,
1835 idtr: bool,
1836 isize: super::vals::SizeInBits,
1837 admode: super::vals::PhaseMode,
1838 addtr: bool,
1839 adsize: super::vals::SizeInBits,
1840 abmode: super::vals::PhaseMode,
1841 abdtr: bool,
1842 absize: super::vals::SizeInBits,
1843 dmode: super::vals::PhaseMode,
1844 ddtr: bool,
1845 dqse: bool,
1846 }
1847 let proxy = Wccr {
1848 imode: self.imode(),
1849 idtr: self.idtr(),
1850 isize: self.isize(),
1851 admode: self.admode(),
1852 addtr: self.addtr(),
1853 adsize: self.adsize(),
1854 abmode: self.abmode(),
1855 abdtr: self.abdtr(),
1856 absize: self.absize(),
1857 dmode: self.dmode(),
1858 ddtr: self.ddtr(),
1859 dqse: self.dqse(),
1860 };
1861 defmt::write!(f, "{}", proxy)
1862 }
1863 }
1864 #[doc = "write instruction register"]
1865 #[repr(transparent)]
1866 #[derive(Copy, Clone, Eq, PartialEq)]
1867 pub struct Wir(pub u32);
1868 impl Wir {
1869 #[doc = "Instruction Instruction to be sent to the external SPI device"]
1870 #[inline(always)]
1871 pub const fn instruction(&self) -> u32 {
1872 let val = (self.0 >> 0usize) & 0xffff_ffff;
1873 val as u32
1874 }
1875 #[doc = "Instruction Instruction to be sent to the external SPI device"]
1876 #[inline(always)]
1877 pub fn set_instruction(&mut self, val: u32) {
1878 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1879 }
1880 }
1881 impl Default for Wir {
1882 #[inline(always)]
1883 fn default() -> Wir {
1884 Wir(0)
1885 }
1886 }
1887 impl core::fmt::Debug for Wir {
1888 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1889 f.debug_struct("Wir").field("instruction", &self.instruction()).finish()
1890 }
1891 }
1892 #[cfg(feature = "defmt")]
1893 impl defmt::Format for Wir {
1894 fn format(&self, f: defmt::Formatter) {
1895 #[derive(defmt :: Format)]
1896 struct Wir {
1897 instruction: u32,
1898 }
1899 let proxy = Wir {
1900 instruction: self.instruction(),
1901 };
1902 defmt::write!(f, "{}", proxy)
1903 }
1904 }
1905 #[doc = "wrap alternate bytes register"]
1906 #[repr(transparent)]
1907 #[derive(Copy, Clone, Eq, PartialEq)]
1908 pub struct Wpabr(pub u32);
1909 impl Wpabr {
1910 #[doc = "31: 0\\]: Alternate bytes Optional data to be sent to the external SPI device right after the address"]
1911 #[inline(always)]
1912 pub const fn alternate(&self) -> u32 {
1913 let val = (self.0 >> 0usize) & 0xffff_ffff;
1914 val as u32
1915 }
1916 #[doc = "31: 0\\]: Alternate bytes Optional data to be sent to the external SPI device right after the address"]
1917 #[inline(always)]
1918 pub fn set_alternate(&mut self, val: u32) {
1919 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1920 }
1921 }
1922 impl Default for Wpabr {
1923 #[inline(always)]
1924 fn default() -> Wpabr {
1925 Wpabr(0)
1926 }
1927 }
1928 impl core::fmt::Debug for Wpabr {
1929 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1930 f.debug_struct("Wpabr").field("alternate", &self.alternate()).finish()
1931 }
1932 }
1933 #[cfg(feature = "defmt")]
1934 impl defmt::Format for Wpabr {
1935 fn format(&self, f: defmt::Formatter) {
1936 #[derive(defmt :: Format)]
1937 struct Wpabr {
1938 alternate: u32,
1939 }
1940 let proxy = Wpabr {
1941 alternate: self.alternate(),
1942 };
1943 defmt::write!(f, "{}", proxy)
1944 }
1945 }
1946 #[doc = "OCTOSPI wrap communication configuration register"]
1947 #[repr(transparent)]
1948 #[derive(Copy, Clone, Eq, PartialEq)]
1949 pub struct Wpccr(pub u32);
1950 impl Wpccr {
1951 #[doc = "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved"]
1952 #[inline(always)]
1953 pub const fn imode(&self) -> super::vals::PhaseMode {
1954 let val = (self.0 >> 0usize) & 0x07;
1955 super::vals::PhaseMode::from_bits(val as u8)
1956 }
1957 #[doc = "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved"]
1958 #[inline(always)]
1959 pub fn set_imode(&mut self, val: super::vals::PhaseMode) {
1960 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
1961 }
1962 #[doc = "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase."]
1963 #[inline(always)]
1964 pub const fn idtr(&self) -> bool {
1965 let val = (self.0 >> 3usize) & 0x01;
1966 val != 0
1967 }
1968 #[doc = "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase."]
1969 #[inline(always)]
1970 pub fn set_idtr(&mut self, val: bool) {
1971 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1972 }
1973 #[doc = "Instruction size. This field defines instruction size."]
1974 #[inline(always)]
1975 pub const fn isize(&self) -> super::vals::SizeInBits {
1976 let val = (self.0 >> 4usize) & 0x03;
1977 super::vals::SizeInBits::from_bits(val as u8)
1978 }
1979 #[doc = "Instruction size. This field defines instruction size."]
1980 #[inline(always)]
1981 pub fn set_isize(&mut self, val: super::vals::SizeInBits) {
1982 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
1983 }
1984 #[doc = "Address mode. This field defines the address phase mode of operation. 101-111: Reserved"]
1985 #[inline(always)]
1986 pub const fn admode(&self) -> super::vals::PhaseMode {
1987 let val = (self.0 >> 8usize) & 0x07;
1988 super::vals::PhaseMode::from_bits(val as u8)
1989 }
1990 #[doc = "Address mode. This field defines the address phase mode of operation. 101-111: Reserved"]
1991 #[inline(always)]
1992 pub fn set_admode(&mut self, val: super::vals::PhaseMode) {
1993 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
1994 }
1995 #[doc = "Address double transfer rate. This bit sets the DTR mode for the address phase."]
1996 #[inline(always)]
1997 pub const fn addtr(&self) -> bool {
1998 let val = (self.0 >> 11usize) & 0x01;
1999 val != 0
2000 }
2001 #[doc = "Address double transfer rate. This bit sets the DTR mode for the address phase."]
2002 #[inline(always)]
2003 pub fn set_addtr(&mut self, val: bool) {
2004 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2005 }
2006 #[doc = "Address size. This field defines address size."]
2007 #[inline(always)]
2008 pub const fn adsize(&self) -> super::vals::SizeInBits {
2009 let val = (self.0 >> 12usize) & 0x03;
2010 super::vals::SizeInBits::from_bits(val as u8)
2011 }
2012 #[doc = "Address size. This field defines address size."]
2013 #[inline(always)]
2014 pub fn set_adsize(&mut self, val: super::vals::SizeInBits) {
2015 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
2016 }
2017 #[doc = "Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved"]
2018 #[inline(always)]
2019 pub const fn abmode(&self) -> super::vals::PhaseMode {
2020 let val = (self.0 >> 16usize) & 0x07;
2021 super::vals::PhaseMode::from_bits(val as u8)
2022 }
2023 #[doc = "Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved"]
2024 #[inline(always)]
2025 pub fn set_abmode(&mut self, val: super::vals::PhaseMode) {
2026 self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
2027 }
2028 #[doc = "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase."]
2029 #[inline(always)]
2030 pub const fn abdtr(&self) -> bool {
2031 let val = (self.0 >> 19usize) & 0x01;
2032 val != 0
2033 }
2034 #[doc = "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase."]
2035 #[inline(always)]
2036 pub fn set_abdtr(&mut self, val: bool) {
2037 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2038 }
2039 #[doc = "Alternate bytes size. This bit defines alternate bytes size."]
2040 #[inline(always)]
2041 pub const fn absize(&self) -> super::vals::SizeInBits {
2042 let val = (self.0 >> 20usize) & 0x03;
2043 super::vals::SizeInBits::from_bits(val as u8)
2044 }
2045 #[doc = "Alternate bytes size. This bit defines alternate bytes size."]
2046 #[inline(always)]
2047 pub fn set_absize(&mut self, val: super::vals::SizeInBits) {
2048 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
2049 }
2050 #[doc = "Data mode. This field defines the data phase mode of operation. 101-111: Reserved"]
2051 #[inline(always)]
2052 pub const fn dmode(&self) -> super::vals::PhaseMode {
2053 let val = (self.0 >> 24usize) & 0x07;
2054 super::vals::PhaseMode::from_bits(val as u8)
2055 }
2056 #[doc = "Data mode. This field defines the data phase mode of operation. 101-111: Reserved"]
2057 #[inline(always)]
2058 pub fn set_dmode(&mut self, val: super::vals::PhaseMode) {
2059 self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
2060 }
2061 #[doc = "Data double transfer rate. This bit sets the DTR mode for the data phase."]
2062 #[inline(always)]
2063 pub const fn ddtr(&self) -> bool {
2064 let val = (self.0 >> 27usize) & 0x01;
2065 val != 0
2066 }
2067 #[doc = "Data double transfer rate. This bit sets the DTR mode for the data phase."]
2068 #[inline(always)]
2069 pub fn set_ddtr(&mut self, val: bool) {
2070 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2071 }
2072 #[doc = "DQS enable. This bit enables the data strobe management."]
2073 #[inline(always)]
2074 pub const fn dqse(&self) -> bool {
2075 let val = (self.0 >> 29usize) & 0x01;
2076 val != 0
2077 }
2078 #[doc = "DQS enable. This bit enables the data strobe management."]
2079 #[inline(always)]
2080 pub fn set_dqse(&mut self, val: bool) {
2081 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
2082 }
2083 }
2084 impl Default for Wpccr {
2085 #[inline(always)]
2086 fn default() -> Wpccr {
2087 Wpccr(0)
2088 }
2089 }
2090 impl core::fmt::Debug for Wpccr {
2091 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2092 f.debug_struct("Wpccr")
2093 .field("imode", &self.imode())
2094 .field("idtr", &self.idtr())
2095 .field("isize", &self.isize())
2096 .field("admode", &self.admode())
2097 .field("addtr", &self.addtr())
2098 .field("adsize", &self.adsize())
2099 .field("abmode", &self.abmode())
2100 .field("abdtr", &self.abdtr())
2101 .field("absize", &self.absize())
2102 .field("dmode", &self.dmode())
2103 .field("ddtr", &self.ddtr())
2104 .field("dqse", &self.dqse())
2105 .finish()
2106 }
2107 }
2108 #[cfg(feature = "defmt")]
2109 impl defmt::Format for Wpccr {
2110 fn format(&self, f: defmt::Formatter) {
2111 #[derive(defmt :: Format)]
2112 struct Wpccr {
2113 imode: super::vals::PhaseMode,
2114 idtr: bool,
2115 isize: super::vals::SizeInBits,
2116 admode: super::vals::PhaseMode,
2117 addtr: bool,
2118 adsize: super::vals::SizeInBits,
2119 abmode: super::vals::PhaseMode,
2120 abdtr: bool,
2121 absize: super::vals::SizeInBits,
2122 dmode: super::vals::PhaseMode,
2123 ddtr: bool,
2124 dqse: bool,
2125 }
2126 let proxy = Wpccr {
2127 imode: self.imode(),
2128 idtr: self.idtr(),
2129 isize: self.isize(),
2130 admode: self.admode(),
2131 addtr: self.addtr(),
2132 adsize: self.adsize(),
2133 abmode: self.abmode(),
2134 abdtr: self.abdtr(),
2135 absize: self.absize(),
2136 dmode: self.dmode(),
2137 ddtr: self.ddtr(),
2138 dqse: self.dqse(),
2139 };
2140 defmt::write!(f, "{}", proxy)
2141 }
2142 }
2143 #[doc = "wrap instruction register"]
2144 #[repr(transparent)]
2145 #[derive(Copy, Clone, Eq, PartialEq)]
2146 pub struct Wpir(pub u32);
2147 impl Wpir {
2148 #[doc = "31: 0\\]: Instruction Instruction to be sent to the external SPI device"]
2149 #[inline(always)]
2150 pub const fn instruction(&self) -> u32 {
2151 let val = (self.0 >> 0usize) & 0xffff_ffff;
2152 val as u32
2153 }
2154 #[doc = "31: 0\\]: Instruction Instruction to be sent to the external SPI device"]
2155 #[inline(always)]
2156 pub fn set_instruction(&mut self, val: u32) {
2157 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2158 }
2159 }
2160 impl Default for Wpir {
2161 #[inline(always)]
2162 fn default() -> Wpir {
2163 Wpir(0)
2164 }
2165 }
2166 impl core::fmt::Debug for Wpir {
2167 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2168 f.debug_struct("Wpir")
2169 .field("instruction", &self.instruction())
2170 .finish()
2171 }
2172 }
2173 #[cfg(feature = "defmt")]
2174 impl defmt::Format for Wpir {
2175 fn format(&self, f: defmt::Formatter) {
2176 #[derive(defmt :: Format)]
2177 struct Wpir {
2178 instruction: u32,
2179 }
2180 let proxy = Wpir {
2181 instruction: self.instruction(),
2182 };
2183 defmt::write!(f, "{}", proxy)
2184 }
2185 }
2186 #[doc = "wrap timing configuration register"]
2187 #[repr(transparent)]
2188 #[derive(Copy, Clone, Eq, PartialEq)]
2189 pub struct Wptcr(pub u32);
2190 impl Wptcr {
2191 #[doc = "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2192 #[inline(always)]
2193 pub const fn dcyc(&self) -> u8 {
2194 let val = (self.0 >> 0usize) & 0x1f;
2195 val as u8
2196 }
2197 #[doc = "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2198 #[inline(always)]
2199 pub fn set_dcyc(&mut self, val: u8) {
2200 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
2201 }
2202 #[doc = "Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement."]
2203 #[inline(always)]
2204 pub const fn dhqc(&self) -> bool {
2205 let val = (self.0 >> 28usize) & 0x01;
2206 val != 0
2207 }
2208 #[doc = "Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement."]
2209 #[inline(always)]
2210 pub fn set_dhqc(&mut self, val: bool) {
2211 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2212 }
2213 #[doc = "Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1)."]
2214 #[inline(always)]
2215 pub const fn sshift(&self) -> super::vals::SampleShift {
2216 let val = (self.0 >> 30usize) & 0x01;
2217 super::vals::SampleShift::from_bits(val as u8)
2218 }
2219 #[doc = "Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1)."]
2220 #[inline(always)]
2221 pub fn set_sshift(&mut self, val: super::vals::SampleShift) {
2222 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize);
2223 }
2224 }
2225 impl Default for Wptcr {
2226 #[inline(always)]
2227 fn default() -> Wptcr {
2228 Wptcr(0)
2229 }
2230 }
2231 impl core::fmt::Debug for Wptcr {
2232 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2233 f.debug_struct("Wptcr")
2234 .field("dcyc", &self.dcyc())
2235 .field("dhqc", &self.dhqc())
2236 .field("sshift", &self.sshift())
2237 .finish()
2238 }
2239 }
2240 #[cfg(feature = "defmt")]
2241 impl defmt::Format for Wptcr {
2242 fn format(&self, f: defmt::Formatter) {
2243 #[derive(defmt :: Format)]
2244 struct Wptcr {
2245 dcyc: u8,
2246 dhqc: bool,
2247 sshift: super::vals::SampleShift,
2248 }
2249 let proxy = Wptcr {
2250 dcyc: self.dcyc(),
2251 dhqc: self.dhqc(),
2252 sshift: self.sshift(),
2253 };
2254 defmt::write!(f, "{}", proxy)
2255 }
2256 }
2257 #[doc = "write timing configuration register"]
2258 #[repr(transparent)]
2259 #[derive(Copy, Clone, Eq, PartialEq)]
2260 pub struct Wtcr(pub u32);
2261 impl Wtcr {
2262 #[doc = "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2263 #[inline(always)]
2264 pub const fn dcyc(&self) -> u8 {
2265 let val = (self.0 >> 0usize) & 0x1f;
2266 val as u8
2267 }
2268 #[doc = "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated."]
2269 #[inline(always)]
2270 pub fn set_dcyc(&mut self, val: u8) {
2271 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
2272 }
2273 }
2274 impl Default for Wtcr {
2275 #[inline(always)]
2276 fn default() -> Wtcr {
2277 Wtcr(0)
2278 }
2279 }
2280 impl core::fmt::Debug for Wtcr {
2281 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2282 f.debug_struct("Wtcr").field("dcyc", &self.dcyc()).finish()
2283 }
2284 }
2285 #[cfg(feature = "defmt")]
2286 impl defmt::Format for Wtcr {
2287 fn format(&self, f: defmt::Formatter) {
2288 #[derive(defmt :: Format)]
2289 struct Wtcr {
2290 dcyc: u8,
2291 }
2292 let proxy = Wtcr { dcyc: self.dcyc() };
2293 defmt::write!(f, "{}", proxy)
2294 }
2295 }
2296}
2297pub mod vals {
2298 #[repr(u8)]
2299 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2300 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2301 pub enum FlashSelect {
2302 #[doc = "FLASH 1 selected (data exchanged over IO\\[3:0\\])"]
2303 FLASH_ONE = 0x0,
2304 #[doc = "FLASH 2 selected (data exchanged over IO\\[7:4\\])"]
2305 FLASH_TWO = 0x01,
2306 }
2307 impl FlashSelect {
2308 #[inline(always)]
2309 pub const fn from_bits(val: u8) -> FlashSelect {
2310 unsafe { core::mem::transmute(val & 0x01) }
2311 }
2312 #[inline(always)]
2313 pub const fn to_bits(self) -> u8 {
2314 unsafe { core::mem::transmute(self) }
2315 }
2316 }
2317 impl From<u8> for FlashSelect {
2318 #[inline(always)]
2319 fn from(val: u8) -> FlashSelect {
2320 FlashSelect::from_bits(val)
2321 }
2322 }
2323 impl From<FlashSelect> for u8 {
2324 #[inline(always)]
2325 fn from(val: FlashSelect) -> u8 {
2326 FlashSelect::to_bits(val)
2327 }
2328 }
2329 #[repr(u8)]
2330 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2331 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2332 pub enum FunctionalMode {
2333 #[doc = "Indirect-write mode"]
2334 INDIRECT_WRITE = 0x0,
2335 #[doc = "Indirect-read mode"]
2336 INDIRECT_READ = 0x01,
2337 #[doc = "Automatic status-polling mode"]
2338 AUTO_STATUS_POLLING = 0x02,
2339 #[doc = "Memory-mapped mode"]
2340 MEMORY_MAPPED = 0x03,
2341 }
2342 impl FunctionalMode {
2343 #[inline(always)]
2344 pub const fn from_bits(val: u8) -> FunctionalMode {
2345 unsafe { core::mem::transmute(val & 0x03) }
2346 }
2347 #[inline(always)]
2348 pub const fn to_bits(self) -> u8 {
2349 unsafe { core::mem::transmute(self) }
2350 }
2351 }
2352 impl From<u8> for FunctionalMode {
2353 #[inline(always)]
2354 fn from(val: u8) -> FunctionalMode {
2355 FunctionalMode::from_bits(val)
2356 }
2357 }
2358 impl From<FunctionalMode> for u8 {
2359 #[inline(always)]
2360 fn from(val: FunctionalMode) -> u8 {
2361 FunctionalMode::to_bits(val)
2362 }
2363 }
2364 #[repr(u8)]
2365 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2366 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2367 pub enum LatencyMode {
2368 #[doc = "Variable initial latency"]
2369 VARIABLE = 0x0,
2370 #[doc = "Fixed latency"]
2371 FIXED = 0x01,
2372 }
2373 impl LatencyMode {
2374 #[inline(always)]
2375 pub const fn from_bits(val: u8) -> LatencyMode {
2376 unsafe { core::mem::transmute(val & 0x01) }
2377 }
2378 #[inline(always)]
2379 pub const fn to_bits(self) -> u8 {
2380 unsafe { core::mem::transmute(self) }
2381 }
2382 }
2383 impl From<u8> for LatencyMode {
2384 #[inline(always)]
2385 fn from(val: u8) -> LatencyMode {
2386 LatencyMode::from_bits(val)
2387 }
2388 }
2389 impl From<LatencyMode> for u8 {
2390 #[inline(always)]
2391 fn from(val: LatencyMode) -> u8 {
2392 LatencyMode::to_bits(val)
2393 }
2394 }
2395 #[repr(u8)]
2396 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2397 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2398 pub enum MatchMode {
2399 #[doc = "AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register."]
2400 MATCH_AND = 0x0,
2401 #[doc = "OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register."]
2402 MATCH_OR = 0x01,
2403 }
2404 impl MatchMode {
2405 #[inline(always)]
2406 pub const fn from_bits(val: u8) -> MatchMode {
2407 unsafe { core::mem::transmute(val & 0x01) }
2408 }
2409 #[inline(always)]
2410 pub const fn to_bits(self) -> u8 {
2411 unsafe { core::mem::transmute(self) }
2412 }
2413 }
2414 impl From<u8> for MatchMode {
2415 #[inline(always)]
2416 fn from(val: u8) -> MatchMode {
2417 MatchMode::from_bits(val)
2418 }
2419 }
2420 impl From<MatchMode> for u8 {
2421 #[inline(always)]
2422 fn from(val: MatchMode) -> u8 {
2423 MatchMode::to_bits(val)
2424 }
2425 }
2426 #[repr(u8)]
2427 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2428 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2429 pub enum MemType {
2430 #[doc = "Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes."]
2431 MICRON = 0x0,
2432 #[doc = "Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes."]
2433 MACRONIX = 0x01,
2434 #[doc = "Standard mode"]
2435 B_STANDARD = 0x02,
2436 #[doc = "Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping."]
2437 MACRONIX_RAM = 0x03,
2438 #[doc = "HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected."]
2439 HYPER_BUS_MEMORY = 0x04,
2440 #[doc = "HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used."]
2441 HYPER_BUS_REGISTER = 0x05,
2442 _RESERVED_6 = 0x06,
2443 _RESERVED_7 = 0x07,
2444 }
2445 impl MemType {
2446 #[inline(always)]
2447 pub const fn from_bits(val: u8) -> MemType {
2448 unsafe { core::mem::transmute(val & 0x07) }
2449 }
2450 #[inline(always)]
2451 pub const fn to_bits(self) -> u8 {
2452 unsafe { core::mem::transmute(self) }
2453 }
2454 }
2455 impl From<u8> for MemType {
2456 #[inline(always)]
2457 fn from(val: u8) -> MemType {
2458 MemType::from_bits(val)
2459 }
2460 }
2461 impl From<MemType> for u8 {
2462 #[inline(always)]
2463 fn from(val: MemType) -> u8 {
2464 MemType::to_bits(val)
2465 }
2466 }
2467 #[repr(u8)]
2468 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2469 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2470 pub enum PhaseMode {
2471 #[doc = "No alternate bytes"]
2472 NONE = 0x0,
2473 #[doc = "Alternate bytes on a single line"]
2474 ONE_LINE = 0x01,
2475 #[doc = "Alternate bytes on two lines"]
2476 TWO_LINES = 0x02,
2477 #[doc = "Alternate bytes on four lines"]
2478 FOUR_LINES = 0x03,
2479 #[doc = "Alternate bytes on eight lines"]
2480 EIGHT_LINES = 0x04,
2481 _RESERVED_5 = 0x05,
2482 _RESERVED_6 = 0x06,
2483 _RESERVED_7 = 0x07,
2484 }
2485 impl PhaseMode {
2486 #[inline(always)]
2487 pub const fn from_bits(val: u8) -> PhaseMode {
2488 unsafe { core::mem::transmute(val & 0x07) }
2489 }
2490 #[inline(always)]
2491 pub const fn to_bits(self) -> u8 {
2492 unsafe { core::mem::transmute(self) }
2493 }
2494 }
2495 impl From<u8> for PhaseMode {
2496 #[inline(always)]
2497 fn from(val: u8) -> PhaseMode {
2498 PhaseMode::from_bits(val)
2499 }
2500 }
2501 impl From<PhaseMode> for u8 {
2502 #[inline(always)]
2503 fn from(val: PhaseMode) -> u8 {
2504 PhaseMode::to_bits(val)
2505 }
2506 }
2507 #[repr(u8)]
2508 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2509 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2510 pub enum SampleShift {
2511 #[doc = "No shift"]
2512 NONE = 0x0,
2513 #[doc = "1/2 cycle shift"]
2514 HALF_CYCLE = 0x01,
2515 }
2516 impl SampleShift {
2517 #[inline(always)]
2518 pub const fn from_bits(val: u8) -> SampleShift {
2519 unsafe { core::mem::transmute(val & 0x01) }
2520 }
2521 #[inline(always)]
2522 pub const fn to_bits(self) -> u8 {
2523 unsafe { core::mem::transmute(self) }
2524 }
2525 }
2526 impl From<u8> for SampleShift {
2527 #[inline(always)]
2528 fn from(val: u8) -> SampleShift {
2529 SampleShift::from_bits(val)
2530 }
2531 }
2532 impl From<SampleShift> for u8 {
2533 #[inline(always)]
2534 fn from(val: SampleShift) -> u8 {
2535 SampleShift::to_bits(val)
2536 }
2537 }
2538 #[repr(u8)]
2539 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2540 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2541 pub enum SizeInBits {
2542 #[doc = "8-bit alternate bytes"]
2543 _8BIT = 0x0,
2544 #[doc = "16-bit alternate bytes"]
2545 _16BIT = 0x01,
2546 #[doc = "24-bit alternate bytes"]
2547 _24BIT = 0x02,
2548 #[doc = "32-bit alternate bytes"]
2549 _32BIT = 0x03,
2550 }
2551 impl SizeInBits {
2552 #[inline(always)]
2553 pub const fn from_bits(val: u8) -> SizeInBits {
2554 unsafe { core::mem::transmute(val & 0x03) }
2555 }
2556 #[inline(always)]
2557 pub const fn to_bits(self) -> u8 {
2558 unsafe { core::mem::transmute(self) }
2559 }
2560 }
2561 impl From<u8> for SizeInBits {
2562 #[inline(always)]
2563 fn from(val: u8) -> SizeInBits {
2564 SizeInBits::from_bits(val)
2565 }
2566 }
2567 impl From<SizeInBits> for u8 {
2568 #[inline(always)]
2569 fn from(val: SizeInBits) -> u8 {
2570 SizeInBits::to_bits(val)
2571 }
2572 }
2573 #[repr(transparent)]
2574 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2575 pub struct Threshold(pub u8);
2576 impl Threshold {
2577 #[doc = "FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode."]
2578 pub const NEED_ONE_BYTE: Self = Self(0x0);
2579 #[doc = "FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect‑write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode."]
2580 pub const NEED_TWO_BYTES: Self = Self(0x01);
2581 #[doc = "FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode."]
2582 pub const NEED_THIRTY_TWO_BYTES: Self = Self(0x1f);
2583 }
2584 impl Threshold {
2585 pub const fn from_bits(val: u8) -> Threshold {
2586 Self(val & 0x1f)
2587 }
2588 pub const fn to_bits(self) -> u8 {
2589 self.0
2590 }
2591 }
2592 impl core::fmt::Debug for Threshold {
2593 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2594 match self.0 {
2595 0x0 => f.write_str("NEED_ONE_BYTE"),
2596 0x01 => f.write_str("NEED_TWO_BYTES"),
2597 0x1f => f.write_str("NEED_THIRTY_TWO_BYTES"),
2598 other => core::write!(f, "0x{:02X}", other),
2599 }
2600 }
2601 }
2602 #[cfg(feature = "defmt")]
2603 impl defmt::Format for Threshold {
2604 fn format(&self, f: defmt::Formatter) {
2605 match self.0 {
2606 0x0 => defmt::write!(f, "NEED_ONE_BYTE"),
2607 0x01 => defmt::write!(f, "NEED_TWO_BYTES"),
2608 0x1f => defmt::write!(f, "NEED_THIRTY_TWO_BYTES"),
2609 other => defmt::write!(f, "0x{:02X}", other),
2610 }
2611 }
2612 }
2613 impl From<u8> for Threshold {
2614 #[inline(always)]
2615 fn from(val: u8) -> Threshold {
2616 Threshold::from_bits(val)
2617 }
2618 }
2619 impl From<Threshold> for u8 {
2620 #[inline(always)]
2621 fn from(val: Threshold) -> u8 {
2622 Threshold::to_bits(val)
2623 }
2624 }
2625}
2626